Low Jitter Programmable Clock Multipliers

Silicon Labs' Si5322, Si5325, Si5365 and Si5367 low-jitter programmable clock multiplier family provides flexible integer clock multiplication and clock distribution in high-performance timing applications requiring sub 1 ps jitter performance without jitter attenuation.

The programmable clock multiplier devices accept multiple clock inputs ranging from 10 to 710 MHz and generate two independent, synchronous clock outputs ranging from 10 to 945 MHz and select frequencies to 1.4 GHz.

Features

Flexible integer clock multiplier from 10 to 945 MHz and select frequencies to 1.4 GHz from an input frequency of 10 to 710 MHz
Low jitter clock outputs with jitter generation as low as 0.6 ps rms
Integrated loop filter with selectable loop bandwidth (30 kHz to 1.3 MHz)
Manual or automatic (revertive, non-revertive) input clock selection
Loss of signal (LOS), frequency offset (FOS) alarm outputs
Selectable output clock signal format (LVPECL, LVDS, CML, CMOS)
I²C/SPI programmable or pin-controlled

Applications

SONET/SDH OC-48/OC-192 line cards
GbE/10GbE, 1/2/4/8/10GFC line cards
ITU G.709 and custom FEC line cards
Wireless base stations
Test and measurement
Data converter clocking
DSLAM
Cable infrastructure
Optical modules
SONET/SDH + PDH clock synthesis

Technologies

Learn more: patented DSPLL technology

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Data Sheet (3)

Document Name	Description	Version
Si5322.pdf	Si5322 Data Sheet	0.5
Si5365.pdf	Si5365 Data Sheet	0.4
Si5367.pdf	Si5367 Data Sheet	0.4

User Guides (3)

Document Name	Description	Version	Last Updated
Si5316_19_22_23_24_25_26_27EVB.pdf	Si5316/19/22/23/24/25/26/27-EVB User's Guide	0.6	1/12/2012
Si5365_66_67_68_69-EVB.pdf	Si5365/66/67/68/69-EVB User's Guide	0.6	1/12/2012
Si53xxReferenceManual.pdf	Si53xxReferenceManual	0.51	12/14/2011

Application Notes (5)

Document Name	Description	Version	Last Updated
AN377.pdf	AN377: Timing and Synchronization in Broadcast Video	0.1	9/9/2009
AN428.pdf	AN428: Jump Start: In-System, Flash-Based Programming for Silicon Labs’ Timing Products	0.6	10/5/2010
AN491.pdf	AN491: Power Supply Rejection for Low Jitter Clocks	0.1	4/2/2010
AN513.pdf	AN513: Jitter Attenuation--Choosing the Right Phase-Locked Loop Bandwidth	0.1	6/10/2010
AN581.pdf	AN581: Meeting SerDes Jitter Requirements Simplified with Silicon Labs Clocks and Oscillators	0.1	9/2/2011

White Papers (2)

Document Name	Description	Version	Last Updated
DSP_Driven_Clocks.PDF	DSP-driven High-performance Clock Sources Radically Alter System Timing Architectures White Paper
Timing-ICs-Keep-Beat-with-Needs-of-Todays-Embedded-Market.pdf	Timing ICs Keep Beat with Needs of Today’s Embedded Market	1.0	11/21/2011

Miscellaneous (5)

Document Name	Description	Version	Last Updated
Silicon-Labs-Timing-Cross-Reference.pdf	Silicon Labs Timing Cross-Reference to Xilinx, Altera and Lattice FPGA Devices	2.1	2/8/2012
timing-solutions-for-cavium-processors.pdf	Silicon Labs' Timing Solutions for Cavium Processors	1.2	7/15/2011
timing-solutions-for-freescale-processors.pdf	Silicon Labs' Timing Solutions for Freescale Processors	1.0	12/20/2011
Timing-Solutions-for-Altera.pdf	Timing Solutions for Altera	0.3	12/7/2011
timing-solutions-for-plx-technology.pdf	Timing Solutions for PLX Technology	1.0	11/8/2011

Design Resources

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Software (3)

Document Name	Description	Version	Updated
AN428SW.zip	AN428 Jumpstart Software Ver 1.3	1.3	8/23/2010
release_notes_dspllsim.txt	Release Notes for the Precision Clock (DSPLLsim) EVB Software		12/14/2011
PrecisionClock_EVBSoftware.zip	Si531x/2x/6x DSPLLsim Software Version 4.6	4.6	12/14/2011

Models (1)

Document Name	Description	Version	Updated
Si531x_2x_Any-rate_Clocks3v3IBIS.zip	Si531x/2x Any-Rate Precision Clock IBIS Model 3.3 V	2.0

Training (1)

Document Name	Description	Version	Updated
DSP_Driven_Clocks.PDF	DSP-driven High-performance Clock Sources Radically Alter System Timing Architectures White Paper

Product Matrix

Part Number	Available Documents	Control	Package	Reference Inputs	Clock Outputs	Input Frequency	Output Frequency	Phase Jitter (RMS)	Output Format(s)	VDD	VDDO
Si5322	Data Sheet	Pin	6x6mm 36-QFN	2	2	19-707	19-1050	0.6 ps	LVPECL, LVDS, CML, LVCMOS	1.8, 2.5, 3.3V	1.8, 2.5, 3.3V
Si5325A	Data Sheet	I2C/SPI	6x6mm 36-QFN	2	2	10-945 MHz, 970-1134 MHz, 1.213-1.417 GHz	10-945 MHz, 970-1134 MHz, 1.213-1.417 GHz	0.6 ps	LVPECL, LVDS, CML, LVCMOS	1.8, 2.5, 3.3 V	1.8, 2.5, 3.3 V
Si5325B	Data Sheet	I2C/SPI	6x6mm 36-QFN	2	2	10-808 MHz	10-808 MHz	0.6 ps	LVPECL, LVDS, CML, LVCMOS	1.8, 2.5, 3.3 V	1.8, 2.5, 3.3 V
Si5325C	Data Sheet	I2C/SPI	6x6mm 36-QFN	2	2	10-346 MHz	10-346 MHz	0.6 ps	LVPECL, LVDS, CML, LVCMOS	1.8, 2.5, 3.3 V	1.8, 2.5, 3.3 V
Si5365	Data Sheet	Pin	14x14mm 100-TQFP	4	5	19-707	19-1050	0.6 ps	LVPECL, LVDS, CML, LVCMOS	1.8, 2.5, 3.3V	n/a
Si5367	Data Sheet	I2C/SPI	14x14mm 100-TQFP	4	5	10-710	10-1417	0.6 ps	LVPECL, LVDS, CML, LVCMOS	1.8, 2.5, 3.3V	n/a

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Microprocessor-controlled devices provide a wide range of frequency translation combinations across this operating range. For ease of use, pin-controlled devices are preconfigured to support popular SONET/SDH, Ethernet, Fibre Channel and HDTV frequencies. The low-jitter clock multipliers are based on Silicon Labs' third-generation DSPLL® technology, which provides any frequency synthesis and 0.6 ps rms jitter performance in a highly-integrated PLL solution that eliminates the need for external VCXO and loop filter components.

The DSPLL loop bandwidth is digitally-programmable from 30 kHz to 1.3 MHz. Programmable clock IC devices are offered in two package options: a 6 x 6 mm 36-pin QFN for devices with two clock outputs and a 14 x 14 mm 100-pin TQFP for products with five clock outputs. Silicon Labs low-jitter clock multipliers are ideal for providing clock multiplication and clock distribution in high-performance timing applications.

Clocks and Oscillators

Title Content
Low Jitter Integer Clock Multipliers

Features

Applications

Technologies