
Clocks and Oscillators
Timing IC Solutions
Silicon Labs offers the industry's broadest portfolio of clocks and oscillators for communications, computing, consumer and broadcast video applications. Our timing IC products leverage patented DSPLL, MultiSynth and silicon oscillator technologies to eliminate expensive discrete components while improving performance, minimizing board space and simplifying system design.
Download the Clock and Oscillator Selector Guide
Download Silicon Labs' Timing Solutions for Altera
Download Silicon Labs' Timing Solutions for Cavium Processors
Download Silicon Labs' Timing Solutions for PLX Technology
Download Silicon Labs' Cross Reference for Xilinx, Altera and Lattice FPGA Devices
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CDR/PHYs
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- PCI Express (PCIe) Gen 1/2/3 Clocks NEW!
Si52142/43/44/46/47, Si5334/35/38/56
- Differential + LVCMOS Clocks
Si5334/35/38
- LVCMOS Clocks (<4 outputs)
Tiny Clock Family NEW!Si51210/1/4/9, SL15xxx, SL160xx
- LVCMOS Clocks (5+ outputs)
Si5350/51, SL38xxx
- Integrated Clock + VCXO Solutions
Si5350/51, SL38000/160
- Embedded Intel x86 Clocks
CY28xxx, SL28xxx, Wxxx
- EMI Reduction Clocks NEW!Si5335/38/50/51/56, SL15xx,
Si52142/43/44/46/47, SL160xx
SONET Jitter Attenuating Clocks
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Industry's Shortest Lead Times for Timing ICs
To help you get to market faster, Silicon Labs offers custom, factory-programmable clocks and oscillators. Samples generally ship in two weeks or less.
- Custom Clocks – Specify any combination of input/output frequencies, and build a custom, application-specific clock.
- Custom Oscillators – Specify a custom oscillator and build a part number in minutes.
- Clock Tree Design Services – Send your clock requirements, and Silicon Labs will return a custom clock tree proposal within 3 business days that maximizes system performance while minimizing BOM cost and complexity.
Design Resources
White Paper: Minimize System-Level Noise and Interference
Download the Clock and Oscillator Selector Guide
Download Silicon Labs Cross Reference for Xilinx, Altera and Lattice FPGA Devices
Learn lab techniques to aid in minimizing noise and interference with PSRR