Silicon Labs’ family of SONET/SDH clock multiplier and jitter attenuator timing ICs include the Si5310 clock multiplier and the Si5320, Si5321 and Si5364 precision clock ICs .
The Si5310 is a fully-integrated low-power clock multiplier and clock regenerator IC designed to provide low-jitter clock synthesis/regeneration in high-speed communication systems.
The Si5310 synthesizes an output clock in either the 150–167 MHz or the 600–668 MHz frequency range from an input clock that is an integer submultiple between 10 and 311 MHz. Additionally, the Si5310 also regenerates a "clean" version of the input clock by using the clock synthesis phase-locked loop (PLL) to remove unwanted jitter and square up the input clock's rising and falling edges.
The Si5310 uses Silicon Labs’ patented DSPLL and features high-performance, small size, low-power and ease of use. It operates from a single 2.5 V supply and is packaged in a small 4 x 4 mm, 20-pin Micro Leaded Package (MLP).
The Si5320 SONET/SDH precision clock multiplier and jitter attenuator IC provides jitter performance that significantly exceeds the jitter requirements of high-speed data communications systems, including OC-192/STM-64, OC-48/STM-16 and 10 Gigabit Ethernet.
The Si5320 generates a user-selectable output clock centered at 19, 155 or 622 MHz from an input clock centered at one of six frequencies between 19 and 622 MHz. To support long-haul applications, frequency translation between standard SONET/SDH reference clock frequencies and 15/14 FEC frequencies is also supported.
The Si5320 uses Silicon Labs’ DSPLL technology and establishes a new standard for jitter performance, integration level and power usage in clock generation devices. It is available in a small 9 x 9 mm ball grid array (BGA) package, operates over a –20 to +85 °C temperature range and is powered from a single 3.3 V supply.
The Si5321 SONET/SDH precision clock multiplier and jitter attenuator IC features industry-leading jitter performance that significantly exceeds the jitter requirements of high-speed data communications systems, including OC-192/STM-64, OC-48/STM-16 and 10 Gigabit Ethernet.
The Si5321 generates a user-selectable output clock centered at 19, 39, 78, 155, 622, 1244 or 2488 MHz from an input clock centered at one of six frequencies between 19 and 622 MHz. Frequency translation between standard SONET/SDH reference clock frequencies and FEC frequencies is also supported, including G.709 and 10 GbE FEC rates.
Using Silicon Labs’ DSPLL technology, the Si5321 extends Silicon Laboratories’ expertise for industry-leading jitter performance, integration level and power usage in clock generation devices and is available in a small 9 x 9 mm BGA package. It operates over a –20 to 85 °C temperature range and is powered from a single 3.3 V supply.
The Si5364 is a complete solution for ultra-low jitter, high-speed clock generation and distribution in precision clocking applications, such as OC-192/OC-48 SONET/SDH line/port cards.
This device phase locks to one of three reference inputs in the range of 19.44 MHz and generates four synchronous clock outputs that can be independently configured for operation in the 19, 155 or 622 MHz range (1x, 8x and 32x input clock). The device reference monitoring and clock switching functions support MTIE compliant clock switching with excellent output phase transient characteristics. FEC rates are supported with selectable 15/14 or 14/15 scaling of the clock multiplication ratios.
Utilizing Silicon Labs’ DSPLL technology, the Si5364 establishes a new standard in performance and integration for ultra-low jitter clock generation and is available in a small 11 x 11 mm BGA package. It operates over a –20 to +85 °C temperature range and is powered from a single 3.3 V supply.