Micriµm

µC/CPU - Release Notes

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Version 1.29.02

Release date : 2013-03-18

Requirements

  • µC/LIB V1.35.00

New features & improvements

  • ARMv7 memory barriers: New memory barriers implementation for the Cortex A, R and M ports.
  • Stack alignment: New cpu specific define CPU_STK_ALIGN_BYTES for the platform required stack alignment.
  • Cortex A8: New port for the IAR toolchain.
  • Cortex A9: New port for the RealView/ARMCC toolchain.
  • Endianness test: New global constant CPU_EndiannessTest for testing endianness at runtime.

Bug fixes

  • (CPU-20) Renesas RX: Volatile registers require the __evenaccess type qualifier on RXC.
  • (CPU-15) cpu_bsp.c not buildable by default.
  • (CPU-13) ARMv7-AR: Add missing data synchronisation barriers in critical sections.
  • (CPU-6) Cortex-M: Interrupt priority incorrectly set for the M0, M3 and M4 ports.
Version 1.29.01.01

Release date : 2012-12-03

Requirements

  • µC/LIB V1.35.00

New features & improvements

  • Renesas RX port: New unified port for most of the Renesas RX series other than the RX610.
  • Configurable endianness: CPU endianness can now be configured in cpu_cfg.h for bi-endian architectures. Currently only the RX port supports this feature.

API Changes

  • N/A

Bug fixes

  • N/A

Deprecated features

  • The following CPU architectures are now supported by the new RX port and will be removed in a future release. Note that the RX610 still requires a separate port.
    • RX210
    • RX62N
    • RX63N
    • RX600
    • RX630
Previous versions