CMSIS Cortex-M3 Peripheral Access Layer for EFM EFM32G890F128. More...

#include "core_cm3.h"
#include "system_efm32.h"
#include <stdint.h>

Include dependency graph for efm32g890f128.h:

Data Structures
struct	MSC_TypeDef
struct	EMU_TypeDef
struct	RMU_TypeDef
struct	CMU_TypeDef
struct	AES_TypeDef
struct	EBI_TypeDef
struct	GPIO_P_TypeDef
	GPIO_P. More...
struct	GPIO_TypeDef
struct	PRS_CH_TypeDef
	PRS_CH. More...
struct	PRS_TypeDef
struct	DMA_CH_TypeDef
	DMA_CH. More...
struct	DMA_TypeDef
struct	TIMER_CC_TypeDef
	TIMER_CC. More...
struct	TIMER_TypeDef
struct	USART_TypeDef
struct	LEUART_TypeDef
struct	LETIMER_TypeDef
struct	PCNT_TypeDef
struct	I2C_TypeDef
struct	ADC_TypeDef
struct	DAC_TypeDef
struct	ACMP_TypeDef
struct	VCMP_TypeDef
struct	LCD_TypeDef
struct	RTC_TypeDef
struct	WDOG_TypeDef
struct	DEVINFO_TypeDef
struct	ROMTABLE_TypeDef
struct	CALIBRATE_TypeDef
struct	DMA_DESCRIPTOR_TypeDef
	DMA channel control data structure (descriptor) for PL230 controller. More...
Defines
#define	__MPU_PRESENT 1
#define	__NVIC_PRIO_BITS 3
#define	__Vendor_SysTickConfig 0
#define	EFM32G890F128
#define	PART_NUMBER "EFM32G890F128"
#define	EBI_MEM_BASE ((uint32_t) 0x80000000UL)
#define	EBI_MEM_SIZE ((uint32_t) 0x10000000UL)
#define	EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL)
#define	EBI_MEM_BITS ((uint32_t) 0x28UL)
#define	AES_MEM_BASE ((uint32_t) 0x400E0000UL)
#define	AES_MEM_SIZE ((uint32_t) 0x400UL)
#define	AES_MEM_END ((uint32_t) 0x400E03FFUL)
#define	AES_MEM_BITS ((uint32_t) 0x10UL)
#define	PER_MEM_BASE ((uint32_t) 0x40000000UL)
#define	PER_MEM_SIZE ((uint32_t) 0xE0000UL)
#define	PER_MEM_END ((uint32_t) 0x400DFFFFUL)
#define	PER_MEM_BITS ((uint32_t) 0x20UL)
#define	RAM_MEM_BASE ((uint32_t) 0x20000000UL)
#define	RAM_MEM_SIZE ((uint32_t) 0x4000UL)
#define	RAM_MEM_END ((uint32_t) 0x20003FFFUL)
#define	RAM_MEM_BITS ((uint32_t) 0x15UL)
#define	RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL)
#define	RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL)
#define	RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL)
#define	RAM_CODE_MEM_BITS ((uint32_t) 0x14UL)
#define	FLASH_MEM_BASE ((uint32_t) 0x0UL)
#define	FLASH_MEM_SIZE ((uint32_t) 0x10000000UL)
#define	FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL)
#define	FLASH_MEM_BITS ((uint32_t) 0x28UL)
#define	BITBAND_PER_BASE ((uint32_t) 0x42000000UL)
#define	BITBAND_RAM_BASE ((uint32_t) 0x22000000UL)
#define	FLASH_SIZE 0x00020000UL
#define	SRAM_SIZE 0x00004000UL
#define	__CM3_REV 0x200
#define	PRS_CHAN_COUNT 8
#define	DMA_CHAN_COUNT 8
#define	TIMER_PRESENT
#define	TIMER_COUNT 3
#define	USART_PRESENT
#define	USART_COUNT 3
#define	UART_PRESENT
#define	UART_COUNT 1
#define	LEUART_PRESENT
#define	LEUART_COUNT 2
#define	LETIMER_PRESENT
#define	LETIMER_COUNT 1
#define	PCNT_PRESENT
#define	PCNT_COUNT 3
#define	I2C_PRESENT
#define	I2C_COUNT 1
#define	ADC_PRESENT
#define	ADC_COUNT 1
#define	DAC_PRESENT
#define	DAC_COUNT 1
#define	ACMP_PRESENT
#define	ACMP_COUNT 2
#define	LE_PRESENT
#define	LE_COUNT 1
#define	MSC_PRESENT
#define	MSC_COUNT 1
#define	EMU_PRESENT
#define	EMU_COUNT 1
#define	RMU_PRESENT
#define	RMU_COUNT 1
#define	CMU_PRESENT
#define	CMU_COUNT 1
#define	AES_PRESENT
#define	AES_COUNT 1
#define	EBI_PRESENT
#define	EBI_COUNT 1
#define	GPIO_PRESENT
#define	GPIO_COUNT 1
#define	PRS_PRESENT
#define	PRS_COUNT 1
#define	DMA_PRESENT
#define	DMA_COUNT 1
#define	VCMP_PRESENT
#define	VCMP_COUNT 1
#define	LCD_PRESENT
#define	LCD_COUNT 1
#define	RTC_PRESENT
#define	RTC_COUNT 1
#define	HFXTAL_PRESENT
#define	HFXTAL_COUNT 1
#define	LFXTAL_PRESENT
#define	LFXTAL_COUNT 1
#define	WDOG_PRESENT
#define	WDOG_COUNT 1
#define	DBG_PRESENT
#define	DBG_COUNT 1
#define	CALIBRATE_MAX_REGISTERS 50
#define	MSC_BASE (0x400C0000UL)
#define	EMU_BASE (0x400C6000UL)
#define	RMU_BASE (0x400CA000UL)
#define	CMU_BASE (0x400C8000UL)
#define	AES_BASE (0x400E0000UL)
#define	EBI_BASE (0x40008000UL)
#define	GPIO_BASE (0x40006000UL)
#define	PRS_BASE (0x400CC000UL)
#define	DMA_BASE (0x400C2000UL)
#define	TIMER0_BASE (0x40010000UL)
#define	TIMER1_BASE (0x40010400UL)
#define	TIMER2_BASE (0x40010800UL)
#define	USART0_BASE (0x4000C000UL)
#define	USART1_BASE (0x4000C400UL)
#define	USART2_BASE (0x4000C800UL)
#define	UART0_BASE (0x4000E000UL)
#define	LEUART0_BASE (0x40084000UL)
#define	LEUART1_BASE (0x40084400UL)
#define	LETIMER0_BASE (0x40082000UL)
#define	PCNT0_BASE (0x40086000UL)
#define	PCNT1_BASE (0x40086400UL)
#define	PCNT2_BASE (0x40086800UL)
#define	I2C0_BASE (0x4000A000UL)
#define	ADC0_BASE (0x40002000UL)
#define	DAC0_BASE (0x40004000UL)
#define	ACMP0_BASE (0x40001000UL)
#define	ACMP1_BASE (0x40001400UL)
#define	VCMP_BASE (0x40000000UL)
#define	LCD_BASE (0x4008A000UL)
#define	RTC_BASE (0x40080000UL)
#define	WDOG_BASE (0x40088000UL)
#define	CALIBRATE_BASE (0x0FE08000UL)
#define	DEVINFO_BASE (0x0FE081B0UL)
#define	ROMTABLE_BASE (0xE00FFFD0)
#define	MSC ((MSC_TypeDef *) MSC_BASE)
#define	EMU ((EMU_TypeDef *) EMU_BASE)
#define	RMU ((RMU_TypeDef *) RMU_BASE)
#define	CMU ((CMU_TypeDef *) CMU_BASE)
#define	AES ((AES_TypeDef *) AES_BASE)
#define	EBI ((EBI_TypeDef *) EBI_BASE)
#define	GPIO ((GPIO_TypeDef *) GPIO_BASE)
#define	PRS ((PRS_TypeDef *) PRS_BASE)
#define	DMA ((DMA_TypeDef *) DMA_BASE)
#define	TIMER0 ((TIMER_TypeDef *) TIMER0_BASE)
#define	TIMER1 ((TIMER_TypeDef *) TIMER1_BASE)
#define	TIMER2 ((TIMER_TypeDef *) TIMER2_BASE)
#define	USART0 ((USART_TypeDef *) USART0_BASE)
#define	USART1 ((USART_TypeDef *) USART1_BASE)
#define	USART2 ((USART_TypeDef *) USART2_BASE)
#define	UART0 ((USART_TypeDef *) UART0_BASE)
#define	LEUART0 ((LEUART_TypeDef *) LEUART0_BASE)
#define	LEUART1 ((LEUART_TypeDef *) LEUART1_BASE)
#define	LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE)
#define	PCNT0 ((PCNT_TypeDef *) PCNT0_BASE)
#define	PCNT1 ((PCNT_TypeDef *) PCNT1_BASE)
#define	PCNT2 ((PCNT_TypeDef *) PCNT2_BASE)
#define	I2C0 ((I2C_TypeDef *) I2C0_BASE)
#define	ADC0 ((ADC_TypeDef *) ADC0_BASE)
#define	DAC0 ((DAC_TypeDef *) DAC0_BASE)
#define	ACMP0 ((ACMP_TypeDef *) ACMP0_BASE)
#define	ACMP1 ((ACMP_TypeDef *) ACMP1_BASE)
#define	VCMP ((VCMP_TypeDef *) VCMP_BASE)
#define	LCD ((LCD_TypeDef *) LCD_BASE)
#define	RTC ((RTC_TypeDef *) RTC_BASE)
#define	WDOG ((WDOG_TypeDef *) WDOG_BASE)
#define	CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE)
#define	DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE)
#define	ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE)
#define	PRS_VCMP_OUT ((1 << 16) + 0)
#define	PRS_ACMP0_OUT ((2 << 16) + 0)
#define	PRS_ACMP1_OUT ((3 << 16) + 0)
#define	PRS_DAC0_CH0 ((6 << 16) + 0)
#define	PRS_DAC0_CH1 ((6 << 16) + 1)
#define	PRS_ADC0_SINGLE ((8 << 16) + 0)
#define	PRS_ADC0_SCAN ((8 << 16) + 1)
#define	PRS_USART0_IRTX ((16 << 16) + 0)
#define	PRS_USART0_TXC ((16 << 16) + 1)
#define	PRS_USART0_RXDATAV ((16 << 16) + 2)
#define	PRS_USART1_IRTX ((17 << 16) + 0)
#define	PRS_USART1_TXC ((17 << 16) + 1)
#define	PRS_USART1_RXDATAV ((17 << 16) + 2)
#define	PRS_USART2_IRTX ((18 << 16) + 0)
#define	PRS_USART2_TXC ((18 << 16) + 1)
#define	PRS_USART2_RXDATAV ((18 << 16) + 2)
#define	PRS_TIMER0_UF ((28 << 16) + 0)
#define	PRS_TIMER0_OF ((28 << 16) + 1)
#define	PRS_TIMER0_CC0 ((28 << 16) + 2)
#define	PRS_TIMER0_CC1 ((28 << 16) + 3)
#define	PRS_TIMER0_CC2 ((28 << 16) + 4)
#define	PRS_TIMER1_UF ((29 << 16) + 0)
#define	PRS_TIMER1_OF ((29 << 16) + 1)
#define	PRS_TIMER1_CC0 ((29 << 16) + 2)
#define	PRS_TIMER1_CC1 ((29 << 16) + 3)
#define	PRS_TIMER1_CC2 ((29 << 16) + 4)
#define	PRS_TIMER2_UF ((30 << 16) + 0)
#define	PRS_TIMER2_OF ((30 << 16) + 1)
#define	PRS_TIMER2_CC0 ((30 << 16) + 2)
#define	PRS_TIMER2_CC1 ((30 << 16) + 3)
#define	PRS_TIMER2_CC2 ((30 << 16) + 4)
#define	PRS_RTC_OF ((40 << 16) + 0)
#define	PRS_RTC_COMP0 ((40 << 16) + 1)
#define	PRS_RTC_COMP1 ((40 << 16) + 2)
#define	PRS_UART0_IRTX ((41 << 16) + 0)
#define	PRS_UART0_TXC ((41 << 16) + 1)
#define	PRS_UART0_RXDATAV ((41 << 16) + 2)
#define	PRS_GPIO_PIN0 ((48 << 16) + 0)
#define	PRS_GPIO_PIN1 ((48 << 16) + 1)
#define	PRS_GPIO_PIN2 ((48 << 16) + 2)
#define	PRS_GPIO_PIN3 ((48 << 16) + 3)
#define	PRS_GPIO_PIN4 ((48 << 16) + 4)
#define	PRS_GPIO_PIN5 ((48 << 16) + 5)
#define	PRS_GPIO_PIN6 ((48 << 16) + 6)
#define	PRS_GPIO_PIN7 ((48 << 16) + 7)
#define	PRS_GPIO_PIN8 ((49 << 16) + 0)
#define	PRS_GPIO_PIN9 ((49 << 16) + 1)
#define	PRS_GPIO_PIN10 ((49 << 16) + 2)
#define	PRS_GPIO_PIN11 ((49 << 16) + 3)
#define	PRS_GPIO_PIN12 ((49 << 16) + 4)
#define	PRS_GPIO_PIN13 ((49 << 16) + 5)
#define	PRS_GPIO_PIN14 ((49 << 16) + 6)
#define	PRS_GPIO_PIN15 ((49 << 16) + 7)
#define	DMAREQ_ADC0_SINGLE ((8 << 16) + 0)
#define	DMAREQ_ADC0_SCAN ((8 << 16) + 1)
#define	DMAREQ_DAC0_CH0 ((10 << 16) + 0)
#define	DMAREQ_DAC0_CH1 ((10 << 16) + 1)
#define	DMAREQ_USART0_RXDATAV ((12 << 16) + 0)
#define	DMAREQ_USART0_TXBL ((12 << 16) + 1)
#define	DMAREQ_USART0_TXEMPTY ((12 << 16) + 2)
#define	DMAREQ_USART1_RXDATAV ((13 << 16) + 0)
#define	DMAREQ_USART1_TXBL ((13 << 16) + 1)
#define	DMAREQ_USART1_TXEMPTY ((13 << 16) + 2)
#define	DMAREQ_USART2_RXDATAV ((14 << 16) + 0)
#define	DMAREQ_USART2_TXBL ((14 << 16) + 1)
#define	DMAREQ_USART2_TXEMPTY ((14 << 16) + 2)
#define	DMAREQ_LEUART0_RXDATAV ((16 << 16) + 0)
#define	DMAREQ_LEUART0_TXBL ((16 << 16) + 1)
#define	DMAREQ_LEUART0_TXEMPTY ((16 << 16) + 2)
#define	DMAREQ_LEUART1_RXDATAV ((17 << 16) + 0)
#define	DMAREQ_LEUART1_TXBL ((17 << 16) + 1)
#define	DMAREQ_LEUART1_TXEMPTY ((17 << 16) + 2)
#define	DMAREQ_I2C0_RXDATAV ((20 << 16) + 0)
#define	DMAREQ_I2C0_TXBL ((20 << 16) + 1)
#define	DMAREQ_TIMER0_UFOF ((24 << 16) + 0)
#define	DMAREQ_TIMER0_CC0 ((24 << 16) + 1)
#define	DMAREQ_TIMER0_CC1 ((24 << 16) + 2)
#define	DMAREQ_TIMER0_CC2 ((24 << 16) + 3)
#define	DMAREQ_TIMER1_UFOF ((25 << 16) + 0)
#define	DMAREQ_TIMER1_CC0 ((25 << 16) + 1)
#define	DMAREQ_TIMER1_CC1 ((25 << 16) + 2)
#define	DMAREQ_TIMER1_CC2 ((25 << 16) + 3)
#define	DMAREQ_TIMER2_UFOF ((26 << 16) + 0)
#define	DMAREQ_TIMER2_CC0 ((26 << 16) + 1)
#define	DMAREQ_TIMER2_CC1 ((26 << 16) + 2)
#define	DMAREQ_TIMER2_CC2 ((26 << 16) + 3)
#define	DMAREQ_UART0_RXDATAV ((44 << 16) + 0)
#define	DMAREQ_UART0_TXBL ((44 << 16) + 1)
#define	DMAREQ_UART0_TXEMPTY ((44 << 16) + 2)
#define	DMAREQ_MSC_WDATA ((48 << 16) + 0)
#define	DMAREQ_AES_DATAWR ((49 << 16) + 0)
#define	DMAREQ_AES_XORDATAWR ((49 << 16) + 1)
#define	DMAREQ_AES_DATARD ((49 << 16) + 2)
#define	DMAREQ_AES_KEYWR ((49 << 16) + 3)
#define	_DMA_CTRL_DST_INC_MASK 0xC0000000UL
#define	_DMA_CTRL_DST_INC_SHIFT 30
#define	_DMA_CTRL_DST_INC_BYTE 0x00
#define	_DMA_CTRL_DST_INC_HALFWORD 0x01
#define	_DMA_CTRL_DST_INC_WORD 0x02
#define	_DMA_CTRL_DST_INC_NONE 0x03
#define	DMA_CTRL_DST_INC_BYTE 0x00000000UL
#define	DMA_CTRL_DST_INC_HALFWORD 0x40000000UL
#define	DMA_CTRL_DST_INC_WORD 0x80000000UL
#define	DMA_CTRL_DST_INC_NONE 0xC0000000UL
#define	_DMA_CTRL_DST_SIZE_MASK 0x30000000UL
#define	_DMA_CTRL_DST_SIZE_SHIFT 28
#define	_DMA_CTRL_DST_SIZE_BYTE 0x00
#define	_DMA_CTRL_DST_SIZE_HALFWORD 0x01
#define	_DMA_CTRL_DST_SIZE_WORD 0x02
#define	_DMA_CTRL_DST_SIZE_RSVD 0x03
#define	DMA_CTRL_DST_SIZE_BYTE 0x00000000UL
#define	DMA_CTRL_DST_SIZE_HALFWORD 0x10000000UL
#define	DMA_CTRL_DST_SIZE_WORD 0x20000000UL
#define	DMA_CTRL_DST_SIZE_RSVD 0x30000000UL
#define	_DMA_CTRL_SRC_INC_MASK 0x0C000000UL
#define	_DMA_CTRL_SRC_INC_SHIFT 26
#define	_DMA_CTRL_SRC_INC_BYTE 0x00
#define	_DMA_CTRL_SRC_INC_HALFWORD 0x01
#define	_DMA_CTRL_SRC_INC_WORD 0x02
#define	_DMA_CTRL_SRC_INC_NONE 0x03
#define	DMA_CTRL_SRC_INC_BYTE 0x00000000UL
#define	DMA_CTRL_SRC_INC_HALFWORD 0x04000000UL
#define	DMA_CTRL_SRC_INC_WORD 0x08000000UL
#define	DMA_CTRL_SRC_INC_NONE 0x0C000000UL
#define	_DMA_CTRL_SRC_SIZE_MASK 0x03000000UL
#define	_DMA_CTRL_SRC_SIZE_SHIFT 24
#define	_DMA_CTRL_SRC_SIZE_BYTE 0x00
#define	_DMA_CTRL_SRC_SIZE_HALFWORD 0x01
#define	_DMA_CTRL_SRC_SIZE_WORD 0x02
#define	_DMA_CTRL_SRC_SIZE_RSVD 0x03
#define	DMA_CTRL_SRC_SIZE_BYTE 0x00000000UL
#define	DMA_CTRL_SRC_SIZE_HALFWORD 0x01000000UL
#define	DMA_CTRL_SRC_SIZE_WORD 0x02000000UL
#define	DMA_CTRL_SRC_SIZE_RSVD 0x03000000UL
#define	_DMA_CTRL_DST_PROT_CTRL_MASK 0x00E00000UL
#define	_DMA_CTRL_DST_PROT_CTRL_SHIFT 21
#define	DMA_CTRL_DST_PROT_PRIVILEGED 0x00200000UL
#define	DMA_CTRL_DST_PROT_NON_PRIVILEGED 0x00000000UL
#define	_DMA_CTRL_SRC_PROT_CTRL_MASK 0x001C0000UL
#define	_DMA_CTRL_SRC_PROT_CTRL_SHIFT 18
#define	DMA_CTRL_SRC_PROT_PRIVILEGED 0x00040000UL
#define	DMA_CTRL_SRC_PROT_NON_PRIVILEGED 0x00000000UL
#define	_DMA_CTRL_PROT_NON_PRIVILEGED 0x00
#define	_DMA_CTRL_PROT_PRIVILEGED 0x01
#define	_DMA_CTRL_R_POWER_MASK 0x0003C000UL
#define	_DMA_CTRL_R_POWER_SHIFT 14
#define	_DMA_CTRL_R_POWER_1 0x00
#define	_DMA_CTRL_R_POWER_2 0x01
#define	_DMA_CTRL_R_POWER_4 0x02
#define	_DMA_CTRL_R_POWER_8 0x03
#define	_DMA_CTRL_R_POWER_16 0x04
#define	_DMA_CTRL_R_POWER_32 0x05
#define	_DMA_CTRL_R_POWER_64 0x06
#define	_DMA_CTRL_R_POWER_128 0x07
#define	_DMA_CTRL_R_POWER_256 0x08
#define	_DMA_CTRL_R_POWER_512 0x09
#define	_DMA_CTRL_R_POWER_1024 0x0a
#define	DMA_CTRL_R_POWER_1 0x00000000UL
#define	DMA_CTRL_R_POWER_2 0x00004000UL
#define	DMA_CTRL_R_POWER_4 0x00008000UL
#define	DMA_CTRL_R_POWER_8 0x0000c000UL
#define	DMA_CTRL_R_POWER_16 0x00010000UL
#define	DMA_CTRL_R_POWER_32 0x00014000UL
#define	DMA_CTRL_R_POWER_64 0x00018000UL
#define	DMA_CTRL_R_POWER_128 0x0001c000UL
#define	DMA_CTRL_R_POWER_256 0x00020000UL
#define	DMA_CTRL_R_POWER_512 0x00024000UL
#define	DMA_CTRL_R_POWER_1024 0x00028000UL
#define	_DMA_CTRL_N_MINUS_1_MASK 0x00003FF0UL
#define	_DMA_CTRL_N_MINUS_1_SHIFT 4
#define	_DMA_CTRL_NEXT_USEBURST_MASK 0x00000008UL
#define	_DMA_CTRL_NEXT_USEBURST_SHIFT 3
#define	_DMA_CTRL_CYCLE_CTRL_MASK 0x00000007UL
#define	_DMA_CTRL_CYCLE_CTRL_SHIFT 0
#define	_DMA_CTRL_CYCLE_CTRL_INVALID 0x00
#define	_DMA_CTRL_CYCLE_CTRL_BASIC 0x01
#define	_DMA_CTRL_CYCLE_CTRL_AUTO 0x02
#define	_DMA_CTRL_CYCLE_CTRL_PINGPONG 0x03
#define	_DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER 0x04
#define	_DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER_ALT 0x05
#define	_DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER 0x06
#define	_DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT 0x07
#define	DMA_CTRL_CYCLE_CTRL_INVALID 0x00000000UL
#define	DMA_CTRL_CYCLE_CTRL_BASIC 0x00000001UL
#define	DMA_CTRL_CYCLE_CTRL_AUTO 0x00000002UL
#define	DMA_CTRL_CYCLE_CTRL_PINGPONG 0x00000003UL
#define	DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER 0x000000004UL
#define	DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER_ALT 0x000000005UL
#define	DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER 0x000000006UL
#define	DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT 0x000000007UL
#define	_TIMER_CTRL_RESETVALUE 0x00000000UL
#define	_TIMER_CTRL_MASK 0x0F030FFBUL
#define	_TIMER_CTRL_MODE_SHIFT 0
#define	_TIMER_CTRL_MODE_MASK 0x3UL
#define	_TIMER_CTRL_MODE_DEFAULT 0x00000000UL
#define	_TIMER_CTRL_MODE_UP 0x00000000UL
#define	_TIMER_CTRL_MODE_DOWN 0x00000001UL
#define	_TIMER_CTRL_MODE_UPDOWN 0x00000002UL
#define	_TIMER_CTRL_MODE_QDEC 0x00000003UL
#define	TIMER_CTRL_MODE_DEFAULT (_TIMER_CTRL_MODE_DEFAULT << 0)
#define	TIMER_CTRL_MODE_UP (_TIMER_CTRL_MODE_UP << 0)
#define	TIMER_CTRL_MODE_DOWN (_TIMER_CTRL_MODE_DOWN << 0)
#define	TIMER_CTRL_MODE_UPDOWN (_TIMER_CTRL_MODE_UPDOWN << 0)
#define	TIMER_CTRL_MODE_QDEC (_TIMER_CTRL_MODE_QDEC << 0)
#define	TIMER_CTRL_SYNC (0x1UL << 3)
#define	_TIMER_CTRL_SYNC_SHIFT 3
#define	_TIMER_CTRL_SYNC_MASK 0x8UL
#define	_TIMER_CTRL_SYNC_DEFAULT 0x00000000UL
#define	TIMER_CTRL_SYNC_DEFAULT (_TIMER_CTRL_SYNC_DEFAULT << 3)
#define	TIMER_CTRL_OSMEN (0x1UL << 4)
#define	_TIMER_CTRL_OSMEN_SHIFT 4
#define	_TIMER_CTRL_OSMEN_MASK 0x10UL
#define	_TIMER_CTRL_OSMEN_DEFAULT 0x00000000UL
#define	TIMER_CTRL_OSMEN_DEFAULT (_TIMER_CTRL_OSMEN_DEFAULT << 4)
#define	TIMER_CTRL_QDM (0x1UL << 5)
#define	_TIMER_CTRL_QDM_SHIFT 5
#define	_TIMER_CTRL_QDM_MASK 0x20UL
#define	_TIMER_CTRL_QDM_DEFAULT 0x00000000UL
#define	_TIMER_CTRL_QDM_X2 0x00000000UL
#define	_TIMER_CTRL_QDM_X4 0x00000001UL
#define	TIMER_CTRL_QDM_DEFAULT (_TIMER_CTRL_QDM_DEFAULT << 5)
#define	TIMER_CTRL_QDM_X2 (_TIMER_CTRL_QDM_X2 << 5)
#define	TIMER_CTRL_QDM_X4 (_TIMER_CTRL_QDM_X4 << 5)
#define	TIMER_CTRL_DEBUGRUN (0x1UL << 6)
#define	_TIMER_CTRL_DEBUGRUN_SHIFT 6
#define	_TIMER_CTRL_DEBUGRUN_MASK 0x40UL
#define	_TIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL
#define	TIMER_CTRL_DEBUGRUN_DEFAULT (_TIMER_CTRL_DEBUGRUN_DEFAULT << 6)
#define	TIMER_CTRL_DMACLRACT (0x1UL << 7)
#define	_TIMER_CTRL_DMACLRACT_SHIFT 7
#define	_TIMER_CTRL_DMACLRACT_MASK 0x80UL
#define	_TIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL
#define	TIMER_CTRL_DMACLRACT_DEFAULT (_TIMER_CTRL_DMACLRACT_DEFAULT << 7)
#define	_TIMER_CTRL_RISEA_SHIFT 8
#define	_TIMER_CTRL_RISEA_MASK 0x300UL
#define	_TIMER_CTRL_RISEA_DEFAULT 0x00000000UL
#define	_TIMER_CTRL_RISEA_NONE 0x00000000UL
#define	_TIMER_CTRL_RISEA_START 0x00000001UL
#define	_TIMER_CTRL_RISEA_STOP 0x00000002UL
#define	_TIMER_CTRL_RISEA_RELOADSTART 0x00000003UL
#define	TIMER_CTRL_RISEA_DEFAULT (_TIMER_CTRL_RISEA_DEFAULT << 8)
#define	TIMER_CTRL_RISEA_NONE (_TIMER_CTRL_RISEA_NONE << 8)
#define	TIMER_CTRL_RISEA_START (_TIMER_CTRL_RISEA_START << 8)
#define	TIMER_CTRL_RISEA_STOP (_TIMER_CTRL_RISEA_STOP << 8)
#define	TIMER_CTRL_RISEA_RELOADSTART (_TIMER_CTRL_RISEA_RELOADSTART << 8)
#define	_TIMER_CTRL_FALLA_SHIFT 10
#define	_TIMER_CTRL_FALLA_MASK 0xC00UL
#define	_TIMER_CTRL_FALLA_DEFAULT 0x00000000UL
#define	_TIMER_CTRL_FALLA_NONE 0x00000000UL
#define	_TIMER_CTRL_FALLA_START 0x00000001UL
#define	_TIMER_CTRL_FALLA_STOP 0x00000002UL
#define	_TIMER_CTRL_FALLA_RELOADSTART 0x00000003UL
#define	TIMER_CTRL_FALLA_DEFAULT (_TIMER_CTRL_FALLA_DEFAULT << 10)
#define	TIMER_CTRL_FALLA_NONE (_TIMER_CTRL_FALLA_NONE << 10)
#define	TIMER_CTRL_FALLA_START (_TIMER_CTRL_FALLA_START << 10)
#define	TIMER_CTRL_FALLA_STOP (_TIMER_CTRL_FALLA_STOP << 10)
#define	TIMER_CTRL_FALLA_RELOADSTART (_TIMER_CTRL_FALLA_RELOADSTART << 10)
#define	_TIMER_CTRL_CLKSEL_SHIFT 16
#define	_TIMER_CTRL_CLKSEL_MASK 0x30000UL
#define	_TIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL
#define	_TIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL
#define	_TIMER_CTRL_CLKSEL_CC1 0x00000001UL
#define	_TIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL
#define	TIMER_CTRL_CLKSEL_DEFAULT (_TIMER_CTRL_CLKSEL_DEFAULT << 16)
#define	TIMER_CTRL_CLKSEL_PRESCHFPERCLK (_TIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16)
#define	TIMER_CTRL_CLKSEL_CC1 (_TIMER_CTRL_CLKSEL_CC1 << 16)
#define	TIMER_CTRL_CLKSEL_TIMEROUF (_TIMER_CTRL_CLKSEL_TIMEROUF << 16)
#define	_TIMER_CTRL_PRESC_SHIFT 24
#define	_TIMER_CTRL_PRESC_MASK 0xF000000UL
#define	_TIMER_CTRL_PRESC_DEFAULT 0x00000000UL
#define	_TIMER_CTRL_PRESC_DIV1 0x00000000UL
#define	_TIMER_CTRL_PRESC_DIV2 0x00000001UL
#define	_TIMER_CTRL_PRESC_DIV4 0x00000002UL
#define	_TIMER_CTRL_PRESC_DIV8 0x00000003UL
#define	_TIMER_CTRL_PRESC_DIV16 0x00000004UL
#define	_TIMER_CTRL_PRESC_DIV32 0x00000005UL
#define	_TIMER_CTRL_PRESC_DIV64 0x00000006UL
#define	_TIMER_CTRL_PRESC_DIV128 0x00000007UL
#define	_TIMER_CTRL_PRESC_DIV256 0x00000008UL
#define	_TIMER_CTRL_PRESC_DIV512 0x00000009UL
#define	_TIMER_CTRL_PRESC_DIV1024 0x0000000AUL
#define	TIMER_CTRL_PRESC_DEFAULT (_TIMER_CTRL_PRESC_DEFAULT << 24)
#define	TIMER_CTRL_PRESC_DIV1 (_TIMER_CTRL_PRESC_DIV1 << 24)
#define	TIMER_CTRL_PRESC_DIV2 (_TIMER_CTRL_PRESC_DIV2 << 24)
#define	TIMER_CTRL_PRESC_DIV4 (_TIMER_CTRL_PRESC_DIV4 << 24)
#define	TIMER_CTRL_PRESC_DIV8 (_TIMER_CTRL_PRESC_DIV8 << 24)
#define	TIMER_CTRL_PRESC_DIV16 (_TIMER_CTRL_PRESC_DIV16 << 24)
#define	TIMER_CTRL_PRESC_DIV32 (_TIMER_CTRL_PRESC_DIV32 << 24)
#define	TIMER_CTRL_PRESC_DIV64 (_TIMER_CTRL_PRESC_DIV64 << 24)
#define	TIMER_CTRL_PRESC_DIV128 (_TIMER_CTRL_PRESC_DIV128 << 24)
#define	TIMER_CTRL_PRESC_DIV256 (_TIMER_CTRL_PRESC_DIV256 << 24)
#define	TIMER_CTRL_PRESC_DIV512 (_TIMER_CTRL_PRESC_DIV512 << 24)
#define	TIMER_CTRL_PRESC_DIV1024 (_TIMER_CTRL_PRESC_DIV1024 << 24)
#define	_TIMER_CMD_RESETVALUE 0x00000000UL
#define	_TIMER_CMD_MASK 0x00000003UL
#define	TIMER_CMD_START (0x1UL << 0)
#define	_TIMER_CMD_START_SHIFT 0
#define	_TIMER_CMD_START_MASK 0x1UL
#define	_TIMER_CMD_START_DEFAULT 0x00000000UL
#define	TIMER_CMD_START_DEFAULT (_TIMER_CMD_START_DEFAULT << 0)
#define	TIMER_CMD_STOP (0x1UL << 1)
#define	_TIMER_CMD_STOP_SHIFT 1
#define	_TIMER_CMD_STOP_MASK 0x2UL
#define	_TIMER_CMD_STOP_DEFAULT 0x00000000UL
#define	TIMER_CMD_STOP_DEFAULT (_TIMER_CMD_STOP_DEFAULT << 1)
#define	_TIMER_STATUS_RESETVALUE 0x00000000UL
#define	_TIMER_STATUS_MASK 0x07070707UL
#define	TIMER_STATUS_RUNNING (0x1UL << 0)
#define	_TIMER_STATUS_RUNNING_SHIFT 0
#define	_TIMER_STATUS_RUNNING_MASK 0x1UL
#define	_TIMER_STATUS_RUNNING_DEFAULT 0x00000000UL
#define	TIMER_STATUS_RUNNING_DEFAULT (_TIMER_STATUS_RUNNING_DEFAULT << 0)
#define	TIMER_STATUS_DIR (0x1UL << 1)
#define	_TIMER_STATUS_DIR_SHIFT 1
#define	_TIMER_STATUS_DIR_MASK 0x2UL
#define	_TIMER_STATUS_DIR_DEFAULT 0x00000000UL
#define	_TIMER_STATUS_DIR_UP 0x00000000UL
#define	_TIMER_STATUS_DIR_DOWN 0x00000001UL
#define	TIMER_STATUS_DIR_DEFAULT (_TIMER_STATUS_DIR_DEFAULT << 1)
#define	TIMER_STATUS_DIR_UP (_TIMER_STATUS_DIR_UP << 1)
#define	TIMER_STATUS_DIR_DOWN (_TIMER_STATUS_DIR_DOWN << 1)
#define	TIMER_STATUS_TOPBV (0x1UL << 2)
#define	_TIMER_STATUS_TOPBV_SHIFT 2
#define	_TIMER_STATUS_TOPBV_MASK 0x4UL
#define	_TIMER_STATUS_TOPBV_DEFAULT 0x00000000UL
#define	TIMER_STATUS_TOPBV_DEFAULT (_TIMER_STATUS_TOPBV_DEFAULT << 2)
#define	TIMER_STATUS_CCVBV0 (0x1UL << 8)
#define	_TIMER_STATUS_CCVBV0_SHIFT 8
#define	_TIMER_STATUS_CCVBV0_MASK 0x100UL
#define	_TIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL
#define	TIMER_STATUS_CCVBV0_DEFAULT (_TIMER_STATUS_CCVBV0_DEFAULT << 8)
#define	TIMER_STATUS_CCVBV1 (0x1UL << 9)
#define	_TIMER_STATUS_CCVBV1_SHIFT 9
#define	_TIMER_STATUS_CCVBV1_MASK 0x200UL
#define	_TIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL
#define	TIMER_STATUS_CCVBV1_DEFAULT (_TIMER_STATUS_CCVBV1_DEFAULT << 9)
#define	TIMER_STATUS_CCVBV2 (0x1UL << 10)
#define	_TIMER_STATUS_CCVBV2_SHIFT 10
#define	_TIMER_STATUS_CCVBV2_MASK 0x400UL
#define	_TIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL
#define	TIMER_STATUS_CCVBV2_DEFAULT (_TIMER_STATUS_CCVBV2_DEFAULT << 10)
#define	TIMER_STATUS_ICV0 (0x1UL << 16)
#define	_TIMER_STATUS_ICV0_SHIFT 16
#define	_TIMER_STATUS_ICV0_MASK 0x10000UL
#define	_TIMER_STATUS_ICV0_DEFAULT 0x00000000UL
#define	TIMER_STATUS_ICV0_DEFAULT (_TIMER_STATUS_ICV0_DEFAULT << 16)
#define	TIMER_STATUS_ICV1 (0x1UL << 17)
#define	_TIMER_STATUS_ICV1_SHIFT 17
#define	_TIMER_STATUS_ICV1_MASK 0x20000UL
#define	_TIMER_STATUS_ICV1_DEFAULT 0x00000000UL
#define	TIMER_STATUS_ICV1_DEFAULT (_TIMER_STATUS_ICV1_DEFAULT << 17)
#define	TIMER_STATUS_ICV2 (0x1UL << 18)
#define	_TIMER_STATUS_ICV2_SHIFT 18
#define	_TIMER_STATUS_ICV2_MASK 0x40000UL
#define	_TIMER_STATUS_ICV2_DEFAULT 0x00000000UL
#define	TIMER_STATUS_ICV2_DEFAULT (_TIMER_STATUS_ICV2_DEFAULT << 18)
#define	TIMER_STATUS_CCPOL0 (0x1UL << 24)
#define	_TIMER_STATUS_CCPOL0_SHIFT 24
#define	_TIMER_STATUS_CCPOL0_MASK 0x1000000UL
#define	_TIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL
#define	_TIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL
#define	_TIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL
#define	TIMER_STATUS_CCPOL0_DEFAULT (_TIMER_STATUS_CCPOL0_DEFAULT << 24)
#define	TIMER_STATUS_CCPOL0_LOWRISE (_TIMER_STATUS_CCPOL0_LOWRISE << 24)
#define	TIMER_STATUS_CCPOL0_HIGHFALL (_TIMER_STATUS_CCPOL0_HIGHFALL << 24)
#define	TIMER_STATUS_CCPOL1 (0x1UL << 25)
#define	_TIMER_STATUS_CCPOL1_SHIFT 25
#define	_TIMER_STATUS_CCPOL1_MASK 0x2000000UL
#define	_TIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL
#define	_TIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL
#define	_TIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL
#define	TIMER_STATUS_CCPOL1_DEFAULT (_TIMER_STATUS_CCPOL1_DEFAULT << 25)
#define	TIMER_STATUS_CCPOL1_LOWRISE (_TIMER_STATUS_CCPOL1_LOWRISE << 25)
#define	TIMER_STATUS_CCPOL1_HIGHFALL (_TIMER_STATUS_CCPOL1_HIGHFALL << 25)
#define	TIMER_STATUS_CCPOL2 (0x1UL << 26)
#define	_TIMER_STATUS_CCPOL2_SHIFT 26
#define	_TIMER_STATUS_CCPOL2_MASK 0x4000000UL
#define	_TIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL
#define	_TIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL
#define	_TIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL
#define	TIMER_STATUS_CCPOL2_DEFAULT (_TIMER_STATUS_CCPOL2_DEFAULT << 26)
#define	TIMER_STATUS_CCPOL2_LOWRISE (_TIMER_STATUS_CCPOL2_LOWRISE << 26)
#define	TIMER_STATUS_CCPOL2_HIGHFALL (_TIMER_STATUS_CCPOL2_HIGHFALL << 26)
#define	_TIMER_IEN_RESETVALUE 0x00000000UL
#define	_TIMER_IEN_MASK 0x00000773UL
#define	TIMER_IEN_OF (0x1UL << 0)
#define	_TIMER_IEN_OF_SHIFT 0
#define	_TIMER_IEN_OF_MASK 0x1UL
#define	_TIMER_IEN_OF_DEFAULT 0x00000000UL
#define	TIMER_IEN_OF_DEFAULT (_TIMER_IEN_OF_DEFAULT << 0)
#define	TIMER_IEN_UF (0x1UL << 1)
#define	_TIMER_IEN_UF_SHIFT 1
#define	_TIMER_IEN_UF_MASK 0x2UL
#define	_TIMER_IEN_UF_DEFAULT 0x00000000UL
#define	TIMER_IEN_UF_DEFAULT (_TIMER_IEN_UF_DEFAULT << 1)
#define	TIMER_IEN_CC0 (0x1UL << 4)
#define	_TIMER_IEN_CC0_SHIFT 4
#define	_TIMER_IEN_CC0_MASK 0x10UL
#define	_TIMER_IEN_CC0_DEFAULT 0x00000000UL
#define	TIMER_IEN_CC0_DEFAULT (_TIMER_IEN_CC0_DEFAULT << 4)
#define	TIMER_IEN_CC1 (0x1UL << 5)
#define	_TIMER_IEN_CC1_SHIFT 5
#define	_TIMER_IEN_CC1_MASK 0x20UL
#define	_TIMER_IEN_CC1_DEFAULT 0x00000000UL
#define	TIMER_IEN_CC1_DEFAULT (_TIMER_IEN_CC1_DEFAULT << 5)
#define	TIMER_IEN_CC2 (0x1UL << 6)
#define	_TIMER_IEN_CC2_SHIFT 6
#define	_TIMER_IEN_CC2_MASK 0x40UL
#define	_TIMER_IEN_CC2_DEFAULT 0x00000000UL
#define	TIMER_IEN_CC2_DEFAULT (_TIMER_IEN_CC2_DEFAULT << 6)
#define	TIMER_IEN_ICBOF0 (0x1UL << 8)
#define	_TIMER_IEN_ICBOF0_SHIFT 8
#define	_TIMER_IEN_ICBOF0_MASK 0x100UL
#define	_TIMER_IEN_ICBOF0_DEFAULT 0x00000000UL
#define	TIMER_IEN_ICBOF0_DEFAULT (_TIMER_IEN_ICBOF0_DEFAULT << 8)
#define	TIMER_IEN_ICBOF1 (0x1UL << 9)
#define	_TIMER_IEN_ICBOF1_SHIFT 9
#define	_TIMER_IEN_ICBOF1_MASK 0x200UL
#define	_TIMER_IEN_ICBOF1_DEFAULT 0x00000000UL
#define	TIMER_IEN_ICBOF1_DEFAULT (_TIMER_IEN_ICBOF1_DEFAULT << 9)
#define	TIMER_IEN_ICBOF2 (0x1UL << 10)
#define	_TIMER_IEN_ICBOF2_SHIFT 10
#define	_TIMER_IEN_ICBOF2_MASK 0x400UL
#define	_TIMER_IEN_ICBOF2_DEFAULT 0x00000000UL
#define	TIMER_IEN_ICBOF2_DEFAULT (_TIMER_IEN_ICBOF2_DEFAULT << 10)
#define	_TIMER_IF_RESETVALUE 0x00000000UL
#define	_TIMER_IF_MASK 0x00000773UL
#define	TIMER_IF_OF (0x1UL << 0)
#define	_TIMER_IF_OF_SHIFT 0
#define	_TIMER_IF_OF_MASK 0x1UL
#define	_TIMER_IF_OF_DEFAULT 0x00000000UL
#define	TIMER_IF_OF_DEFAULT (_TIMER_IF_OF_DEFAULT << 0)
#define	TIMER_IF_UF (0x1UL << 1)
#define	_TIMER_IF_UF_SHIFT 1
#define	_TIMER_IF_UF_MASK 0x2UL
#define	_TIMER_IF_UF_DEFAULT 0x00000000UL
#define	TIMER_IF_UF_DEFAULT (_TIMER_IF_UF_DEFAULT << 1)
#define	TIMER_IF_CC0 (0x1UL << 4)
#define	_TIMER_IF_CC0_SHIFT 4
#define	_TIMER_IF_CC0_MASK 0x10UL
#define	_TIMER_IF_CC0_DEFAULT 0x00000000UL
#define	TIMER_IF_CC0_DEFAULT (_TIMER_IF_CC0_DEFAULT << 4)
#define	TIMER_IF_CC1 (0x1UL << 5)
#define	_TIMER_IF_CC1_SHIFT 5
#define	_TIMER_IF_CC1_MASK 0x20UL
#define	_TIMER_IF_CC1_DEFAULT 0x00000000UL
#define	TIMER_IF_CC1_DEFAULT (_TIMER_IF_CC1_DEFAULT << 5)
#define	TIMER_IF_CC2 (0x1UL << 6)
#define	_TIMER_IF_CC2_SHIFT 6
#define	_TIMER_IF_CC2_MASK 0x40UL
#define	_TIMER_IF_CC2_DEFAULT 0x00000000UL
#define	TIMER_IF_CC2_DEFAULT (_TIMER_IF_CC2_DEFAULT << 6)
#define	TIMER_IF_ICBOF0 (0x1UL << 8)
#define	_TIMER_IF_ICBOF0_SHIFT 8
#define	_TIMER_IF_ICBOF0_MASK 0x100UL
#define	_TIMER_IF_ICBOF0_DEFAULT 0x00000000UL
#define	TIMER_IF_ICBOF0_DEFAULT (_TIMER_IF_ICBOF0_DEFAULT << 8)
#define	TIMER_IF_ICBOF1 (0x1UL << 9)
#define	_TIMER_IF_ICBOF1_SHIFT 9
#define	_TIMER_IF_ICBOF1_MASK 0x200UL
#define	_TIMER_IF_ICBOF1_DEFAULT 0x00000000UL
#define	TIMER_IF_ICBOF1_DEFAULT (_TIMER_IF_ICBOF1_DEFAULT << 9)
#define	TIMER_IF_ICBOF2 (0x1UL << 10)
#define	_TIMER_IF_ICBOF2_SHIFT 10
#define	_TIMER_IF_ICBOF2_MASK 0x400UL
#define	_TIMER_IF_ICBOF2_DEFAULT 0x00000000UL
#define	TIMER_IF_ICBOF2_DEFAULT (_TIMER_IF_ICBOF2_DEFAULT << 10)
#define	_TIMER_IFS_RESETVALUE 0x00000000UL
#define	_TIMER_IFS_MASK 0x00000773UL
#define	TIMER_IFS_OF (0x1UL << 0)
#define	_TIMER_IFS_OF_SHIFT 0
#define	_TIMER_IFS_OF_MASK 0x1UL
#define	_TIMER_IFS_OF_DEFAULT 0x00000000UL
#define	TIMER_IFS_OF_DEFAULT (_TIMER_IFS_OF_DEFAULT << 0)
#define	TIMER_IFS_UF (0x1UL << 1)
#define	_TIMER_IFS_UF_SHIFT 1
#define	_TIMER_IFS_UF_MASK 0x2UL
#define	_TIMER_IFS_UF_DEFAULT 0x00000000UL
#define	TIMER_IFS_UF_DEFAULT (_TIMER_IFS_UF_DEFAULT << 1)
#define	TIMER_IFS_CC0 (0x1UL << 4)
#define	_TIMER_IFS_CC0_SHIFT 4
#define	_TIMER_IFS_CC0_MASK 0x10UL
#define	_TIMER_IFS_CC0_DEFAULT 0x00000000UL
#define	TIMER_IFS_CC0_DEFAULT (_TIMER_IFS_CC0_DEFAULT << 4)
#define	TIMER_IFS_CC1 (0x1UL << 5)
#define	_TIMER_IFS_CC1_SHIFT 5
#define	_TIMER_IFS_CC1_MASK 0x20UL
#define	_TIMER_IFS_CC1_DEFAULT 0x00000000UL
#define	TIMER_IFS_CC1_DEFAULT (_TIMER_IFS_CC1_DEFAULT << 5)
#define	TIMER_IFS_CC2 (0x1UL << 6)
#define	_TIMER_IFS_CC2_SHIFT 6
#define	_TIMER_IFS_CC2_MASK 0x40UL
#define	_TIMER_IFS_CC2_DEFAULT 0x00000000UL
#define	TIMER_IFS_CC2_DEFAULT (_TIMER_IFS_CC2_DEFAULT << 6)
#define	TIMER_IFS_ICBOF0 (0x1UL << 8)
#define	_TIMER_IFS_ICBOF0_SHIFT 8
#define	_TIMER_IFS_ICBOF0_MASK 0x100UL
#define	_TIMER_IFS_ICBOF0_DEFAULT 0x00000000UL
#define	TIMER_IFS_ICBOF0_DEFAULT (_TIMER_IFS_ICBOF0_DEFAULT << 8)
#define	TIMER_IFS_ICBOF1 (0x1UL << 9)
#define	_TIMER_IFS_ICBOF1_SHIFT 9
#define	_TIMER_IFS_ICBOF1_MASK 0x200UL
#define	_TIMER_IFS_ICBOF1_DEFAULT 0x00000000UL
#define	TIMER_IFS_ICBOF1_DEFAULT (_TIMER_IFS_ICBOF1_DEFAULT << 9)
#define	TIMER_IFS_ICBOF2 (0x1UL << 10)
#define	_TIMER_IFS_ICBOF2_SHIFT 10
#define	_TIMER_IFS_ICBOF2_MASK 0x400UL
#define	_TIMER_IFS_ICBOF2_DEFAULT 0x00000000UL
#define	TIMER_IFS_ICBOF2_DEFAULT (_TIMER_IFS_ICBOF2_DEFAULT << 10)
#define	_TIMER_IFC_RESETVALUE 0x00000000UL
#define	_TIMER_IFC_MASK 0x00000773UL
#define	TIMER_IFC_OF (0x1UL << 0)
#define	_TIMER_IFC_OF_SHIFT 0
#define	_TIMER_IFC_OF_MASK 0x1UL
#define	_TIMER_IFC_OF_DEFAULT 0x00000000UL
#define	TIMER_IFC_OF_DEFAULT (_TIMER_IFC_OF_DEFAULT << 0)
#define	TIMER_IFC_UF (0x1UL << 1)
#define	_TIMER_IFC_UF_SHIFT 1
#define	_TIMER_IFC_UF_MASK 0x2UL
#define	_TIMER_IFC_UF_DEFAULT 0x00000000UL
#define	TIMER_IFC_UF_DEFAULT (_TIMER_IFC_UF_DEFAULT << 1)
#define	TIMER_IFC_CC0 (0x1UL << 4)
#define	_TIMER_IFC_CC0_SHIFT 4
#define	_TIMER_IFC_CC0_MASK 0x10UL
#define	_TIMER_IFC_CC0_DEFAULT 0x00000000UL
#define	TIMER_IFC_CC0_DEFAULT (_TIMER_IFC_CC0_DEFAULT << 4)
#define	TIMER_IFC_CC1 (0x1UL << 5)
#define	_TIMER_IFC_CC1_SHIFT 5
#define	_TIMER_IFC_CC1_MASK 0x20UL
#define	_TIMER_IFC_CC1_DEFAULT 0x00000000UL
#define	TIMER_IFC_CC1_DEFAULT (_TIMER_IFC_CC1_DEFAULT << 5)
#define	TIMER_IFC_CC2 (0x1UL << 6)
#define	_TIMER_IFC_CC2_SHIFT 6
#define	_TIMER_IFC_CC2_MASK 0x40UL
#define	_TIMER_IFC_CC2_DEFAULT 0x00000000UL
#define	TIMER_IFC_CC2_DEFAULT (_TIMER_IFC_CC2_DEFAULT << 6)
#define	TIMER_IFC_ICBOF0 (0x1UL << 8)
#define	_TIMER_IFC_ICBOF0_SHIFT 8
#define	_TIMER_IFC_ICBOF0_MASK 0x100UL
#define	_TIMER_IFC_ICBOF0_DEFAULT 0x00000000UL
#define	TIMER_IFC_ICBOF0_DEFAULT (_TIMER_IFC_ICBOF0_DEFAULT << 8)
#define	TIMER_IFC_ICBOF1 (0x1UL << 9)
#define	_TIMER_IFC_ICBOF1_SHIFT 9
#define	_TIMER_IFC_ICBOF1_MASK 0x200UL
#define	_TIMER_IFC_ICBOF1_DEFAULT 0x00000000UL
#define	TIMER_IFC_ICBOF1_DEFAULT (_TIMER_IFC_ICBOF1_DEFAULT << 9)
#define	TIMER_IFC_ICBOF2 (0x1UL << 10)
#define	_TIMER_IFC_ICBOF2_SHIFT 10
#define	_TIMER_IFC_ICBOF2_MASK 0x400UL
#define	_TIMER_IFC_ICBOF2_DEFAULT 0x00000000UL
#define	TIMER_IFC_ICBOF2_DEFAULT (_TIMER_IFC_ICBOF2_DEFAULT << 10)
#define	_TIMER_TOP_RESETVALUE 0x0000FFFFUL
#define	_TIMER_TOP_MASK 0x0000FFFFUL
#define	_TIMER_TOP_TOP_SHIFT 0
#define	_TIMER_TOP_TOP_MASK 0xFFFFUL
#define	_TIMER_TOP_TOP_DEFAULT 0x0000FFFFUL
#define	TIMER_TOP_TOP_DEFAULT (_TIMER_TOP_TOP_DEFAULT << 0)
#define	_TIMER_TOPB_RESETVALUE 0x00000000UL
#define	_TIMER_TOPB_MASK 0x0000FFFFUL
#define	_TIMER_TOPB_TOPB_SHIFT 0
#define	_TIMER_TOPB_TOPB_MASK 0xFFFFUL
#define	_TIMER_TOPB_TOPB_DEFAULT 0x00000000UL
#define	TIMER_TOPB_TOPB_DEFAULT (_TIMER_TOPB_TOPB_DEFAULT << 0)
#define	_TIMER_CNT_RESETVALUE 0x00000000UL
#define	_TIMER_CNT_MASK 0x0000FFFFUL
#define	_TIMER_CNT_CNT_SHIFT 0
#define	_TIMER_CNT_CNT_MASK 0xFFFFUL
#define	_TIMER_CNT_CNT_DEFAULT 0x00000000UL
#define	TIMER_CNT_CNT_DEFAULT (_TIMER_CNT_CNT_DEFAULT << 0)
#define	_TIMER_ROUTE_RESETVALUE 0x00000000UL
#define	_TIMER_ROUTE_MASK 0x00030707UL
#define	TIMER_ROUTE_CC0PEN (0x1UL << 0)
#define	_TIMER_ROUTE_CC0PEN_SHIFT 0
#define	_TIMER_ROUTE_CC0PEN_MASK 0x1UL
#define	_TIMER_ROUTE_CC0PEN_DEFAULT 0x00000000UL
#define	TIMER_ROUTE_CC0PEN_DEFAULT (_TIMER_ROUTE_CC0PEN_DEFAULT << 0)
#define	TIMER_ROUTE_CC1PEN (0x1UL << 1)
#define	_TIMER_ROUTE_CC1PEN_SHIFT 1
#define	_TIMER_ROUTE_CC1PEN_MASK 0x2UL
#define	_TIMER_ROUTE_CC1PEN_DEFAULT 0x00000000UL
#define	TIMER_ROUTE_CC1PEN_DEFAULT (_TIMER_ROUTE_CC1PEN_DEFAULT << 1)
#define	TIMER_ROUTE_CC2PEN (0x1UL << 2)
#define	_TIMER_ROUTE_CC2PEN_SHIFT 2
#define	_TIMER_ROUTE_CC2PEN_MASK 0x4UL
#define	_TIMER_ROUTE_CC2PEN_DEFAULT 0x00000000UL
#define	TIMER_ROUTE_CC2PEN_DEFAULT (_TIMER_ROUTE_CC2PEN_DEFAULT << 2)
#define	TIMER_ROUTE_CDTI0PEN (0x1UL << 8)
#define	_TIMER_ROUTE_CDTI0PEN_SHIFT 8
#define	_TIMER_ROUTE_CDTI0PEN_MASK 0x100UL
#define	_TIMER_ROUTE_CDTI0PEN_DEFAULT 0x00000000UL
#define	TIMER_ROUTE_CDTI0PEN_DEFAULT (_TIMER_ROUTE_CDTI0PEN_DEFAULT << 8)
#define	TIMER_ROUTE_CDTI1PEN (0x1UL << 9)
#define	_TIMER_ROUTE_CDTI1PEN_SHIFT 9
#define	_TIMER_ROUTE_CDTI1PEN_MASK 0x200UL
#define	_TIMER_ROUTE_CDTI1PEN_DEFAULT 0x00000000UL
#define	TIMER_ROUTE_CDTI1PEN_DEFAULT (_TIMER_ROUTE_CDTI1PEN_DEFAULT << 9)
#define	TIMER_ROUTE_CDTI2PEN (0x1UL << 10)
#define	_TIMER_ROUTE_CDTI2PEN_SHIFT 10
#define	_TIMER_ROUTE_CDTI2PEN_MASK 0x400UL
#define	_TIMER_ROUTE_CDTI2PEN_DEFAULT 0x00000000UL
#define	TIMER_ROUTE_CDTI2PEN_DEFAULT (_TIMER_ROUTE_CDTI2PEN_DEFAULT << 10)
#define	_TIMER_ROUTE_LOCATION_SHIFT 16
#define	_TIMER_ROUTE_LOCATION_MASK 0x30000UL
#define	_TIMER_ROUTE_LOCATION_DEFAULT 0x00000000UL
#define	_TIMER_ROUTE_LOCATION_LOC0 0x00000000UL
#define	_TIMER_ROUTE_LOCATION_LOC1 0x00000001UL
#define	_TIMER_ROUTE_LOCATION_LOC2 0x00000002UL
#define	_TIMER_ROUTE_LOCATION_LOC3 0x00000003UL
#define	TIMER_ROUTE_LOCATION_DEFAULT (_TIMER_ROUTE_LOCATION_DEFAULT << 16)
#define	TIMER_ROUTE_LOCATION_LOC0 (_TIMER_ROUTE_LOCATION_LOC0 << 16)
#define	TIMER_ROUTE_LOCATION_LOC1 (_TIMER_ROUTE_LOCATION_LOC1 << 16)
#define	TIMER_ROUTE_LOCATION_LOC2 (_TIMER_ROUTE_LOCATION_LOC2 << 16)
#define	TIMER_ROUTE_LOCATION_LOC3 (_TIMER_ROUTE_LOCATION_LOC3 << 16)
#define	_TIMER_CC_CTRL_RESETVALUE 0x00000000UL
#define	_TIMER_CC_CTRL_MASK 0x0F373F17UL
#define	_TIMER_CC_CTRL_MODE_SHIFT 0
#define	_TIMER_CC_CTRL_MODE_MASK 0x3UL
#define	_TIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL
#define	_TIMER_CC_CTRL_MODE_OFF 0x00000000UL
#define	_TIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL
#define	_TIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL
#define	_TIMER_CC_CTRL_MODE_PWM 0x00000003UL
#define	TIMER_CC_CTRL_MODE_DEFAULT (_TIMER_CC_CTRL_MODE_DEFAULT << 0)
#define	TIMER_CC_CTRL_MODE_OFF (_TIMER_CC_CTRL_MODE_OFF << 0)
#define	TIMER_CC_CTRL_MODE_INPUTCAPTURE (_TIMER_CC_CTRL_MODE_INPUTCAPTURE << 0)
#define	TIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_TIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0)
#define	TIMER_CC_CTRL_MODE_PWM (_TIMER_CC_CTRL_MODE_PWM << 0)
#define	TIMER_CC_CTRL_OUTINV (0x1UL << 2)
#define	_TIMER_CC_CTRL_OUTINV_SHIFT 2
#define	_TIMER_CC_CTRL_OUTINV_MASK 0x4UL
#define	_TIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL
#define	TIMER_CC_CTRL_OUTINV_DEFAULT (_TIMER_CC_CTRL_OUTINV_DEFAULT << 2)
#define	TIMER_CC_CTRL_COIST (0x1UL << 4)
#define	_TIMER_CC_CTRL_COIST_SHIFT 4
#define	_TIMER_CC_CTRL_COIST_MASK 0x10UL
#define	_TIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL
#define	TIMER_CC_CTRL_COIST_DEFAULT (_TIMER_CC_CTRL_COIST_DEFAULT << 4)
#define	_TIMER_CC_CTRL_CMOA_SHIFT 8
#define	_TIMER_CC_CTRL_CMOA_MASK 0x300UL
#define	_TIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL
#define	_TIMER_CC_CTRL_CMOA_NONE 0x00000000UL
#define	_TIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL
#define	_TIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL
#define	_TIMER_CC_CTRL_CMOA_SET 0x00000003UL
#define	TIMER_CC_CTRL_CMOA_DEFAULT (_TIMER_CC_CTRL_CMOA_DEFAULT << 8)
#define	TIMER_CC_CTRL_CMOA_NONE (_TIMER_CC_CTRL_CMOA_NONE << 8)
#define	TIMER_CC_CTRL_CMOA_TOGGLE (_TIMER_CC_CTRL_CMOA_TOGGLE << 8)
#define	TIMER_CC_CTRL_CMOA_CLEAR (_TIMER_CC_CTRL_CMOA_CLEAR << 8)
#define	TIMER_CC_CTRL_CMOA_SET (_TIMER_CC_CTRL_CMOA_SET << 8)
#define	_TIMER_CC_CTRL_COFOA_SHIFT 10
#define	_TIMER_CC_CTRL_COFOA_MASK 0xC00UL
#define	_TIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL
#define	_TIMER_CC_CTRL_COFOA_NONE 0x00000000UL
#define	_TIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL
#define	_TIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL
#define	_TIMER_CC_CTRL_COFOA_SET 0x00000003UL
#define	TIMER_CC_CTRL_COFOA_DEFAULT (_TIMER_CC_CTRL_COFOA_DEFAULT << 10)
#define	TIMER_CC_CTRL_COFOA_NONE (_TIMER_CC_CTRL_COFOA_NONE << 10)
#define	TIMER_CC_CTRL_COFOA_TOGGLE (_TIMER_CC_CTRL_COFOA_TOGGLE << 10)
#define	TIMER_CC_CTRL_COFOA_CLEAR (_TIMER_CC_CTRL_COFOA_CLEAR << 10)
#define	TIMER_CC_CTRL_COFOA_SET (_TIMER_CC_CTRL_COFOA_SET << 10)
#define	_TIMER_CC_CTRL_CUFOA_SHIFT 12
#define	_TIMER_CC_CTRL_CUFOA_MASK 0x3000UL
#define	_TIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL
#define	_TIMER_CC_CTRL_CUFOA_NONE 0x00000000UL
#define	_TIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL
#define	_TIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL
#define	_TIMER_CC_CTRL_CUFOA_SET 0x00000003UL
#define	TIMER_CC_CTRL_CUFOA_DEFAULT (_TIMER_CC_CTRL_CUFOA_DEFAULT << 12)
#define	TIMER_CC_CTRL_CUFOA_NONE (_TIMER_CC_CTRL_CUFOA_NONE << 12)
#define	TIMER_CC_CTRL_CUFOA_TOGGLE (_TIMER_CC_CTRL_CUFOA_TOGGLE << 12)
#define	TIMER_CC_CTRL_CUFOA_CLEAR (_TIMER_CC_CTRL_CUFOA_CLEAR << 12)
#define	TIMER_CC_CTRL_CUFOA_SET (_TIMER_CC_CTRL_CUFOA_SET << 12)
#define	_TIMER_CC_CTRL_PRSSEL_SHIFT 16
#define	_TIMER_CC_CTRL_PRSSEL_MASK 0x70000UL
#define	_TIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL
#define	_TIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL
#define	_TIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL
#define	_TIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL
#define	_TIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL
#define	_TIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL
#define	_TIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL
#define	_TIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL
#define	_TIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL
#define	TIMER_CC_CTRL_PRSSEL_DEFAULT (_TIMER_CC_CTRL_PRSSEL_DEFAULT << 16)
#define	TIMER_CC_CTRL_PRSSEL_PRSCH0 (_TIMER_CC_CTRL_PRSSEL_PRSCH0 << 16)
#define	TIMER_CC_CTRL_PRSSEL_PRSCH1 (_TIMER_CC_CTRL_PRSSEL_PRSCH1 << 16)
#define	TIMER_CC_CTRL_PRSSEL_PRSCH2 (_TIMER_CC_CTRL_PRSSEL_PRSCH2 << 16)
#define	TIMER_CC_CTRL_PRSSEL_PRSCH3 (_TIMER_CC_CTRL_PRSSEL_PRSCH3 << 16)
#define	TIMER_CC_CTRL_PRSSEL_PRSCH4 (_TIMER_CC_CTRL_PRSSEL_PRSCH4 << 16)
#define	TIMER_CC_CTRL_PRSSEL_PRSCH5 (_TIMER_CC_CTRL_PRSSEL_PRSCH5 << 16)
#define	TIMER_CC_CTRL_PRSSEL_PRSCH6 (_TIMER_CC_CTRL_PRSSEL_PRSCH6 << 16)
#define	TIMER_CC_CTRL_PRSSEL_PRSCH7 (_TIMER_CC_CTRL_PRSSEL_PRSCH7 << 16)
#define	TIMER_CC_CTRL_INSEL (0x1UL << 20)
#define	_TIMER_CC_CTRL_INSEL_SHIFT 20
#define	_TIMER_CC_CTRL_INSEL_MASK 0x100000UL
#define	_TIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL
#define	_TIMER_CC_CTRL_INSEL_PIN 0x00000000UL
#define	_TIMER_CC_CTRL_INSEL_PRS 0x00000001UL
#define	TIMER_CC_CTRL_INSEL_DEFAULT (_TIMER_CC_CTRL_INSEL_DEFAULT << 20)
#define	TIMER_CC_CTRL_INSEL_PIN (_TIMER_CC_CTRL_INSEL_PIN << 20)
#define	TIMER_CC_CTRL_INSEL_PRS (_TIMER_CC_CTRL_INSEL_PRS << 20)
#define	TIMER_CC_CTRL_FILT (0x1UL << 21)
#define	_TIMER_CC_CTRL_FILT_SHIFT 21
#define	_TIMER_CC_CTRL_FILT_MASK 0x200000UL
#define	_TIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL
#define	_TIMER_CC_CTRL_FILT_DISABLE 0x00000000UL
#define	_TIMER_CC_CTRL_FILT_ENABLE 0x00000001UL
#define	TIMER_CC_CTRL_FILT_DEFAULT (_TIMER_CC_CTRL_FILT_DEFAULT << 21)
#define	TIMER_CC_CTRL_FILT_DISABLE (_TIMER_CC_CTRL_FILT_DISABLE << 21)
#define	TIMER_CC_CTRL_FILT_ENABLE (_TIMER_CC_CTRL_FILT_ENABLE << 21)
#define	_TIMER_CC_CTRL_ICEDGE_SHIFT 24
#define	_TIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL
#define	_TIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL
#define	_TIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL
#define	_TIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL
#define	_TIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL
#define	_TIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL
#define	TIMER_CC_CTRL_ICEDGE_DEFAULT (_TIMER_CC_CTRL_ICEDGE_DEFAULT << 24)
#define	TIMER_CC_CTRL_ICEDGE_RISING (_TIMER_CC_CTRL_ICEDGE_RISING << 24)
#define	TIMER_CC_CTRL_ICEDGE_FALLING (_TIMER_CC_CTRL_ICEDGE_FALLING << 24)
#define	TIMER_CC_CTRL_ICEDGE_BOTH (_TIMER_CC_CTRL_ICEDGE_BOTH << 24)
#define	TIMER_CC_CTRL_ICEDGE_NONE (_TIMER_CC_CTRL_ICEDGE_NONE << 24)
#define	_TIMER_CC_CTRL_ICEVCTRL_SHIFT 26
#define	_TIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL
#define	_TIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL
#define	_TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL
#define	_TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL
#define	_TIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL
#define	_TIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL
#define	TIMER_CC_CTRL_ICEVCTRL_DEFAULT (_TIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26)
#define	TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26)
#define	TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26)
#define	TIMER_CC_CTRL_ICEVCTRL_RISING (_TIMER_CC_CTRL_ICEVCTRL_RISING << 26)
#define	TIMER_CC_CTRL_ICEVCTRL_FALLING (_TIMER_CC_CTRL_ICEVCTRL_FALLING << 26)
#define	_TIMER_CC_CCV_RESETVALUE 0x00000000UL
#define	_TIMER_CC_CCV_MASK 0x0000FFFFUL
#define	_TIMER_CC_CCV_CCV_SHIFT 0
#define	_TIMER_CC_CCV_CCV_MASK 0xFFFFUL
#define	_TIMER_CC_CCV_CCV_DEFAULT 0x00000000UL
#define	TIMER_CC_CCV_CCV_DEFAULT (_TIMER_CC_CCV_CCV_DEFAULT << 0)
#define	_TIMER_CC_CCVP_RESETVALUE 0x00000000UL
#define	_TIMER_CC_CCVP_MASK 0x0000FFFFUL
#define	_TIMER_CC_CCVP_CCVP_SHIFT 0
#define	_TIMER_CC_CCVP_CCVP_MASK 0xFFFFUL
#define	_TIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL
#define	TIMER_CC_CCVP_CCVP_DEFAULT (_TIMER_CC_CCVP_CCVP_DEFAULT << 0)
#define	_TIMER_CC_CCVB_RESETVALUE 0x00000000UL
#define	_TIMER_CC_CCVB_MASK 0x0000FFFFUL
#define	_TIMER_CC_CCVB_CCVB_SHIFT 0
#define	_TIMER_CC_CCVB_CCVB_MASK 0xFFFFUL
#define	_TIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL
#define	TIMER_CC_CCVB_CCVB_DEFAULT (_TIMER_CC_CCVB_CCVB_DEFAULT << 0)
#define	_TIMER_DTCTRL_RESETVALUE 0x00000000UL
#define	_TIMER_DTCTRL_MASK 0x0100007FUL
#define	TIMER_DTCTRL_DTEN (0x1UL << 0)
#define	_TIMER_DTCTRL_DTEN_SHIFT 0
#define	_TIMER_DTCTRL_DTEN_MASK 0x1UL
#define	_TIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL
#define	TIMER_DTCTRL_DTEN_DEFAULT (_TIMER_DTCTRL_DTEN_DEFAULT << 0)
#define	TIMER_DTCTRL_DTDAS (0x1UL << 1)
#define	_TIMER_DTCTRL_DTDAS_SHIFT 1
#define	_TIMER_DTCTRL_DTDAS_MASK 0x2UL
#define	_TIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL
#define	_TIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL
#define	_TIMER_DTCTRL_DTDAS_RESTART 0x00000001UL
#define	TIMER_DTCTRL_DTDAS_DEFAULT (_TIMER_DTCTRL_DTDAS_DEFAULT << 1)
#define	TIMER_DTCTRL_DTDAS_NORESTART (_TIMER_DTCTRL_DTDAS_NORESTART << 1)
#define	TIMER_DTCTRL_DTDAS_RESTART (_TIMER_DTCTRL_DTDAS_RESTART << 1)
#define	TIMER_DTCTRL_DTIPOL (0x1UL << 2)
#define	_TIMER_DTCTRL_DTIPOL_SHIFT 2
#define	_TIMER_DTCTRL_DTIPOL_MASK 0x4UL
#define	_TIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL
#define	TIMER_DTCTRL_DTIPOL_DEFAULT (_TIMER_DTCTRL_DTIPOL_DEFAULT << 2)
#define	TIMER_DTCTRL_DTCINV (0x1UL << 3)
#define	_TIMER_DTCTRL_DTCINV_SHIFT 3
#define	_TIMER_DTCTRL_DTCINV_MASK 0x8UL
#define	_TIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL
#define	TIMER_DTCTRL_DTCINV_DEFAULT (_TIMER_DTCTRL_DTCINV_DEFAULT << 3)
#define	_TIMER_DTCTRL_DTPRSSEL_SHIFT 4
#define	_TIMER_DTCTRL_DTPRSSEL_MASK 0x70UL
#define	_TIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL
#define	_TIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL
#define	_TIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL
#define	_TIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL
#define	_TIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL
#define	_TIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL
#define	_TIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL
#define	_TIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL
#define	_TIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL
#define	TIMER_DTCTRL_DTPRSSEL_DEFAULT (_TIMER_DTCTRL_DTPRSSEL_DEFAULT << 4)
#define	TIMER_DTCTRL_DTPRSSEL_PRSCH0 (_TIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4)
#define	TIMER_DTCTRL_DTPRSSEL_PRSCH1 (_TIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4)
#define	TIMER_DTCTRL_DTPRSSEL_PRSCH2 (_TIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4)
#define	TIMER_DTCTRL_DTPRSSEL_PRSCH3 (_TIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4)
#define	TIMER_DTCTRL_DTPRSSEL_PRSCH4 (_TIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4)
#define	TIMER_DTCTRL_DTPRSSEL_PRSCH5 (_TIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4)
#define	TIMER_DTCTRL_DTPRSSEL_PRSCH6 (_TIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4)
#define	TIMER_DTCTRL_DTPRSSEL_PRSCH7 (_TIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4)
#define	TIMER_DTCTRL_DTPRSEN (0x1UL << 24)
#define	_TIMER_DTCTRL_DTPRSEN_SHIFT 24
#define	_TIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL
#define	_TIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL
#define	TIMER_DTCTRL_DTPRSEN_DEFAULT (_TIMER_DTCTRL_DTPRSEN_DEFAULT << 24)
#define	_TIMER_DTTIME_RESETVALUE 0x00000000UL
#define	_TIMER_DTTIME_MASK 0x003F3F0FUL
#define	_TIMER_DTTIME_DTPRESC_SHIFT 0
#define	_TIMER_DTTIME_DTPRESC_MASK 0xFUL
#define	_TIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL
#define	_TIMER_DTTIME_DTPRESC_DIV1 0x00000000UL
#define	_TIMER_DTTIME_DTPRESC_DIV2 0x00000001UL
#define	_TIMER_DTTIME_DTPRESC_DIV4 0x00000002UL
#define	_TIMER_DTTIME_DTPRESC_DIV8 0x00000003UL
#define	_TIMER_DTTIME_DTPRESC_DIV16 0x00000004UL
#define	_TIMER_DTTIME_DTPRESC_DIV32 0x00000005UL
#define	_TIMER_DTTIME_DTPRESC_DIV64 0x00000006UL
#define	_TIMER_DTTIME_DTPRESC_DIV128 0x00000007UL
#define	_TIMER_DTTIME_DTPRESC_DIV256 0x00000008UL
#define	_TIMER_DTTIME_DTPRESC_DIV512 0x00000009UL
#define	_TIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL
#define	TIMER_DTTIME_DTPRESC_DEFAULT (_TIMER_DTTIME_DTPRESC_DEFAULT << 0)
#define	TIMER_DTTIME_DTPRESC_DIV1 (_TIMER_DTTIME_DTPRESC_DIV1 << 0)
#define	TIMER_DTTIME_DTPRESC_DIV2 (_TIMER_DTTIME_DTPRESC_DIV2 << 0)
#define	TIMER_DTTIME_DTPRESC_DIV4 (_TIMER_DTTIME_DTPRESC_DIV4 << 0)
#define	TIMER_DTTIME_DTPRESC_DIV8 (_TIMER_DTTIME_DTPRESC_DIV8 << 0)
#define	TIMER_DTTIME_DTPRESC_DIV16 (_TIMER_DTTIME_DTPRESC_DIV16 << 0)
#define	TIMER_DTTIME_DTPRESC_DIV32 (_TIMER_DTTIME_DTPRESC_DIV32 << 0)
#define	TIMER_DTTIME_DTPRESC_DIV64 (_TIMER_DTTIME_DTPRESC_DIV64 << 0)
#define	TIMER_DTTIME_DTPRESC_DIV128 (_TIMER_DTTIME_DTPRESC_DIV128 << 0)
#define	TIMER_DTTIME_DTPRESC_DIV256 (_TIMER_DTTIME_DTPRESC_DIV256 << 0)
#define	TIMER_DTTIME_DTPRESC_DIV512 (_TIMER_DTTIME_DTPRESC_DIV512 << 0)
#define	TIMER_DTTIME_DTPRESC_DIV1024 (_TIMER_DTTIME_DTPRESC_DIV1024 << 0)
#define	_TIMER_DTTIME_DTRISET_SHIFT 8
#define	_TIMER_DTTIME_DTRISET_MASK 0x3F00UL
#define	_TIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL
#define	TIMER_DTTIME_DTRISET_DEFAULT (_TIMER_DTTIME_DTRISET_DEFAULT << 8)
#define	_TIMER_DTTIME_DTFALLT_SHIFT 16
#define	_TIMER_DTTIME_DTFALLT_MASK 0x3F0000UL
#define	_TIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL
#define	TIMER_DTTIME_DTFALLT_DEFAULT (_TIMER_DTTIME_DTFALLT_DEFAULT << 16)
#define	_TIMER_DTFC_RESETVALUE 0x00000000UL
#define	_TIMER_DTFC_MASK 0x0F030707UL
#define	_TIMER_DTFC_DTPRS0FSEL_SHIFT 0
#define	_TIMER_DTFC_DTPRS0FSEL_MASK 0x7UL
#define	_TIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL
#define	_TIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL
#define	_TIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL
#define	_TIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL
#define	_TIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL
#define	_TIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL
#define	_TIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL
#define	_TIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL
#define	_TIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL
#define	TIMER_DTFC_DTPRS0FSEL_DEFAULT (_TIMER_DTFC_DTPRS0FSEL_DEFAULT << 0)
#define	TIMER_DTFC_DTPRS0FSEL_PRSCH0 (_TIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0)
#define	TIMER_DTFC_DTPRS0FSEL_PRSCH1 (_TIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0)
#define	TIMER_DTFC_DTPRS0FSEL_PRSCH2 (_TIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0)
#define	TIMER_DTFC_DTPRS0FSEL_PRSCH3 (_TIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0)
#define	TIMER_DTFC_DTPRS0FSEL_PRSCH4 (_TIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0)
#define	TIMER_DTFC_DTPRS0FSEL_PRSCH5 (_TIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0)
#define	TIMER_DTFC_DTPRS0FSEL_PRSCH6 (_TIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0)
#define	TIMER_DTFC_DTPRS0FSEL_PRSCH7 (_TIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0)
#define	_TIMER_DTFC_DTPRS1FSEL_SHIFT 8
#define	_TIMER_DTFC_DTPRS1FSEL_MASK 0x700UL
#define	_TIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL
#define	_TIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL
#define	_TIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL
#define	_TIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL
#define	_TIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL
#define	_TIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL
#define	_TIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL
#define	_TIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL
#define	_TIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL
#define	TIMER_DTFC_DTPRS1FSEL_DEFAULT (_TIMER_DTFC_DTPRS1FSEL_DEFAULT << 8)
#define	TIMER_DTFC_DTPRS1FSEL_PRSCH0 (_TIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8)
#define	TIMER_DTFC_DTPRS1FSEL_PRSCH1 (_TIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8)
#define	TIMER_DTFC_DTPRS1FSEL_PRSCH2 (_TIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8)
#define	TIMER_DTFC_DTPRS1FSEL_PRSCH3 (_TIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8)
#define	TIMER_DTFC_DTPRS1FSEL_PRSCH4 (_TIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8)
#define	TIMER_DTFC_DTPRS1FSEL_PRSCH5 (_TIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8)
#define	TIMER_DTFC_DTPRS1FSEL_PRSCH6 (_TIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8)
#define	TIMER_DTFC_DTPRS1FSEL_PRSCH7 (_TIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8)
#define	_TIMER_DTFC_DTFA_SHIFT 16
#define	_TIMER_DTFC_DTFA_MASK 0x30000UL
#define	_TIMER_DTFC_DTFA_DEFAULT 0x00000000UL
#define	_TIMER_DTFC_DTFA_NONE 0x00000000UL
#define	_TIMER_DTFC_DTFA_INACTIVE 0x00000001UL
#define	_TIMER_DTFC_DTFA_CLEAR 0x00000002UL
#define	_TIMER_DTFC_DTFA_TRISTATE 0x00000003UL
#define	TIMER_DTFC_DTFA_DEFAULT (_TIMER_DTFC_DTFA_DEFAULT << 16)
#define	TIMER_DTFC_DTFA_NONE (_TIMER_DTFC_DTFA_NONE << 16)
#define	TIMER_DTFC_DTFA_INACTIVE (_TIMER_DTFC_DTFA_INACTIVE << 16)
#define	TIMER_DTFC_DTFA_CLEAR (_TIMER_DTFC_DTFA_CLEAR << 16)
#define	TIMER_DTFC_DTFA_TRISTATE (_TIMER_DTFC_DTFA_TRISTATE << 16)
#define	TIMER_DTFC_DTPRS0FEN (0x1UL << 24)
#define	_TIMER_DTFC_DTPRS0FEN_SHIFT 24
#define	_TIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL
#define	_TIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL
#define	TIMER_DTFC_DTPRS0FEN_DEFAULT (_TIMER_DTFC_DTPRS0FEN_DEFAULT << 24)
#define	TIMER_DTFC_DTPRS1FEN (0x1UL << 25)
#define	_TIMER_DTFC_DTPRS1FEN_SHIFT 25
#define	_TIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL
#define	_TIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL
#define	TIMER_DTFC_DTPRS1FEN_DEFAULT (_TIMER_DTFC_DTPRS1FEN_DEFAULT << 25)
#define	TIMER_DTFC_DTDBGFEN (0x1UL << 26)
#define	_TIMER_DTFC_DTDBGFEN_SHIFT 26
#define	_TIMER_DTFC_DTDBGFEN_MASK 0x4000000UL
#define	_TIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL
#define	TIMER_DTFC_DTDBGFEN_DEFAULT (_TIMER_DTFC_DTDBGFEN_DEFAULT << 26)
#define	TIMER_DTFC_DTLOCKUPFEN (0x1UL << 27)
#define	_TIMER_DTFC_DTLOCKUPFEN_SHIFT 27
#define	_TIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL
#define	_TIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL
#define	TIMER_DTFC_DTLOCKUPFEN_DEFAULT (_TIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27)
#define	_TIMER_DTOGEN_RESETVALUE 0x00000000UL
#define	_TIMER_DTOGEN_MASK 0x0000003FUL
#define	TIMER_DTOGEN_DTOGCC0EN (0x1UL << 0)
#define	_TIMER_DTOGEN_DTOGCC0EN_SHIFT 0
#define	_TIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL
#define	_TIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL
#define	TIMER_DTOGEN_DTOGCC0EN_DEFAULT (_TIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0)
#define	TIMER_DTOGEN_DTOGCC1EN (0x1UL << 1)
#define	_TIMER_DTOGEN_DTOGCC1EN_SHIFT 1
#define	_TIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL
#define	_TIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL
#define	TIMER_DTOGEN_DTOGCC1EN_DEFAULT (_TIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1)
#define	TIMER_DTOGEN_DTOGCC2EN (0x1UL << 2)
#define	_TIMER_DTOGEN_DTOGCC2EN_SHIFT 2
#define	_TIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL
#define	_TIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL
#define	TIMER_DTOGEN_DTOGCC2EN_DEFAULT (_TIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2)
#define	TIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3)
#define	_TIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3
#define	_TIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL
#define	_TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL
#define	TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3)
#define	TIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4)
#define	_TIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4
#define	_TIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL
#define	_TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL
#define	TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4)
#define	TIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5)
#define	_TIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5
#define	_TIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL
#define	_TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL
#define	TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5)
#define	_TIMER_DTFAULT_RESETVALUE 0x00000000UL
#define	_TIMER_DTFAULT_MASK 0x0000000FUL
#define	TIMER_DTFAULT_DTPRS0F (0x1UL << 0)
#define	_TIMER_DTFAULT_DTPRS0F_SHIFT 0
#define	_TIMER_DTFAULT_DTPRS0F_MASK 0x1UL
#define	_TIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL
#define	TIMER_DTFAULT_DTPRS0F_DEFAULT (_TIMER_DTFAULT_DTPRS0F_DEFAULT << 0)
#define	TIMER_DTFAULT_DTPRS1F (0x1UL << 1)
#define	_TIMER_DTFAULT_DTPRS1F_SHIFT 1
#define	_TIMER_DTFAULT_DTPRS1F_MASK 0x2UL
#define	_TIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL
#define	TIMER_DTFAULT_DTPRS1F_DEFAULT (_TIMER_DTFAULT_DTPRS1F_DEFAULT << 1)
#define	TIMER_DTFAULT_DTDBGF (0x1UL << 2)
#define	_TIMER_DTFAULT_DTDBGF_SHIFT 2
#define	_TIMER_DTFAULT_DTDBGF_MASK 0x4UL
#define	_TIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL
#define	TIMER_DTFAULT_DTDBGF_DEFAULT (_TIMER_DTFAULT_DTDBGF_DEFAULT << 2)
#define	TIMER_DTFAULT_DTLOCKUPF (0x1UL << 3)
#define	_TIMER_DTFAULT_DTLOCKUPF_SHIFT 3
#define	_TIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL
#define	_TIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL
#define	TIMER_DTFAULT_DTLOCKUPF_DEFAULT (_TIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3)
#define	_TIMER_DTFAULTC_RESETVALUE 0x00000000UL
#define	_TIMER_DTFAULTC_MASK 0x0000000FUL
#define	TIMER_DTFAULTC_DTPRS0FC (0x1UL << 0)
#define	_TIMER_DTFAULTC_DTPRS0FC_SHIFT 0
#define	_TIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL
#define	_TIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL
#define	TIMER_DTFAULTC_DTPRS0FC_DEFAULT (_TIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0)
#define	TIMER_DTFAULTC_DTPRS1FC (0x1UL << 1)
#define	_TIMER_DTFAULTC_DTPRS1FC_SHIFT 1
#define	_TIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL
#define	_TIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL
#define	TIMER_DTFAULTC_DTPRS1FC_DEFAULT (_TIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1)
#define	TIMER_DTFAULTC_DTDBGFC (0x1UL << 2)
#define	_TIMER_DTFAULTC_DTDBGFC_SHIFT 2
#define	_TIMER_DTFAULTC_DTDBGFC_MASK 0x4UL
#define	_TIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL
#define	TIMER_DTFAULTC_DTDBGFC_DEFAULT (_TIMER_DTFAULTC_DTDBGFC_DEFAULT << 2)
#define	TIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3)
#define	_TIMER_DTFAULTC_TLOCKUPFC_SHIFT 3
#define	_TIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL
#define	_TIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL
#define	TIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_TIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3)
#define	_TIMER_DTLOCK_RESETVALUE 0x00000000UL
#define	_TIMER_DTLOCK_MASK 0x0000FFFFUL
#define	_TIMER_DTLOCK_LOCKKEY_SHIFT 0
#define	_TIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL
#define	_TIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL
#define	_TIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL
#define	_TIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL
#define	_TIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL
#define	_TIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL
#define	TIMER_DTLOCK_LOCKKEY_DEFAULT (_TIMER_DTLOCK_LOCKKEY_DEFAULT << 0)
#define	TIMER_DTLOCK_LOCKKEY_LOCK (_TIMER_DTLOCK_LOCKKEY_LOCK << 0)
#define	TIMER_DTLOCK_LOCKKEY_UNLOCKED (_TIMER_DTLOCK_LOCKKEY_UNLOCKED << 0)
#define	TIMER_DTLOCK_LOCKKEY_LOCKED (_TIMER_DTLOCK_LOCKKEY_LOCKED << 0)
#define	TIMER_DTLOCK_LOCKKEY_UNLOCK (_TIMER_DTLOCK_LOCKKEY_UNLOCK << 0)
#define	_USART_CTRL_RESETVALUE 0x00000000UL
#define	_USART_CTRL_MASK 0x1DFFFF7FUL
#define	USART_CTRL_SYNC (0x1UL << 0)
#define	_USART_CTRL_SYNC_SHIFT 0
#define	_USART_CTRL_SYNC_MASK 0x1UL
#define	_USART_CTRL_SYNC_DEFAULT 0x00000000UL
#define	USART_CTRL_SYNC_DEFAULT (_USART_CTRL_SYNC_DEFAULT << 0)
#define	USART_CTRL_LOOPBK (0x1UL << 1)
#define	_USART_CTRL_LOOPBK_SHIFT 1
#define	_USART_CTRL_LOOPBK_MASK 0x2UL
#define	_USART_CTRL_LOOPBK_DEFAULT 0x00000000UL
#define	USART_CTRL_LOOPBK_DEFAULT (_USART_CTRL_LOOPBK_DEFAULT << 1)
#define	USART_CTRL_CCEN (0x1UL << 2)
#define	_USART_CTRL_CCEN_SHIFT 2
#define	_USART_CTRL_CCEN_MASK 0x4UL
#define	_USART_CTRL_CCEN_DEFAULT 0x00000000UL
#define	USART_CTRL_CCEN_DEFAULT (_USART_CTRL_CCEN_DEFAULT << 2)
#define	USART_CTRL_MPM (0x1UL << 3)
#define	_USART_CTRL_MPM_SHIFT 3
#define	_USART_CTRL_MPM_MASK 0x8UL
#define	_USART_CTRL_MPM_DEFAULT 0x00000000UL
#define	USART_CTRL_MPM_DEFAULT (_USART_CTRL_MPM_DEFAULT << 3)
#define	USART_CTRL_MPAB (0x1UL << 4)
#define	_USART_CTRL_MPAB_SHIFT 4
#define	_USART_CTRL_MPAB_MASK 0x10UL
#define	_USART_CTRL_MPAB_DEFAULT 0x00000000UL
#define	USART_CTRL_MPAB_DEFAULT (_USART_CTRL_MPAB_DEFAULT << 4)
#define	_USART_CTRL_OVS_SHIFT 5
#define	_USART_CTRL_OVS_MASK 0x60UL
#define	_USART_CTRL_OVS_DEFAULT 0x00000000UL
#define	_USART_CTRL_OVS_X16 0x00000000UL
#define	_USART_CTRL_OVS_X8 0x00000001UL
#define	_USART_CTRL_OVS_X6 0x00000002UL
#define	_USART_CTRL_OVS_X4 0x00000003UL
#define	USART_CTRL_OVS_DEFAULT (_USART_CTRL_OVS_DEFAULT << 5)
#define	USART_CTRL_OVS_X16 (_USART_CTRL_OVS_X16 << 5)
#define	USART_CTRL_OVS_X8 (_USART_CTRL_OVS_X8 << 5)
#define	USART_CTRL_OVS_X6 (_USART_CTRL_OVS_X6 << 5)
#define	USART_CTRL_OVS_X4 (_USART_CTRL_OVS_X4 << 5)
#define	USART_CTRL_CLKPOL (0x1UL << 8)
#define	_USART_CTRL_CLKPOL_SHIFT 8
#define	_USART_CTRL_CLKPOL_MASK 0x100UL
#define	_USART_CTRL_CLKPOL_DEFAULT 0x00000000UL
#define	_USART_CTRL_CLKPOL_IDLELOW 0x00000000UL
#define	_USART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL
#define	USART_CTRL_CLKPOL_DEFAULT (_USART_CTRL_CLKPOL_DEFAULT << 8)
#define	USART_CTRL_CLKPOL_IDLELOW (_USART_CTRL_CLKPOL_IDLELOW << 8)
#define	USART_CTRL_CLKPOL_IDLEHIGH (_USART_CTRL_CLKPOL_IDLEHIGH << 8)
#define	USART_CTRL_CLKPHA (0x1UL << 9)
#define	_USART_CTRL_CLKPHA_SHIFT 9
#define	_USART_CTRL_CLKPHA_MASK 0x200UL
#define	_USART_CTRL_CLKPHA_DEFAULT 0x00000000UL
#define	_USART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL
#define	_USART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL
#define	USART_CTRL_CLKPHA_DEFAULT (_USART_CTRL_CLKPHA_DEFAULT << 9)
#define	USART_CTRL_CLKPHA_SAMPLELEADING (_USART_CTRL_CLKPHA_SAMPLELEADING << 9)
#define	USART_CTRL_CLKPHA_SAMPLETRAILING (_USART_CTRL_CLKPHA_SAMPLETRAILING << 9)
#define	USART_CTRL_MSBF (0x1UL << 10)
#define	_USART_CTRL_MSBF_SHIFT 10
#define	_USART_CTRL_MSBF_MASK 0x400UL
#define	_USART_CTRL_MSBF_DEFAULT 0x00000000UL
#define	USART_CTRL_MSBF_DEFAULT (_USART_CTRL_MSBF_DEFAULT << 10)
#define	USART_CTRL_CSMA (0x1UL << 11)
#define	_USART_CTRL_CSMA_SHIFT 11
#define	_USART_CTRL_CSMA_MASK 0x800UL
#define	_USART_CTRL_CSMA_DEFAULT 0x00000000UL
#define	_USART_CTRL_CSMA_NOACTION 0x00000000UL
#define	_USART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL
#define	USART_CTRL_CSMA_DEFAULT (_USART_CTRL_CSMA_DEFAULT << 11)
#define	USART_CTRL_CSMA_NOACTION (_USART_CTRL_CSMA_NOACTION << 11)
#define	USART_CTRL_CSMA_GOTOSLAVEMODE (_USART_CTRL_CSMA_GOTOSLAVEMODE << 11)
#define	USART_CTRL_TXBIL (0x1UL << 12)
#define	_USART_CTRL_TXBIL_SHIFT 12
#define	_USART_CTRL_TXBIL_MASK 0x1000UL
#define	_USART_CTRL_TXBIL_DEFAULT 0x00000000UL
#define	_USART_CTRL_TXBIL_EMPTY 0x00000000UL
#define	_USART_CTRL_TXBIL_HALFFULL 0x00000001UL
#define	USART_CTRL_TXBIL_DEFAULT (_USART_CTRL_TXBIL_DEFAULT << 12)
#define	USART_CTRL_TXBIL_EMPTY (_USART_CTRL_TXBIL_EMPTY << 12)
#define	USART_CTRL_TXBIL_HALFFULL (_USART_CTRL_TXBIL_HALFFULL << 12)
#define	USART_CTRL_RXINV (0x1UL << 13)
#define	_USART_CTRL_RXINV_SHIFT 13
#define	_USART_CTRL_RXINV_MASK 0x2000UL
#define	_USART_CTRL_RXINV_DEFAULT 0x00000000UL
#define	USART_CTRL_RXINV_DEFAULT (_USART_CTRL_RXINV_DEFAULT << 13)
#define	USART_CTRL_TXINV (0x1UL << 14)
#define	_USART_CTRL_TXINV_SHIFT 14
#define	_USART_CTRL_TXINV_MASK 0x4000UL
#define	_USART_CTRL_TXINV_DEFAULT 0x00000000UL
#define	USART_CTRL_TXINV_DEFAULT (_USART_CTRL_TXINV_DEFAULT << 14)
#define	USART_CTRL_CSINV (0x1UL << 15)
#define	_USART_CTRL_CSINV_SHIFT 15
#define	_USART_CTRL_CSINV_MASK 0x8000UL
#define	_USART_CTRL_CSINV_DEFAULT 0x00000000UL
#define	USART_CTRL_CSINV_DEFAULT (_USART_CTRL_CSINV_DEFAULT << 15)
#define	USART_CTRL_AUTOCS (0x1UL << 16)
#define	_USART_CTRL_AUTOCS_SHIFT 16
#define	_USART_CTRL_AUTOCS_MASK 0x10000UL
#define	_USART_CTRL_AUTOCS_DEFAULT 0x00000000UL
#define	USART_CTRL_AUTOCS_DEFAULT (_USART_CTRL_AUTOCS_DEFAULT << 16)
#define	USART_CTRL_AUTOTRI (0x1UL << 17)
#define	_USART_CTRL_AUTOTRI_SHIFT 17
#define	_USART_CTRL_AUTOTRI_MASK 0x20000UL
#define	_USART_CTRL_AUTOTRI_DEFAULT 0x00000000UL
#define	USART_CTRL_AUTOTRI_DEFAULT (_USART_CTRL_AUTOTRI_DEFAULT << 17)
#define	USART_CTRL_SCMODE (0x1UL << 18)
#define	_USART_CTRL_SCMODE_SHIFT 18
#define	_USART_CTRL_SCMODE_MASK 0x40000UL
#define	_USART_CTRL_SCMODE_DEFAULT 0x00000000UL
#define	USART_CTRL_SCMODE_DEFAULT (_USART_CTRL_SCMODE_DEFAULT << 18)
#define	USART_CTRL_SCRETRANS (0x1UL << 19)
#define	_USART_CTRL_SCRETRANS_SHIFT 19
#define	_USART_CTRL_SCRETRANS_MASK 0x80000UL
#define	_USART_CTRL_SCRETRANS_DEFAULT 0x00000000UL
#define	USART_CTRL_SCRETRANS_DEFAULT (_USART_CTRL_SCRETRANS_DEFAULT << 19)
#define	USART_CTRL_SKIPPERRF (0x1UL << 20)
#define	_USART_CTRL_SKIPPERRF_SHIFT 20
#define	_USART_CTRL_SKIPPERRF_MASK 0x100000UL
#define	_USART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL
#define	USART_CTRL_SKIPPERRF_DEFAULT (_USART_CTRL_SKIPPERRF_DEFAULT << 20)
#define	USART_CTRL_BIT8DV (0x1UL << 21)
#define	_USART_CTRL_BIT8DV_SHIFT 21
#define	_USART_CTRL_BIT8DV_MASK 0x200000UL
#define	_USART_CTRL_BIT8DV_DEFAULT 0x00000000UL
#define	USART_CTRL_BIT8DV_DEFAULT (_USART_CTRL_BIT8DV_DEFAULT << 21)
#define	USART_CTRL_ERRSDMA (0x1UL << 22)
#define	_USART_CTRL_ERRSDMA_SHIFT 22
#define	_USART_CTRL_ERRSDMA_MASK 0x400000UL
#define	_USART_CTRL_ERRSDMA_DEFAULT 0x00000000UL
#define	USART_CTRL_ERRSDMA_DEFAULT (_USART_CTRL_ERRSDMA_DEFAULT << 22)
#define	USART_CTRL_ERRSRX (0x1UL << 23)
#define	_USART_CTRL_ERRSRX_SHIFT 23
#define	_USART_CTRL_ERRSRX_MASK 0x800000UL
#define	_USART_CTRL_ERRSRX_DEFAULT 0x00000000UL
#define	USART_CTRL_ERRSRX_DEFAULT (_USART_CTRL_ERRSRX_DEFAULT << 23)
#define	USART_CTRL_ERRSTX (0x1UL << 24)
#define	_USART_CTRL_ERRSTX_SHIFT 24
#define	_USART_CTRL_ERRSTX_MASK 0x1000000UL
#define	_USART_CTRL_ERRSTX_DEFAULT 0x00000000UL
#define	USART_CTRL_ERRSTX_DEFAULT (_USART_CTRL_ERRSTX_DEFAULT << 24)
#define	_USART_CTRL_TXDELAY_SHIFT 26
#define	_USART_CTRL_TXDELAY_MASK 0xC000000UL
#define	_USART_CTRL_TXDELAY_DEFAULT 0x00000000UL
#define	_USART_CTRL_TXDELAY_NONE 0x00000000UL
#define	_USART_CTRL_TXDELAY_SINGLE 0x00000001UL
#define	_USART_CTRL_TXDELAY_DOUBLE 0x00000002UL
#define	_USART_CTRL_TXDELAY_TRIPLE 0x00000003UL
#define	USART_CTRL_TXDELAY_DEFAULT (_USART_CTRL_TXDELAY_DEFAULT << 26)
#define	USART_CTRL_TXDELAY_NONE (_USART_CTRL_TXDELAY_NONE << 26)
#define	USART_CTRL_TXDELAY_SINGLE (_USART_CTRL_TXDELAY_SINGLE << 26)
#define	USART_CTRL_TXDELAY_DOUBLE (_USART_CTRL_TXDELAY_DOUBLE << 26)
#define	USART_CTRL_TXDELAY_TRIPLE (_USART_CTRL_TXDELAY_TRIPLE << 26)
#define	USART_CTRL_BYTESWAP (0x1UL << 28)
#define	_USART_CTRL_BYTESWAP_SHIFT 28
#define	_USART_CTRL_BYTESWAP_MASK 0x10000000UL
#define	_USART_CTRL_BYTESWAP_DEFAULT 0x00000000UL
#define	USART_CTRL_BYTESWAP_DEFAULT (_USART_CTRL_BYTESWAP_DEFAULT << 28)
#define	_USART_FRAME_RESETVALUE 0x00001005UL
#define	_USART_FRAME_MASK 0x0000330FUL
#define	_USART_FRAME_DATABITS_SHIFT 0
#define	_USART_FRAME_DATABITS_MASK 0xFUL
#define	_USART_FRAME_DATABITS_FOUR 0x00000001UL
#define	_USART_FRAME_DATABITS_FIVE 0x00000002UL
#define	_USART_FRAME_DATABITS_SIX 0x00000003UL
#define	_USART_FRAME_DATABITS_SEVEN 0x00000004UL
#define	_USART_FRAME_DATABITS_DEFAULT 0x00000005UL
#define	_USART_FRAME_DATABITS_EIGHT 0x00000005UL
#define	_USART_FRAME_DATABITS_NINE 0x00000006UL
#define	_USART_FRAME_DATABITS_TEN 0x00000007UL
#define	_USART_FRAME_DATABITS_ELEVEN 0x00000008UL
#define	_USART_FRAME_DATABITS_TWELVE 0x00000009UL
#define	_USART_FRAME_DATABITS_THIRTEEN 0x0000000AUL
#define	_USART_FRAME_DATABITS_FOURTEEN 0x0000000BUL
#define	_USART_FRAME_DATABITS_FIFTEEN 0x0000000CUL
#define	_USART_FRAME_DATABITS_SIXTEEN 0x0000000DUL
#define	USART_FRAME_DATABITS_FOUR (_USART_FRAME_DATABITS_FOUR << 0)
#define	USART_FRAME_DATABITS_FIVE (_USART_FRAME_DATABITS_FIVE << 0)
#define	USART_FRAME_DATABITS_SIX (_USART_FRAME_DATABITS_SIX << 0)
#define	USART_FRAME_DATABITS_SEVEN (_USART_FRAME_DATABITS_SEVEN << 0)
#define	USART_FRAME_DATABITS_DEFAULT (_USART_FRAME_DATABITS_DEFAULT << 0)
#define	USART_FRAME_DATABITS_EIGHT (_USART_FRAME_DATABITS_EIGHT << 0)
#define	USART_FRAME_DATABITS_NINE (_USART_FRAME_DATABITS_NINE << 0)
#define	USART_FRAME_DATABITS_TEN (_USART_FRAME_DATABITS_TEN << 0)
#define	USART_FRAME_DATABITS_ELEVEN (_USART_FRAME_DATABITS_ELEVEN << 0)
#define	USART_FRAME_DATABITS_TWELVE (_USART_FRAME_DATABITS_TWELVE << 0)
#define	USART_FRAME_DATABITS_THIRTEEN (_USART_FRAME_DATABITS_THIRTEEN << 0)
#define	USART_FRAME_DATABITS_FOURTEEN (_USART_FRAME_DATABITS_FOURTEEN << 0)
#define	USART_FRAME_DATABITS_FIFTEEN (_USART_FRAME_DATABITS_FIFTEEN << 0)
#define	USART_FRAME_DATABITS_SIXTEEN (_USART_FRAME_DATABITS_SIXTEEN << 0)
#define	_USART_FRAME_PARITY_SHIFT 8
#define	_USART_FRAME_PARITY_MASK 0x300UL
#define	_USART_FRAME_PARITY_DEFAULT 0x00000000UL
#define	_USART_FRAME_PARITY_NONE 0x00000000UL
#define	_USART_FRAME_PARITY_EVEN 0x00000002UL
#define	_USART_FRAME_PARITY_ODD 0x00000003UL
#define	USART_FRAME_PARITY_DEFAULT (_USART_FRAME_PARITY_DEFAULT << 8)
#define	USART_FRAME_PARITY_NONE (_USART_FRAME_PARITY_NONE << 8)
#define	USART_FRAME_PARITY_EVEN (_USART_FRAME_PARITY_EVEN << 8)
#define	USART_FRAME_PARITY_ODD (_USART_FRAME_PARITY_ODD << 8)
#define	_USART_FRAME_STOPBITS_SHIFT 12
#define	_USART_FRAME_STOPBITS_MASK 0x3000UL
#define	_USART_FRAME_STOPBITS_HALF 0x00000000UL
#define	_USART_FRAME_STOPBITS_DEFAULT 0x00000001UL
#define	_USART_FRAME_STOPBITS_ONE 0x00000001UL
#define	_USART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL
#define	_USART_FRAME_STOPBITS_TWO 0x00000003UL
#define	USART_FRAME_STOPBITS_HALF (_USART_FRAME_STOPBITS_HALF << 12)
#define	USART_FRAME_STOPBITS_DEFAULT (_USART_FRAME_STOPBITS_DEFAULT << 12)
#define	USART_FRAME_STOPBITS_ONE (_USART_FRAME_STOPBITS_ONE << 12)
#define	USART_FRAME_STOPBITS_ONEANDAHALF (_USART_FRAME_STOPBITS_ONEANDAHALF << 12)
#define	USART_FRAME_STOPBITS_TWO (_USART_FRAME_STOPBITS_TWO << 12)
#define	_USART_TRIGCTRL_RESETVALUE 0x00000000UL
#define	_USART_TRIGCTRL_MASK 0x00000037UL
#define	_USART_TRIGCTRL_TSEL_SHIFT 0
#define	_USART_TRIGCTRL_TSEL_MASK 0x7UL
#define	_USART_TRIGCTRL_TSEL_DEFAULT 0x00000000UL
#define	_USART_TRIGCTRL_TSEL_PRSCH0 0x00000000UL
#define	_USART_TRIGCTRL_TSEL_PRSCH1 0x00000001UL
#define	_USART_TRIGCTRL_TSEL_PRSCH2 0x00000002UL
#define	_USART_TRIGCTRL_TSEL_PRSCH3 0x00000003UL
#define	_USART_TRIGCTRL_TSEL_PRSCH4 0x00000004UL
#define	_USART_TRIGCTRL_TSEL_PRSCH5 0x00000005UL
#define	_USART_TRIGCTRL_TSEL_PRSCH6 0x00000006UL
#define	_USART_TRIGCTRL_TSEL_PRSCH7 0x00000007UL
#define	USART_TRIGCTRL_TSEL_DEFAULT (_USART_TRIGCTRL_TSEL_DEFAULT << 0)
#define	USART_TRIGCTRL_TSEL_PRSCH0 (_USART_TRIGCTRL_TSEL_PRSCH0 << 0)
#define	USART_TRIGCTRL_TSEL_PRSCH1 (_USART_TRIGCTRL_TSEL_PRSCH1 << 0)
#define	USART_TRIGCTRL_TSEL_PRSCH2 (_USART_TRIGCTRL_TSEL_PRSCH2 << 0)
#define	USART_TRIGCTRL_TSEL_PRSCH3 (_USART_TRIGCTRL_TSEL_PRSCH3 << 0)
#define	USART_TRIGCTRL_TSEL_PRSCH4 (_USART_TRIGCTRL_TSEL_PRSCH4 << 0)
#define	USART_TRIGCTRL_TSEL_PRSCH5 (_USART_TRIGCTRL_TSEL_PRSCH5 << 0)
#define	USART_TRIGCTRL_TSEL_PRSCH6 (_USART_TRIGCTRL_TSEL_PRSCH6 << 0)
#define	USART_TRIGCTRL_TSEL_PRSCH7 (_USART_TRIGCTRL_TSEL_PRSCH7 << 0)
#define	USART_TRIGCTRL_RXTEN (0x1UL << 4)
#define	_USART_TRIGCTRL_RXTEN_SHIFT 4
#define	_USART_TRIGCTRL_RXTEN_MASK 0x10UL
#define	_USART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL
#define	USART_TRIGCTRL_RXTEN_DEFAULT (_USART_TRIGCTRL_RXTEN_DEFAULT << 4)
#define	USART_TRIGCTRL_TXTEN (0x1UL << 5)
#define	_USART_TRIGCTRL_TXTEN_SHIFT 5
#define	_USART_TRIGCTRL_TXTEN_MASK 0x20UL
#define	_USART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL
#define	USART_TRIGCTRL_TXTEN_DEFAULT (_USART_TRIGCTRL_TXTEN_DEFAULT << 5)
#define	_USART_CMD_RESETVALUE 0x00000000UL
#define	_USART_CMD_MASK 0x00000FFFUL
#define	USART_CMD_RXEN (0x1UL << 0)
#define	_USART_CMD_RXEN_SHIFT 0
#define	_USART_CMD_RXEN_MASK 0x1UL
#define	_USART_CMD_RXEN_DEFAULT 0x00000000UL
#define	USART_CMD_RXEN_DEFAULT (_USART_CMD_RXEN_DEFAULT << 0)
#define	USART_CMD_RXDIS (0x1UL << 1)
#define	_USART_CMD_RXDIS_SHIFT 1
#define	_USART_CMD_RXDIS_MASK 0x2UL
#define	_USART_CMD_RXDIS_DEFAULT 0x00000000UL
#define	USART_CMD_RXDIS_DEFAULT (_USART_CMD_RXDIS_DEFAULT << 1)
#define	USART_CMD_TXEN (0x1UL << 2)
#define	_USART_CMD_TXEN_SHIFT 2
#define	_USART_CMD_TXEN_MASK 0x4UL
#define	_USART_CMD_TXEN_DEFAULT 0x00000000UL
#define	USART_CMD_TXEN_DEFAULT (_USART_CMD_TXEN_DEFAULT << 2)
#define	USART_CMD_TXDIS (0x1UL << 3)
#define	_USART_CMD_TXDIS_SHIFT 3
#define	_USART_CMD_TXDIS_MASK 0x8UL
#define	_USART_CMD_TXDIS_DEFAULT 0x00000000UL
#define	USART_CMD_TXDIS_DEFAULT (_USART_CMD_TXDIS_DEFAULT << 3)
#define	USART_CMD_MASTEREN (0x1UL << 4)
#define	_USART_CMD_MASTEREN_SHIFT 4
#define	_USART_CMD_MASTEREN_MASK 0x10UL
#define	_USART_CMD_MASTEREN_DEFAULT 0x00000000UL
#define	USART_CMD_MASTEREN_DEFAULT (_USART_CMD_MASTEREN_DEFAULT << 4)
#define	USART_CMD_MASTERDIS (0x1UL << 5)
#define	_USART_CMD_MASTERDIS_SHIFT 5
#define	_USART_CMD_MASTERDIS_MASK 0x20UL
#define	_USART_CMD_MASTERDIS_DEFAULT 0x00000000UL
#define	USART_CMD_MASTERDIS_DEFAULT (_USART_CMD_MASTERDIS_DEFAULT << 5)
#define	USART_CMD_RXBLOCKEN (0x1UL << 6)
#define	_USART_CMD_RXBLOCKEN_SHIFT 6
#define	_USART_CMD_RXBLOCKEN_MASK 0x40UL
#define	_USART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL
#define	USART_CMD_RXBLOCKEN_DEFAULT (_USART_CMD_RXBLOCKEN_DEFAULT << 6)
#define	USART_CMD_RXBLOCKDIS (0x1UL << 7)
#define	_USART_CMD_RXBLOCKDIS_SHIFT 7
#define	_USART_CMD_RXBLOCKDIS_MASK 0x80UL
#define	_USART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL
#define	USART_CMD_RXBLOCKDIS_DEFAULT (_USART_CMD_RXBLOCKDIS_DEFAULT << 7)
#define	USART_CMD_TXTRIEN (0x1UL << 8)
#define	_USART_CMD_TXTRIEN_SHIFT 8
#define	_USART_CMD_TXTRIEN_MASK 0x100UL
#define	_USART_CMD_TXTRIEN_DEFAULT 0x00000000UL
#define	USART_CMD_TXTRIEN_DEFAULT (_USART_CMD_TXTRIEN_DEFAULT << 8)
#define	USART_CMD_TXTRIDIS (0x1UL << 9)
#define	_USART_CMD_TXTRIDIS_SHIFT 9
#define	_USART_CMD_TXTRIDIS_MASK 0x200UL
#define	_USART_CMD_TXTRIDIS_DEFAULT 0x00000000UL
#define	USART_CMD_TXTRIDIS_DEFAULT (_USART_CMD_TXTRIDIS_DEFAULT << 9)
#define	USART_CMD_CLEARTX (0x1UL << 10)
#define	_USART_CMD_CLEARTX_SHIFT 10
#define	_USART_CMD_CLEARTX_MASK 0x400UL
#define	_USART_CMD_CLEARTX_DEFAULT 0x00000000UL
#define	USART_CMD_CLEARTX_DEFAULT (_USART_CMD_CLEARTX_DEFAULT << 10)
#define	USART_CMD_CLEARRX (0x1UL << 11)
#define	_USART_CMD_CLEARRX_SHIFT 11
#define	_USART_CMD_CLEARRX_MASK 0x800UL
#define	_USART_CMD_CLEARRX_DEFAULT 0x00000000UL
#define	USART_CMD_CLEARRX_DEFAULT (_USART_CMD_CLEARRX_DEFAULT << 11)
#define	_USART_STATUS_RESETVALUE 0x00000040UL
#define	_USART_STATUS_MASK 0x000001FFUL
#define	USART_STATUS_RXENS (0x1UL << 0)
#define	_USART_STATUS_RXENS_SHIFT 0
#define	_USART_STATUS_RXENS_MASK 0x1UL
#define	_USART_STATUS_RXENS_DEFAULT 0x00000000UL
#define	USART_STATUS_RXENS_DEFAULT (_USART_STATUS_RXENS_DEFAULT << 0)
#define	USART_STATUS_TXENS (0x1UL << 1)
#define	_USART_STATUS_TXENS_SHIFT 1
#define	_USART_STATUS_TXENS_MASK 0x2UL
#define	_USART_STATUS_TXENS_DEFAULT 0x00000000UL
#define	USART_STATUS_TXENS_DEFAULT (_USART_STATUS_TXENS_DEFAULT << 1)
#define	USART_STATUS_MASTER (0x1UL << 2)
#define	_USART_STATUS_MASTER_SHIFT 2
#define	_USART_STATUS_MASTER_MASK 0x4UL
#define	_USART_STATUS_MASTER_DEFAULT 0x00000000UL
#define	USART_STATUS_MASTER_DEFAULT (_USART_STATUS_MASTER_DEFAULT << 2)
#define	USART_STATUS_RXBLOCK (0x1UL << 3)
#define	_USART_STATUS_RXBLOCK_SHIFT 3
#define	_USART_STATUS_RXBLOCK_MASK 0x8UL
#define	_USART_STATUS_RXBLOCK_DEFAULT 0x00000000UL
#define	USART_STATUS_RXBLOCK_DEFAULT (_USART_STATUS_RXBLOCK_DEFAULT << 3)
#define	USART_STATUS_TXTRI (0x1UL << 4)
#define	_USART_STATUS_TXTRI_SHIFT 4
#define	_USART_STATUS_TXTRI_MASK 0x10UL
#define	_USART_STATUS_TXTRI_DEFAULT 0x00000000UL
#define	USART_STATUS_TXTRI_DEFAULT (_USART_STATUS_TXTRI_DEFAULT << 4)
#define	USART_STATUS_TXC (0x1UL << 5)
#define	_USART_STATUS_TXC_SHIFT 5
#define	_USART_STATUS_TXC_MASK 0x20UL
#define	_USART_STATUS_TXC_DEFAULT 0x00000000UL
#define	USART_STATUS_TXC_DEFAULT (_USART_STATUS_TXC_DEFAULT << 5)
#define	USART_STATUS_TXBL (0x1UL << 6)
#define	_USART_STATUS_TXBL_SHIFT 6
#define	_USART_STATUS_TXBL_MASK 0x40UL
#define	_USART_STATUS_TXBL_DEFAULT 0x00000001UL
#define	USART_STATUS_TXBL_DEFAULT (_USART_STATUS_TXBL_DEFAULT << 6)
#define	USART_STATUS_RXDATAV (0x1UL << 7)
#define	_USART_STATUS_RXDATAV_SHIFT 7
#define	_USART_STATUS_RXDATAV_MASK 0x80UL
#define	_USART_STATUS_RXDATAV_DEFAULT 0x00000000UL
#define	USART_STATUS_RXDATAV_DEFAULT (_USART_STATUS_RXDATAV_DEFAULT << 7)
#define	USART_STATUS_RXFULL (0x1UL << 8)
#define	_USART_STATUS_RXFULL_SHIFT 8
#define	_USART_STATUS_RXFULL_MASK 0x100UL
#define	_USART_STATUS_RXFULL_DEFAULT 0x00000000UL
#define	USART_STATUS_RXFULL_DEFAULT (_USART_STATUS_RXFULL_DEFAULT << 8)
#define	_USART_CLKDIV_RESETVALUE 0x00000000UL
#define	_USART_CLKDIV_MASK 0x001FFFC0UL
#define	_USART_CLKDIV_DIV_SHIFT 6
#define	_USART_CLKDIV_DIV_MASK 0x1FFFC0UL
#define	_USART_CLKDIV_DIV_DEFAULT 0x00000000UL
#define	USART_CLKDIV_DIV_DEFAULT (_USART_CLKDIV_DIV_DEFAULT << 6)
#define	_USART_RXDATAX_RESETVALUE 0x00000000UL
#define	_USART_RXDATAX_MASK 0x0000C1FFUL
#define	_USART_RXDATAX_RXDATA_SHIFT 0
#define	_USART_RXDATAX_RXDATA_MASK 0x1FFUL
#define	_USART_RXDATAX_RXDATA_DEFAULT 0x00000000UL
#define	USART_RXDATAX_RXDATA_DEFAULT (_USART_RXDATAX_RXDATA_DEFAULT << 0)
#define	USART_RXDATAX_PERR (0x1UL << 14)
#define	_USART_RXDATAX_PERR_SHIFT 14
#define	_USART_RXDATAX_PERR_MASK 0x4000UL
#define	_USART_RXDATAX_PERR_DEFAULT 0x00000000UL
#define	USART_RXDATAX_PERR_DEFAULT (_USART_RXDATAX_PERR_DEFAULT << 14)
#define	USART_RXDATAX_FERR (0x1UL << 15)
#define	_USART_RXDATAX_FERR_SHIFT 15
#define	_USART_RXDATAX_FERR_MASK 0x8000UL
#define	_USART_RXDATAX_FERR_DEFAULT 0x00000000UL
#define	USART_RXDATAX_FERR_DEFAULT (_USART_RXDATAX_FERR_DEFAULT << 15)
#define	_USART_RXDATA_RESETVALUE 0x00000000UL
#define	_USART_RXDATA_MASK 0x000000FFUL
#define	_USART_RXDATA_RXDATA_SHIFT 0
#define	_USART_RXDATA_RXDATA_MASK 0xFFUL
#define	_USART_RXDATA_RXDATA_DEFAULT 0x00000000UL
#define	USART_RXDATA_RXDATA_DEFAULT (_USART_RXDATA_RXDATA_DEFAULT << 0)
#define	_USART_RXDOUBLEX_RESETVALUE 0x00000000UL
#define	_USART_RXDOUBLEX_MASK 0xC1FFC1FFUL
#define	_USART_RXDOUBLEX_RXDATA0_SHIFT 0
#define	_USART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL
#define	_USART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL
#define	USART_RXDOUBLEX_RXDATA0_DEFAULT (_USART_RXDOUBLEX_RXDATA0_DEFAULT << 0)
#define	USART_RXDOUBLEX_PERR0 (0x1UL << 14)
#define	_USART_RXDOUBLEX_PERR0_SHIFT 14
#define	_USART_RXDOUBLEX_PERR0_MASK 0x4000UL
#define	_USART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL
#define	USART_RXDOUBLEX_PERR0_DEFAULT (_USART_RXDOUBLEX_PERR0_DEFAULT << 14)
#define	USART_RXDOUBLEX_FERR0 (0x1UL << 15)
#define	_USART_RXDOUBLEX_FERR0_SHIFT 15
#define	_USART_RXDOUBLEX_FERR0_MASK 0x8000UL
#define	_USART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL
#define	USART_RXDOUBLEX_FERR0_DEFAULT (_USART_RXDOUBLEX_FERR0_DEFAULT << 15)
#define	_USART_RXDOUBLEX_RXDATA1_SHIFT 16
#define	_USART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL
#define	_USART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL
#define	USART_RXDOUBLEX_RXDATA1_DEFAULT (_USART_RXDOUBLEX_RXDATA1_DEFAULT << 16)
#define	USART_RXDOUBLEX_PERR1 (0x1UL << 30)
#define	_USART_RXDOUBLEX_PERR1_SHIFT 30
#define	_USART_RXDOUBLEX_PERR1_MASK 0x40000000UL
#define	_USART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL
#define	USART_RXDOUBLEX_PERR1_DEFAULT (_USART_RXDOUBLEX_PERR1_DEFAULT << 30)
#define	USART_RXDOUBLEX_FERR1 (0x1UL << 31)
#define	_USART_RXDOUBLEX_FERR1_SHIFT 31
#define	_USART_RXDOUBLEX_FERR1_MASK 0x80000000UL
#define	_USART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL
#define	USART_RXDOUBLEX_FERR1_DEFAULT (_USART_RXDOUBLEX_FERR1_DEFAULT << 31)
#define	_USART_RXDOUBLE_RESETVALUE 0x00000000UL
#define	_USART_RXDOUBLE_MASK 0x0000FFFFUL
#define	_USART_RXDOUBLE_RXDATA0_SHIFT 0
#define	_USART_RXDOUBLE_RXDATA0_MASK 0xFFUL
#define	_USART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL
#define	USART_RXDOUBLE_RXDATA0_DEFAULT (_USART_RXDOUBLE_RXDATA0_DEFAULT << 0)
#define	_USART_RXDOUBLE_RXDATA1_SHIFT 8
#define	_USART_RXDOUBLE_RXDATA1_MASK 0xFF00UL
#define	_USART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL
#define	USART_RXDOUBLE_RXDATA1_DEFAULT (_USART_RXDOUBLE_RXDATA1_DEFAULT << 8)
#define	_USART_RXDATAXP_RESETVALUE 0x00000000UL
#define	_USART_RXDATAXP_MASK 0x0000C1FFUL
#define	_USART_RXDATAXP_RXDATAP_SHIFT 0
#define	_USART_RXDATAXP_RXDATAP_MASK 0x1FFUL
#define	_USART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL
#define	USART_RXDATAXP_RXDATAP_DEFAULT (_USART_RXDATAXP_RXDATAP_DEFAULT << 0)
#define	USART_RXDATAXP_PERRP (0x1UL << 14)
#define	_USART_RXDATAXP_PERRP_SHIFT 14
#define	_USART_RXDATAXP_PERRP_MASK 0x4000UL
#define	_USART_RXDATAXP_PERRP_DEFAULT 0x00000000UL
#define	USART_RXDATAXP_PERRP_DEFAULT (_USART_RXDATAXP_PERRP_DEFAULT << 14)
#define	USART_RXDATAXP_FERRP (0x1UL << 15)
#define	_USART_RXDATAXP_FERRP_SHIFT 15
#define	_USART_RXDATAXP_FERRP_MASK 0x8000UL
#define	_USART_RXDATAXP_FERRP_DEFAULT 0x00000000UL
#define	USART_RXDATAXP_FERRP_DEFAULT (_USART_RXDATAXP_FERRP_DEFAULT << 15)
#define	_USART_RXDOUBLEXP_RESETVALUE 0x00000000UL
#define	_USART_RXDOUBLEXP_MASK 0xC1FFC1FFUL
#define	_USART_RXDOUBLEXP_RXDATAP0_SHIFT 0
#define	_USART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL
#define	_USART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL
#define	USART_RXDOUBLEXP_RXDATAP0_DEFAULT (_USART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0)
#define	USART_RXDOUBLEXP_PERRP0 (0x1UL << 14)
#define	_USART_RXDOUBLEXP_PERRP0_SHIFT 14
#define	_USART_RXDOUBLEXP_PERRP0_MASK 0x4000UL
#define	_USART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL
#define	USART_RXDOUBLEXP_PERRP0_DEFAULT (_USART_RXDOUBLEXP_PERRP0_DEFAULT << 14)
#define	USART_RXDOUBLEXP_FERRP0 (0x1UL << 15)
#define	_USART_RXDOUBLEXP_FERRP0_SHIFT 15
#define	_USART_RXDOUBLEXP_FERRP0_MASK 0x8000UL
#define	_USART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL
#define	USART_RXDOUBLEXP_FERRP0_DEFAULT (_USART_RXDOUBLEXP_FERRP0_DEFAULT << 15)
#define	_USART_RXDOUBLEXP_RXDATAP1_SHIFT 16
#define	_USART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL
#define	_USART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL
#define	USART_RXDOUBLEXP_RXDATAP1_DEFAULT (_USART_RXDOUBLEXP_RXDATAP1_DEFAULT << 16)
#define	USART_RXDOUBLEXP_PERRP1 (0x1UL << 30)
#define	_USART_RXDOUBLEXP_PERRP1_SHIFT 30
#define	_USART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL
#define	_USART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL
#define	USART_RXDOUBLEXP_PERRP1_DEFAULT (_USART_RXDOUBLEXP_PERRP1_DEFAULT << 30)
#define	USART_RXDOUBLEXP_FERRP1 (0x1UL << 31)
#define	_USART_RXDOUBLEXP_FERRP1_SHIFT 31
#define	_USART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL
#define	_USART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL
#define	USART_RXDOUBLEXP_FERRP1_DEFAULT (_USART_RXDOUBLEXP_FERRP1_DEFAULT << 31)
#define	_USART_TXDATAX_RESETVALUE 0x00000000UL
#define	_USART_TXDATAX_MASK 0x0000F9FFUL
#define	_USART_TXDATAX_TXDATAX_SHIFT 0
#define	_USART_TXDATAX_TXDATAX_MASK 0x1FFUL
#define	_USART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL
#define	USART_TXDATAX_TXDATAX_DEFAULT (_USART_TXDATAX_TXDATAX_DEFAULT << 0)
#define	USART_TXDATAX_UBRXAT (0x1UL << 11)
#define	_USART_TXDATAX_UBRXAT_SHIFT 11
#define	_USART_TXDATAX_UBRXAT_MASK 0x800UL
#define	_USART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL
#define	USART_TXDATAX_UBRXAT_DEFAULT (_USART_TXDATAX_UBRXAT_DEFAULT << 11)
#define	USART_TXDATAX_TXTRIAT (0x1UL << 12)
#define	_USART_TXDATAX_TXTRIAT_SHIFT 12
#define	_USART_TXDATAX_TXTRIAT_MASK 0x1000UL
#define	_USART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL
#define	USART_TXDATAX_TXTRIAT_DEFAULT (_USART_TXDATAX_TXTRIAT_DEFAULT << 12)
#define	USART_TXDATAX_TXBREAK (0x1UL << 13)
#define	_USART_TXDATAX_TXBREAK_SHIFT 13
#define	_USART_TXDATAX_TXBREAK_MASK 0x2000UL
#define	_USART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL
#define	USART_TXDATAX_TXBREAK_DEFAULT (_USART_TXDATAX_TXBREAK_DEFAULT << 13)
#define	USART_TXDATAX_TXDISAT (0x1UL << 14)
#define	_USART_TXDATAX_TXDISAT_SHIFT 14
#define	_USART_TXDATAX_TXDISAT_MASK 0x4000UL
#define	_USART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL
#define	USART_TXDATAX_TXDISAT_DEFAULT (_USART_TXDATAX_TXDISAT_DEFAULT << 14)
#define	USART_TXDATAX_RXENAT (0x1UL << 15)
#define	_USART_TXDATAX_RXENAT_SHIFT 15
#define	_USART_TXDATAX_RXENAT_MASK 0x8000UL
#define	_USART_TXDATAX_RXENAT_DEFAULT 0x00000000UL
#define	USART_TXDATAX_RXENAT_DEFAULT (_USART_TXDATAX_RXENAT_DEFAULT << 15)
#define	_USART_TXDATA_RESETVALUE 0x00000000UL
#define	_USART_TXDATA_MASK 0x000000FFUL
#define	_USART_TXDATA_TXDATA_SHIFT 0
#define	_USART_TXDATA_TXDATA_MASK 0xFFUL
#define	_USART_TXDATA_TXDATA_DEFAULT 0x00000000UL
#define	USART_TXDATA_TXDATA_DEFAULT (_USART_TXDATA_TXDATA_DEFAULT << 0)
#define	_USART_TXDOUBLEX_RESETVALUE 0x00000000UL
#define	_USART_TXDOUBLEX_MASK 0xF9FFF9FFUL
#define	_USART_TXDOUBLEX_TXDATA0_SHIFT 0
#define	_USART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL
#define	_USART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL
#define	USART_TXDOUBLEX_TXDATA0_DEFAULT (_USART_TXDOUBLEX_TXDATA0_DEFAULT << 0)
#define	USART_TXDOUBLEX_UBRXAT0 (0x1UL << 11)
#define	_USART_TXDOUBLEX_UBRXAT0_SHIFT 11
#define	_USART_TXDOUBLEX_UBRXAT0_MASK 0x800UL
#define	_USART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL
#define	USART_TXDOUBLEX_UBRXAT0_DEFAULT (_USART_TXDOUBLEX_UBRXAT0_DEFAULT << 11)
#define	USART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12)
#define	_USART_TXDOUBLEX_TXTRIAT0_SHIFT 12
#define	_USART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL
#define	_USART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL
#define	USART_TXDOUBLEX_TXTRIAT0_DEFAULT (_USART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12)
#define	USART_TXDOUBLEX_TXBREAK0 (0x1UL << 13)
#define	_USART_TXDOUBLEX_TXBREAK0_SHIFT 13
#define	_USART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL
#define	_USART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL
#define	USART_TXDOUBLEX_TXBREAK0_DEFAULT (_USART_TXDOUBLEX_TXBREAK0_DEFAULT << 13)
#define	USART_TXDOUBLEX_TXDISAT0 (0x1UL << 14)
#define	_USART_TXDOUBLEX_TXDISAT0_SHIFT 14
#define	_USART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL
#define	_USART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL
#define	USART_TXDOUBLEX_TXDISAT0_DEFAULT (_USART_TXDOUBLEX_TXDISAT0_DEFAULT << 14)
#define	USART_TXDOUBLEX_RXENAT0 (0x1UL << 15)
#define	_USART_TXDOUBLEX_RXENAT0_SHIFT 15
#define	_USART_TXDOUBLEX_RXENAT0_MASK 0x8000UL
#define	_USART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL
#define	USART_TXDOUBLEX_RXENAT0_DEFAULT (_USART_TXDOUBLEX_RXENAT0_DEFAULT << 15)
#define	_USART_TXDOUBLEX_TXDATA1_SHIFT 16
#define	_USART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL
#define	_USART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL
#define	USART_TXDOUBLEX_TXDATA1_DEFAULT (_USART_TXDOUBLEX_TXDATA1_DEFAULT << 16)
#define	USART_TXDOUBLEX_UBRXAT1 (0x1UL << 27)
#define	_USART_TXDOUBLEX_UBRXAT1_SHIFT 27
#define	_USART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL
#define	_USART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL
#define	USART_TXDOUBLEX_UBRXAT1_DEFAULT (_USART_TXDOUBLEX_UBRXAT1_DEFAULT << 27)
#define	USART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28)
#define	_USART_TXDOUBLEX_TXTRIAT1_SHIFT 28
#define	_USART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL
#define	_USART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL
#define	USART_TXDOUBLEX_TXTRIAT1_DEFAULT (_USART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28)
#define	USART_TXDOUBLEX_TXBREAK1 (0x1UL << 29)
#define	_USART_TXDOUBLEX_TXBREAK1_SHIFT 29
#define	_USART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL
#define	_USART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL
#define	USART_TXDOUBLEX_TXBREAK1_DEFAULT (_USART_TXDOUBLEX_TXBREAK1_DEFAULT << 29)
#define	USART_TXDOUBLEX_TXDISAT1 (0x1UL << 30)
#define	_USART_TXDOUBLEX_TXDISAT1_SHIFT 30
#define	_USART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL
#define	_USART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL
#define	USART_TXDOUBLEX_TXDISAT1_DEFAULT (_USART_TXDOUBLEX_TXDISAT1_DEFAULT << 30)
#define	USART_TXDOUBLEX_RXENAT1 (0x1UL << 31)
#define	_USART_TXDOUBLEX_RXENAT1_SHIFT 31
#define	_USART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL
#define	_USART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL
#define	USART_TXDOUBLEX_RXENAT1_DEFAULT (_USART_TXDOUBLEX_RXENAT1_DEFAULT << 31)
#define	_USART_TXDOUBLE_RESETVALUE 0x00000000UL
#define	_USART_TXDOUBLE_MASK 0x0000FFFFUL
#define	_USART_TXDOUBLE_TXDATA0_SHIFT 0
#define	_USART_TXDOUBLE_TXDATA0_MASK 0xFFUL
#define	_USART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL
#define	USART_TXDOUBLE_TXDATA0_DEFAULT (_USART_TXDOUBLE_TXDATA0_DEFAULT << 0)
#define	_USART_TXDOUBLE_TXDATA1_SHIFT 8
#define	_USART_TXDOUBLE_TXDATA1_MASK 0xFF00UL
#define	_USART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL
#define	USART_TXDOUBLE_TXDATA1_DEFAULT (_USART_TXDOUBLE_TXDATA1_DEFAULT << 8)
#define	_USART_IF_RESETVALUE 0x00000002UL
#define	_USART_IF_MASK 0x00001FFFUL
#define	USART_IF_TXC (0x1UL << 0)
#define	_USART_IF_TXC_SHIFT 0
#define	_USART_IF_TXC_MASK 0x1UL
#define	_USART_IF_TXC_DEFAULT 0x00000000UL
#define	USART_IF_TXC_DEFAULT (_USART_IF_TXC_DEFAULT << 0)
#define	USART_IF_TXBL (0x1UL << 1)
#define	_USART_IF_TXBL_SHIFT 1
#define	_USART_IF_TXBL_MASK 0x2UL
#define	_USART_IF_TXBL_DEFAULT 0x00000001UL
#define	USART_IF_TXBL_DEFAULT (_USART_IF_TXBL_DEFAULT << 1)
#define	USART_IF_RXDATAV (0x1UL << 2)
#define	_USART_IF_RXDATAV_SHIFT 2
#define	_USART_IF_RXDATAV_MASK 0x4UL
#define	_USART_IF_RXDATAV_DEFAULT 0x00000000UL
#define	USART_IF_RXDATAV_DEFAULT (_USART_IF_RXDATAV_DEFAULT << 2)
#define	USART_IF_RXFULL (0x1UL << 3)
#define	_USART_IF_RXFULL_SHIFT 3
#define	_USART_IF_RXFULL_MASK 0x8UL
#define	_USART_IF_RXFULL_DEFAULT 0x00000000UL
#define	USART_IF_RXFULL_DEFAULT (_USART_IF_RXFULL_DEFAULT << 3)
#define	USART_IF_RXOF (0x1UL << 4)
#define	_USART_IF_RXOF_SHIFT 4
#define	_USART_IF_RXOF_MASK 0x10UL
#define	_USART_IF_RXOF_DEFAULT 0x00000000UL
#define	USART_IF_RXOF_DEFAULT (_USART_IF_RXOF_DEFAULT << 4)
#define	USART_IF_RXUF (0x1UL << 5)
#define	_USART_IF_RXUF_SHIFT 5
#define	_USART_IF_RXUF_MASK 0x20UL
#define	_USART_IF_RXUF_DEFAULT 0x00000000UL
#define	USART_IF_RXUF_DEFAULT (_USART_IF_RXUF_DEFAULT << 5)
#define	USART_IF_TXOF (0x1UL << 6)
#define	_USART_IF_TXOF_SHIFT 6
#define	_USART_IF_TXOF_MASK 0x40UL
#define	_USART_IF_TXOF_DEFAULT 0x00000000UL
#define	USART_IF_TXOF_DEFAULT (_USART_IF_TXOF_DEFAULT << 6)
#define	USART_IF_TXUF (0x1UL << 7)
#define	_USART_IF_TXUF_SHIFT 7
#define	_USART_IF_TXUF_MASK 0x80UL
#define	_USART_IF_TXUF_DEFAULT 0x00000000UL
#define	USART_IF_TXUF_DEFAULT (_USART_IF_TXUF_DEFAULT << 7)
#define	USART_IF_PERR (0x1UL << 8)
#define	_USART_IF_PERR_SHIFT 8
#define	_USART_IF_PERR_MASK 0x100UL
#define	_USART_IF_PERR_DEFAULT 0x00000000UL
#define	USART_IF_PERR_DEFAULT (_USART_IF_PERR_DEFAULT << 8)
#define	USART_IF_FERR (0x1UL << 9)
#define	_USART_IF_FERR_SHIFT 9
#define	_USART_IF_FERR_MASK 0x200UL
#define	_USART_IF_FERR_DEFAULT 0x00000000UL
#define	USART_IF_FERR_DEFAULT (_USART_IF_FERR_DEFAULT << 9)
#define	USART_IF_MPAF (0x1UL << 10)
#define	_USART_IF_MPAF_SHIFT 10
#define	_USART_IF_MPAF_MASK 0x400UL
#define	_USART_IF_MPAF_DEFAULT 0x00000000UL
#define	USART_IF_MPAF_DEFAULT (_USART_IF_MPAF_DEFAULT << 10)
#define	USART_IF_SSM (0x1UL << 11)
#define	_USART_IF_SSM_SHIFT 11
#define	_USART_IF_SSM_MASK 0x800UL
#define	_USART_IF_SSM_DEFAULT 0x00000000UL
#define	USART_IF_SSM_DEFAULT (_USART_IF_SSM_DEFAULT << 11)
#define	USART_IF_CCF (0x1UL << 12)
#define	_USART_IF_CCF_SHIFT 12
#define	_USART_IF_CCF_MASK 0x1000UL
#define	_USART_IF_CCF_DEFAULT 0x00000000UL
#define	USART_IF_CCF_DEFAULT (_USART_IF_CCF_DEFAULT << 12)
#define	_USART_IFS_RESETVALUE 0x00000000UL
#define	_USART_IFS_MASK 0x00001FF9UL
#define	USART_IFS_TXC (0x1UL << 0)
#define	_USART_IFS_TXC_SHIFT 0
#define	_USART_IFS_TXC_MASK 0x1UL
#define	_USART_IFS_TXC_DEFAULT 0x00000000UL
#define	USART_IFS_TXC_DEFAULT (_USART_IFS_TXC_DEFAULT << 0)
#define	USART_IFS_RXFULL (0x1UL << 3)
#define	_USART_IFS_RXFULL_SHIFT 3
#define	_USART_IFS_RXFULL_MASK 0x8UL
#define	_USART_IFS_RXFULL_DEFAULT 0x00000000UL
#define	USART_IFS_RXFULL_DEFAULT (_USART_IFS_RXFULL_DEFAULT << 3)
#define	USART_IFS_RXOF (0x1UL << 4)
#define	_USART_IFS_RXOF_SHIFT 4
#define	_USART_IFS_RXOF_MASK 0x10UL
#define	_USART_IFS_RXOF_DEFAULT 0x00000000UL
#define	USART_IFS_RXOF_DEFAULT (_USART_IFS_RXOF_DEFAULT << 4)
#define	USART_IFS_RXUF (0x1UL << 5)
#define	_USART_IFS_RXUF_SHIFT 5
#define	_USART_IFS_RXUF_MASK 0x20UL
#define	_USART_IFS_RXUF_DEFAULT 0x00000000UL
#define	USART_IFS_RXUF_DEFAULT (_USART_IFS_RXUF_DEFAULT << 5)
#define	USART_IFS_TXOF (0x1UL << 6)
#define	_USART_IFS_TXOF_SHIFT 6
#define	_USART_IFS_TXOF_MASK 0x40UL
#define	_USART_IFS_TXOF_DEFAULT 0x00000000UL
#define	USART_IFS_TXOF_DEFAULT (_USART_IFS_TXOF_DEFAULT << 6)
#define	USART_IFS_TXUF (0x1UL << 7)
#define	_USART_IFS_TXUF_SHIFT 7
#define	_USART_IFS_TXUF_MASK 0x80UL
#define	_USART_IFS_TXUF_DEFAULT 0x00000000UL
#define	USART_IFS_TXUF_DEFAULT (_USART_IFS_TXUF_DEFAULT << 7)
#define	USART_IFS_PERR (0x1UL << 8)
#define	_USART_IFS_PERR_SHIFT 8
#define	_USART_IFS_PERR_MASK 0x100UL
#define	_USART_IFS_PERR_DEFAULT 0x00000000UL
#define	USART_IFS_PERR_DEFAULT (_USART_IFS_PERR_DEFAULT << 8)
#define	USART_IFS_FERR (0x1UL << 9)
#define	_USART_IFS_FERR_SHIFT 9
#define	_USART_IFS_FERR_MASK 0x200UL
#define	_USART_IFS_FERR_DEFAULT 0x00000000UL
#define	USART_IFS_FERR_DEFAULT (_USART_IFS_FERR_DEFAULT << 9)
#define	USART_IFS_MPAF (0x1UL << 10)
#define	_USART_IFS_MPAF_SHIFT 10
#define	_USART_IFS_MPAF_MASK 0x400UL
#define	_USART_IFS_MPAF_DEFAULT 0x00000000UL
#define	USART_IFS_MPAF_DEFAULT (_USART_IFS_MPAF_DEFAULT << 10)
#define	USART_IFS_SSM (0x1UL << 11)
#define	_USART_IFS_SSM_SHIFT 11
#define	_USART_IFS_SSM_MASK 0x800UL
#define	_USART_IFS_SSM_DEFAULT 0x00000000UL
#define	USART_IFS_SSM_DEFAULT (_USART_IFS_SSM_DEFAULT << 11)
#define	USART_IFS_CCF (0x1UL << 12)
#define	_USART_IFS_CCF_SHIFT 12
#define	_USART_IFS_CCF_MASK 0x1000UL
#define	_USART_IFS_CCF_DEFAULT 0x00000000UL
#define	USART_IFS_CCF_DEFAULT (_USART_IFS_CCF_DEFAULT << 12)
#define	_USART_IFC_RESETVALUE 0x00000000UL
#define	_USART_IFC_MASK 0x00001FF9UL
#define	USART_IFC_TXC (0x1UL << 0)
#define	_USART_IFC_TXC_SHIFT 0
#define	_USART_IFC_TXC_MASK 0x1UL
#define	_USART_IFC_TXC_DEFAULT 0x00000000UL
#define	USART_IFC_TXC_DEFAULT (_USART_IFC_TXC_DEFAULT << 0)
#define	USART_IFC_RXFULL (0x1UL << 3)
#define	_USART_IFC_RXFULL_SHIFT 3
#define	_USART_IFC_RXFULL_MASK 0x8UL
#define	_USART_IFC_RXFULL_DEFAULT 0x00000000UL
#define	USART_IFC_RXFULL_DEFAULT (_USART_IFC_RXFULL_DEFAULT << 3)
#define	USART_IFC_RXOF (0x1UL << 4)
#define	_USART_IFC_RXOF_SHIFT 4
#define	_USART_IFC_RXOF_MASK 0x10UL
#define	_USART_IFC_RXOF_DEFAULT 0x00000000UL
#define	USART_IFC_RXOF_DEFAULT (_USART_IFC_RXOF_DEFAULT << 4)
#define	USART_IFC_RXUF (0x1UL << 5)
#define	_USART_IFC_RXUF_SHIFT 5
#define	_USART_IFC_RXUF_MASK 0x20UL
#define	_USART_IFC_RXUF_DEFAULT 0x00000000UL
#define	USART_IFC_RXUF_DEFAULT (_USART_IFC_RXUF_DEFAULT << 5)
#define	USART_IFC_TXOF (0x1UL << 6)
#define	_USART_IFC_TXOF_SHIFT 6
#define	_USART_IFC_TXOF_MASK 0x40UL
#define	_USART_IFC_TXOF_DEFAULT 0x00000000UL
#define	USART_IFC_TXOF_DEFAULT (_USART_IFC_TXOF_DEFAULT << 6)
#define	USART_IFC_TXUF (0x1UL << 7)
#define	_USART_IFC_TXUF_SHIFT 7
#define	_USART_IFC_TXUF_MASK 0x80UL
#define	_USART_IFC_TXUF_DEFAULT 0x00000000UL
#define	USART_IFC_TXUF_DEFAULT (_USART_IFC_TXUF_DEFAULT << 7)
#define	USART_IFC_PERR (0x1UL << 8)
#define	_USART_IFC_PERR_SHIFT 8
#define	_USART_IFC_PERR_MASK 0x100UL
#define	_USART_IFC_PERR_DEFAULT 0x00000000UL
#define	USART_IFC_PERR_DEFAULT (_USART_IFC_PERR_DEFAULT << 8)
#define	USART_IFC_FERR (0x1UL << 9)
#define	_USART_IFC_FERR_SHIFT 9
#define	_USART_IFC_FERR_MASK 0x200UL
#define	_USART_IFC_FERR_DEFAULT 0x00000000UL
#define	USART_IFC_FERR_DEFAULT (_USART_IFC_FERR_DEFAULT << 9)
#define	USART_IFC_MPAF (0x1UL << 10)
#define	_USART_IFC_MPAF_SHIFT 10
#define	_USART_IFC_MPAF_MASK 0x400UL
#define	_USART_IFC_MPAF_DEFAULT 0x00000000UL
#define	USART_IFC_MPAF_DEFAULT (_USART_IFC_MPAF_DEFAULT << 10)
#define	USART_IFC_SSM (0x1UL << 11)
#define	_USART_IFC_SSM_SHIFT 11
#define	_USART_IFC_SSM_MASK 0x800UL
#define	_USART_IFC_SSM_DEFAULT 0x00000000UL
#define	USART_IFC_SSM_DEFAULT (_USART_IFC_SSM_DEFAULT << 11)
#define	USART_IFC_CCF (0x1UL << 12)
#define	_USART_IFC_CCF_SHIFT 12
#define	_USART_IFC_CCF_MASK 0x1000UL
#define	_USART_IFC_CCF_DEFAULT 0x00000000UL
#define	USART_IFC_CCF_DEFAULT (_USART_IFC_CCF_DEFAULT << 12)
#define	_USART_IEN_RESETVALUE 0x00000000UL
#define	_USART_IEN_MASK 0x00001FFFUL
#define	USART_IEN_TXC (0x1UL << 0)
#define	_USART_IEN_TXC_SHIFT 0
#define	_USART_IEN_TXC_MASK 0x1UL
#define	_USART_IEN_TXC_DEFAULT 0x00000000UL
#define	USART_IEN_TXC_DEFAULT (_USART_IEN_TXC_DEFAULT << 0)
#define	USART_IEN_TXBL (0x1UL << 1)
#define	_USART_IEN_TXBL_SHIFT 1
#define	_USART_IEN_TXBL_MASK 0x2UL
#define	_USART_IEN_TXBL_DEFAULT 0x00000000UL
#define	USART_IEN_TXBL_DEFAULT (_USART_IEN_TXBL_DEFAULT << 1)
#define	USART_IEN_RXDATAV (0x1UL << 2)
#define	_USART_IEN_RXDATAV_SHIFT 2
#define	_USART_IEN_RXDATAV_MASK 0x4UL
#define	_USART_IEN_RXDATAV_DEFAULT 0x00000000UL
#define	USART_IEN_RXDATAV_DEFAULT (_USART_IEN_RXDATAV_DEFAULT << 2)
#define	USART_IEN_RXFULL (0x1UL << 3)
#define	_USART_IEN_RXFULL_SHIFT 3
#define	_USART_IEN_RXFULL_MASK 0x8UL
#define	_USART_IEN_RXFULL_DEFAULT 0x00000000UL
#define	USART_IEN_RXFULL_DEFAULT (_USART_IEN_RXFULL_DEFAULT << 3)
#define	USART_IEN_RXOF (0x1UL << 4)
#define	_USART_IEN_RXOF_SHIFT 4
#define	_USART_IEN_RXOF_MASK 0x10UL
#define	_USART_IEN_RXOF_DEFAULT 0x00000000UL
#define	USART_IEN_RXOF_DEFAULT (_USART_IEN_RXOF_DEFAULT << 4)
#define	USART_IEN_RXUF (0x1UL << 5)
#define	_USART_IEN_RXUF_SHIFT 5
#define	_USART_IEN_RXUF_MASK 0x20UL
#define	_USART_IEN_RXUF_DEFAULT 0x00000000UL
#define	USART_IEN_RXUF_DEFAULT (_USART_IEN_RXUF_DEFAULT << 5)
#define	USART_IEN_TXOF (0x1UL << 6)
#define	_USART_IEN_TXOF_SHIFT 6
#define	_USART_IEN_TXOF_MASK 0x40UL
#define	_USART_IEN_TXOF_DEFAULT 0x00000000UL
#define	USART_IEN_TXOF_DEFAULT (_USART_IEN_TXOF_DEFAULT << 6)
#define	USART_IEN_TXUF (0x1UL << 7)
#define	_USART_IEN_TXUF_SHIFT 7
#define	_USART_IEN_TXUF_MASK 0x80UL
#define	_USART_IEN_TXUF_DEFAULT 0x00000000UL
#define	USART_IEN_TXUF_DEFAULT (_USART_IEN_TXUF_DEFAULT << 7)
#define	USART_IEN_PERR (0x1UL << 8)
#define	_USART_IEN_PERR_SHIFT 8
#define	_USART_IEN_PERR_MASK 0x100UL
#define	_USART_IEN_PERR_DEFAULT 0x00000000UL
#define	USART_IEN_PERR_DEFAULT (_USART_IEN_PERR_DEFAULT << 8)
#define	USART_IEN_FERR (0x1UL << 9)
#define	_USART_IEN_FERR_SHIFT 9
#define	_USART_IEN_FERR_MASK 0x200UL
#define	_USART_IEN_FERR_DEFAULT 0x00000000UL
#define	USART_IEN_FERR_DEFAULT (_USART_IEN_FERR_DEFAULT << 9)
#define	USART_IEN_MPAF (0x1UL << 10)
#define	_USART_IEN_MPAF_SHIFT 10
#define	_USART_IEN_MPAF_MASK 0x400UL
#define	_USART_IEN_MPAF_DEFAULT 0x00000000UL
#define	USART_IEN_MPAF_DEFAULT (_USART_IEN_MPAF_DEFAULT << 10)
#define	USART_IEN_SSM (0x1UL << 11)
#define	_USART_IEN_SSM_SHIFT 11
#define	_USART_IEN_SSM_MASK 0x800UL
#define	_USART_IEN_SSM_DEFAULT 0x00000000UL
#define	USART_IEN_SSM_DEFAULT (_USART_IEN_SSM_DEFAULT << 11)
#define	USART_IEN_CCF (0x1UL << 12)
#define	_USART_IEN_CCF_SHIFT 12
#define	_USART_IEN_CCF_MASK 0x1000UL
#define	_USART_IEN_CCF_DEFAULT 0x00000000UL
#define	USART_IEN_CCF_DEFAULT (_USART_IEN_CCF_DEFAULT << 12)
#define	_USART_IRCTRL_RESETVALUE 0x00000000UL
#define	_USART_IRCTRL_MASK 0x000000FFUL
#define	USART_IRCTRL_IREN (0x1UL << 0)
#define	_USART_IRCTRL_IREN_SHIFT 0
#define	_USART_IRCTRL_IREN_MASK 0x1UL
#define	_USART_IRCTRL_IREN_DEFAULT 0x00000000UL
#define	USART_IRCTRL_IREN_DEFAULT (_USART_IRCTRL_IREN_DEFAULT << 0)
#define	_USART_IRCTRL_IRPW_SHIFT 1
#define	_USART_IRCTRL_IRPW_MASK 0x6UL
#define	_USART_IRCTRL_IRPW_DEFAULT 0x00000000UL
#define	_USART_IRCTRL_IRPW_ONE 0x00000000UL
#define	_USART_IRCTRL_IRPW_TWO 0x00000001UL
#define	_USART_IRCTRL_IRPW_THREE 0x00000002UL
#define	_USART_IRCTRL_IRPW_FOUR 0x00000003UL
#define	USART_IRCTRL_IRPW_DEFAULT (_USART_IRCTRL_IRPW_DEFAULT << 1)
#define	USART_IRCTRL_IRPW_ONE (_USART_IRCTRL_IRPW_ONE << 1)
#define	USART_IRCTRL_IRPW_TWO (_USART_IRCTRL_IRPW_TWO << 1)
#define	USART_IRCTRL_IRPW_THREE (_USART_IRCTRL_IRPW_THREE << 1)
#define	USART_IRCTRL_IRPW_FOUR (_USART_IRCTRL_IRPW_FOUR << 1)
#define	USART_IRCTRL_IRFILT (0x1UL << 3)
#define	_USART_IRCTRL_IRFILT_SHIFT 3
#define	_USART_IRCTRL_IRFILT_MASK 0x8UL
#define	_USART_IRCTRL_IRFILT_DEFAULT 0x00000000UL
#define	USART_IRCTRL_IRFILT_DEFAULT (_USART_IRCTRL_IRFILT_DEFAULT << 3)
#define	_USART_IRCTRL_IRPRSSEL_SHIFT 4
#define	_USART_IRCTRL_IRPRSSEL_MASK 0x70UL
#define	_USART_IRCTRL_IRPRSSEL_DEFAULT 0x00000000UL
#define	_USART_IRCTRL_IRPRSSEL_PRSCH0 0x00000000UL
#define	_USART_IRCTRL_IRPRSSEL_PRSCH1 0x00000001UL
#define	_USART_IRCTRL_IRPRSSEL_PRSCH2 0x00000002UL
#define	_USART_IRCTRL_IRPRSSEL_PRSCH3 0x00000003UL
#define	_USART_IRCTRL_IRPRSSEL_PRSCH4 0x00000004UL
#define	_USART_IRCTRL_IRPRSSEL_PRSCH5 0x00000005UL
#define	_USART_IRCTRL_IRPRSSEL_PRSCH6 0x00000006UL
#define	_USART_IRCTRL_IRPRSSEL_PRSCH7 0x00000007UL
#define	USART_IRCTRL_IRPRSSEL_DEFAULT (_USART_IRCTRL_IRPRSSEL_DEFAULT << 4)
#define	USART_IRCTRL_IRPRSSEL_PRSCH0 (_USART_IRCTRL_IRPRSSEL_PRSCH0 << 4)
#define	USART_IRCTRL_IRPRSSEL_PRSCH1 (_USART_IRCTRL_IRPRSSEL_PRSCH1 << 4)
#define	USART_IRCTRL_IRPRSSEL_PRSCH2 (_USART_IRCTRL_IRPRSSEL_PRSCH2 << 4)
#define	USART_IRCTRL_IRPRSSEL_PRSCH3 (_USART_IRCTRL_IRPRSSEL_PRSCH3 << 4)
#define	USART_IRCTRL_IRPRSSEL_PRSCH4 (_USART_IRCTRL_IRPRSSEL_PRSCH4 << 4)
#define	USART_IRCTRL_IRPRSSEL_PRSCH5 (_USART_IRCTRL_IRPRSSEL_PRSCH5 << 4)
#define	USART_IRCTRL_IRPRSSEL_PRSCH6 (_USART_IRCTRL_IRPRSSEL_PRSCH6 << 4)
#define	USART_IRCTRL_IRPRSSEL_PRSCH7 (_USART_IRCTRL_IRPRSSEL_PRSCH7 << 4)
#define	USART_IRCTRL_IRPRSEN (0x1UL << 7)
#define	_USART_IRCTRL_IRPRSEN_SHIFT 7
#define	_USART_IRCTRL_IRPRSEN_MASK 0x80UL
#define	_USART_IRCTRL_IRPRSEN_DEFAULT 0x00000000UL
#define	USART_IRCTRL_IRPRSEN_DEFAULT (_USART_IRCTRL_IRPRSEN_DEFAULT << 7)
#define	_USART_ROUTE_RESETVALUE 0x00000000UL
#define	_USART_ROUTE_MASK 0x0000030FUL
#define	USART_ROUTE_RXPEN (0x1UL << 0)
#define	_USART_ROUTE_RXPEN_SHIFT 0
#define	_USART_ROUTE_RXPEN_MASK 0x1UL
#define	_USART_ROUTE_RXPEN_DEFAULT 0x00000000UL
#define	USART_ROUTE_RXPEN_DEFAULT (_USART_ROUTE_RXPEN_DEFAULT << 0)
#define	USART_ROUTE_TXPEN (0x1UL << 1)
#define	_USART_ROUTE_TXPEN_SHIFT 1
#define	_USART_ROUTE_TXPEN_MASK 0x2UL
#define	_USART_ROUTE_TXPEN_DEFAULT 0x00000000UL
#define	USART_ROUTE_TXPEN_DEFAULT (_USART_ROUTE_TXPEN_DEFAULT << 1)
#define	USART_ROUTE_CSPEN (0x1UL << 2)
#define	_USART_ROUTE_CSPEN_SHIFT 2
#define	_USART_ROUTE_CSPEN_MASK 0x4UL
#define	_USART_ROUTE_CSPEN_DEFAULT 0x00000000UL
#define	USART_ROUTE_CSPEN_DEFAULT (_USART_ROUTE_CSPEN_DEFAULT << 2)
#define	USART_ROUTE_CLKPEN (0x1UL << 3)
#define	_USART_ROUTE_CLKPEN_SHIFT 3
#define	_USART_ROUTE_CLKPEN_MASK 0x8UL
#define	_USART_ROUTE_CLKPEN_DEFAULT 0x00000000UL
#define	USART_ROUTE_CLKPEN_DEFAULT (_USART_ROUTE_CLKPEN_DEFAULT << 3)
#define	_USART_ROUTE_LOCATION_SHIFT 8
#define	_USART_ROUTE_LOCATION_MASK 0x300UL
#define	_USART_ROUTE_LOCATION_DEFAULT 0x00000000UL
#define	_USART_ROUTE_LOCATION_LOC0 0x00000000UL
#define	_USART_ROUTE_LOCATION_LOC1 0x00000001UL
#define	_USART_ROUTE_LOCATION_LOC2 0x00000002UL
#define	_USART_ROUTE_LOCATION_LOC3 0x00000003UL
#define	USART_ROUTE_LOCATION_DEFAULT (_USART_ROUTE_LOCATION_DEFAULT << 8)
#define	USART_ROUTE_LOCATION_LOC0 (_USART_ROUTE_LOCATION_LOC0 << 8)
#define	USART_ROUTE_LOCATION_LOC1 (_USART_ROUTE_LOCATION_LOC1 << 8)
#define	USART_ROUTE_LOCATION_LOC2 (_USART_ROUTE_LOCATION_LOC2 << 8)
#define	USART_ROUTE_LOCATION_LOC3 (_USART_ROUTE_LOCATION_LOC3 << 8)
#define	_UART_CTRL_RESETVALUE 0x00000000UL
#define	_UART_CTRL_MASK 0x1DFFFF7FUL
#define	UART_CTRL_SYNC (0x1UL << 0)
#define	_UART_CTRL_SYNC_SHIFT 0
#define	_UART_CTRL_SYNC_MASK 0x1UL
#define	_UART_CTRL_SYNC_DEFAULT 0x00000000UL
#define	UART_CTRL_SYNC_DEFAULT (_UART_CTRL_SYNC_DEFAULT << 0)
#define	UART_CTRL_LOOPBK (0x1UL << 1)
#define	_UART_CTRL_LOOPBK_SHIFT 1
#define	_UART_CTRL_LOOPBK_MASK 0x2UL
#define	_UART_CTRL_LOOPBK_DEFAULT 0x00000000UL
#define	UART_CTRL_LOOPBK_DEFAULT (_UART_CTRL_LOOPBK_DEFAULT << 1)
#define	UART_CTRL_CCEN (0x1UL << 2)
#define	_UART_CTRL_CCEN_SHIFT 2
#define	_UART_CTRL_CCEN_MASK 0x4UL
#define	_UART_CTRL_CCEN_DEFAULT 0x00000000UL
#define	UART_CTRL_CCEN_DEFAULT (_UART_CTRL_CCEN_DEFAULT << 2)
#define	UART_CTRL_MPM (0x1UL << 3)
#define	_UART_CTRL_MPM_SHIFT 3
#define	_UART_CTRL_MPM_MASK 0x8UL
#define	_UART_CTRL_MPM_DEFAULT 0x00000000UL
#define	UART_CTRL_MPM_DEFAULT (_UART_CTRL_MPM_DEFAULT << 3)
#define	UART_CTRL_MPAB (0x1UL << 4)
#define	_UART_CTRL_MPAB_SHIFT 4
#define	_UART_CTRL_MPAB_MASK 0x10UL
#define	_UART_CTRL_MPAB_DEFAULT 0x00000000UL
#define	UART_CTRL_MPAB_DEFAULT (_UART_CTRL_MPAB_DEFAULT << 4)
#define	_UART_CTRL_OVS_SHIFT 5
#define	_UART_CTRL_OVS_MASK 0x60UL
#define	_UART_CTRL_OVS_DEFAULT 0x00000000UL
#define	_UART_CTRL_OVS_X16 0x00000000UL
#define	_UART_CTRL_OVS_X8 0x00000001UL
#define	_UART_CTRL_OVS_X6 0x00000002UL
#define	_UART_CTRL_OVS_X4 0x00000003UL
#define	UART_CTRL_OVS_DEFAULT (_UART_CTRL_OVS_DEFAULT << 5)
#define	UART_CTRL_OVS_X16 (_UART_CTRL_OVS_X16 << 5)
#define	UART_CTRL_OVS_X8 (_UART_CTRL_OVS_X8 << 5)
#define	UART_CTRL_OVS_X6 (_UART_CTRL_OVS_X6 << 5)
#define	UART_CTRL_OVS_X4 (_UART_CTRL_OVS_X4 << 5)
#define	UART_CTRL_CLKPOL (0x1UL << 8)
#define	_UART_CTRL_CLKPOL_SHIFT 8
#define	_UART_CTRL_CLKPOL_MASK 0x100UL
#define	_UART_CTRL_CLKPOL_DEFAULT 0x00000000UL
#define	_UART_CTRL_CLKPOL_IDLELOW 0x00000000UL
#define	_UART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL
#define	UART_CTRL_CLKPOL_DEFAULT (_UART_CTRL_CLKPOL_DEFAULT << 8)
#define	UART_CTRL_CLKPOL_IDLELOW (_UART_CTRL_CLKPOL_IDLELOW << 8)
#define	UART_CTRL_CLKPOL_IDLEHIGH (_UART_CTRL_CLKPOL_IDLEHIGH << 8)
#define	UART_CTRL_CLKPHA (0x1UL << 9)
#define	_UART_CTRL_CLKPHA_SHIFT 9
#define	_UART_CTRL_CLKPHA_MASK 0x200UL
#define	_UART_CTRL_CLKPHA_DEFAULT 0x00000000UL
#define	_UART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL
#define	_UART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL
#define	UART_CTRL_CLKPHA_DEFAULT (_UART_CTRL_CLKPHA_DEFAULT << 9)
#define	UART_CTRL_CLKPHA_SAMPLELEADING (_UART_CTRL_CLKPHA_SAMPLELEADING << 9)
#define	UART_CTRL_CLKPHA_SAMPLETRAILING (_UART_CTRL_CLKPHA_SAMPLETRAILING << 9)
#define	UART_CTRL_MSBF (0x1UL << 10)
#define	_UART_CTRL_MSBF_SHIFT 10
#define	_UART_CTRL_MSBF_MASK 0x400UL
#define	_UART_CTRL_MSBF_DEFAULT 0x00000000UL
#define	UART_CTRL_MSBF_DEFAULT (_UART_CTRL_MSBF_DEFAULT << 10)
#define	UART_CTRL_CSMA (0x1UL << 11)
#define	_UART_CTRL_CSMA_SHIFT 11
#define	_UART_CTRL_CSMA_MASK 0x800UL
#define	_UART_CTRL_CSMA_DEFAULT 0x00000000UL
#define	_UART_CTRL_CSMA_NOACTION 0x00000000UL
#define	_UART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL
#define	UART_CTRL_CSMA_DEFAULT (_UART_CTRL_CSMA_DEFAULT << 11)
#define	UART_CTRL_CSMA_NOACTION (_UART_CTRL_CSMA_NOACTION << 11)
#define	UART_CTRL_CSMA_GOTOSLAVEMODE (_UART_CTRL_CSMA_GOTOSLAVEMODE << 11)
#define	UART_CTRL_TXBIL (0x1UL << 12)
#define	_UART_CTRL_TXBIL_SHIFT 12
#define	_UART_CTRL_TXBIL_MASK 0x1000UL
#define	_UART_CTRL_TXBIL_DEFAULT 0x00000000UL
#define	_UART_CTRL_TXBIL_EMPTY 0x00000000UL
#define	_UART_CTRL_TXBIL_HALFFULL 0x00000001UL
#define	UART_CTRL_TXBIL_DEFAULT (_UART_CTRL_TXBIL_DEFAULT << 12)
#define	UART_CTRL_TXBIL_EMPTY (_UART_CTRL_TXBIL_EMPTY << 12)
#define	UART_CTRL_TXBIL_HALFFULL (_UART_CTRL_TXBIL_HALFFULL << 12)
#define	UART_CTRL_RXINV (0x1UL << 13)
#define	_UART_CTRL_RXINV_SHIFT 13
#define	_UART_CTRL_RXINV_MASK 0x2000UL
#define	_UART_CTRL_RXINV_DEFAULT 0x00000000UL
#define	UART_CTRL_RXINV_DEFAULT (_UART_CTRL_RXINV_DEFAULT << 13)
#define	UART_CTRL_TXINV (0x1UL << 14)
#define	_UART_CTRL_TXINV_SHIFT 14
#define	_UART_CTRL_TXINV_MASK 0x4000UL
#define	_UART_CTRL_TXINV_DEFAULT 0x00000000UL
#define	UART_CTRL_TXINV_DEFAULT (_UART_CTRL_TXINV_DEFAULT << 14)
#define	UART_CTRL_CSINV (0x1UL << 15)
#define	_UART_CTRL_CSINV_SHIFT 15
#define	_UART_CTRL_CSINV_MASK 0x8000UL
#define	_UART_CTRL_CSINV_DEFAULT 0x00000000UL
#define	UART_CTRL_CSINV_DEFAULT (_UART_CTRL_CSINV_DEFAULT << 15)
#define	UART_CTRL_AUTOCS (0x1UL << 16)
#define	_UART_CTRL_AUTOCS_SHIFT 16
#define	_UART_CTRL_AUTOCS_MASK 0x10000UL
#define	_UART_CTRL_AUTOCS_DEFAULT 0x00000000UL
#define	UART_CTRL_AUTOCS_DEFAULT (_UART_CTRL_AUTOCS_DEFAULT << 16)
#define	UART_CTRL_AUTOTRI (0x1UL << 17)
#define	_UART_CTRL_AUTOTRI_SHIFT 17
#define	_UART_CTRL_AUTOTRI_MASK 0x20000UL
#define	_UART_CTRL_AUTOTRI_DEFAULT 0x00000000UL
#define	UART_CTRL_AUTOTRI_DEFAULT (_UART_CTRL_AUTOTRI_DEFAULT << 17)
#define	UART_CTRL_SCMODE (0x1UL << 18)
#define	_UART_CTRL_SCMODE_SHIFT 18
#define	_UART_CTRL_SCMODE_MASK 0x40000UL
#define	_UART_CTRL_SCMODE_DEFAULT 0x00000000UL
#define	UART_CTRL_SCMODE_DEFAULT (_UART_CTRL_SCMODE_DEFAULT << 18)
#define	UART_CTRL_SCRETRANS (0x1UL << 19)
#define	_UART_CTRL_SCRETRANS_SHIFT 19
#define	_UART_CTRL_SCRETRANS_MASK 0x80000UL
#define	_UART_CTRL_SCRETRANS_DEFAULT 0x00000000UL
#define	UART_CTRL_SCRETRANS_DEFAULT (_UART_CTRL_SCRETRANS_DEFAULT << 19)
#define	UART_CTRL_SKIPPERRF (0x1UL << 20)
#define	_UART_CTRL_SKIPPERRF_SHIFT 20
#define	_UART_CTRL_SKIPPERRF_MASK 0x100000UL
#define	_UART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL
#define	UART_CTRL_SKIPPERRF_DEFAULT (_UART_CTRL_SKIPPERRF_DEFAULT << 20)
#define	UART_CTRL_BIT8DV (0x1UL << 21)
#define	_UART_CTRL_BIT8DV_SHIFT 21
#define	_UART_CTRL_BIT8DV_MASK 0x200000UL
#define	_UART_CTRL_BIT8DV_DEFAULT 0x00000000UL
#define	UART_CTRL_BIT8DV_DEFAULT (_UART_CTRL_BIT8DV_DEFAULT << 21)
#define	UART_CTRL_ERRSDMA (0x1UL << 22)
#define	_UART_CTRL_ERRSDMA_SHIFT 22
#define	_UART_CTRL_ERRSDMA_MASK 0x400000UL
#define	_UART_CTRL_ERRSDMA_DEFAULT 0x00000000UL
#define	UART_CTRL_ERRSDMA_DEFAULT (_UART_CTRL_ERRSDMA_DEFAULT << 22)
#define	UART_CTRL_ERRSRX (0x1UL << 23)
#define	_UART_CTRL_ERRSRX_SHIFT 23
#define	_UART_CTRL_ERRSRX_MASK 0x800000UL
#define	_UART_CTRL_ERRSRX_DEFAULT 0x00000000UL
#define	UART_CTRL_ERRSRX_DEFAULT (_UART_CTRL_ERRSRX_DEFAULT << 23)
#define	UART_CTRL_ERRSTX (0x1UL << 24)
#define	_UART_CTRL_ERRSTX_SHIFT 24
#define	_UART_CTRL_ERRSTX_MASK 0x1000000UL
#define	_UART_CTRL_ERRSTX_DEFAULT 0x00000000UL
#define	UART_CTRL_ERRSTX_DEFAULT (_UART_CTRL_ERRSTX_DEFAULT << 24)
#define	_UART_CTRL_TXDELAY_SHIFT 26
#define	_UART_CTRL_TXDELAY_MASK 0xC000000UL
#define	_UART_CTRL_TXDELAY_DEFAULT 0x00000000UL
#define	_UART_CTRL_TXDELAY_NONE 0x00000000UL
#define	_UART_CTRL_TXDELAY_SINGLE 0x00000001UL
#define	_UART_CTRL_TXDELAY_DOUBLE 0x00000002UL
#define	_UART_CTRL_TXDELAY_TRIPLE 0x00000003UL
#define	UART_CTRL_TXDELAY_DEFAULT (_UART_CTRL_TXDELAY_DEFAULT << 26)
#define	UART_CTRL_TXDELAY_NONE (_UART_CTRL_TXDELAY_NONE << 26)
#define	UART_CTRL_TXDELAY_SINGLE (_UART_CTRL_TXDELAY_SINGLE << 26)
#define	UART_CTRL_TXDELAY_DOUBLE (_UART_CTRL_TXDELAY_DOUBLE << 26)
#define	UART_CTRL_TXDELAY_TRIPLE (_UART_CTRL_TXDELAY_TRIPLE << 26)
#define	UART_CTRL_BYTESWAP (0x1UL << 28)
#define	_UART_CTRL_BYTESWAP_SHIFT 28
#define	_UART_CTRL_BYTESWAP_MASK 0x10000000UL
#define	_UART_CTRL_BYTESWAP_DEFAULT 0x00000000UL
#define	UART_CTRL_BYTESWAP_DEFAULT (_UART_CTRL_BYTESWAP_DEFAULT << 28)
#define	_UART_FRAME_RESETVALUE 0x00001005UL
#define	_UART_FRAME_MASK 0x0000330FUL
#define	_UART_FRAME_DATABITS_SHIFT 0
#define	_UART_FRAME_DATABITS_MASK 0xFUL
#define	_UART_FRAME_DATABITS_FOUR 0x00000001UL
#define	_UART_FRAME_DATABITS_FIVE 0x00000002UL
#define	_UART_FRAME_DATABITS_SIX 0x00000003UL
#define	_UART_FRAME_DATABITS_SEVEN 0x00000004UL
#define	_UART_FRAME_DATABITS_DEFAULT 0x00000005UL
#define	_UART_FRAME_DATABITS_EIGHT 0x00000005UL
#define	_UART_FRAME_DATABITS_NINE 0x00000006UL
#define	_UART_FRAME_DATABITS_TEN 0x00000007UL
#define	_UART_FRAME_DATABITS_ELEVEN 0x00000008UL
#define	_UART_FRAME_DATABITS_TWELVE 0x00000009UL
#define	_UART_FRAME_DATABITS_THIRTEEN 0x0000000AUL
#define	_UART_FRAME_DATABITS_FOURTEEN 0x0000000BUL
#define	_UART_FRAME_DATABITS_FIFTEEN 0x0000000CUL
#define	_UART_FRAME_DATABITS_SIXTEEN 0x0000000DUL
#define	UART_FRAME_DATABITS_FOUR (_UART_FRAME_DATABITS_FOUR << 0)
#define	UART_FRAME_DATABITS_FIVE (_UART_FRAME_DATABITS_FIVE << 0)
#define	UART_FRAME_DATABITS_SIX (_UART_FRAME_DATABITS_SIX << 0)
#define	UART_FRAME_DATABITS_SEVEN (_UART_FRAME_DATABITS_SEVEN << 0)
#define	UART_FRAME_DATABITS_DEFAULT (_UART_FRAME_DATABITS_DEFAULT << 0)
#define	UART_FRAME_DATABITS_EIGHT (_UART_FRAME_DATABITS_EIGHT << 0)
#define	UART_FRAME_DATABITS_NINE (_UART_FRAME_DATABITS_NINE << 0)
#define	UART_FRAME_DATABITS_TEN (_UART_FRAME_DATABITS_TEN << 0)
#define	UART_FRAME_DATABITS_ELEVEN (_UART_FRAME_DATABITS_ELEVEN << 0)
#define	UART_FRAME_DATABITS_TWELVE (_UART_FRAME_DATABITS_TWELVE << 0)
#define	UART_FRAME_DATABITS_THIRTEEN (_UART_FRAME_DATABITS_THIRTEEN << 0)
#define	UART_FRAME_DATABITS_FOURTEEN (_UART_FRAME_DATABITS_FOURTEEN << 0)
#define	UART_FRAME_DATABITS_FIFTEEN (_UART_FRAME_DATABITS_FIFTEEN << 0)
#define	UART_FRAME_DATABITS_SIXTEEN (_UART_FRAME_DATABITS_SIXTEEN << 0)
#define	_UART_FRAME_PARITY_SHIFT 8
#define	_UART_FRAME_PARITY_MASK 0x300UL
#define	_UART_FRAME_PARITY_DEFAULT 0x00000000UL
#define	_UART_FRAME_PARITY_NONE 0x00000000UL
#define	_UART_FRAME_PARITY_EVEN 0x00000002UL
#define	_UART_FRAME_PARITY_ODD 0x00000003UL
#define	UART_FRAME_PARITY_DEFAULT (_UART_FRAME_PARITY_DEFAULT << 8)
#define	UART_FRAME_PARITY_NONE (_UART_FRAME_PARITY_NONE << 8)
#define	UART_FRAME_PARITY_EVEN (_UART_FRAME_PARITY_EVEN << 8)
#define	UART_FRAME_PARITY_ODD (_UART_FRAME_PARITY_ODD << 8)
#define	_UART_FRAME_STOPBITS_SHIFT 12
#define	_UART_FRAME_STOPBITS_MASK 0x3000UL
#define	_UART_FRAME_STOPBITS_HALF 0x00000000UL
#define	_UART_FRAME_STOPBITS_DEFAULT 0x00000001UL
#define	_UART_FRAME_STOPBITS_ONE 0x00000001UL
#define	_UART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL
#define	_UART_FRAME_STOPBITS_TWO 0x00000003UL
#define	UART_FRAME_STOPBITS_HALF (_UART_FRAME_STOPBITS_HALF << 12)
#define	UART_FRAME_STOPBITS_DEFAULT (_UART_FRAME_STOPBITS_DEFAULT << 12)
#define	UART_FRAME_STOPBITS_ONE (_UART_FRAME_STOPBITS_ONE << 12)
#define	UART_FRAME_STOPBITS_ONEANDAHALF (_UART_FRAME_STOPBITS_ONEANDAHALF << 12)
#define	UART_FRAME_STOPBITS_TWO (_UART_FRAME_STOPBITS_TWO << 12)
#define	_UART_TRIGCTRL_RESETVALUE 0x00000000UL
#define	_UART_TRIGCTRL_MASK 0x00000037UL
#define	_UART_TRIGCTRL_TSEL_SHIFT 0
#define	_UART_TRIGCTRL_TSEL_MASK 0x7UL
#define	_UART_TRIGCTRL_TSEL_DEFAULT 0x00000000UL
#define	_UART_TRIGCTRL_TSEL_PRSCH0 0x00000000UL
#define	_UART_TRIGCTRL_TSEL_PRSCH1 0x00000001UL
#define	_UART_TRIGCTRL_TSEL_PRSCH2 0x00000002UL
#define	_UART_TRIGCTRL_TSEL_PRSCH3 0x00000003UL
#define	_UART_TRIGCTRL_TSEL_PRSCH4 0x00000004UL
#define	_UART_TRIGCTRL_TSEL_PRSCH5 0x00000005UL
#define	_UART_TRIGCTRL_TSEL_PRSCH6 0x00000006UL
#define	_UART_TRIGCTRL_TSEL_PRSCH7 0x00000007UL
#define	UART_TRIGCTRL_TSEL_DEFAULT (_UART_TRIGCTRL_TSEL_DEFAULT << 0)
#define	UART_TRIGCTRL_TSEL_PRSCH0 (_UART_TRIGCTRL_TSEL_PRSCH0 << 0)
#define	UART_TRIGCTRL_TSEL_PRSCH1 (_UART_TRIGCTRL_TSEL_PRSCH1 << 0)
#define	UART_TRIGCTRL_TSEL_PRSCH2 (_UART_TRIGCTRL_TSEL_PRSCH2 << 0)
#define	UART_TRIGCTRL_TSEL_PRSCH3 (_UART_TRIGCTRL_TSEL_PRSCH3 << 0)
#define	UART_TRIGCTRL_TSEL_PRSCH4 (_UART_TRIGCTRL_TSEL_PRSCH4 << 0)
#define	UART_TRIGCTRL_TSEL_PRSCH5 (_UART_TRIGCTRL_TSEL_PRSCH5 << 0)
#define	UART_TRIGCTRL_TSEL_PRSCH6 (_UART_TRIGCTRL_TSEL_PRSCH6 << 0)
#define	UART_TRIGCTRL_TSEL_PRSCH7 (_UART_TRIGCTRL_TSEL_PRSCH7 << 0)
#define	UART_TRIGCTRL_RXTEN (0x1UL << 4)
#define	_UART_TRIGCTRL_RXTEN_SHIFT 4
#define	_UART_TRIGCTRL_RXTEN_MASK 0x10UL
#define	_UART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL
#define	UART_TRIGCTRL_RXTEN_DEFAULT (_UART_TRIGCTRL_RXTEN_DEFAULT << 4)
#define	UART_TRIGCTRL_TXTEN (0x1UL << 5)
#define	_UART_TRIGCTRL_TXTEN_SHIFT 5
#define	_UART_TRIGCTRL_TXTEN_MASK 0x20UL
#define	_UART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL
#define	UART_TRIGCTRL_TXTEN_DEFAULT (_UART_TRIGCTRL_TXTEN_DEFAULT << 5)
#define	_UART_CMD_RESETVALUE 0x00000000UL
#define	_UART_CMD_MASK 0x00000FFFUL
#define	UART_CMD_RXEN (0x1UL << 0)
#define	_UART_CMD_RXEN_SHIFT 0
#define	_UART_CMD_RXEN_MASK 0x1UL
#define	_UART_CMD_RXEN_DEFAULT 0x00000000UL
#define	UART_CMD_RXEN_DEFAULT (_UART_CMD_RXEN_DEFAULT << 0)
#define	UART_CMD_RXDIS (0x1UL << 1)
#define	_UART_CMD_RXDIS_SHIFT 1
#define	_UART_CMD_RXDIS_MASK 0x2UL
#define	_UART_CMD_RXDIS_DEFAULT 0x00000000UL
#define	UART_CMD_RXDIS_DEFAULT (_UART_CMD_RXDIS_DEFAULT << 1)
#define	UART_CMD_TXEN (0x1UL << 2)
#define	_UART_CMD_TXEN_SHIFT 2
#define	_UART_CMD_TXEN_MASK 0x4UL
#define	_UART_CMD_TXEN_DEFAULT 0x00000000UL
#define	UART_CMD_TXEN_DEFAULT (_UART_CMD_TXEN_DEFAULT << 2)
#define	UART_CMD_TXDIS (0x1UL << 3)
#define	_UART_CMD_TXDIS_SHIFT 3
#define	_UART_CMD_TXDIS_MASK 0x8UL
#define	_UART_CMD_TXDIS_DEFAULT 0x00000000UL
#define	UART_CMD_TXDIS_DEFAULT (_UART_CMD_TXDIS_DEFAULT << 3)
#define	UART_CMD_MASTEREN (0x1UL << 4)
#define	_UART_CMD_MASTEREN_SHIFT 4
#define	_UART_CMD_MASTEREN_MASK 0x10UL
#define	_UART_CMD_MASTEREN_DEFAULT 0x00000000UL
#define	UART_CMD_MASTEREN_DEFAULT (_UART_CMD_MASTEREN_DEFAULT << 4)
#define	UART_CMD_MASTERDIS (0x1UL << 5)
#define	_UART_CMD_MASTERDIS_SHIFT 5
#define	_UART_CMD_MASTERDIS_MASK 0x20UL
#define	_UART_CMD_MASTERDIS_DEFAULT 0x00000000UL
#define	UART_CMD_MASTERDIS_DEFAULT (_UART_CMD_MASTERDIS_DEFAULT << 5)
#define	UART_CMD_RXBLOCKEN (0x1UL << 6)
#define	_UART_CMD_RXBLOCKEN_SHIFT 6
#define	_UART_CMD_RXBLOCKEN_MASK 0x40UL
#define	_UART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL
#define	UART_CMD_RXBLOCKEN_DEFAULT (_UART_CMD_RXBLOCKEN_DEFAULT << 6)
#define	UART_CMD_RXBLOCKDIS (0x1UL << 7)
#define	_UART_CMD_RXBLOCKDIS_SHIFT 7
#define	_UART_CMD_RXBLOCKDIS_MASK 0x80UL
#define	_UART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL
#define	UART_CMD_RXBLOCKDIS_DEFAULT (_UART_CMD_RXBLOCKDIS_DEFAULT << 7)
#define	UART_CMD_TXTRIEN (0x1UL << 8)
#define	_UART_CMD_TXTRIEN_SHIFT 8
#define	_UART_CMD_TXTRIEN_MASK 0x100UL
#define	_UART_CMD_TXTRIEN_DEFAULT 0x00000000UL
#define	UART_CMD_TXTRIEN_DEFAULT (_UART_CMD_TXTRIEN_DEFAULT << 8)
#define	UART_CMD_TXTRIDIS (0x1UL << 9)
#define	_UART_CMD_TXTRIDIS_SHIFT 9
#define	_UART_CMD_TXTRIDIS_MASK 0x200UL
#define	_UART_CMD_TXTRIDIS_DEFAULT 0x00000000UL
#define	UART_CMD_TXTRIDIS_DEFAULT (_UART_CMD_TXTRIDIS_DEFAULT << 9)
#define	UART_CMD_CLEARTX (0x1UL << 10)
#define	_UART_CMD_CLEARTX_SHIFT 10
#define	_UART_CMD_CLEARTX_MASK 0x400UL
#define	_UART_CMD_CLEARTX_DEFAULT 0x00000000UL
#define	UART_CMD_CLEARTX_DEFAULT (_UART_CMD_CLEARTX_DEFAULT << 10)
#define	UART_CMD_CLEARRX (0x1UL << 11)
#define	_UART_CMD_CLEARRX_SHIFT 11
#define	_UART_CMD_CLEARRX_MASK 0x800UL
#define	_UART_CMD_CLEARRX_DEFAULT 0x00000000UL
#define	UART_CMD_CLEARRX_DEFAULT (_UART_CMD_CLEARRX_DEFAULT << 11)
#define	_UART_STATUS_RESETVALUE 0x00000040UL
#define	_UART_STATUS_MASK 0x000001FFUL
#define	UART_STATUS_RXENS (0x1UL << 0)
#define	_UART_STATUS_RXENS_SHIFT 0
#define	_UART_STATUS_RXENS_MASK 0x1UL
#define	_UART_STATUS_RXENS_DEFAULT 0x00000000UL
#define	UART_STATUS_RXENS_DEFAULT (_UART_STATUS_RXENS_DEFAULT << 0)
#define	UART_STATUS_TXENS (0x1UL << 1)
#define	_UART_STATUS_TXENS_SHIFT 1
#define	_UART_STATUS_TXENS_MASK 0x2UL
#define	_UART_STATUS_TXENS_DEFAULT 0x00000000UL
#define	UART_STATUS_TXENS_DEFAULT (_UART_STATUS_TXENS_DEFAULT << 1)
#define	UART_STATUS_MASTER (0x1UL << 2)
#define	_UART_STATUS_MASTER_SHIFT 2
#define	_UART_STATUS_MASTER_MASK 0x4UL
#define	_UART_STATUS_MASTER_DEFAULT 0x00000000UL
#define	UART_STATUS_MASTER_DEFAULT (_UART_STATUS_MASTER_DEFAULT << 2)
#define	UART_STATUS_RXBLOCK (0x1UL << 3)
#define	_UART_STATUS_RXBLOCK_SHIFT 3
#define	_UART_STATUS_RXBLOCK_MASK 0x8UL
#define	_UART_STATUS_RXBLOCK_DEFAULT 0x00000000UL
#define	UART_STATUS_RXBLOCK_DEFAULT (_UART_STATUS_RXBLOCK_DEFAULT << 3)
#define	UART_STATUS_TXTRI (0x1UL << 4)
#define	_UART_STATUS_TXTRI_SHIFT 4
#define	_UART_STATUS_TXTRI_MASK 0x10UL
#define	_UART_STATUS_TXTRI_DEFAULT 0x00000000UL
#define	UART_STATUS_TXTRI_DEFAULT (_UART_STATUS_TXTRI_DEFAULT << 4)
#define	UART_STATUS_TXC (0x1UL << 5)
#define	_UART_STATUS_TXC_SHIFT 5
#define	_UART_STATUS_TXC_MASK 0x20UL
#define	_UART_STATUS_TXC_DEFAULT 0x00000000UL
#define	UART_STATUS_TXC_DEFAULT (_UART_STATUS_TXC_DEFAULT << 5)
#define	UART_STATUS_TXBL (0x1UL << 6)
#define	_UART_STATUS_TXBL_SHIFT 6
#define	_UART_STATUS_TXBL_MASK 0x40UL
#define	_UART_STATUS_TXBL_DEFAULT 0x00000001UL
#define	UART_STATUS_TXBL_DEFAULT (_UART_STATUS_TXBL_DEFAULT << 6)
#define	UART_STATUS_RXDATAV (0x1UL << 7)
#define	_UART_STATUS_RXDATAV_SHIFT 7
#define	_UART_STATUS_RXDATAV_MASK 0x80UL
#define	_UART_STATUS_RXDATAV_DEFAULT 0x00000000UL
#define	UART_STATUS_RXDATAV_DEFAULT (_UART_STATUS_RXDATAV_DEFAULT << 7)
#define	UART_STATUS_RXFULL (0x1UL << 8)
#define	_UART_STATUS_RXFULL_SHIFT 8
#define	_UART_STATUS_RXFULL_MASK 0x100UL
#define	_UART_STATUS_RXFULL_DEFAULT 0x00000000UL
#define	UART_STATUS_RXFULL_DEFAULT (_UART_STATUS_RXFULL_DEFAULT << 8)
#define	_UART_CLKDIV_RESETVALUE 0x00000000UL
#define	_UART_CLKDIV_MASK 0x001FFFC0UL
#define	_UART_CLKDIV_DIV_SHIFT 6
#define	_UART_CLKDIV_DIV_MASK 0x1FFFC0UL
#define	_UART_CLKDIV_DIV_DEFAULT 0x00000000UL
#define	UART_CLKDIV_DIV_DEFAULT (_UART_CLKDIV_DIV_DEFAULT << 6)
#define	_UART_RXDATAX_RESETVALUE 0x00000000UL
#define	_UART_RXDATAX_MASK 0x0000C1FFUL
#define	_UART_RXDATAX_RXDATA_SHIFT 0
#define	_UART_RXDATAX_RXDATA_MASK 0x1FFUL
#define	_UART_RXDATAX_RXDATA_DEFAULT 0x00000000UL
#define	UART_RXDATAX_RXDATA_DEFAULT (_UART_RXDATAX_RXDATA_DEFAULT << 0)
#define	UART_RXDATAX_PERR (0x1UL << 14)
#define	_UART_RXDATAX_PERR_SHIFT 14
#define	_UART_RXDATAX_PERR_MASK 0x4000UL
#define	_UART_RXDATAX_PERR_DEFAULT 0x00000000UL
#define	UART_RXDATAX_PERR_DEFAULT (_UART_RXDATAX_PERR_DEFAULT << 14)
#define	UART_RXDATAX_FERR (0x1UL << 15)
#define	_UART_RXDATAX_FERR_SHIFT 15
#define	_UART_RXDATAX_FERR_MASK 0x8000UL
#define	_UART_RXDATAX_FERR_DEFAULT 0x00000000UL
#define	UART_RXDATAX_FERR_DEFAULT (_UART_RXDATAX_FERR_DEFAULT << 15)
#define	_UART_RXDATA_RESETVALUE 0x00000000UL
#define	_UART_RXDATA_MASK 0x000000FFUL
#define	_UART_RXDATA_RXDATA_SHIFT 0
#define	_UART_RXDATA_RXDATA_MASK 0xFFUL
#define	_UART_RXDATA_RXDATA_DEFAULT 0x00000000UL
#define	UART_RXDATA_RXDATA_DEFAULT (_UART_RXDATA_RXDATA_DEFAULT << 0)
#define	_UART_RXDOUBLEX_RESETVALUE 0x00000000UL
#define	_UART_RXDOUBLEX_MASK 0xC1FFC1FFUL
#define	_UART_RXDOUBLEX_RXDATA0_SHIFT 0
#define	_UART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL
#define	_UART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL
#define	UART_RXDOUBLEX_RXDATA0_DEFAULT (_UART_RXDOUBLEX_RXDATA0_DEFAULT << 0)
#define	UART_RXDOUBLEX_PERR0 (0x1UL << 14)
#define	_UART_RXDOUBLEX_PERR0_SHIFT 14
#define	_UART_RXDOUBLEX_PERR0_MASK 0x4000UL
#define	_UART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL
#define	UART_RXDOUBLEX_PERR0_DEFAULT (_UART_RXDOUBLEX_PERR0_DEFAULT << 14)
#define	UART_RXDOUBLEX_FERR0 (0x1UL << 15)
#define	_UART_RXDOUBLEX_FERR0_SHIFT 15
#define	_UART_RXDOUBLEX_FERR0_MASK 0x8000UL
#define	_UART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL
#define	UART_RXDOUBLEX_FERR0_DEFAULT (_UART_RXDOUBLEX_FERR0_DEFAULT << 15)
#define	_UART_RXDOUBLEX_RXDATA1_SHIFT 16
#define	_UART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL
#define	_UART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL
#define	UART_RXDOUBLEX_RXDATA1_DEFAULT (_UART_RXDOUBLEX_RXDATA1_DEFAULT << 16)
#define	UART_RXDOUBLEX_PERR1 (0x1UL << 30)
#define	_UART_RXDOUBLEX_PERR1_SHIFT 30
#define	_UART_RXDOUBLEX_PERR1_MASK 0x40000000UL
#define	_UART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL
#define	UART_RXDOUBLEX_PERR1_DEFAULT (_UART_RXDOUBLEX_PERR1_DEFAULT << 30)
#define	UART_RXDOUBLEX_FERR1 (0x1UL << 31)
#define	_UART_RXDOUBLEX_FERR1_SHIFT 31
#define	_UART_RXDOUBLEX_FERR1_MASK 0x80000000UL
#define	_UART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL
#define	UART_RXDOUBLEX_FERR1_DEFAULT (_UART_RXDOUBLEX_FERR1_DEFAULT << 31)
#define	_UART_RXDOUBLE_RESETVALUE 0x00000000UL
#define	_UART_RXDOUBLE_MASK 0x0000FFFFUL
#define	_UART_RXDOUBLE_RXDATA0_SHIFT 0
#define	_UART_RXDOUBLE_RXDATA0_MASK 0xFFUL
#define	_UART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL
#define	UART_RXDOUBLE_RXDATA0_DEFAULT (_UART_RXDOUBLE_RXDATA0_DEFAULT << 0)
#define	_UART_RXDOUBLE_RXDATA1_SHIFT 8
#define	_UART_RXDOUBLE_RXDATA1_MASK 0xFF00UL
#define	_UART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL
#define	UART_RXDOUBLE_RXDATA1_DEFAULT (_UART_RXDOUBLE_RXDATA1_DEFAULT << 8)
#define	_UART_RXDATAXP_RESETVALUE 0x00000000UL
#define	_UART_RXDATAXP_MASK 0x0000C1FFUL
#define	_UART_RXDATAXP_RXDATAP_SHIFT 0
#define	_UART_RXDATAXP_RXDATAP_MASK 0x1FFUL
#define	_UART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL
#define	UART_RXDATAXP_RXDATAP_DEFAULT (_UART_RXDATAXP_RXDATAP_DEFAULT << 0)
#define	UART_RXDATAXP_PERRP (0x1UL << 14)
#define	_UART_RXDATAXP_PERRP_SHIFT 14
#define	_UART_RXDATAXP_PERRP_MASK 0x4000UL
#define	_UART_RXDATAXP_PERRP_DEFAULT 0x00000000UL
#define	UART_RXDATAXP_PERRP_DEFAULT (_UART_RXDATAXP_PERRP_DEFAULT << 14)
#define	UART_RXDATAXP_FERRP (0x1UL << 15)
#define	_UART_RXDATAXP_FERRP_SHIFT 15
#define	_UART_RXDATAXP_FERRP_MASK 0x8000UL
#define	_UART_RXDATAXP_FERRP_DEFAULT 0x00000000UL
#define	UART_RXDATAXP_FERRP_DEFAULT (_UART_RXDATAXP_FERRP_DEFAULT << 15)
#define	_UART_RXDOUBLEXP_RESETVALUE 0x00000000UL
#define	_UART_RXDOUBLEXP_MASK 0xC1FFC1FFUL
#define	_UART_RXDOUBLEXP_RXDATAP0_SHIFT 0
#define	_UART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL
#define	_UART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL
#define	UART_RXDOUBLEXP_RXDATAP0_DEFAULT (_UART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0)
#define	UART_RXDOUBLEXP_PERRP0 (0x1UL << 14)
#define	_UART_RXDOUBLEXP_PERRP0_SHIFT 14
#define	_UART_RXDOUBLEXP_PERRP0_MASK 0x4000UL
#define	_UART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL
#define	UART_RXDOUBLEXP_PERRP0_DEFAULT (_UART_RXDOUBLEXP_PERRP0_DEFAULT << 14)
#define	UART_RXDOUBLEXP_FERRP0 (0x1UL << 15)
#define	_UART_RXDOUBLEXP_FERRP0_SHIFT 15
#define	_UART_RXDOUBLEXP_FERRP0_MASK 0x8000UL
#define	_UART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL
#define	UART_RXDOUBLEXP_FERRP0_DEFAULT (_UART_RXDOUBLEXP_FERRP0_DEFAULT << 15)
#define	_UART_RXDOUBLEXP_RXDATAP1_SHIFT 16
#define	_UART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL
#define	_UART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL
#define	UART_RXDOUBLEXP_RXDATAP1_DEFAULT (_UART_RXDOUBLEXP_RXDATAP1_DEFAULT << 16)
#define	UART_RXDOUBLEXP_PERRP1 (0x1UL << 30)
#define	_UART_RXDOUBLEXP_PERRP1_SHIFT 30
#define	_UART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL
#define	_UART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL
#define	UART_RXDOUBLEXP_PERRP1_DEFAULT (_UART_RXDOUBLEXP_PERRP1_DEFAULT << 30)
#define	UART_RXDOUBLEXP_FERRP1 (0x1UL << 31)
#define	_UART_RXDOUBLEXP_FERRP1_SHIFT 31
#define	_UART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL
#define	_UART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL
#define	UART_RXDOUBLEXP_FERRP1_DEFAULT (_UART_RXDOUBLEXP_FERRP1_DEFAULT << 31)
#define	_UART_TXDATAX_RESETVALUE 0x00000000UL
#define	_UART_TXDATAX_MASK 0x0000F9FFUL
#define	_UART_TXDATAX_TXDATAX_SHIFT 0
#define	_UART_TXDATAX_TXDATAX_MASK 0x1FFUL
#define	_UART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL
#define	UART_TXDATAX_TXDATAX_DEFAULT (_UART_TXDATAX_TXDATAX_DEFAULT << 0)
#define	UART_TXDATAX_UBRXAT (0x1UL << 11)
#define	_UART_TXDATAX_UBRXAT_SHIFT 11
#define	_UART_TXDATAX_UBRXAT_MASK 0x800UL
#define	_UART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL
#define	UART_TXDATAX_UBRXAT_DEFAULT (_UART_TXDATAX_UBRXAT_DEFAULT << 11)
#define	UART_TXDATAX_TXTRIAT (0x1UL << 12)
#define	_UART_TXDATAX_TXTRIAT_SHIFT 12
#define	_UART_TXDATAX_TXTRIAT_MASK 0x1000UL
#define	_UART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL
#define	UART_TXDATAX_TXTRIAT_DEFAULT (_UART_TXDATAX_TXTRIAT_DEFAULT << 12)
#define	UART_TXDATAX_TXBREAK (0x1UL << 13)
#define	_UART_TXDATAX_TXBREAK_SHIFT 13
#define	_UART_TXDATAX_TXBREAK_MASK 0x2000UL
#define	_UART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL
#define	UART_TXDATAX_TXBREAK_DEFAULT (_UART_TXDATAX_TXBREAK_DEFAULT << 13)
#define	UART_TXDATAX_TXDISAT (0x1UL << 14)
#define	_UART_TXDATAX_TXDISAT_SHIFT 14
#define	_UART_TXDATAX_TXDISAT_MASK 0x4000UL
#define	_UART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL
#define	UART_TXDATAX_TXDISAT_DEFAULT (_UART_TXDATAX_TXDISAT_DEFAULT << 14)
#define	UART_TXDATAX_RXENAT (0x1UL << 15)
#define	_UART_TXDATAX_RXENAT_SHIFT 15
#define	_UART_TXDATAX_RXENAT_MASK 0x8000UL
#define	_UART_TXDATAX_RXENAT_DEFAULT 0x00000000UL
#define	UART_TXDATAX_RXENAT_DEFAULT (_UART_TXDATAX_RXENAT_DEFAULT << 15)
#define	_UART_TXDATA_RESETVALUE 0x00000000UL
#define	_UART_TXDATA_MASK 0x000000FFUL
#define	_UART_TXDATA_TXDATA_SHIFT 0
#define	_UART_TXDATA_TXDATA_MASK 0xFFUL
#define	_UART_TXDATA_TXDATA_DEFAULT 0x00000000UL
#define	UART_TXDATA_TXDATA_DEFAULT (_UART_TXDATA_TXDATA_DEFAULT << 0)
#define	_UART_TXDOUBLEX_RESETVALUE 0x00000000UL
#define	_UART_TXDOUBLEX_MASK 0xF9FFF9FFUL
#define	_UART_TXDOUBLEX_TXDATA0_SHIFT 0
#define	_UART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL
#define	_UART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL
#define	UART_TXDOUBLEX_TXDATA0_DEFAULT (_UART_TXDOUBLEX_TXDATA0_DEFAULT << 0)
#define	UART_TXDOUBLEX_UBRXAT0 (0x1UL << 11)
#define	_UART_TXDOUBLEX_UBRXAT0_SHIFT 11
#define	_UART_TXDOUBLEX_UBRXAT0_MASK 0x800UL
#define	_UART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL
#define	UART_TXDOUBLEX_UBRXAT0_DEFAULT (_UART_TXDOUBLEX_UBRXAT0_DEFAULT << 11)
#define	UART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12)
#define	_UART_TXDOUBLEX_TXTRIAT0_SHIFT 12
#define	_UART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL
#define	_UART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL
#define	UART_TXDOUBLEX_TXTRIAT0_DEFAULT (_UART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12)
#define	UART_TXDOUBLEX_TXBREAK0 (0x1UL << 13)
#define	_UART_TXDOUBLEX_TXBREAK0_SHIFT 13
#define	_UART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL
#define	_UART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL
#define	UART_TXDOUBLEX_TXBREAK0_DEFAULT (_UART_TXDOUBLEX_TXBREAK0_DEFAULT << 13)
#define	UART_TXDOUBLEX_TXDISAT0 (0x1UL << 14)
#define	_UART_TXDOUBLEX_TXDISAT0_SHIFT 14
#define	_UART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL
#define	_UART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL
#define	UART_TXDOUBLEX_TXDISAT0_DEFAULT (_UART_TXDOUBLEX_TXDISAT0_DEFAULT << 14)
#define	UART_TXDOUBLEX_RXENAT0 (0x1UL << 15)
#define	_UART_TXDOUBLEX_RXENAT0_SHIFT 15
#define	_UART_TXDOUBLEX_RXENAT0_MASK 0x8000UL
#define	_UART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL
#define	UART_TXDOUBLEX_RXENAT0_DEFAULT (_UART_TXDOUBLEX_RXENAT0_DEFAULT << 15)
#define	_UART_TXDOUBLEX_TXDATA1_SHIFT 16
#define	_UART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL
#define	_UART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL
#define	UART_TXDOUBLEX_TXDATA1_DEFAULT (_UART_TXDOUBLEX_TXDATA1_DEFAULT << 16)
#define	UART_TXDOUBLEX_UBRXAT1 (0x1UL << 27)
#define	_UART_TXDOUBLEX_UBRXAT1_SHIFT 27
#define	_UART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL
#define	_UART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL
#define	UART_TXDOUBLEX_UBRXAT1_DEFAULT (_UART_TXDOUBLEX_UBRXAT1_DEFAULT << 27)
#define	UART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28)
#define	_UART_TXDOUBLEX_TXTRIAT1_SHIFT 28
#define	_UART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL
#define	_UART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL
#define	UART_TXDOUBLEX_TXTRIAT1_DEFAULT (_UART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28)
#define	UART_TXDOUBLEX_TXBREAK1 (0x1UL << 29)
#define	_UART_TXDOUBLEX_TXBREAK1_SHIFT 29
#define	_UART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL
#define	_UART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL
#define	UART_TXDOUBLEX_TXBREAK1_DEFAULT (_UART_TXDOUBLEX_TXBREAK1_DEFAULT << 29)
#define	UART_TXDOUBLEX_TXDISAT1 (0x1UL << 30)
#define	_UART_TXDOUBLEX_TXDISAT1_SHIFT 30
#define	_UART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL
#define	_UART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL
#define	UART_TXDOUBLEX_TXDISAT1_DEFAULT (_UART_TXDOUBLEX_TXDISAT1_DEFAULT << 30)
#define	UART_TXDOUBLEX_RXENAT1 (0x1UL << 31)
#define	_UART_TXDOUBLEX_RXENAT1_SHIFT 31
#define	_UART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL
#define	_UART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL
#define	UART_TXDOUBLEX_RXENAT1_DEFAULT (_UART_TXDOUBLEX_RXENAT1_DEFAULT << 31)
#define	_UART_TXDOUBLE_RESETVALUE 0x00000000UL
#define	_UART_TXDOUBLE_MASK 0x0000FFFFUL
#define	_UART_TXDOUBLE_TXDATA0_SHIFT 0
#define	_UART_TXDOUBLE_TXDATA0_MASK 0xFFUL
#define	_UART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL
#define	UART_TXDOUBLE_TXDATA0_DEFAULT (_UART_TXDOUBLE_TXDATA0_DEFAULT << 0)
#define	_UART_TXDOUBLE_TXDATA1_SHIFT 8
#define	_UART_TXDOUBLE_TXDATA1_MASK 0xFF00UL
#define	_UART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL
#define	UART_TXDOUBLE_TXDATA1_DEFAULT (_UART_TXDOUBLE_TXDATA1_DEFAULT << 8)
#define	_UART_IF_RESETVALUE 0x00000002UL
#define	_UART_IF_MASK 0x00001FFFUL
#define	UART_IF_TXC (0x1UL << 0)
#define	_UART_IF_TXC_SHIFT 0
#define	_UART_IF_TXC_MASK 0x1UL
#define	_UART_IF_TXC_DEFAULT 0x00000000UL
#define	UART_IF_TXC_DEFAULT (_UART_IF_TXC_DEFAULT << 0)
#define	UART_IF_TXBL (0x1UL << 1)
#define	_UART_IF_TXBL_SHIFT 1
#define	_UART_IF_TXBL_MASK 0x2UL
#define	_UART_IF_TXBL_DEFAULT 0x00000001UL
#define	UART_IF_TXBL_DEFAULT (_UART_IF_TXBL_DEFAULT << 1)
#define	UART_IF_RXDATAV (0x1UL << 2)
#define	_UART_IF_RXDATAV_SHIFT 2
#define	_UART_IF_RXDATAV_MASK 0x4UL
#define	_UART_IF_RXDATAV_DEFAULT 0x00000000UL
#define	UART_IF_RXDATAV_DEFAULT (_UART_IF_RXDATAV_DEFAULT << 2)
#define	UART_IF_RXFULL (0x1UL << 3)
#define	_UART_IF_RXFULL_SHIFT 3
#define	_UART_IF_RXFULL_MASK 0x8UL
#define	_UART_IF_RXFULL_DEFAULT 0x00000000UL
#define	UART_IF_RXFULL_DEFAULT (_UART_IF_RXFULL_DEFAULT << 3)
#define	UART_IF_RXOF (0x1UL << 4)
#define	_UART_IF_RXOF_SHIFT 4
#define	_UART_IF_RXOF_MASK 0x10UL
#define	_UART_IF_RXOF_DEFAULT 0x00000000UL
#define	UART_IF_RXOF_DEFAULT (_UART_IF_RXOF_DEFAULT << 4)
#define	UART_IF_RXUF (0x1UL << 5)
#define	_UART_IF_RXUF_SHIFT 5
#define	_UART_IF_RXUF_MASK 0x20UL
#define	_UART_IF_RXUF_DEFAULT 0x00000000UL
#define	UART_IF_RXUF_DEFAULT (_UART_IF_RXUF_DEFAULT << 5)
#define	UART_IF_TXOF (0x1UL << 6)
#define	_UART_IF_TXOF_SHIFT 6
#define	_UART_IF_TXOF_MASK 0x40UL
#define	_UART_IF_TXOF_DEFAULT 0x00000000UL
#define	UART_IF_TXOF_DEFAULT (_UART_IF_TXOF_DEFAULT << 6)
#define	UART_IF_TXUF (0x1UL << 7)
#define	_UART_IF_TXUF_SHIFT 7
#define	_UART_IF_TXUF_MASK 0x80UL
#define	_UART_IF_TXUF_DEFAULT 0x00000000UL
#define	UART_IF_TXUF_DEFAULT (_UART_IF_TXUF_DEFAULT << 7)
#define	UART_IF_PERR (0x1UL << 8)
#define	_UART_IF_PERR_SHIFT 8
#define	_UART_IF_PERR_MASK 0x100UL
#define	_UART_IF_PERR_DEFAULT 0x00000000UL
#define	UART_IF_PERR_DEFAULT (_UART_IF_PERR_DEFAULT << 8)
#define	UART_IF_FERR (0x1UL << 9)
#define	_UART_IF_FERR_SHIFT 9
#define	_UART_IF_FERR_MASK 0x200UL
#define	_UART_IF_FERR_DEFAULT 0x00000000UL
#define	UART_IF_FERR_DEFAULT (_UART_IF_FERR_DEFAULT << 9)
#define	UART_IF_MPAF (0x1UL << 10)
#define	_UART_IF_MPAF_SHIFT 10
#define	_UART_IF_MPAF_MASK 0x400UL
#define	_UART_IF_MPAF_DEFAULT 0x00000000UL
#define	UART_IF_MPAF_DEFAULT (_UART_IF_MPAF_DEFAULT << 10)
#define	UART_IF_SSM (0x1UL << 11)
#define	_UART_IF_SSM_SHIFT 11
#define	_UART_IF_SSM_MASK 0x800UL
#define	_UART_IF_SSM_DEFAULT 0x00000000UL
#define	UART_IF_SSM_DEFAULT (_UART_IF_SSM_DEFAULT << 11)
#define	UART_IF_CCF (0x1UL << 12)
#define	_UART_IF_CCF_SHIFT 12
#define	_UART_IF_CCF_MASK 0x1000UL
#define	_UART_IF_CCF_DEFAULT 0x00000000UL
#define	UART_IF_CCF_DEFAULT (_UART_IF_CCF_DEFAULT << 12)
#define	_UART_IFS_RESETVALUE 0x00000000UL
#define	_UART_IFS_MASK 0x00001FF9UL
#define	UART_IFS_TXC (0x1UL << 0)
#define	_UART_IFS_TXC_SHIFT 0
#define	_UART_IFS_TXC_MASK 0x1UL
#define	_UART_IFS_TXC_DEFAULT 0x00000000UL
#define	UART_IFS_TXC_DEFAULT (_UART_IFS_TXC_DEFAULT << 0)
#define	UART_IFS_RXFULL (0x1UL << 3)
#define	_UART_IFS_RXFULL_SHIFT 3
#define	_UART_IFS_RXFULL_MASK 0x8UL
#define	_UART_IFS_RXFULL_DEFAULT 0x00000000UL
#define	UART_IFS_RXFULL_DEFAULT (_UART_IFS_RXFULL_DEFAULT << 3)
#define	UART_IFS_RXOF (0x1UL << 4)
#define	_UART_IFS_RXOF_SHIFT 4
#define	_UART_IFS_RXOF_MASK 0x10UL
#define	_UART_IFS_RXOF_DEFAULT 0x00000000UL
#define	UART_IFS_RXOF_DEFAULT (_UART_IFS_RXOF_DEFAULT << 4)
#define	UART_IFS_RXUF (0x1UL << 5)
#define	_UART_IFS_RXUF_SHIFT 5
#define	_UART_IFS_RXUF_MASK 0x20UL
#define	_UART_IFS_RXUF_DEFAULT 0x00000000UL
#define	UART_IFS_RXUF_DEFAULT (_UART_IFS_RXUF_DEFAULT << 5)
#define	UART_IFS_TXOF (0x1UL << 6)
#define	_UART_IFS_TXOF_SHIFT 6
#define	_UART_IFS_TXOF_MASK 0x40UL
#define	_UART_IFS_TXOF_DEFAULT 0x00000000UL
#define	UART_IFS_TXOF_DEFAULT (_UART_IFS_TXOF_DEFAULT << 6)
#define	UART_IFS_TXUF (0x1UL << 7)
#define	_UART_IFS_TXUF_SHIFT 7
#define	_UART_IFS_TXUF_MASK 0x80UL
#define	_UART_IFS_TXUF_DEFAULT 0x00000000UL
#define	UART_IFS_TXUF_DEFAULT (_UART_IFS_TXUF_DEFAULT << 7)
#define	UART_IFS_PERR (0x1UL << 8)
#define	_UART_IFS_PERR_SHIFT 8
#define	_UART_IFS_PERR_MASK 0x100UL
#define	_UART_IFS_PERR_DEFAULT 0x00000000UL
#define	UART_IFS_PERR_DEFAULT (_UART_IFS_PERR_DEFAULT << 8)
#define	UART_IFS_FERR (0x1UL << 9)
#define	_UART_IFS_FERR_SHIFT 9
#define	_UART_IFS_FERR_MASK 0x200UL
#define	_UART_IFS_FERR_DEFAULT 0x00000000UL
#define	UART_IFS_FERR_DEFAULT (_UART_IFS_FERR_DEFAULT << 9)
#define	UART_IFS_MPAF (0x1UL << 10)
#define	_UART_IFS_MPAF_SHIFT 10
#define	_UART_IFS_MPAF_MASK 0x400UL
#define	_UART_IFS_MPAF_DEFAULT 0x00000000UL
#define	UART_IFS_MPAF_DEFAULT (_UART_IFS_MPAF_DEFAULT << 10)
#define	UART_IFS_SSM (0x1UL << 11)
#define	_UART_IFS_SSM_SHIFT 11
#define	_UART_IFS_SSM_MASK 0x800UL
#define	_UART_IFS_SSM_DEFAULT 0x00000000UL
#define	UART_IFS_SSM_DEFAULT (_UART_IFS_SSM_DEFAULT << 11)
#define	UART_IFS_CCF (0x1UL << 12)
#define	_UART_IFS_CCF_SHIFT 12
#define	_UART_IFS_CCF_MASK 0x1000UL
#define	_UART_IFS_CCF_DEFAULT 0x00000000UL
#define	UART_IFS_CCF_DEFAULT (_UART_IFS_CCF_DEFAULT << 12)
#define	_UART_IFC_RESETVALUE 0x00000000UL
#define	_UART_IFC_MASK 0x00001FF9UL
#define	UART_IFC_TXC (0x1UL << 0)
#define	_UART_IFC_TXC_SHIFT 0
#define	_UART_IFC_TXC_MASK 0x1UL
#define	_UART_IFC_TXC_DEFAULT 0x00000000UL
#define	UART_IFC_TXC_DEFAULT (_UART_IFC_TXC_DEFAULT << 0)
#define	UART_IFC_RXFULL (0x1UL << 3)
#define	_UART_IFC_RXFULL_SHIFT 3
#define	_UART_IFC_RXFULL_MASK 0x8UL
#define	_UART_IFC_RXFULL_DEFAULT 0x00000000UL
#define	UART_IFC_RXFULL_DEFAULT (_UART_IFC_RXFULL_DEFAULT << 3)
#define	UART_IFC_RXOF (0x1UL << 4)
#define	_UART_IFC_RXOF_SHIFT 4
#define	_UART_IFC_RXOF_MASK 0x10UL
#define	_UART_IFC_RXOF_DEFAULT 0x00000000UL
#define	UART_IFC_RXOF_DEFAULT (_UART_IFC_RXOF_DEFAULT << 4)
#define	UART_IFC_RXUF (0x1UL << 5)
#define	_UART_IFC_RXUF_SHIFT 5
#define	_UART_IFC_RXUF_MASK 0x20UL
#define	_UART_IFC_RXUF_DEFAULT 0x00000000UL
#define	UART_IFC_RXUF_DEFAULT (_UART_IFC_RXUF_DEFAULT << 5)
#define	UART_IFC_TXOF (0x1UL << 6)
#define	_UART_IFC_TXOF_SHIFT 6
#define	_UART_IFC_TXOF_MASK 0x40UL
#define	_UART_IFC_TXOF_DEFAULT 0x00000000UL
#define	UART_IFC_TXOF_DEFAULT (_UART_IFC_TXOF_DEFAULT << 6)
#define	UART_IFC_TXUF (0x1UL << 7)
#define	_UART_IFC_TXUF_SHIFT 7
#define	_UART_IFC_TXUF_MASK 0x80UL
#define	_UART_IFC_TXUF_DEFAULT 0x00000000UL
#define	UART_IFC_TXUF_DEFAULT (_UART_IFC_TXUF_DEFAULT << 7)
#define	UART_IFC_PERR (0x1UL << 8)
#define	_UART_IFC_PERR_SHIFT 8
#define	_UART_IFC_PERR_MASK 0x100UL
#define	_UART_IFC_PERR_DEFAULT 0x00000000UL
#define	UART_IFC_PERR_DEFAULT (_UART_IFC_PERR_DEFAULT << 8)
#define	UART_IFC_FERR (0x1UL << 9)
#define	_UART_IFC_FERR_SHIFT 9
#define	_UART_IFC_FERR_MASK 0x200UL
#define	_UART_IFC_FERR_DEFAULT 0x00000000UL
#define	UART_IFC_FERR_DEFAULT (_UART_IFC_FERR_DEFAULT << 9)
#define	UART_IFC_MPAF (0x1UL << 10)
#define	_UART_IFC_MPAF_SHIFT 10
#define	_UART_IFC_MPAF_MASK 0x400UL
#define	_UART_IFC_MPAF_DEFAULT 0x00000000UL
#define	UART_IFC_MPAF_DEFAULT (_UART_IFC_MPAF_DEFAULT << 10)
#define	UART_IFC_SSM (0x1UL << 11)
#define	_UART_IFC_SSM_SHIFT 11
#define	_UART_IFC_SSM_MASK 0x800UL
#define	_UART_IFC_SSM_DEFAULT 0x00000000UL
#define	UART_IFC_SSM_DEFAULT (_UART_IFC_SSM_DEFAULT << 11)
#define	UART_IFC_CCF (0x1UL << 12)
#define	_UART_IFC_CCF_SHIFT 12
#define	_UART_IFC_CCF_MASK 0x1000UL
#define	_UART_IFC_CCF_DEFAULT 0x00000000UL
#define	UART_IFC_CCF_DEFAULT (_UART_IFC_CCF_DEFAULT << 12)
#define	_UART_IEN_RESETVALUE 0x00000000UL
#define	_UART_IEN_MASK 0x00001FFFUL
#define	UART_IEN_TXC (0x1UL << 0)
#define	_UART_IEN_TXC_SHIFT 0
#define	_UART_IEN_TXC_MASK 0x1UL
#define	_UART_IEN_TXC_DEFAULT 0x00000000UL
#define	UART_IEN_TXC_DEFAULT (_UART_IEN_TXC_DEFAULT << 0)
#define	UART_IEN_TXBL (0x1UL << 1)
#define	_UART_IEN_TXBL_SHIFT 1
#define	_UART_IEN_TXBL_MASK 0x2UL
#define	_UART_IEN_TXBL_DEFAULT 0x00000000UL
#define	UART_IEN_TXBL_DEFAULT (_UART_IEN_TXBL_DEFAULT << 1)
#define	UART_IEN_RXDATAV (0x1UL << 2)
#define	_UART_IEN_RXDATAV_SHIFT 2
#define	_UART_IEN_RXDATAV_MASK 0x4UL
#define	_UART_IEN_RXDATAV_DEFAULT 0x00000000UL
#define	UART_IEN_RXDATAV_DEFAULT (_UART_IEN_RXDATAV_DEFAULT << 2)
#define	UART_IEN_RXFULL (0x1UL << 3)
#define	_UART_IEN_RXFULL_SHIFT 3
#define	_UART_IEN_RXFULL_MASK 0x8UL
#define	_UART_IEN_RXFULL_DEFAULT 0x00000000UL
#define	UART_IEN_RXFULL_DEFAULT (_UART_IEN_RXFULL_DEFAULT << 3)
#define	UART_IEN_RXOF (0x1UL << 4)
#define	_UART_IEN_RXOF_SHIFT 4
#define	_UART_IEN_RXOF_MASK 0x10UL
#define	_UART_IEN_RXOF_DEFAULT 0x00000000UL
#define	UART_IEN_RXOF_DEFAULT (_UART_IEN_RXOF_DEFAULT << 4)
#define	UART_IEN_RXUF (0x1UL << 5)
#define	_UART_IEN_RXUF_SHIFT 5
#define	_UART_IEN_RXUF_MASK 0x20UL
#define	_UART_IEN_RXUF_DEFAULT 0x00000000UL
#define	UART_IEN_RXUF_DEFAULT (_UART_IEN_RXUF_DEFAULT << 5)
#define	UART_IEN_TXOF (0x1UL << 6)
#define	_UART_IEN_TXOF_SHIFT 6
#define	_UART_IEN_TXOF_MASK 0x40UL
#define	_UART_IEN_TXOF_DEFAULT 0x00000000UL
#define	UART_IEN_TXOF_DEFAULT (_UART_IEN_TXOF_DEFAULT << 6)
#define	UART_IEN_TXUF (0x1UL << 7)
#define	_UART_IEN_TXUF_SHIFT 7
#define	_UART_IEN_TXUF_MASK 0x80UL
#define	_UART_IEN_TXUF_DEFAULT 0x00000000UL
#define	UART_IEN_TXUF_DEFAULT (_UART_IEN_TXUF_DEFAULT << 7)
#define	UART_IEN_PERR (0x1UL << 8)
#define	_UART_IEN_PERR_SHIFT 8
#define	_UART_IEN_PERR_MASK 0x100UL
#define	_UART_IEN_PERR_DEFAULT 0x00000000UL
#define	UART_IEN_PERR_DEFAULT (_UART_IEN_PERR_DEFAULT << 8)
#define	UART_IEN_FERR (0x1UL << 9)
#define	_UART_IEN_FERR_SHIFT 9
#define	_UART_IEN_FERR_MASK 0x200UL
#define	_UART_IEN_FERR_DEFAULT 0x00000000UL
#define	UART_IEN_FERR_DEFAULT (_UART_IEN_FERR_DEFAULT << 9)
#define	UART_IEN_MPAF (0x1UL << 10)
#define	_UART_IEN_MPAF_SHIFT 10
#define	_UART_IEN_MPAF_MASK 0x400UL
#define	_UART_IEN_MPAF_DEFAULT 0x00000000UL
#define	UART_IEN_MPAF_DEFAULT (_UART_IEN_MPAF_DEFAULT << 10)
#define	UART_IEN_SSM (0x1UL << 11)
#define	_UART_IEN_SSM_SHIFT 11
#define	_UART_IEN_SSM_MASK 0x800UL
#define	_UART_IEN_SSM_DEFAULT 0x00000000UL
#define	UART_IEN_SSM_DEFAULT (_UART_IEN_SSM_DEFAULT << 11)
#define	UART_IEN_CCF (0x1UL << 12)
#define	_UART_IEN_CCF_SHIFT 12
#define	_UART_IEN_CCF_MASK 0x1000UL
#define	_UART_IEN_CCF_DEFAULT 0x00000000UL
#define	UART_IEN_CCF_DEFAULT (_UART_IEN_CCF_DEFAULT << 12)
#define	_UART_IRCTRL_RESETVALUE 0x00000000UL
#define	_UART_IRCTRL_MASK 0x000000FFUL
#define	UART_IRCTRL_IREN (0x1UL << 0)
#define	_UART_IRCTRL_IREN_SHIFT 0
#define	_UART_IRCTRL_IREN_MASK 0x1UL
#define	_UART_IRCTRL_IREN_DEFAULT 0x00000000UL
#define	UART_IRCTRL_IREN_DEFAULT (_UART_IRCTRL_IREN_DEFAULT << 0)
#define	_UART_IRCTRL_IRPW_SHIFT 1
#define	_UART_IRCTRL_IRPW_MASK 0x6UL
#define	_UART_IRCTRL_IRPW_DEFAULT 0x00000000UL
#define	_UART_IRCTRL_IRPW_ONE 0x00000000UL
#define	_UART_IRCTRL_IRPW_TWO 0x00000001UL
#define	_UART_IRCTRL_IRPW_THREE 0x00000002UL
#define	_UART_IRCTRL_IRPW_FOUR 0x00000003UL
#define	UART_IRCTRL_IRPW_DEFAULT (_UART_IRCTRL_IRPW_DEFAULT << 1)
#define	UART_IRCTRL_IRPW_ONE (_UART_IRCTRL_IRPW_ONE << 1)
#define	UART_IRCTRL_IRPW_TWO (_UART_IRCTRL_IRPW_TWO << 1)
#define	UART_IRCTRL_IRPW_THREE (_UART_IRCTRL_IRPW_THREE << 1)
#define	UART_IRCTRL_IRPW_FOUR (_UART_IRCTRL_IRPW_FOUR << 1)
#define	UART_IRCTRL_IRFILT (0x1UL << 3)
#define	_UART_IRCTRL_IRFILT_SHIFT 3
#define	_UART_IRCTRL_IRFILT_MASK 0x8UL
#define	_UART_IRCTRL_IRFILT_DEFAULT 0x00000000UL
#define	UART_IRCTRL_IRFILT_DEFAULT (_UART_IRCTRL_IRFILT_DEFAULT << 3)
#define	_UART_IRCTRL_IRPRSSEL_SHIFT 4
#define	_UART_IRCTRL_IRPRSSEL_MASK 0x70UL
#define	_UART_IRCTRL_IRPRSSEL_DEFAULT 0x00000000UL
#define	_UART_IRCTRL_IRPRSSEL_PRSCH0 0x00000000UL
#define	_UART_IRCTRL_IRPRSSEL_PRSCH1 0x00000001UL
#define	_UART_IRCTRL_IRPRSSEL_PRSCH2 0x00000002UL
#define	_UART_IRCTRL_IRPRSSEL_PRSCH3 0x00000003UL
#define	_UART_IRCTRL_IRPRSSEL_PRSCH4 0x00000004UL
#define	_UART_IRCTRL_IRPRSSEL_PRSCH5 0x00000005UL
#define	_UART_IRCTRL_IRPRSSEL_PRSCH6 0x00000006UL
#define	_UART_IRCTRL_IRPRSSEL_PRSCH7 0x00000007UL
#define	UART_IRCTRL_IRPRSSEL_DEFAULT (_UART_IRCTRL_IRPRSSEL_DEFAULT << 4)
#define	UART_IRCTRL_IRPRSSEL_PRSCH0 (_UART_IRCTRL_IRPRSSEL_PRSCH0 << 4)
#define	UART_IRCTRL_IRPRSSEL_PRSCH1 (_UART_IRCTRL_IRPRSSEL_PRSCH1 << 4)
#define	UART_IRCTRL_IRPRSSEL_PRSCH2 (_UART_IRCTRL_IRPRSSEL_PRSCH2 << 4)
#define	UART_IRCTRL_IRPRSSEL_PRSCH3 (_UART_IRCTRL_IRPRSSEL_PRSCH3 << 4)
#define	UART_IRCTRL_IRPRSSEL_PRSCH4 (_UART_IRCTRL_IRPRSSEL_PRSCH4 << 4)
#define	UART_IRCTRL_IRPRSSEL_PRSCH5 (_UART_IRCTRL_IRPRSSEL_PRSCH5 << 4)
#define	UART_IRCTRL_IRPRSSEL_PRSCH6 (_UART_IRCTRL_IRPRSSEL_PRSCH6 << 4)
#define	UART_IRCTRL_IRPRSSEL_PRSCH7 (_UART_IRCTRL_IRPRSSEL_PRSCH7 << 4)
#define	UART_IRCTRL_IRPRSEN (0x1UL << 7)
#define	_UART_IRCTRL_IRPRSEN_SHIFT 7
#define	_UART_IRCTRL_IRPRSEN_MASK 0x80UL
#define	_UART_IRCTRL_IRPRSEN_DEFAULT 0x00000000UL
#define	UART_IRCTRL_IRPRSEN_DEFAULT (_UART_IRCTRL_IRPRSEN_DEFAULT << 7)
#define	_UART_ROUTE_RESETVALUE 0x00000000UL
#define	_UART_ROUTE_MASK 0x0000030FUL
#define	UART_ROUTE_RXPEN (0x1UL << 0)
#define	_UART_ROUTE_RXPEN_SHIFT 0
#define	_UART_ROUTE_RXPEN_MASK 0x1UL
#define	_UART_ROUTE_RXPEN_DEFAULT 0x00000000UL
#define	UART_ROUTE_RXPEN_DEFAULT (_UART_ROUTE_RXPEN_DEFAULT << 0)
#define	UART_ROUTE_TXPEN (0x1UL << 1)
#define	_UART_ROUTE_TXPEN_SHIFT 1
#define	_UART_ROUTE_TXPEN_MASK 0x2UL
#define	_UART_ROUTE_TXPEN_DEFAULT 0x00000000UL
#define	UART_ROUTE_TXPEN_DEFAULT (_UART_ROUTE_TXPEN_DEFAULT << 1)
#define	UART_ROUTE_CSPEN (0x1UL << 2)
#define	_UART_ROUTE_CSPEN_SHIFT 2
#define	_UART_ROUTE_CSPEN_MASK 0x4UL
#define	_UART_ROUTE_CSPEN_DEFAULT 0x00000000UL
#define	UART_ROUTE_CSPEN_DEFAULT (_UART_ROUTE_CSPEN_DEFAULT << 2)
#define	UART_ROUTE_CLKPEN (0x1UL << 3)
#define	_UART_ROUTE_CLKPEN_SHIFT 3
#define	_UART_ROUTE_CLKPEN_MASK 0x8UL
#define	_UART_ROUTE_CLKPEN_DEFAULT 0x00000000UL
#define	UART_ROUTE_CLKPEN_DEFAULT (_UART_ROUTE_CLKPEN_DEFAULT << 3)
#define	_UART_ROUTE_LOCATION_SHIFT 8
#define	_UART_ROUTE_LOCATION_MASK 0x300UL
#define	_UART_ROUTE_LOCATION_DEFAULT 0x00000000UL
#define	_UART_ROUTE_LOCATION_LOC0 0x00000000UL
#define	_UART_ROUTE_LOCATION_LOC1 0x00000001UL
#define	_UART_ROUTE_LOCATION_LOC2 0x00000002UL
#define	_UART_ROUTE_LOCATION_LOC3 0x00000003UL
#define	UART_ROUTE_LOCATION_DEFAULT (_UART_ROUTE_LOCATION_DEFAULT << 8)
#define	UART_ROUTE_LOCATION_LOC0 (_UART_ROUTE_LOCATION_LOC0 << 8)
#define	UART_ROUTE_LOCATION_LOC1 (_UART_ROUTE_LOCATION_LOC1 << 8)
#define	UART_ROUTE_LOCATION_LOC2 (_UART_ROUTE_LOCATION_LOC2 << 8)
#define	UART_ROUTE_LOCATION_LOC3 (_UART_ROUTE_LOCATION_LOC3 << 8)
#define	_LEUART_CTRL_RESETVALUE 0x00000000UL
#define	_LEUART_CTRL_MASK 0x0000FFFFUL
#define	LEUART_CTRL_AUTOTRI (0x1UL << 0)
#define	_LEUART_CTRL_AUTOTRI_SHIFT 0
#define	_LEUART_CTRL_AUTOTRI_MASK 0x1UL
#define	_LEUART_CTRL_AUTOTRI_DEFAULT 0x00000000UL
#define	LEUART_CTRL_AUTOTRI_DEFAULT (_LEUART_CTRL_AUTOTRI_DEFAULT << 0)
#define	LEUART_CTRL_DATABITS (0x1UL << 1)
#define	_LEUART_CTRL_DATABITS_SHIFT 1
#define	_LEUART_CTRL_DATABITS_MASK 0x2UL
#define	_LEUART_CTRL_DATABITS_DEFAULT 0x00000000UL
#define	_LEUART_CTRL_DATABITS_EIGHT 0x00000000UL
#define	_LEUART_CTRL_DATABITS_NINE 0x00000001UL
#define	LEUART_CTRL_DATABITS_DEFAULT (_LEUART_CTRL_DATABITS_DEFAULT << 1)
#define	LEUART_CTRL_DATABITS_EIGHT (_LEUART_CTRL_DATABITS_EIGHT << 1)
#define	LEUART_CTRL_DATABITS_NINE (_LEUART_CTRL_DATABITS_NINE << 1)
#define	_LEUART_CTRL_PARITY_SHIFT 2
#define	_LEUART_CTRL_PARITY_MASK 0xCUL
#define	_LEUART_CTRL_PARITY_DEFAULT 0x00000000UL
#define	_LEUART_CTRL_PARITY_NONE 0x00000000UL
#define	_LEUART_CTRL_PARITY_EVEN 0x00000002UL
#define	_LEUART_CTRL_PARITY_ODD 0x00000003UL
#define	LEUART_CTRL_PARITY_DEFAULT (_LEUART_CTRL_PARITY_DEFAULT << 2)
#define	LEUART_CTRL_PARITY_NONE (_LEUART_CTRL_PARITY_NONE << 2)
#define	LEUART_CTRL_PARITY_EVEN (_LEUART_CTRL_PARITY_EVEN << 2)
#define	LEUART_CTRL_PARITY_ODD (_LEUART_CTRL_PARITY_ODD << 2)
#define	LEUART_CTRL_STOPBITS (0x1UL << 4)
#define	_LEUART_CTRL_STOPBITS_SHIFT 4
#define	_LEUART_CTRL_STOPBITS_MASK 0x10UL
#define	_LEUART_CTRL_STOPBITS_DEFAULT 0x00000000UL
#define	_LEUART_CTRL_STOPBITS_ONE 0x00000000UL
#define	_LEUART_CTRL_STOPBITS_TWO 0x00000001UL
#define	LEUART_CTRL_STOPBITS_DEFAULT (_LEUART_CTRL_STOPBITS_DEFAULT << 4)
#define	LEUART_CTRL_STOPBITS_ONE (_LEUART_CTRL_STOPBITS_ONE << 4)
#define	LEUART_CTRL_STOPBITS_TWO (_LEUART_CTRL_STOPBITS_TWO << 4)
#define	LEUART_CTRL_INV (0x1UL << 5)
#define	_LEUART_CTRL_INV_SHIFT 5
#define	_LEUART_CTRL_INV_MASK 0x20UL
#define	_LEUART_CTRL_INV_DEFAULT 0x00000000UL
#define	LEUART_CTRL_INV_DEFAULT (_LEUART_CTRL_INV_DEFAULT << 5)
#define	LEUART_CTRL_ERRSDMA (0x1UL << 6)
#define	_LEUART_CTRL_ERRSDMA_SHIFT 6
#define	_LEUART_CTRL_ERRSDMA_MASK 0x40UL
#define	_LEUART_CTRL_ERRSDMA_DEFAULT 0x00000000UL
#define	LEUART_CTRL_ERRSDMA_DEFAULT (_LEUART_CTRL_ERRSDMA_DEFAULT << 6)
#define	LEUART_CTRL_LOOPBK (0x1UL << 7)
#define	_LEUART_CTRL_LOOPBK_SHIFT 7
#define	_LEUART_CTRL_LOOPBK_MASK 0x80UL
#define	_LEUART_CTRL_LOOPBK_DEFAULT 0x00000000UL
#define	LEUART_CTRL_LOOPBK_DEFAULT (_LEUART_CTRL_LOOPBK_DEFAULT << 7)
#define	LEUART_CTRL_SFUBRX (0x1UL << 8)
#define	_LEUART_CTRL_SFUBRX_SHIFT 8
#define	_LEUART_CTRL_SFUBRX_MASK 0x100UL
#define	_LEUART_CTRL_SFUBRX_DEFAULT 0x00000000UL
#define	LEUART_CTRL_SFUBRX_DEFAULT (_LEUART_CTRL_SFUBRX_DEFAULT << 8)
#define	LEUART_CTRL_MPM (0x1UL << 9)
#define	_LEUART_CTRL_MPM_SHIFT 9
#define	_LEUART_CTRL_MPM_MASK 0x200UL
#define	_LEUART_CTRL_MPM_DEFAULT 0x00000000UL
#define	LEUART_CTRL_MPM_DEFAULT (_LEUART_CTRL_MPM_DEFAULT << 9)
#define	LEUART_CTRL_MPAB (0x1UL << 10)
#define	_LEUART_CTRL_MPAB_SHIFT 10
#define	_LEUART_CTRL_MPAB_MASK 0x400UL
#define	_LEUART_CTRL_MPAB_DEFAULT 0x00000000UL
#define	LEUART_CTRL_MPAB_DEFAULT (_LEUART_CTRL_MPAB_DEFAULT << 10)
#define	LEUART_CTRL_BIT8DV (0x1UL << 11)
#define	_LEUART_CTRL_BIT8DV_SHIFT 11
#define	_LEUART_CTRL_BIT8DV_MASK 0x800UL
#define	_LEUART_CTRL_BIT8DV_DEFAULT 0x00000000UL
#define	LEUART_CTRL_BIT8DV_DEFAULT (_LEUART_CTRL_BIT8DV_DEFAULT << 11)
#define	LEUART_CTRL_RXDMAWU (0x1UL << 12)
#define	_LEUART_CTRL_RXDMAWU_SHIFT 12
#define	_LEUART_CTRL_RXDMAWU_MASK 0x1000UL
#define	_LEUART_CTRL_RXDMAWU_DEFAULT 0x00000000UL
#define	LEUART_CTRL_RXDMAWU_DEFAULT (_LEUART_CTRL_RXDMAWU_DEFAULT << 12)
#define	LEUART_CTRL_TXDMAWU (0x1UL << 13)
#define	_LEUART_CTRL_TXDMAWU_SHIFT 13
#define	_LEUART_CTRL_TXDMAWU_MASK 0x2000UL
#define	_LEUART_CTRL_TXDMAWU_DEFAULT 0x00000000UL
#define	LEUART_CTRL_TXDMAWU_DEFAULT (_LEUART_CTRL_TXDMAWU_DEFAULT << 13)
#define	_LEUART_CTRL_TXDELAY_SHIFT 14
#define	_LEUART_CTRL_TXDELAY_MASK 0xC000UL
#define	_LEUART_CTRL_TXDELAY_DEFAULT 0x00000000UL
#define	_LEUART_CTRL_TXDELAY_NONE 0x00000000UL
#define	_LEUART_CTRL_TXDELAY_SINGLE 0x00000001UL
#define	_LEUART_CTRL_TXDELAY_DOUBLE 0x00000002UL
#define	_LEUART_CTRL_TXDELAY_TRIPLE 0x00000003UL
#define	LEUART_CTRL_TXDELAY_DEFAULT (_LEUART_CTRL_TXDELAY_DEFAULT << 14)
#define	LEUART_CTRL_TXDELAY_NONE (_LEUART_CTRL_TXDELAY_NONE << 14)
#define	LEUART_CTRL_TXDELAY_SINGLE (_LEUART_CTRL_TXDELAY_SINGLE << 14)
#define	LEUART_CTRL_TXDELAY_DOUBLE (_LEUART_CTRL_TXDELAY_DOUBLE << 14)
#define	LEUART_CTRL_TXDELAY_TRIPLE (_LEUART_CTRL_TXDELAY_TRIPLE << 14)
#define	_LEUART_CMD_RESETVALUE 0x00000000UL
#define	_LEUART_CMD_MASK 0x000000FFUL
#define	LEUART_CMD_RXEN (0x1UL << 0)
#define	_LEUART_CMD_RXEN_SHIFT 0
#define	_LEUART_CMD_RXEN_MASK 0x1UL
#define	_LEUART_CMD_RXEN_DEFAULT 0x00000000UL
#define	LEUART_CMD_RXEN_DEFAULT (_LEUART_CMD_RXEN_DEFAULT << 0)
#define	LEUART_CMD_RXDIS (0x1UL << 1)
#define	_LEUART_CMD_RXDIS_SHIFT 1
#define	_LEUART_CMD_RXDIS_MASK 0x2UL
#define	_LEUART_CMD_RXDIS_DEFAULT 0x00000000UL
#define	LEUART_CMD_RXDIS_DEFAULT (_LEUART_CMD_RXDIS_DEFAULT << 1)
#define	LEUART_CMD_TXEN (0x1UL << 2)
#define	_LEUART_CMD_TXEN_SHIFT 2
#define	_LEUART_CMD_TXEN_MASK 0x4UL
#define	_LEUART_CMD_TXEN_DEFAULT 0x00000000UL
#define	LEUART_CMD_TXEN_DEFAULT (_LEUART_CMD_TXEN_DEFAULT << 2)
#define	LEUART_CMD_TXDIS (0x1UL << 3)
#define	_LEUART_CMD_TXDIS_SHIFT 3
#define	_LEUART_CMD_TXDIS_MASK 0x8UL
#define	_LEUART_CMD_TXDIS_DEFAULT 0x00000000UL
#define	LEUART_CMD_TXDIS_DEFAULT (_LEUART_CMD_TXDIS_DEFAULT << 3)
#define	LEUART_CMD_RXBLOCKEN (0x1UL << 4)
#define	_LEUART_CMD_RXBLOCKEN_SHIFT 4
#define	_LEUART_CMD_RXBLOCKEN_MASK 0x10UL
#define	_LEUART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL
#define	LEUART_CMD_RXBLOCKEN_DEFAULT (_LEUART_CMD_RXBLOCKEN_DEFAULT << 4)
#define	LEUART_CMD_RXBLOCKDIS (0x1UL << 5)
#define	_LEUART_CMD_RXBLOCKDIS_SHIFT 5
#define	_LEUART_CMD_RXBLOCKDIS_MASK 0x20UL
#define	_LEUART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL
#define	LEUART_CMD_RXBLOCKDIS_DEFAULT (_LEUART_CMD_RXBLOCKDIS_DEFAULT << 5)
#define	LEUART_CMD_CLEARTX (0x1UL << 6)
#define	_LEUART_CMD_CLEARTX_SHIFT 6
#define	_LEUART_CMD_CLEARTX_MASK 0x40UL
#define	_LEUART_CMD_CLEARTX_DEFAULT 0x00000000UL
#define	LEUART_CMD_CLEARTX_DEFAULT (_LEUART_CMD_CLEARTX_DEFAULT << 6)
#define	LEUART_CMD_CLEARRX (0x1UL << 7)
#define	_LEUART_CMD_CLEARRX_SHIFT 7
#define	_LEUART_CMD_CLEARRX_MASK 0x80UL
#define	_LEUART_CMD_CLEARRX_DEFAULT 0x00000000UL
#define	LEUART_CMD_CLEARRX_DEFAULT (_LEUART_CMD_CLEARRX_DEFAULT << 7)
#define	_LEUART_STATUS_RESETVALUE 0x00000010UL
#define	_LEUART_STATUS_MASK 0x0000003FUL
#define	LEUART_STATUS_RXENS (0x1UL << 0)
#define	_LEUART_STATUS_RXENS_SHIFT 0
#define	_LEUART_STATUS_RXENS_MASK 0x1UL
#define	_LEUART_STATUS_RXENS_DEFAULT 0x00000000UL
#define	LEUART_STATUS_RXENS_DEFAULT (_LEUART_STATUS_RXENS_DEFAULT << 0)
#define	LEUART_STATUS_TXENS (0x1UL << 1)
#define	_LEUART_STATUS_TXENS_SHIFT 1
#define	_LEUART_STATUS_TXENS_MASK 0x2UL
#define	_LEUART_STATUS_TXENS_DEFAULT 0x00000000UL
#define	LEUART_STATUS_TXENS_DEFAULT (_LEUART_STATUS_TXENS_DEFAULT << 1)
#define	LEUART_STATUS_RXBLOCK (0x1UL << 2)
#define	_LEUART_STATUS_RXBLOCK_SHIFT 2
#define	_LEUART_STATUS_RXBLOCK_MASK 0x4UL
#define	_LEUART_STATUS_RXBLOCK_DEFAULT 0x00000000UL
#define	LEUART_STATUS_RXBLOCK_DEFAULT (_LEUART_STATUS_RXBLOCK_DEFAULT << 2)
#define	LEUART_STATUS_TXC (0x1UL << 3)
#define	_LEUART_STATUS_TXC_SHIFT 3
#define	_LEUART_STATUS_TXC_MASK 0x8UL
#define	_LEUART_STATUS_TXC_DEFAULT 0x00000000UL
#define	LEUART_STATUS_TXC_DEFAULT (_LEUART_STATUS_TXC_DEFAULT << 3)
#define	LEUART_STATUS_TXBL (0x1UL << 4)
#define	_LEUART_STATUS_TXBL_SHIFT 4
#define	_LEUART_STATUS_TXBL_MASK 0x10UL
#define	_LEUART_STATUS_TXBL_DEFAULT 0x00000001UL
#define	LEUART_STATUS_TXBL_DEFAULT (_LEUART_STATUS_TXBL_DEFAULT << 4)
#define	LEUART_STATUS_RXDATAV (0x1UL << 5)
#define	_LEUART_STATUS_RXDATAV_SHIFT 5
#define	_LEUART_STATUS_RXDATAV_MASK 0x20UL
#define	_LEUART_STATUS_RXDATAV_DEFAULT 0x00000000UL
#define	LEUART_STATUS_RXDATAV_DEFAULT (_LEUART_STATUS_RXDATAV_DEFAULT << 5)
#define	_LEUART_CLKDIV_RESETVALUE 0x00000000UL
#define	_LEUART_CLKDIV_MASK 0x00007FF8UL
#define	_LEUART_CLKDIV_DIV_SHIFT 3
#define	_LEUART_CLKDIV_DIV_MASK 0x7FF8UL
#define	_LEUART_CLKDIV_DIV_DEFAULT 0x00000000UL
#define	LEUART_CLKDIV_DIV_DEFAULT (_LEUART_CLKDIV_DIV_DEFAULT << 3)
#define	_LEUART_STARTFRAME_RESETVALUE 0x00000000UL
#define	_LEUART_STARTFRAME_MASK 0x000001FFUL
#define	_LEUART_STARTFRAME_STARTFRAME_SHIFT 0
#define	_LEUART_STARTFRAME_STARTFRAME_MASK 0x1FFUL
#define	_LEUART_STARTFRAME_STARTFRAME_DEFAULT 0x00000000UL
#define	LEUART_STARTFRAME_STARTFRAME_DEFAULT (_LEUART_STARTFRAME_STARTFRAME_DEFAULT << 0)
#define	_LEUART_SIGFRAME_RESETVALUE 0x00000000UL
#define	_LEUART_SIGFRAME_MASK 0x000001FFUL
#define	_LEUART_SIGFRAME_SIGFRAME_SHIFT 0
#define	_LEUART_SIGFRAME_SIGFRAME_MASK 0x1FFUL
#define	_LEUART_SIGFRAME_SIGFRAME_DEFAULT 0x00000000UL
#define	LEUART_SIGFRAME_SIGFRAME_DEFAULT (_LEUART_SIGFRAME_SIGFRAME_DEFAULT << 0)
#define	_LEUART_RXDATAX_RESETVALUE 0x00000000UL
#define	_LEUART_RXDATAX_MASK 0x0000C1FFUL
#define	_LEUART_RXDATAX_RXDATA_SHIFT 0
#define	_LEUART_RXDATAX_RXDATA_MASK 0x1FFUL
#define	_LEUART_RXDATAX_RXDATA_DEFAULT 0x00000000UL
#define	LEUART_RXDATAX_RXDATA_DEFAULT (_LEUART_RXDATAX_RXDATA_DEFAULT << 0)
#define	LEUART_RXDATAX_PERR (0x1UL << 14)
#define	_LEUART_RXDATAX_PERR_SHIFT 14
#define	_LEUART_RXDATAX_PERR_MASK 0x4000UL
#define	_LEUART_RXDATAX_PERR_DEFAULT 0x00000000UL
#define	LEUART_RXDATAX_PERR_DEFAULT (_LEUART_RXDATAX_PERR_DEFAULT << 14)
#define	LEUART_RXDATAX_FERR (0x1UL << 15)
#define	_LEUART_RXDATAX_FERR_SHIFT 15
#define	_LEUART_RXDATAX_FERR_MASK 0x8000UL
#define	_LEUART_RXDATAX_FERR_DEFAULT 0x00000000UL
#define	LEUART_RXDATAX_FERR_DEFAULT (_LEUART_RXDATAX_FERR_DEFAULT << 15)
#define	_LEUART_RXDATA_RESETVALUE 0x00000000UL
#define	_LEUART_RXDATA_MASK 0x000000FFUL
#define	_LEUART_RXDATA_RXDATA_SHIFT 0
#define	_LEUART_RXDATA_RXDATA_MASK 0xFFUL
#define	_LEUART_RXDATA_RXDATA_DEFAULT 0x00000000UL
#define	LEUART_RXDATA_RXDATA_DEFAULT (_LEUART_RXDATA_RXDATA_DEFAULT << 0)
#define	_LEUART_RXDATAXP_RESETVALUE 0x00000000UL
#define	_LEUART_RXDATAXP_MASK 0x0000C1FFUL
#define	_LEUART_RXDATAXP_RXDATAP_SHIFT 0
#define	_LEUART_RXDATAXP_RXDATAP_MASK 0x1FFUL
#define	_LEUART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL
#define	LEUART_RXDATAXP_RXDATAP_DEFAULT (_LEUART_RXDATAXP_RXDATAP_DEFAULT << 0)
#define	LEUART_RXDATAXP_PERRP (0x1UL << 14)
#define	_LEUART_RXDATAXP_PERRP_SHIFT 14
#define	_LEUART_RXDATAXP_PERRP_MASK 0x4000UL
#define	_LEUART_RXDATAXP_PERRP_DEFAULT 0x00000000UL
#define	LEUART_RXDATAXP_PERRP_DEFAULT (_LEUART_RXDATAXP_PERRP_DEFAULT << 14)
#define	LEUART_RXDATAXP_FERRP (0x1UL << 15)
#define	_LEUART_RXDATAXP_FERRP_SHIFT 15
#define	_LEUART_RXDATAXP_FERRP_MASK 0x8000UL
#define	_LEUART_RXDATAXP_FERRP_DEFAULT 0x00000000UL
#define	LEUART_RXDATAXP_FERRP_DEFAULT (_LEUART_RXDATAXP_FERRP_DEFAULT << 15)
#define	_LEUART_TXDATAX_RESETVALUE 0x00000000UL
#define	_LEUART_TXDATAX_MASK 0x0000E1FFUL
#define	_LEUART_TXDATAX_TXDATA_SHIFT 0
#define	_LEUART_TXDATAX_TXDATA_MASK 0x1FFUL
#define	_LEUART_TXDATAX_TXDATA_DEFAULT 0x00000000UL
#define	LEUART_TXDATAX_TXDATA_DEFAULT (_LEUART_TXDATAX_TXDATA_DEFAULT << 0)
#define	LEUART_TXDATAX_TXBREAK (0x1UL << 13)
#define	_LEUART_TXDATAX_TXBREAK_SHIFT 13
#define	_LEUART_TXDATAX_TXBREAK_MASK 0x2000UL
#define	_LEUART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL
#define	LEUART_TXDATAX_TXBREAK_DEFAULT (_LEUART_TXDATAX_TXBREAK_DEFAULT << 13)
#define	LEUART_TXDATAX_TXDISAT (0x1UL << 14)
#define	_LEUART_TXDATAX_TXDISAT_SHIFT 14
#define	_LEUART_TXDATAX_TXDISAT_MASK 0x4000UL
#define	_LEUART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL
#define	LEUART_TXDATAX_TXDISAT_DEFAULT (_LEUART_TXDATAX_TXDISAT_DEFAULT << 14)
#define	LEUART_TXDATAX_RXENAT (0x1UL << 15)
#define	_LEUART_TXDATAX_RXENAT_SHIFT 15
#define	_LEUART_TXDATAX_RXENAT_MASK 0x8000UL
#define	_LEUART_TXDATAX_RXENAT_DEFAULT 0x00000000UL
#define	LEUART_TXDATAX_RXENAT_DEFAULT (_LEUART_TXDATAX_RXENAT_DEFAULT << 15)
#define	_LEUART_TXDATA_RESETVALUE 0x00000000UL
#define	_LEUART_TXDATA_MASK 0x000000FFUL
#define	_LEUART_TXDATA_TXDATA_SHIFT 0
#define	_LEUART_TXDATA_TXDATA_MASK 0xFFUL
#define	_LEUART_TXDATA_TXDATA_DEFAULT 0x00000000UL
#define	LEUART_TXDATA_TXDATA_DEFAULT (_LEUART_TXDATA_TXDATA_DEFAULT << 0)
#define	_LEUART_IF_RESETVALUE 0x00000002UL
#define	_LEUART_IF_MASK 0x000007FFUL
#define	LEUART_IF_TXC (0x1UL << 0)
#define	_LEUART_IF_TXC_SHIFT 0
#define	_LEUART_IF_TXC_MASK 0x1UL
#define	_LEUART_IF_TXC_DEFAULT 0x00000000UL
#define	LEUART_IF_TXC_DEFAULT (_LEUART_IF_TXC_DEFAULT << 0)
#define	LEUART_IF_TXBL (0x1UL << 1)
#define	_LEUART_IF_TXBL_SHIFT 1
#define	_LEUART_IF_TXBL_MASK 0x2UL
#define	_LEUART_IF_TXBL_DEFAULT 0x00000001UL
#define	LEUART_IF_TXBL_DEFAULT (_LEUART_IF_TXBL_DEFAULT << 1)
#define	LEUART_IF_RXDATAV (0x1UL << 2)
#define	_LEUART_IF_RXDATAV_SHIFT 2
#define	_LEUART_IF_RXDATAV_MASK 0x4UL
#define	_LEUART_IF_RXDATAV_DEFAULT 0x00000000UL
#define	LEUART_IF_RXDATAV_DEFAULT (_LEUART_IF_RXDATAV_DEFAULT << 2)
#define	LEUART_IF_RXOF (0x1UL << 3)
#define	_LEUART_IF_RXOF_SHIFT 3
#define	_LEUART_IF_RXOF_MASK 0x8UL
#define	_LEUART_IF_RXOF_DEFAULT 0x00000000UL
#define	LEUART_IF_RXOF_DEFAULT (_LEUART_IF_RXOF_DEFAULT << 3)
#define	LEUART_IF_RXUF (0x1UL << 4)
#define	_LEUART_IF_RXUF_SHIFT 4
#define	_LEUART_IF_RXUF_MASK 0x10UL
#define	_LEUART_IF_RXUF_DEFAULT 0x00000000UL
#define	LEUART_IF_RXUF_DEFAULT (_LEUART_IF_RXUF_DEFAULT << 4)
#define	LEUART_IF_TXOF (0x1UL << 5)
#define	_LEUART_IF_TXOF_SHIFT 5
#define	_LEUART_IF_TXOF_MASK 0x20UL
#define	_LEUART_IF_TXOF_DEFAULT 0x00000000UL
#define	LEUART_IF_TXOF_DEFAULT (_LEUART_IF_TXOF_DEFAULT << 5)
#define	LEUART_IF_PERR (0x1UL << 6)
#define	_LEUART_IF_PERR_SHIFT 6
#define	_LEUART_IF_PERR_MASK 0x40UL
#define	_LEUART_IF_PERR_DEFAULT 0x00000000UL
#define	LEUART_IF_PERR_DEFAULT (_LEUART_IF_PERR_DEFAULT << 6)
#define	LEUART_IF_FERR (0x1UL << 7)
#define	_LEUART_IF_FERR_SHIFT 7
#define	_LEUART_IF_FERR_MASK 0x80UL
#define	_LEUART_IF_FERR_DEFAULT 0x00000000UL
#define	LEUART_IF_FERR_DEFAULT (_LEUART_IF_FERR_DEFAULT << 7)
#define	LEUART_IF_MPAF (0x1UL << 8)
#define	_LEUART_IF_MPAF_SHIFT 8
#define	_LEUART_IF_MPAF_MASK 0x100UL
#define	_LEUART_IF_MPAF_DEFAULT 0x00000000UL
#define	LEUART_IF_MPAF_DEFAULT (_LEUART_IF_MPAF_DEFAULT << 8)
#define	LEUART_IF_STARTF (0x1UL << 9)
#define	_LEUART_IF_STARTF_SHIFT 9
#define	_LEUART_IF_STARTF_MASK 0x200UL
#define	_LEUART_IF_STARTF_DEFAULT 0x00000000UL
#define	LEUART_IF_STARTF_DEFAULT (_LEUART_IF_STARTF_DEFAULT << 9)
#define	LEUART_IF_SIGF (0x1UL << 10)
#define	_LEUART_IF_SIGF_SHIFT 10
#define	_LEUART_IF_SIGF_MASK 0x400UL
#define	_LEUART_IF_SIGF_DEFAULT 0x00000000UL
#define	LEUART_IF_SIGF_DEFAULT (_LEUART_IF_SIGF_DEFAULT << 10)
#define	_LEUART_IFS_RESETVALUE 0x00000000UL
#define	_LEUART_IFS_MASK 0x000007F9UL
#define	LEUART_IFS_TXC (0x1UL << 0)
#define	_LEUART_IFS_TXC_SHIFT 0
#define	_LEUART_IFS_TXC_MASK 0x1UL
#define	_LEUART_IFS_TXC_DEFAULT 0x00000000UL
#define	LEUART_IFS_TXC_DEFAULT (_LEUART_IFS_TXC_DEFAULT << 0)
#define	LEUART_IFS_RXOF (0x1UL << 3)
#define	_LEUART_IFS_RXOF_SHIFT 3
#define	_LEUART_IFS_RXOF_MASK 0x8UL
#define	_LEUART_IFS_RXOF_DEFAULT 0x00000000UL
#define	LEUART_IFS_RXOF_DEFAULT (_LEUART_IFS_RXOF_DEFAULT << 3)
#define	LEUART_IFS_RXUF (0x1UL << 4)
#define	_LEUART_IFS_RXUF_SHIFT 4
#define	_LEUART_IFS_RXUF_MASK 0x10UL
#define	_LEUART_IFS_RXUF_DEFAULT 0x00000000UL
#define	LEUART_IFS_RXUF_DEFAULT (_LEUART_IFS_RXUF_DEFAULT << 4)
#define	LEUART_IFS_TXOF (0x1UL << 5)
#define	_LEUART_IFS_TXOF_SHIFT 5
#define	_LEUART_IFS_TXOF_MASK 0x20UL
#define	_LEUART_IFS_TXOF_DEFAULT 0x00000000UL
#define	LEUART_IFS_TXOF_DEFAULT (_LEUART_IFS_TXOF_DEFAULT << 5)
#define	LEUART_IFS_PERR (0x1UL << 6)
#define	_LEUART_IFS_PERR_SHIFT 6
#define	_LEUART_IFS_PERR_MASK 0x40UL
#define	_LEUART_IFS_PERR_DEFAULT 0x00000000UL
#define	LEUART_IFS_PERR_DEFAULT (_LEUART_IFS_PERR_DEFAULT << 6)
#define	LEUART_IFS_FERR (0x1UL << 7)
#define	_LEUART_IFS_FERR_SHIFT 7
#define	_LEUART_IFS_FERR_MASK 0x80UL
#define	_LEUART_IFS_FERR_DEFAULT 0x00000000UL
#define	LEUART_IFS_FERR_DEFAULT (_LEUART_IFS_FERR_DEFAULT << 7)
#define	LEUART_IFS_MPAF (0x1UL << 8)
#define	_LEUART_IFS_MPAF_SHIFT 8
#define	_LEUART_IFS_MPAF_MASK 0x100UL
#define	_LEUART_IFS_MPAF_DEFAULT 0x00000000UL
#define	LEUART_IFS_MPAF_DEFAULT (_LEUART_IFS_MPAF_DEFAULT << 8)
#define	LEUART_IFS_STARTF (0x1UL << 9)
#define	_LEUART_IFS_STARTF_SHIFT 9
#define	_LEUART_IFS_STARTF_MASK 0x200UL
#define	_LEUART_IFS_STARTF_DEFAULT 0x00000000UL
#define	LEUART_IFS_STARTF_DEFAULT (_LEUART_IFS_STARTF_DEFAULT << 9)
#define	LEUART_IFS_SIGF (0x1UL << 10)
#define	_LEUART_IFS_SIGF_SHIFT 10
#define	_LEUART_IFS_SIGF_MASK 0x400UL
#define	_LEUART_IFS_SIGF_DEFAULT 0x00000000UL
#define	LEUART_IFS_SIGF_DEFAULT (_LEUART_IFS_SIGF_DEFAULT << 10)
#define	_LEUART_IFC_RESETVALUE 0x00000000UL
#define	_LEUART_IFC_MASK 0x000007F9UL
#define	LEUART_IFC_TXC (0x1UL << 0)
#define	_LEUART_IFC_TXC_SHIFT 0
#define	_LEUART_IFC_TXC_MASK 0x1UL
#define	_LEUART_IFC_TXC_DEFAULT 0x00000000UL
#define	LEUART_IFC_TXC_DEFAULT (_LEUART_IFC_TXC_DEFAULT << 0)
#define	LEUART_IFC_RXOF (0x1UL << 3)
#define	_LEUART_IFC_RXOF_SHIFT 3
#define	_LEUART_IFC_RXOF_MASK 0x8UL
#define	_LEUART_IFC_RXOF_DEFAULT 0x00000000UL
#define	LEUART_IFC_RXOF_DEFAULT (_LEUART_IFC_RXOF_DEFAULT << 3)
#define	LEUART_IFC_RXUF (0x1UL << 4)
#define	_LEUART_IFC_RXUF_SHIFT 4
#define	_LEUART_IFC_RXUF_MASK 0x10UL
#define	_LEUART_IFC_RXUF_DEFAULT 0x00000000UL
#define	LEUART_IFC_RXUF_DEFAULT (_LEUART_IFC_RXUF_DEFAULT << 4)
#define	LEUART_IFC_TXOF (0x1UL << 5)
#define	_LEUART_IFC_TXOF_SHIFT 5
#define	_LEUART_IFC_TXOF_MASK 0x20UL
#define	_LEUART_IFC_TXOF_DEFAULT 0x00000000UL
#define	LEUART_IFC_TXOF_DEFAULT (_LEUART_IFC_TXOF_DEFAULT << 5)
#define	LEUART_IFC_PERR (0x1UL << 6)
#define	_LEUART_IFC_PERR_SHIFT 6
#define	_LEUART_IFC_PERR_MASK 0x40UL
#define	_LEUART_IFC_PERR_DEFAULT 0x00000000UL
#define	LEUART_IFC_PERR_DEFAULT (_LEUART_IFC_PERR_DEFAULT << 6)
#define	LEUART_IFC_FERR (0x1UL << 7)
#define	_LEUART_IFC_FERR_SHIFT 7
#define	_LEUART_IFC_FERR_MASK 0x80UL
#define	_LEUART_IFC_FERR_DEFAULT 0x00000000UL
#define	LEUART_IFC_FERR_DEFAULT (_LEUART_IFC_FERR_DEFAULT << 7)
#define	LEUART_IFC_MPAF (0x1UL << 8)
#define	_LEUART_IFC_MPAF_SHIFT 8
#define	_LEUART_IFC_MPAF_MASK 0x100UL
#define	_LEUART_IFC_MPAF_DEFAULT 0x00000000UL
#define	LEUART_IFC_MPAF_DEFAULT (_LEUART_IFC_MPAF_DEFAULT << 8)
#define	LEUART_IFC_STARTF (0x1UL << 9)
#define	_LEUART_IFC_STARTF_SHIFT 9
#define	_LEUART_IFC_STARTF_MASK 0x200UL
#define	_LEUART_IFC_STARTF_DEFAULT 0x00000000UL
#define	LEUART_IFC_STARTF_DEFAULT (_LEUART_IFC_STARTF_DEFAULT << 9)
#define	LEUART_IFC_SIGF (0x1UL << 10)
#define	_LEUART_IFC_SIGF_SHIFT 10
#define	_LEUART_IFC_SIGF_MASK 0x400UL
#define	_LEUART_IFC_SIGF_DEFAULT 0x00000000UL
#define	LEUART_IFC_SIGF_DEFAULT (_LEUART_IFC_SIGF_DEFAULT << 10)
#define	_LEUART_IEN_RESETVALUE 0x00000000UL
#define	_LEUART_IEN_MASK 0x000007FFUL
#define	LEUART_IEN_TXC (0x1UL << 0)
#define	_LEUART_IEN_TXC_SHIFT 0
#define	_LEUART_IEN_TXC_MASK 0x1UL
#define	_LEUART_IEN_TXC_DEFAULT 0x00000000UL
#define	LEUART_IEN_TXC_DEFAULT (_LEUART_IEN_TXC_DEFAULT << 0)
#define	LEUART_IEN_TXBL (0x1UL << 1)
#define	_LEUART_IEN_TXBL_SHIFT 1
#define	_LEUART_IEN_TXBL_MASK 0x2UL
#define	_LEUART_IEN_TXBL_DEFAULT 0x00000000UL
#define	LEUART_IEN_TXBL_DEFAULT (_LEUART_IEN_TXBL_DEFAULT << 1)
#define	LEUART_IEN_RXDATAV (0x1UL << 2)
#define	_LEUART_IEN_RXDATAV_SHIFT 2
#define	_LEUART_IEN_RXDATAV_MASK 0x4UL
#define	_LEUART_IEN_RXDATAV_DEFAULT 0x00000000UL
#define	LEUART_IEN_RXDATAV_DEFAULT (_LEUART_IEN_RXDATAV_DEFAULT << 2)
#define	LEUART_IEN_RXOF (0x1UL << 3)
#define	_LEUART_IEN_RXOF_SHIFT 3
#define	_LEUART_IEN_RXOF_MASK 0x8UL
#define	_LEUART_IEN_RXOF_DEFAULT 0x00000000UL
#define	LEUART_IEN_RXOF_DEFAULT (_LEUART_IEN_RXOF_DEFAULT << 3)
#define	LEUART_IEN_RXUF (0x1UL << 4)
#define	_LEUART_IEN_RXUF_SHIFT 4
#define	_LEUART_IEN_RXUF_MASK 0x10UL
#define	_LEUART_IEN_RXUF_DEFAULT 0x00000000UL
#define	LEUART_IEN_RXUF_DEFAULT (_LEUART_IEN_RXUF_DEFAULT << 4)
#define	LEUART_IEN_TXOF (0x1UL << 5)
#define	_LEUART_IEN_TXOF_SHIFT 5
#define	_LEUART_IEN_TXOF_MASK 0x20UL
#define	_LEUART_IEN_TXOF_DEFAULT 0x00000000UL
#define	LEUART_IEN_TXOF_DEFAULT (_LEUART_IEN_TXOF_DEFAULT << 5)
#define	LEUART_IEN_PERR (0x1UL << 6)
#define	_LEUART_IEN_PERR_SHIFT 6
#define	_LEUART_IEN_PERR_MASK 0x40UL
#define	_LEUART_IEN_PERR_DEFAULT 0x00000000UL
#define	LEUART_IEN_PERR_DEFAULT (_LEUART_IEN_PERR_DEFAULT << 6)
#define	LEUART_IEN_FERR (0x1UL << 7)
#define	_LEUART_IEN_FERR_SHIFT 7
#define	_LEUART_IEN_FERR_MASK 0x80UL
#define	_LEUART_IEN_FERR_DEFAULT 0x00000000UL
#define	LEUART_IEN_FERR_DEFAULT (_LEUART_IEN_FERR_DEFAULT << 7)
#define	LEUART_IEN_MPAF (0x1UL << 8)
#define	_LEUART_IEN_MPAF_SHIFT 8
#define	_LEUART_IEN_MPAF_MASK 0x100UL
#define	_LEUART_IEN_MPAF_DEFAULT 0x00000000UL
#define	LEUART_IEN_MPAF_DEFAULT (_LEUART_IEN_MPAF_DEFAULT << 8)
#define	LEUART_IEN_STARTF (0x1UL << 9)
#define	_LEUART_IEN_STARTF_SHIFT 9
#define	_LEUART_IEN_STARTF_MASK 0x200UL
#define	_LEUART_IEN_STARTF_DEFAULT 0x00000000UL
#define	LEUART_IEN_STARTF_DEFAULT (_LEUART_IEN_STARTF_DEFAULT << 9)
#define	LEUART_IEN_SIGF (0x1UL << 10)
#define	_LEUART_IEN_SIGF_SHIFT 10
#define	_LEUART_IEN_SIGF_MASK 0x400UL
#define	_LEUART_IEN_SIGF_DEFAULT 0x00000000UL
#define	LEUART_IEN_SIGF_DEFAULT (_LEUART_IEN_SIGF_DEFAULT << 10)
#define	_LEUART_PULSECTRL_RESETVALUE 0x00000000UL
#define	_LEUART_PULSECTRL_MASK 0x0000003FUL
#define	_LEUART_PULSECTRL_PULSEW_SHIFT 0
#define	_LEUART_PULSECTRL_PULSEW_MASK 0xFUL
#define	_LEUART_PULSECTRL_PULSEW_DEFAULT 0x00000000UL
#define	LEUART_PULSECTRL_PULSEW_DEFAULT (_LEUART_PULSECTRL_PULSEW_DEFAULT << 0)
#define	LEUART_PULSECTRL_PULSEEN (0x1UL << 4)
#define	_LEUART_PULSECTRL_PULSEEN_SHIFT 4
#define	_LEUART_PULSECTRL_PULSEEN_MASK 0x10UL
#define	_LEUART_PULSECTRL_PULSEEN_DEFAULT 0x00000000UL
#define	LEUART_PULSECTRL_PULSEEN_DEFAULT (_LEUART_PULSECTRL_PULSEEN_DEFAULT << 4)
#define	LEUART_PULSECTRL_PULSEFILT (0x1UL << 5)
#define	_LEUART_PULSECTRL_PULSEFILT_SHIFT 5
#define	_LEUART_PULSECTRL_PULSEFILT_MASK 0x20UL
#define	_LEUART_PULSECTRL_PULSEFILT_DEFAULT 0x00000000UL
#define	LEUART_PULSECTRL_PULSEFILT_DEFAULT (_LEUART_PULSECTRL_PULSEFILT_DEFAULT << 5)
#define	_LEUART_FREEZE_RESETVALUE 0x00000000UL
#define	_LEUART_FREEZE_MASK 0x00000001UL
#define	LEUART_FREEZE_REGFREEZE (0x1UL << 0)
#define	_LEUART_FREEZE_REGFREEZE_SHIFT 0
#define	_LEUART_FREEZE_REGFREEZE_MASK 0x1UL
#define	_LEUART_FREEZE_REGFREEZE_DEFAULT 0x00000000UL
#define	_LEUART_FREEZE_REGFREEZE_UPDATE 0x00000000UL
#define	_LEUART_FREEZE_REGFREEZE_FREEZE 0x00000001UL
#define	LEUART_FREEZE_REGFREEZE_DEFAULT (_LEUART_FREEZE_REGFREEZE_DEFAULT << 0)
#define	LEUART_FREEZE_REGFREEZE_UPDATE (_LEUART_FREEZE_REGFREEZE_UPDATE << 0)
#define	LEUART_FREEZE_REGFREEZE_FREEZE (_LEUART_FREEZE_REGFREEZE_FREEZE << 0)
#define	_LEUART_SYNCBUSY_RESETVALUE 0x00000000UL
#define	_LEUART_SYNCBUSY_MASK 0x000000FFUL
#define	LEUART_SYNCBUSY_CTRL (0x1UL << 0)
#define	_LEUART_SYNCBUSY_CTRL_SHIFT 0
#define	_LEUART_SYNCBUSY_CTRL_MASK 0x1UL
#define	_LEUART_SYNCBUSY_CTRL_DEFAULT 0x00000000UL
#define	LEUART_SYNCBUSY_CTRL_DEFAULT (_LEUART_SYNCBUSY_CTRL_DEFAULT << 0)
#define	LEUART_SYNCBUSY_CMD (0x1UL << 1)
#define	_LEUART_SYNCBUSY_CMD_SHIFT 1
#define	_LEUART_SYNCBUSY_CMD_MASK 0x2UL
#define	_LEUART_SYNCBUSY_CMD_DEFAULT 0x00000000UL
#define	LEUART_SYNCBUSY_CMD_DEFAULT (_LEUART_SYNCBUSY_CMD_DEFAULT << 1)
#define	LEUART_SYNCBUSY_CLKDIV (0x1UL << 2)
#define	_LEUART_SYNCBUSY_CLKDIV_SHIFT 2
#define	_LEUART_SYNCBUSY_CLKDIV_MASK 0x4UL
#define	_LEUART_SYNCBUSY_CLKDIV_DEFAULT 0x00000000UL
#define	LEUART_SYNCBUSY_CLKDIV_DEFAULT (_LEUART_SYNCBUSY_CLKDIV_DEFAULT << 2)
#define	LEUART_SYNCBUSY_STARTFRAME (0x1UL << 3)
#define	_LEUART_SYNCBUSY_STARTFRAME_SHIFT 3
#define	_LEUART_SYNCBUSY_STARTFRAME_MASK 0x8UL
#define	_LEUART_SYNCBUSY_STARTFRAME_DEFAULT 0x00000000UL
#define	LEUART_SYNCBUSY_STARTFRAME_DEFAULT (_LEUART_SYNCBUSY_STARTFRAME_DEFAULT << 3)
#define	LEUART_SYNCBUSY_SIGFRAME (0x1UL << 4)
#define	_LEUART_SYNCBUSY_SIGFRAME_SHIFT 4
#define	_LEUART_SYNCBUSY_SIGFRAME_MASK 0x10UL
#define	_LEUART_SYNCBUSY_SIGFRAME_DEFAULT 0x00000000UL
#define	LEUART_SYNCBUSY_SIGFRAME_DEFAULT (_LEUART_SYNCBUSY_SIGFRAME_DEFAULT << 4)
#define	LEUART_SYNCBUSY_TXDATAX (0x1UL << 5)
#define	_LEUART_SYNCBUSY_TXDATAX_SHIFT 5
#define	_LEUART_SYNCBUSY_TXDATAX_MASK 0x20UL
#define	_LEUART_SYNCBUSY_TXDATAX_DEFAULT 0x00000000UL
#define	LEUART_SYNCBUSY_TXDATAX_DEFAULT (_LEUART_SYNCBUSY_TXDATAX_DEFAULT << 5)
#define	LEUART_SYNCBUSY_TXDATA (0x1UL << 6)
#define	_LEUART_SYNCBUSY_TXDATA_SHIFT 6
#define	_LEUART_SYNCBUSY_TXDATA_MASK 0x40UL
#define	_LEUART_SYNCBUSY_TXDATA_DEFAULT 0x00000000UL
#define	LEUART_SYNCBUSY_TXDATA_DEFAULT (_LEUART_SYNCBUSY_TXDATA_DEFAULT << 6)
#define	LEUART_SYNCBUSY_PULSECTRL (0x1UL << 7)
#define	_LEUART_SYNCBUSY_PULSECTRL_SHIFT 7
#define	_LEUART_SYNCBUSY_PULSECTRL_MASK 0x80UL
#define	_LEUART_SYNCBUSY_PULSECTRL_DEFAULT 0x00000000UL
#define	LEUART_SYNCBUSY_PULSECTRL_DEFAULT (_LEUART_SYNCBUSY_PULSECTRL_DEFAULT << 7)
#define	_LEUART_ROUTE_RESETVALUE 0x00000000UL
#define	_LEUART_ROUTE_MASK 0x00000303UL
#define	LEUART_ROUTE_RXPEN (0x1UL << 0)
#define	_LEUART_ROUTE_RXPEN_SHIFT 0
#define	_LEUART_ROUTE_RXPEN_MASK 0x1UL
#define	_LEUART_ROUTE_RXPEN_DEFAULT 0x00000000UL
#define	LEUART_ROUTE_RXPEN_DEFAULT (_LEUART_ROUTE_RXPEN_DEFAULT << 0)
#define	LEUART_ROUTE_TXPEN (0x1UL << 1)
#define	_LEUART_ROUTE_TXPEN_SHIFT 1
#define	_LEUART_ROUTE_TXPEN_MASK 0x2UL
#define	_LEUART_ROUTE_TXPEN_DEFAULT 0x00000000UL
#define	LEUART_ROUTE_TXPEN_DEFAULT (_LEUART_ROUTE_TXPEN_DEFAULT << 1)
#define	_LEUART_ROUTE_LOCATION_SHIFT 8
#define	_LEUART_ROUTE_LOCATION_MASK 0x300UL
#define	_LEUART_ROUTE_LOCATION_DEFAULT 0x00000000UL
#define	_LEUART_ROUTE_LOCATION_LOC0 0x00000000UL
#define	_LEUART_ROUTE_LOCATION_LOC1 0x00000001UL
#define	_LEUART_ROUTE_LOCATION_LOC2 0x00000002UL
#define	_LEUART_ROUTE_LOCATION_LOC3 0x00000003UL
#define	LEUART_ROUTE_LOCATION_DEFAULT (_LEUART_ROUTE_LOCATION_DEFAULT << 8)
#define	LEUART_ROUTE_LOCATION_LOC0 (_LEUART_ROUTE_LOCATION_LOC0 << 8)
#define	LEUART_ROUTE_LOCATION_LOC1 (_LEUART_ROUTE_LOCATION_LOC1 << 8)
#define	LEUART_ROUTE_LOCATION_LOC2 (_LEUART_ROUTE_LOCATION_LOC2 << 8)
#define	LEUART_ROUTE_LOCATION_LOC3 (_LEUART_ROUTE_LOCATION_LOC3 << 8)
#define	_LETIMER_CTRL_RESETVALUE 0x00000000UL
#define	_LETIMER_CTRL_MASK 0x00001FFFUL
#define	_LETIMER_CTRL_REPMODE_SHIFT 0
#define	_LETIMER_CTRL_REPMODE_MASK 0x3UL
#define	_LETIMER_CTRL_REPMODE_DEFAULT 0x00000000UL
#define	_LETIMER_CTRL_REPMODE_FREE 0x00000000UL
#define	_LETIMER_CTRL_REPMODE_ONESHOT 0x00000001UL
#define	_LETIMER_CTRL_REPMODE_BUFFERED 0x00000002UL
#define	_LETIMER_CTRL_REPMODE_DOUBLE 0x00000003UL
#define	LETIMER_CTRL_REPMODE_DEFAULT (_LETIMER_CTRL_REPMODE_DEFAULT << 0)
#define	LETIMER_CTRL_REPMODE_FREE (_LETIMER_CTRL_REPMODE_FREE << 0)
#define	LETIMER_CTRL_REPMODE_ONESHOT (_LETIMER_CTRL_REPMODE_ONESHOT << 0)
#define	LETIMER_CTRL_REPMODE_BUFFERED (_LETIMER_CTRL_REPMODE_BUFFERED << 0)
#define	LETIMER_CTRL_REPMODE_DOUBLE (_LETIMER_CTRL_REPMODE_DOUBLE << 0)
#define	_LETIMER_CTRL_UFOA0_SHIFT 2
#define	_LETIMER_CTRL_UFOA0_MASK 0xCUL
#define	_LETIMER_CTRL_UFOA0_DEFAULT 0x00000000UL
#define	_LETIMER_CTRL_UFOA0_NONE 0x00000000UL
#define	_LETIMER_CTRL_UFOA0_TOGGLE 0x00000001UL
#define	_LETIMER_CTRL_UFOA0_PULSE 0x00000002UL
#define	_LETIMER_CTRL_UFOA0_PWM 0x00000003UL
#define	LETIMER_CTRL_UFOA0_DEFAULT (_LETIMER_CTRL_UFOA0_DEFAULT << 2)
#define	LETIMER_CTRL_UFOA0_NONE (_LETIMER_CTRL_UFOA0_NONE << 2)
#define	LETIMER_CTRL_UFOA0_TOGGLE (_LETIMER_CTRL_UFOA0_TOGGLE << 2)
#define	LETIMER_CTRL_UFOA0_PULSE (_LETIMER_CTRL_UFOA0_PULSE << 2)
#define	LETIMER_CTRL_UFOA0_PWM (_LETIMER_CTRL_UFOA0_PWM << 2)
#define	_LETIMER_CTRL_UFOA1_SHIFT 4
#define	_LETIMER_CTRL_UFOA1_MASK 0x30UL
#define	_LETIMER_CTRL_UFOA1_DEFAULT 0x00000000UL
#define	_LETIMER_CTRL_UFOA1_NONE 0x00000000UL
#define	_LETIMER_CTRL_UFOA1_TOGGLE 0x00000001UL
#define	_LETIMER_CTRL_UFOA1_PULSE 0x00000002UL
#define	_LETIMER_CTRL_UFOA1_PWM 0x00000003UL
#define	LETIMER_CTRL_UFOA1_DEFAULT (_LETIMER_CTRL_UFOA1_DEFAULT << 4)
#define	LETIMER_CTRL_UFOA1_NONE (_LETIMER_CTRL_UFOA1_NONE << 4)
#define	LETIMER_CTRL_UFOA1_TOGGLE (_LETIMER_CTRL_UFOA1_TOGGLE << 4)
#define	LETIMER_CTRL_UFOA1_PULSE (_LETIMER_CTRL_UFOA1_PULSE << 4)
#define	LETIMER_CTRL_UFOA1_PWM (_LETIMER_CTRL_UFOA1_PWM << 4)
#define	LETIMER_CTRL_OPOL0 (0x1UL << 6)
#define	_LETIMER_CTRL_OPOL0_SHIFT 6
#define	_LETIMER_CTRL_OPOL0_MASK 0x40UL
#define	_LETIMER_CTRL_OPOL0_DEFAULT 0x00000000UL
#define	LETIMER_CTRL_OPOL0_DEFAULT (_LETIMER_CTRL_OPOL0_DEFAULT << 6)
#define	LETIMER_CTRL_OPOL1 (0x1UL << 7)
#define	_LETIMER_CTRL_OPOL1_SHIFT 7
#define	_LETIMER_CTRL_OPOL1_MASK 0x80UL
#define	_LETIMER_CTRL_OPOL1_DEFAULT 0x00000000UL
#define	LETIMER_CTRL_OPOL1_DEFAULT (_LETIMER_CTRL_OPOL1_DEFAULT << 7)
#define	LETIMER_CTRL_BUFTOP (0x1UL << 8)
#define	_LETIMER_CTRL_BUFTOP_SHIFT 8
#define	_LETIMER_CTRL_BUFTOP_MASK 0x100UL
#define	_LETIMER_CTRL_BUFTOP_DEFAULT 0x00000000UL
#define	LETIMER_CTRL_BUFTOP_DEFAULT (_LETIMER_CTRL_BUFTOP_DEFAULT << 8)
#define	LETIMER_CTRL_COMP0TOP (0x1UL << 9)
#define	_LETIMER_CTRL_COMP0TOP_SHIFT 9
#define	_LETIMER_CTRL_COMP0TOP_MASK 0x200UL
#define	_LETIMER_CTRL_COMP0TOP_DEFAULT 0x00000000UL
#define	LETIMER_CTRL_COMP0TOP_DEFAULT (_LETIMER_CTRL_COMP0TOP_DEFAULT << 9)
#define	LETIMER_CTRL_RTCC0TEN (0x1UL << 10)
#define	_LETIMER_CTRL_RTCC0TEN_SHIFT 10
#define	_LETIMER_CTRL_RTCC0TEN_MASK 0x400UL
#define	_LETIMER_CTRL_RTCC0TEN_DEFAULT 0x00000000UL
#define	LETIMER_CTRL_RTCC0TEN_DEFAULT (_LETIMER_CTRL_RTCC0TEN_DEFAULT << 10)
#define	LETIMER_CTRL_RTCC1TEN (0x1UL << 11)
#define	_LETIMER_CTRL_RTCC1TEN_SHIFT 11
#define	_LETIMER_CTRL_RTCC1TEN_MASK 0x800UL
#define	_LETIMER_CTRL_RTCC1TEN_DEFAULT 0x00000000UL
#define	LETIMER_CTRL_RTCC1TEN_DEFAULT (_LETIMER_CTRL_RTCC1TEN_DEFAULT << 11)
#define	LETIMER_CTRL_DEBUGRUN (0x1UL << 12)
#define	_LETIMER_CTRL_DEBUGRUN_SHIFT 12
#define	_LETIMER_CTRL_DEBUGRUN_MASK 0x1000UL
#define	_LETIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL
#define	LETIMER_CTRL_DEBUGRUN_DEFAULT (_LETIMER_CTRL_DEBUGRUN_DEFAULT << 12)
#define	_LETIMER_CMD_RESETVALUE 0x00000000UL
#define	_LETIMER_CMD_MASK 0x0000001FUL
#define	LETIMER_CMD_START (0x1UL << 0)
#define	_LETIMER_CMD_START_SHIFT 0
#define	_LETIMER_CMD_START_MASK 0x1UL
#define	_LETIMER_CMD_START_DEFAULT 0x00000000UL
#define	LETIMER_CMD_START_DEFAULT (_LETIMER_CMD_START_DEFAULT << 0)
#define	LETIMER_CMD_STOP (0x1UL << 1)
#define	_LETIMER_CMD_STOP_SHIFT 1
#define	_LETIMER_CMD_STOP_MASK 0x2UL
#define	_LETIMER_CMD_STOP_DEFAULT 0x00000000UL
#define	LETIMER_CMD_STOP_DEFAULT (_LETIMER_CMD_STOP_DEFAULT << 1)
#define	LETIMER_CMD_CLEAR (0x1UL << 2)
#define	_LETIMER_CMD_CLEAR_SHIFT 2
#define	_LETIMER_CMD_CLEAR_MASK 0x4UL
#define	_LETIMER_CMD_CLEAR_DEFAULT 0x00000000UL
#define	LETIMER_CMD_CLEAR_DEFAULT (_LETIMER_CMD_CLEAR_DEFAULT << 2)
#define	LETIMER_CMD_CTO0 (0x1UL << 3)
#define	_LETIMER_CMD_CTO0_SHIFT 3
#define	_LETIMER_CMD_CTO0_MASK 0x8UL
#define	_LETIMER_CMD_CTO0_DEFAULT 0x00000000UL
#define	LETIMER_CMD_CTO0_DEFAULT (_LETIMER_CMD_CTO0_DEFAULT << 3)
#define	LETIMER_CMD_CTO1 (0x1UL << 4)
#define	_LETIMER_CMD_CTO1_SHIFT 4
#define	_LETIMER_CMD_CTO1_MASK 0x10UL
#define	_LETIMER_CMD_CTO1_DEFAULT 0x00000000UL
#define	LETIMER_CMD_CTO1_DEFAULT (_LETIMER_CMD_CTO1_DEFAULT << 4)
#define	_LETIMER_STATUS_RESETVALUE 0x00000000UL
#define	_LETIMER_STATUS_MASK 0x00000001UL
#define	LETIMER_STATUS_RUNNING (0x1UL << 0)
#define	_LETIMER_STATUS_RUNNING_SHIFT 0
#define	_LETIMER_STATUS_RUNNING_MASK 0x1UL
#define	_LETIMER_STATUS_RUNNING_DEFAULT 0x00000000UL
#define	LETIMER_STATUS_RUNNING_DEFAULT (_LETIMER_STATUS_RUNNING_DEFAULT << 0)
#define	_LETIMER_CNT_RESETVALUE 0x00000000UL
#define	_LETIMER_CNT_MASK 0x0000FFFFUL
#define	_LETIMER_CNT_CNT_SHIFT 0
#define	_LETIMER_CNT_CNT_MASK 0xFFFFUL
#define	_LETIMER_CNT_CNT_DEFAULT 0x00000000UL
#define	LETIMER_CNT_CNT_DEFAULT (_LETIMER_CNT_CNT_DEFAULT << 0)
#define	_LETIMER_COMP0_RESETVALUE 0x00000000UL
#define	_LETIMER_COMP0_MASK 0x0000FFFFUL
#define	_LETIMER_COMP0_COMP0_SHIFT 0
#define	_LETIMER_COMP0_COMP0_MASK 0xFFFFUL
#define	_LETIMER_COMP0_COMP0_DEFAULT 0x00000000UL
#define	LETIMER_COMP0_COMP0_DEFAULT (_LETIMER_COMP0_COMP0_DEFAULT << 0)
#define	_LETIMER_COMP1_RESETVALUE 0x00000000UL
#define	_LETIMER_COMP1_MASK 0x0000FFFFUL
#define	_LETIMER_COMP1_COMP1_SHIFT 0
#define	_LETIMER_COMP1_COMP1_MASK 0xFFFFUL
#define	_LETIMER_COMP1_COMP1_DEFAULT 0x00000000UL
#define	LETIMER_COMP1_COMP1_DEFAULT (_LETIMER_COMP1_COMP1_DEFAULT << 0)
#define	_LETIMER_REP0_RESETVALUE 0x00000000UL
#define	_LETIMER_REP0_MASK 0x000000FFUL
#define	_LETIMER_REP0_REP0_SHIFT 0
#define	_LETIMER_REP0_REP0_MASK 0xFFUL
#define	_LETIMER_REP0_REP0_DEFAULT 0x00000000UL
#define	LETIMER_REP0_REP0_DEFAULT (_LETIMER_REP0_REP0_DEFAULT << 0)
#define	_LETIMER_REP1_RESETVALUE 0x00000000UL
#define	_LETIMER_REP1_MASK 0x000000FFUL
#define	_LETIMER_REP1_REP1_SHIFT 0
#define	_LETIMER_REP1_REP1_MASK 0xFFUL
#define	_LETIMER_REP1_REP1_DEFAULT 0x00000000UL
#define	LETIMER_REP1_REP1_DEFAULT (_LETIMER_REP1_REP1_DEFAULT << 0)
#define	_LETIMER_IF_RESETVALUE 0x00000000UL
#define	_LETIMER_IF_MASK 0x0000001FUL
#define	LETIMER_IF_COMP0 (0x1UL << 0)
#define	_LETIMER_IF_COMP0_SHIFT 0
#define	_LETIMER_IF_COMP0_MASK 0x1UL
#define	_LETIMER_IF_COMP0_DEFAULT 0x00000000UL
#define	LETIMER_IF_COMP0_DEFAULT (_LETIMER_IF_COMP0_DEFAULT << 0)
#define	LETIMER_IF_COMP1 (0x1UL << 1)
#define	_LETIMER_IF_COMP1_SHIFT 1
#define	_LETIMER_IF_COMP1_MASK 0x2UL
#define	_LETIMER_IF_COMP1_DEFAULT 0x00000000UL
#define	LETIMER_IF_COMP1_DEFAULT (_LETIMER_IF_COMP1_DEFAULT << 1)
#define	LETIMER_IF_UF (0x1UL << 2)
#define	_LETIMER_IF_UF_SHIFT 2
#define	_LETIMER_IF_UF_MASK 0x4UL
#define	_LETIMER_IF_UF_DEFAULT 0x00000000UL
#define	LETIMER_IF_UF_DEFAULT (_LETIMER_IF_UF_DEFAULT << 2)
#define	LETIMER_IF_REP0 (0x1UL << 3)
#define	_LETIMER_IF_REP0_SHIFT 3
#define	_LETIMER_IF_REP0_MASK 0x8UL
#define	_LETIMER_IF_REP0_DEFAULT 0x00000000UL
#define	LETIMER_IF_REP0_DEFAULT (_LETIMER_IF_REP0_DEFAULT << 3)
#define	LETIMER_IF_REP1 (0x1UL << 4)
#define	_LETIMER_IF_REP1_SHIFT 4
#define	_LETIMER_IF_REP1_MASK 0x10UL
#define	_LETIMER_IF_REP1_DEFAULT 0x00000000UL
#define	LETIMER_IF_REP1_DEFAULT (_LETIMER_IF_REP1_DEFAULT << 4)
#define	_LETIMER_IFS_RESETVALUE 0x00000000UL
#define	_LETIMER_IFS_MASK 0x0000001FUL
#define	LETIMER_IFS_COMP0 (0x1UL << 0)
#define	_LETIMER_IFS_COMP0_SHIFT 0
#define	_LETIMER_IFS_COMP0_MASK 0x1UL
#define	_LETIMER_IFS_COMP0_DEFAULT 0x00000000UL
#define	LETIMER_IFS_COMP0_DEFAULT (_LETIMER_IFS_COMP0_DEFAULT << 0)
#define	LETIMER_IFS_COMP1 (0x1UL << 1)
#define	_LETIMER_IFS_COMP1_SHIFT 1
#define	_LETIMER_IFS_COMP1_MASK 0x2UL
#define	_LETIMER_IFS_COMP1_DEFAULT 0x00000000UL
#define	LETIMER_IFS_COMP1_DEFAULT (_LETIMER_IFS_COMP1_DEFAULT << 1)
#define	LETIMER_IFS_UF (0x1UL << 2)
#define	_LETIMER_IFS_UF_SHIFT 2
#define	_LETIMER_IFS_UF_MASK 0x4UL
#define	_LETIMER_IFS_UF_DEFAULT 0x00000000UL
#define	LETIMER_IFS_UF_DEFAULT (_LETIMER_IFS_UF_DEFAULT << 2)
#define	LETIMER_IFS_REP0 (0x1UL << 3)
#define	_LETIMER_IFS_REP0_SHIFT 3
#define	_LETIMER_IFS_REP0_MASK 0x8UL
#define	_LETIMER_IFS_REP0_DEFAULT 0x00000000UL
#define	LETIMER_IFS_REP0_DEFAULT (_LETIMER_IFS_REP0_DEFAULT << 3)
#define	LETIMER_IFS_REP1 (0x1UL << 4)
#define	_LETIMER_IFS_REP1_SHIFT 4
#define	_LETIMER_IFS_REP1_MASK 0x10UL
#define	_LETIMER_IFS_REP1_DEFAULT 0x00000000UL
#define	LETIMER_IFS_REP1_DEFAULT (_LETIMER_IFS_REP1_DEFAULT << 4)
#define	_LETIMER_IFC_RESETVALUE 0x00000000UL
#define	_LETIMER_IFC_MASK 0x0000001FUL
#define	LETIMER_IFC_COMP0 (0x1UL << 0)
#define	_LETIMER_IFC_COMP0_SHIFT 0
#define	_LETIMER_IFC_COMP0_MASK 0x1UL
#define	_LETIMER_IFC_COMP0_DEFAULT 0x00000000UL
#define	LETIMER_IFC_COMP0_DEFAULT (_LETIMER_IFC_COMP0_DEFAULT << 0)
#define	LETIMER_IFC_COMP1 (0x1UL << 1)
#define	_LETIMER_IFC_COMP1_SHIFT 1
#define	_LETIMER_IFC_COMP1_MASK 0x2UL
#define	_LETIMER_IFC_COMP1_DEFAULT 0x00000000UL
#define	LETIMER_IFC_COMP1_DEFAULT (_LETIMER_IFC_COMP1_DEFAULT << 1)
#define	LETIMER_IFC_UF (0x1UL << 2)
#define	_LETIMER_IFC_UF_SHIFT 2
#define	_LETIMER_IFC_UF_MASK 0x4UL
#define	_LETIMER_IFC_UF_DEFAULT 0x00000000UL
#define	LETIMER_IFC_UF_DEFAULT (_LETIMER_IFC_UF_DEFAULT << 2)
#define	LETIMER_IFC_REP0 (0x1UL << 3)
#define	_LETIMER_IFC_REP0_SHIFT 3
#define	_LETIMER_IFC_REP0_MASK 0x8UL
#define	_LETIMER_IFC_REP0_DEFAULT 0x00000000UL
#define	LETIMER_IFC_REP0_DEFAULT (_LETIMER_IFC_REP0_DEFAULT << 3)
#define	LETIMER_IFC_REP1 (0x1UL << 4)
#define	_LETIMER_IFC_REP1_SHIFT 4
#define	_LETIMER_IFC_REP1_MASK 0x10UL
#define	_LETIMER_IFC_REP1_DEFAULT 0x00000000UL
#define	LETIMER_IFC_REP1_DEFAULT (_LETIMER_IFC_REP1_DEFAULT << 4)
#define	_LETIMER_IEN_RESETVALUE 0x00000000UL
#define	_LETIMER_IEN_MASK 0x0000001FUL
#define	LETIMER_IEN_COMP0 (0x1UL << 0)
#define	_LETIMER_IEN_COMP0_SHIFT 0
#define	_LETIMER_IEN_COMP0_MASK 0x1UL
#define	_LETIMER_IEN_COMP0_DEFAULT 0x00000000UL
#define	LETIMER_IEN_COMP0_DEFAULT (_LETIMER_IEN_COMP0_DEFAULT << 0)
#define	LETIMER_IEN_COMP1 (0x1UL << 1)
#define	_LETIMER_IEN_COMP1_SHIFT 1
#define	_LETIMER_IEN_COMP1_MASK 0x2UL
#define	_LETIMER_IEN_COMP1_DEFAULT 0x00000000UL
#define	LETIMER_IEN_COMP1_DEFAULT (_LETIMER_IEN_COMP1_DEFAULT << 1)
#define	LETIMER_IEN_UF (0x1UL << 2)
#define	_LETIMER_IEN_UF_SHIFT 2
#define	_LETIMER_IEN_UF_MASK 0x4UL
#define	_LETIMER_IEN_UF_DEFAULT 0x00000000UL
#define	LETIMER_IEN_UF_DEFAULT (_LETIMER_IEN_UF_DEFAULT << 2)
#define	LETIMER_IEN_REP0 (0x1UL << 3)
#define	_LETIMER_IEN_REP0_SHIFT 3
#define	_LETIMER_IEN_REP0_MASK 0x8UL
#define	_LETIMER_IEN_REP0_DEFAULT 0x00000000UL
#define	LETIMER_IEN_REP0_DEFAULT (_LETIMER_IEN_REP0_DEFAULT << 3)
#define	LETIMER_IEN_REP1 (0x1UL << 4)
#define	_LETIMER_IEN_REP1_SHIFT 4
#define	_LETIMER_IEN_REP1_MASK 0x10UL
#define	_LETIMER_IEN_REP1_DEFAULT 0x00000000UL
#define	LETIMER_IEN_REP1_DEFAULT (_LETIMER_IEN_REP1_DEFAULT << 4)
#define	_LETIMER_FREEZE_RESETVALUE 0x00000000UL
#define	_LETIMER_FREEZE_MASK 0x00000001UL
#define	LETIMER_FREEZE_REGFREEZE (0x1UL << 0)
#define	_LETIMER_FREEZE_REGFREEZE_SHIFT 0
#define	_LETIMER_FREEZE_REGFREEZE_MASK 0x1UL
#define	_LETIMER_FREEZE_REGFREEZE_DEFAULT 0x00000000UL
#define	_LETIMER_FREEZE_REGFREEZE_UPDATE 0x00000000UL
#define	_LETIMER_FREEZE_REGFREEZE_FREEZE 0x00000001UL
#define	LETIMER_FREEZE_REGFREEZE_DEFAULT (_LETIMER_FREEZE_REGFREEZE_DEFAULT << 0)
#define	LETIMER_FREEZE_REGFREEZE_UPDATE (_LETIMER_FREEZE_REGFREEZE_UPDATE << 0)
#define	LETIMER_FREEZE_REGFREEZE_FREEZE (_LETIMER_FREEZE_REGFREEZE_FREEZE << 0)
#define	_LETIMER_SYNCBUSY_RESETVALUE 0x00000000UL
#define	_LETIMER_SYNCBUSY_MASK 0x0000003FUL
#define	LETIMER_SYNCBUSY_CTRL (0x1UL << 0)
#define	_LETIMER_SYNCBUSY_CTRL_SHIFT 0
#define	_LETIMER_SYNCBUSY_CTRL_MASK 0x1UL
#define	_LETIMER_SYNCBUSY_CTRL_DEFAULT 0x00000000UL
#define	LETIMER_SYNCBUSY_CTRL_DEFAULT (_LETIMER_SYNCBUSY_CTRL_DEFAULT << 0)
#define	LETIMER_SYNCBUSY_CMD (0x1UL << 1)
#define	_LETIMER_SYNCBUSY_CMD_SHIFT 1
#define	_LETIMER_SYNCBUSY_CMD_MASK 0x2UL
#define	_LETIMER_SYNCBUSY_CMD_DEFAULT 0x00000000UL
#define	LETIMER_SYNCBUSY_CMD_DEFAULT (_LETIMER_SYNCBUSY_CMD_DEFAULT << 1)
#define	LETIMER_SYNCBUSY_COMP0 (0x1UL << 2)
#define	_LETIMER_SYNCBUSY_COMP0_SHIFT 2
#define	_LETIMER_SYNCBUSY_COMP0_MASK 0x4UL
#define	_LETIMER_SYNCBUSY_COMP0_DEFAULT 0x00000000UL
#define	LETIMER_SYNCBUSY_COMP0_DEFAULT (_LETIMER_SYNCBUSY_COMP0_DEFAULT << 2)
#define	LETIMER_SYNCBUSY_COMP1 (0x1UL << 3)
#define	_LETIMER_SYNCBUSY_COMP1_SHIFT 3
#define	_LETIMER_SYNCBUSY_COMP1_MASK 0x8UL
#define	_LETIMER_SYNCBUSY_COMP1_DEFAULT 0x00000000UL
#define	LETIMER_SYNCBUSY_COMP1_DEFAULT (_LETIMER_SYNCBUSY_COMP1_DEFAULT << 3)
#define	LETIMER_SYNCBUSY_REP0 (0x1UL << 4)
#define	_LETIMER_SYNCBUSY_REP0_SHIFT 4
#define	_LETIMER_SYNCBUSY_REP0_MASK 0x10UL
#define	_LETIMER_SYNCBUSY_REP0_DEFAULT 0x00000000UL
#define	LETIMER_SYNCBUSY_REP0_DEFAULT (_LETIMER_SYNCBUSY_REP0_DEFAULT << 4)
#define	LETIMER_SYNCBUSY_REP1 (0x1UL << 5)
#define	_LETIMER_SYNCBUSY_REP1_SHIFT 5
#define	_LETIMER_SYNCBUSY_REP1_MASK 0x20UL
#define	_LETIMER_SYNCBUSY_REP1_DEFAULT 0x00000000UL
#define	LETIMER_SYNCBUSY_REP1_DEFAULT (_LETIMER_SYNCBUSY_REP1_DEFAULT << 5)
#define	_LETIMER_ROUTE_RESETVALUE 0x00000000UL
#define	_LETIMER_ROUTE_MASK 0x00000303UL
#define	LETIMER_ROUTE_OUT0PEN (0x1UL << 0)
#define	_LETIMER_ROUTE_OUT0PEN_SHIFT 0
#define	_LETIMER_ROUTE_OUT0PEN_MASK 0x1UL
#define	_LETIMER_ROUTE_OUT0PEN_DEFAULT 0x00000000UL
#define	LETIMER_ROUTE_OUT0PEN_DEFAULT (_LETIMER_ROUTE_OUT0PEN_DEFAULT << 0)
#define	LETIMER_ROUTE_OUT1PEN (0x1UL << 1)
#define	_LETIMER_ROUTE_OUT1PEN_SHIFT 1
#define	_LETIMER_ROUTE_OUT1PEN_MASK 0x2UL
#define	_LETIMER_ROUTE_OUT1PEN_DEFAULT 0x00000000UL
#define	LETIMER_ROUTE_OUT1PEN_DEFAULT (_LETIMER_ROUTE_OUT1PEN_DEFAULT << 1)
#define	_LETIMER_ROUTE_LOCATION_SHIFT 8
#define	_LETIMER_ROUTE_LOCATION_MASK 0x300UL
#define	_LETIMER_ROUTE_LOCATION_DEFAULT 0x00000000UL
#define	_LETIMER_ROUTE_LOCATION_LOC0 0x00000000UL
#define	_LETIMER_ROUTE_LOCATION_LOC1 0x00000001UL
#define	_LETIMER_ROUTE_LOCATION_LOC2 0x00000002UL
#define	_LETIMER_ROUTE_LOCATION_LOC3 0x00000003UL
#define	LETIMER_ROUTE_LOCATION_DEFAULT (_LETIMER_ROUTE_LOCATION_DEFAULT << 8)
#define	LETIMER_ROUTE_LOCATION_LOC0 (_LETIMER_ROUTE_LOCATION_LOC0 << 8)
#define	LETIMER_ROUTE_LOCATION_LOC1 (_LETIMER_ROUTE_LOCATION_LOC1 << 8)
#define	LETIMER_ROUTE_LOCATION_LOC2 (_LETIMER_ROUTE_LOCATION_LOC2 << 8)
#define	LETIMER_ROUTE_LOCATION_LOC3 (_LETIMER_ROUTE_LOCATION_LOC3 << 8)
#define	_PCNT_CTRL_RESETVALUE 0x00000000UL
#define	_PCNT_CTRL_MASK 0x0000003FUL
#define	_PCNT_CTRL_MODE_SHIFT 0
#define	_PCNT_CTRL_MODE_MASK 0x3UL
#define	_PCNT_CTRL_MODE_DEFAULT 0x00000000UL
#define	_PCNT_CTRL_MODE_DISABLE 0x00000000UL
#define	_PCNT_CTRL_MODE_OVSSINGLE 0x00000001UL
#define	_PCNT_CTRL_MODE_EXTCLKSINGLE 0x00000002UL
#define	_PCNT_CTRL_MODE_EXTCLKQUAD 0x00000003UL
#define	PCNT_CTRL_MODE_DEFAULT (_PCNT_CTRL_MODE_DEFAULT << 0)
#define	PCNT_CTRL_MODE_DISABLE (_PCNT_CTRL_MODE_DISABLE << 0)
#define	PCNT_CTRL_MODE_OVSSINGLE (_PCNT_CTRL_MODE_OVSSINGLE << 0)
#define	PCNT_CTRL_MODE_EXTCLKSINGLE (_PCNT_CTRL_MODE_EXTCLKSINGLE << 0)
#define	PCNT_CTRL_MODE_EXTCLKQUAD (_PCNT_CTRL_MODE_EXTCLKQUAD << 0)
#define	PCNT_CTRL_CNTDIR (0x1UL << 2)
#define	_PCNT_CTRL_CNTDIR_SHIFT 2
#define	_PCNT_CTRL_CNTDIR_MASK 0x4UL
#define	_PCNT_CTRL_CNTDIR_DEFAULT 0x00000000UL
#define	_PCNT_CTRL_CNTDIR_UP 0x00000000UL
#define	_PCNT_CTRL_CNTDIR_DOWN 0x00000001UL
#define	PCNT_CTRL_CNTDIR_DEFAULT (_PCNT_CTRL_CNTDIR_DEFAULT << 2)
#define	PCNT_CTRL_CNTDIR_UP (_PCNT_CTRL_CNTDIR_UP << 2)
#define	PCNT_CTRL_CNTDIR_DOWN (_PCNT_CTRL_CNTDIR_DOWN << 2)
#define	PCNT_CTRL_EDGE (0x1UL << 3)
#define	_PCNT_CTRL_EDGE_SHIFT 3
#define	_PCNT_CTRL_EDGE_MASK 0x8UL
#define	_PCNT_CTRL_EDGE_DEFAULT 0x00000000UL
#define	_PCNT_CTRL_EDGE_POS 0x00000000UL
#define	_PCNT_CTRL_EDGE_NEG 0x00000001UL
#define	PCNT_CTRL_EDGE_DEFAULT (_PCNT_CTRL_EDGE_DEFAULT << 3)
#define	PCNT_CTRL_EDGE_POS (_PCNT_CTRL_EDGE_POS << 3)
#define	PCNT_CTRL_EDGE_NEG (_PCNT_CTRL_EDGE_NEG << 3)
#define	PCNT_CTRL_FILT (0x1UL << 4)
#define	_PCNT_CTRL_FILT_SHIFT 4
#define	_PCNT_CTRL_FILT_MASK 0x10UL
#define	_PCNT_CTRL_FILT_DEFAULT 0x00000000UL
#define	PCNT_CTRL_FILT_DEFAULT (_PCNT_CTRL_FILT_DEFAULT << 4)
#define	PCNT_CTRL_RSTEN (0x1UL << 5)
#define	_PCNT_CTRL_RSTEN_SHIFT 5
#define	_PCNT_CTRL_RSTEN_MASK 0x20UL
#define	_PCNT_CTRL_RSTEN_DEFAULT 0x00000000UL
#define	PCNT_CTRL_RSTEN_DEFAULT (_PCNT_CTRL_RSTEN_DEFAULT << 5)
#define	_PCNT_CMD_RESETVALUE 0x00000000UL
#define	_PCNT_CMD_MASK 0x00000003UL
#define	PCNT_CMD_LCNTIM (0x1UL << 0)
#define	_PCNT_CMD_LCNTIM_SHIFT 0
#define	_PCNT_CMD_LCNTIM_MASK 0x1UL
#define	_PCNT_CMD_LCNTIM_DEFAULT 0x00000000UL
#define	PCNT_CMD_LCNTIM_DEFAULT (_PCNT_CMD_LCNTIM_DEFAULT << 0)
#define	PCNT_CMD_LTOPBIM (0x1UL << 1)
#define	_PCNT_CMD_LTOPBIM_SHIFT 1
#define	_PCNT_CMD_LTOPBIM_MASK 0x2UL
#define	_PCNT_CMD_LTOPBIM_DEFAULT 0x00000000UL
#define	PCNT_CMD_LTOPBIM_DEFAULT (_PCNT_CMD_LTOPBIM_DEFAULT << 1)
#define	_PCNT_STATUS_RESETVALUE 0x00000000UL
#define	_PCNT_STATUS_MASK 0x00000001UL
#define	PCNT_STATUS_DIR (0x1UL << 0)
#define	_PCNT_STATUS_DIR_SHIFT 0
#define	_PCNT_STATUS_DIR_MASK 0x1UL
#define	_PCNT_STATUS_DIR_DEFAULT 0x00000000UL
#define	_PCNT_STATUS_DIR_UP 0x00000000UL
#define	_PCNT_STATUS_DIR_DOWN 0x00000001UL
#define	PCNT_STATUS_DIR_DEFAULT (_PCNT_STATUS_DIR_DEFAULT << 0)
#define	PCNT_STATUS_DIR_UP (_PCNT_STATUS_DIR_UP << 0)
#define	PCNT_STATUS_DIR_DOWN (_PCNT_STATUS_DIR_DOWN << 0)
#define	_PCNT_CNT_RESETVALUE 0x00000000UL
#define	_PCNT_CNT_MASK 0x0000FFFFUL
#define	_PCNT_CNT_CNT_SHIFT 0
#define	_PCNT_CNT_CNT_MASK 0xFFFFUL
#define	_PCNT_CNT_CNT_DEFAULT 0x00000000UL
#define	PCNT_CNT_CNT_DEFAULT (_PCNT_CNT_CNT_DEFAULT << 0)
#define	_PCNT_TOP_RESETVALUE 0x000000FFUL
#define	_PCNT_TOP_MASK 0x0000FFFFUL
#define	_PCNT_TOP_TOP_SHIFT 0
#define	_PCNT_TOP_TOP_MASK 0xFFFFUL
#define	_PCNT_TOP_TOP_DEFAULT 0x000000FFUL
#define	PCNT_TOP_TOP_DEFAULT (_PCNT_TOP_TOP_DEFAULT << 0)
#define	_PCNT_TOPB_RESETVALUE 0x000000FFUL
#define	_PCNT_TOPB_MASK 0x0000FFFFUL
#define	_PCNT_TOPB_TOPB_SHIFT 0
#define	_PCNT_TOPB_TOPB_MASK 0xFFFFUL
#define	_PCNT_TOPB_TOPB_DEFAULT 0x000000FFUL
#define	PCNT_TOPB_TOPB_DEFAULT (_PCNT_TOPB_TOPB_DEFAULT << 0)
#define	_PCNT_IF_RESETVALUE 0x00000000UL
#define	_PCNT_IF_MASK 0x00000007UL
#define	PCNT_IF_UF (0x1UL << 0)
#define	_PCNT_IF_UF_SHIFT 0
#define	_PCNT_IF_UF_MASK 0x1UL
#define	_PCNT_IF_UF_DEFAULT 0x00000000UL
#define	PCNT_IF_UF_DEFAULT (_PCNT_IF_UF_DEFAULT << 0)
#define	PCNT_IF_OF (0x1UL << 1)
#define	_PCNT_IF_OF_SHIFT 1
#define	_PCNT_IF_OF_MASK 0x2UL
#define	_PCNT_IF_OF_DEFAULT 0x00000000UL
#define	PCNT_IF_OF_DEFAULT (_PCNT_IF_OF_DEFAULT << 1)
#define	PCNT_IF_DIRCNG (0x1UL << 2)
#define	_PCNT_IF_DIRCNG_SHIFT 2
#define	_PCNT_IF_DIRCNG_MASK 0x4UL
#define	_PCNT_IF_DIRCNG_DEFAULT 0x00000000UL
#define	PCNT_IF_DIRCNG_DEFAULT (_PCNT_IF_DIRCNG_DEFAULT << 2)
#define	_PCNT_IFS_RESETVALUE 0x00000000UL
#define	_PCNT_IFS_MASK 0x00000007UL
#define	PCNT_IFS_UF (0x1UL << 0)
#define	_PCNT_IFS_UF_SHIFT 0
#define	_PCNT_IFS_UF_MASK 0x1UL
#define	_PCNT_IFS_UF_DEFAULT 0x00000000UL
#define	PCNT_IFS_UF_DEFAULT (_PCNT_IFS_UF_DEFAULT << 0)
#define	PCNT_IFS_OF (0x1UL << 1)
#define	_PCNT_IFS_OF_SHIFT 1
#define	_PCNT_IFS_OF_MASK 0x2UL
#define	_PCNT_IFS_OF_DEFAULT 0x00000000UL
#define	PCNT_IFS_OF_DEFAULT (_PCNT_IFS_OF_DEFAULT << 1)
#define	PCNT_IFS_DIRCNG (0x1UL << 2)
#define	_PCNT_IFS_DIRCNG_SHIFT 2
#define	_PCNT_IFS_DIRCNG_MASK 0x4UL
#define	_PCNT_IFS_DIRCNG_DEFAULT 0x00000000UL
#define	PCNT_IFS_DIRCNG_DEFAULT (_PCNT_IFS_DIRCNG_DEFAULT << 2)
#define	_PCNT_IFC_RESETVALUE 0x00000000UL
#define	_PCNT_IFC_MASK 0x00000007UL
#define	PCNT_IFC_UF (0x1UL << 0)
#define	_PCNT_IFC_UF_SHIFT 0
#define	_PCNT_IFC_UF_MASK 0x1UL
#define	_PCNT_IFC_UF_DEFAULT 0x00000000UL
#define	PCNT_IFC_UF_DEFAULT (_PCNT_IFC_UF_DEFAULT << 0)
#define	PCNT_IFC_OF (0x1UL << 1)
#define	_PCNT_IFC_OF_SHIFT 1
#define	_PCNT_IFC_OF_MASK 0x2UL
#define	_PCNT_IFC_OF_DEFAULT 0x00000000UL
#define	PCNT_IFC_OF_DEFAULT (_PCNT_IFC_OF_DEFAULT << 1)
#define	PCNT_IFC_DIRCNG (0x1UL << 2)
#define	_PCNT_IFC_DIRCNG_SHIFT 2
#define	_PCNT_IFC_DIRCNG_MASK 0x4UL
#define	_PCNT_IFC_DIRCNG_DEFAULT 0x00000000UL
#define	PCNT_IFC_DIRCNG_DEFAULT (_PCNT_IFC_DIRCNG_DEFAULT << 2)
#define	_PCNT_IEN_RESETVALUE 0x00000000UL
#define	_PCNT_IEN_MASK 0x00000007UL
#define	PCNT_IEN_UF (0x1UL << 0)
#define	_PCNT_IEN_UF_SHIFT 0
#define	_PCNT_IEN_UF_MASK 0x1UL
#define	_PCNT_IEN_UF_DEFAULT 0x00000000UL
#define	PCNT_IEN_UF_DEFAULT (_PCNT_IEN_UF_DEFAULT << 0)
#define	PCNT_IEN_OF (0x1UL << 1)
#define	_PCNT_IEN_OF_SHIFT 1
#define	_PCNT_IEN_OF_MASK 0x2UL
#define	_PCNT_IEN_OF_DEFAULT 0x00000000UL
#define	PCNT_IEN_OF_DEFAULT (_PCNT_IEN_OF_DEFAULT << 1)
#define	PCNT_IEN_DIRCNG (0x1UL << 2)
#define	_PCNT_IEN_DIRCNG_SHIFT 2
#define	_PCNT_IEN_DIRCNG_MASK 0x4UL
#define	_PCNT_IEN_DIRCNG_DEFAULT 0x00000000UL
#define	PCNT_IEN_DIRCNG_DEFAULT (_PCNT_IEN_DIRCNG_DEFAULT << 2)
#define	_PCNT_ROUTE_RESETVALUE 0x00000000UL
#define	_PCNT_ROUTE_MASK 0x00000300UL
#define	_PCNT_ROUTE_LOCATION_SHIFT 8
#define	_PCNT_ROUTE_LOCATION_MASK 0x300UL
#define	_PCNT_ROUTE_LOCATION_DEFAULT 0x00000000UL
#define	_PCNT_ROUTE_LOCATION_LOC0 0x00000000UL
#define	_PCNT_ROUTE_LOCATION_LOC1 0x00000001UL
#define	_PCNT_ROUTE_LOCATION_LOC2 0x00000002UL
#define	PCNT_ROUTE_LOCATION_DEFAULT (_PCNT_ROUTE_LOCATION_DEFAULT << 8)
#define	PCNT_ROUTE_LOCATION_LOC0 (_PCNT_ROUTE_LOCATION_LOC0 << 8)
#define	PCNT_ROUTE_LOCATION_LOC1 (_PCNT_ROUTE_LOCATION_LOC1 << 8)
#define	PCNT_ROUTE_LOCATION_LOC2 (_PCNT_ROUTE_LOCATION_LOC2 << 8)
#define	_PCNT_FREEZE_RESETVALUE 0x00000000UL
#define	_PCNT_FREEZE_MASK 0x00000001UL
#define	PCNT_FREEZE_REGFREEZE (0x1UL << 0)
#define	_PCNT_FREEZE_REGFREEZE_SHIFT 0
#define	_PCNT_FREEZE_REGFREEZE_MASK 0x1UL
#define	_PCNT_FREEZE_REGFREEZE_DEFAULT 0x00000000UL
#define	_PCNT_FREEZE_REGFREEZE_UPDATE 0x00000000UL
#define	_PCNT_FREEZE_REGFREEZE_FREEZE 0x00000001UL
#define	PCNT_FREEZE_REGFREEZE_DEFAULT (_PCNT_FREEZE_REGFREEZE_DEFAULT << 0)
#define	PCNT_FREEZE_REGFREEZE_UPDATE (_PCNT_FREEZE_REGFREEZE_UPDATE << 0)
#define	PCNT_FREEZE_REGFREEZE_FREEZE (_PCNT_FREEZE_REGFREEZE_FREEZE << 0)
#define	_PCNT_SYNCBUSY_RESETVALUE 0x00000000UL
#define	_PCNT_SYNCBUSY_MASK 0x00000007UL
#define	PCNT_SYNCBUSY_CTRL (0x1UL << 0)
#define	_PCNT_SYNCBUSY_CTRL_SHIFT 0
#define	_PCNT_SYNCBUSY_CTRL_MASK 0x1UL
#define	_PCNT_SYNCBUSY_CTRL_DEFAULT 0x00000000UL
#define	PCNT_SYNCBUSY_CTRL_DEFAULT (_PCNT_SYNCBUSY_CTRL_DEFAULT << 0)
#define	PCNT_SYNCBUSY_CMD (0x1UL << 1)
#define	_PCNT_SYNCBUSY_CMD_SHIFT 1
#define	_PCNT_SYNCBUSY_CMD_MASK 0x2UL
#define	_PCNT_SYNCBUSY_CMD_DEFAULT 0x00000000UL
#define	PCNT_SYNCBUSY_CMD_DEFAULT (_PCNT_SYNCBUSY_CMD_DEFAULT << 1)
#define	PCNT_SYNCBUSY_TOPB (0x1UL << 2)
#define	_PCNT_SYNCBUSY_TOPB_SHIFT 2
#define	_PCNT_SYNCBUSY_TOPB_MASK 0x4UL
#define	_PCNT_SYNCBUSY_TOPB_DEFAULT 0x00000000UL
#define	PCNT_SYNCBUSY_TOPB_DEFAULT (_PCNT_SYNCBUSY_TOPB_DEFAULT << 2)
#define	_I2C_CTRL_RESETVALUE 0x00000000UL
#define	_I2C_CTRL_MASK 0x0007B37FUL
#define	I2C_CTRL_EN (0x1UL << 0)
#define	_I2C_CTRL_EN_SHIFT 0
#define	_I2C_CTRL_EN_MASK 0x1UL
#define	_I2C_CTRL_EN_DEFAULT 0x00000000UL
#define	I2C_CTRL_EN_DEFAULT (_I2C_CTRL_EN_DEFAULT << 0)
#define	I2C_CTRL_SLAVE (0x1UL << 1)
#define	_I2C_CTRL_SLAVE_SHIFT 1
#define	_I2C_CTRL_SLAVE_MASK 0x2UL
#define	_I2C_CTRL_SLAVE_DEFAULT 0x00000000UL
#define	I2C_CTRL_SLAVE_DEFAULT (_I2C_CTRL_SLAVE_DEFAULT << 1)
#define	I2C_CTRL_AUTOACK (0x1UL << 2)
#define	_I2C_CTRL_AUTOACK_SHIFT 2
#define	_I2C_CTRL_AUTOACK_MASK 0x4UL
#define	_I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL
#define	I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2)
#define	I2C_CTRL_AUTOSE (0x1UL << 3)
#define	_I2C_CTRL_AUTOSE_SHIFT 3
#define	_I2C_CTRL_AUTOSE_MASK 0x8UL
#define	_I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL
#define	I2C_CTRL_AUTOSE_DEFAULT (_I2C_CTRL_AUTOSE_DEFAULT << 3)
#define	I2C_CTRL_AUTOSN (0x1UL << 4)
#define	_I2C_CTRL_AUTOSN_SHIFT 4
#define	_I2C_CTRL_AUTOSN_MASK 0x10UL
#define	_I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL
#define	I2C_CTRL_AUTOSN_DEFAULT (_I2C_CTRL_AUTOSN_DEFAULT << 4)
#define	I2C_CTRL_ARBDIS (0x1UL << 5)
#define	_I2C_CTRL_ARBDIS_SHIFT 5
#define	_I2C_CTRL_ARBDIS_MASK 0x20UL
#define	_I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL
#define	I2C_CTRL_ARBDIS_DEFAULT (_I2C_CTRL_ARBDIS_DEFAULT << 5)
#define	I2C_CTRL_GCAMEN (0x1UL << 6)
#define	_I2C_CTRL_GCAMEN_SHIFT 6
#define	_I2C_CTRL_GCAMEN_MASK 0x40UL
#define	_I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL
#define	I2C_CTRL_GCAMEN_DEFAULT (_I2C_CTRL_GCAMEN_DEFAULT << 6)
#define	_I2C_CTRL_CLHR_SHIFT 8
#define	_I2C_CTRL_CLHR_MASK 0x300UL
#define	_I2C_CTRL_CLHR_DEFAULT 0x00000000UL
#define	_I2C_CTRL_CLHR_STANDARD 0x00000000UL
#define	_I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL
#define	_I2C_CTRL_CLHR_FAST 0x00000002UL
#define	I2C_CTRL_CLHR_DEFAULT (_I2C_CTRL_CLHR_DEFAULT << 8)
#define	I2C_CTRL_CLHR_STANDARD (_I2C_CTRL_CLHR_STANDARD << 8)
#define	I2C_CTRL_CLHR_ASYMMETRIC (_I2C_CTRL_CLHR_ASYMMETRIC << 8)
#define	I2C_CTRL_CLHR_FAST (_I2C_CTRL_CLHR_FAST << 8)
#define	_I2C_CTRL_BITO_SHIFT 12
#define	_I2C_CTRL_BITO_MASK 0x3000UL
#define	_I2C_CTRL_BITO_DEFAULT 0x00000000UL
#define	_I2C_CTRL_BITO_OFF 0x00000000UL
#define	_I2C_CTRL_BITO_40PCC 0x00000001UL
#define	_I2C_CTRL_BITO_80PCC 0x00000002UL
#define	_I2C_CTRL_BITO_160PCC 0x00000003UL
#define	I2C_CTRL_BITO_DEFAULT (_I2C_CTRL_BITO_DEFAULT << 12)
#define	I2C_CTRL_BITO_OFF (_I2C_CTRL_BITO_OFF << 12)
#define	I2C_CTRL_BITO_40PCC (_I2C_CTRL_BITO_40PCC << 12)
#define	I2C_CTRL_BITO_80PCC (_I2C_CTRL_BITO_80PCC << 12)
#define	I2C_CTRL_BITO_160PCC (_I2C_CTRL_BITO_160PCC << 12)
#define	I2C_CTRL_GIBITO (0x1UL << 15)
#define	_I2C_CTRL_GIBITO_SHIFT 15
#define	_I2C_CTRL_GIBITO_MASK 0x8000UL
#define	_I2C_CTRL_GIBITO_DEFAULT 0x00000000UL
#define	I2C_CTRL_GIBITO_DEFAULT (_I2C_CTRL_GIBITO_DEFAULT << 15)
#define	_I2C_CTRL_CLTO_SHIFT 16
#define	_I2C_CTRL_CLTO_MASK 0x70000UL
#define	_I2C_CTRL_CLTO_DEFAULT 0x00000000UL
#define	_I2C_CTRL_CLTO_OFF 0x00000000UL
#define	_I2C_CTRL_CLTO_40PCC 0x00000001UL
#define	_I2C_CTRL_CLTO_80PCC 0x00000002UL
#define	_I2C_CTRL_CLTO_160PCC 0x00000003UL
#define	_I2C_CTRL_CLTO_320PPC 0x00000004UL
#define	_I2C_CTRL_CLTO_1024PPC 0x00000005UL
#define	I2C_CTRL_CLTO_DEFAULT (_I2C_CTRL_CLTO_DEFAULT << 16)
#define	I2C_CTRL_CLTO_OFF (_I2C_CTRL_CLTO_OFF << 16)
#define	I2C_CTRL_CLTO_40PCC (_I2C_CTRL_CLTO_40PCC << 16)
#define	I2C_CTRL_CLTO_80PCC (_I2C_CTRL_CLTO_80PCC << 16)
#define	I2C_CTRL_CLTO_160PCC (_I2C_CTRL_CLTO_160PCC << 16)
#define	I2C_CTRL_CLTO_320PPC (_I2C_CTRL_CLTO_320PPC << 16)
#define	I2C_CTRL_CLTO_1024PPC (_I2C_CTRL_CLTO_1024PPC << 16)
#define	_I2C_CMD_RESETVALUE 0x00000000UL
#define	_I2C_CMD_MASK 0x000000FFUL
#define	I2C_CMD_START (0x1UL << 0)
#define	_I2C_CMD_START_SHIFT 0
#define	_I2C_CMD_START_MASK 0x1UL
#define	_I2C_CMD_START_DEFAULT 0x00000000UL
#define	I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0)
#define	I2C_CMD_STOP (0x1UL << 1)
#define	_I2C_CMD_STOP_SHIFT 1
#define	_I2C_CMD_STOP_MASK 0x2UL
#define	_I2C_CMD_STOP_DEFAULT 0x00000000UL
#define	I2C_CMD_STOP_DEFAULT (_I2C_CMD_STOP_DEFAULT << 1)
#define	I2C_CMD_ACK (0x1UL << 2)
#define	_I2C_CMD_ACK_SHIFT 2
#define	_I2C_CMD_ACK_MASK 0x4UL
#define	_I2C_CMD_ACK_DEFAULT 0x00000000UL
#define	I2C_CMD_ACK_DEFAULT (_I2C_CMD_ACK_DEFAULT << 2)
#define	I2C_CMD_NACK (0x1UL << 3)
#define	_I2C_CMD_NACK_SHIFT 3
#define	_I2C_CMD_NACK_MASK 0x8UL
#define	_I2C_CMD_NACK_DEFAULT 0x00000000UL
#define	I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3)
#define	I2C_CMD_CONT (0x1UL << 4)
#define	_I2C_CMD_CONT_SHIFT 4
#define	_I2C_CMD_CONT_MASK 0x10UL
#define	_I2C_CMD_CONT_DEFAULT 0x00000000UL
#define	I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4)
#define	I2C_CMD_ABORT (0x1UL << 5)
#define	_I2C_CMD_ABORT_SHIFT 5
#define	_I2C_CMD_ABORT_MASK 0x20UL
#define	_I2C_CMD_ABORT_DEFAULT 0x00000000UL
#define	I2C_CMD_ABORT_DEFAULT (_I2C_CMD_ABORT_DEFAULT << 5)
#define	I2C_CMD_CLEARTX (0x1UL << 6)
#define	_I2C_CMD_CLEARTX_SHIFT 6
#define	_I2C_CMD_CLEARTX_MASK 0x40UL
#define	_I2C_CMD_CLEARTX_DEFAULT 0x00000000UL
#define	I2C_CMD_CLEARTX_DEFAULT (_I2C_CMD_CLEARTX_DEFAULT << 6)
#define	I2C_CMD_CLEARPC (0x1UL << 7)
#define	_I2C_CMD_CLEARPC_SHIFT 7
#define	_I2C_CMD_CLEARPC_MASK 0x80UL
#define	_I2C_CMD_CLEARPC_DEFAULT 0x00000000UL
#define	I2C_CMD_CLEARPC_DEFAULT (_I2C_CMD_CLEARPC_DEFAULT << 7)
#define	_I2C_STATE_RESETVALUE 0x00000001UL
#define	_I2C_STATE_MASK 0x000000FFUL
#define	I2C_STATE_BUSY (0x1UL << 0)
#define	_I2C_STATE_BUSY_SHIFT 0
#define	_I2C_STATE_BUSY_MASK 0x1UL
#define	_I2C_STATE_BUSY_DEFAULT 0x00000001UL
#define	I2C_STATE_BUSY_DEFAULT (_I2C_STATE_BUSY_DEFAULT << 0)
#define	I2C_STATE_MASTER (0x1UL << 1)
#define	_I2C_STATE_MASTER_SHIFT 1
#define	_I2C_STATE_MASTER_MASK 0x2UL
#define	_I2C_STATE_MASTER_DEFAULT 0x00000000UL
#define	I2C_STATE_MASTER_DEFAULT (_I2C_STATE_MASTER_DEFAULT << 1)
#define	I2C_STATE_TRANSMITTER (0x1UL << 2)
#define	_I2C_STATE_TRANSMITTER_SHIFT 2
#define	_I2C_STATE_TRANSMITTER_MASK 0x4UL
#define	_I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL
#define	I2C_STATE_TRANSMITTER_DEFAULT (_I2C_STATE_TRANSMITTER_DEFAULT << 2)
#define	I2C_STATE_NACKED (0x1UL << 3)
#define	_I2C_STATE_NACKED_SHIFT 3
#define	_I2C_STATE_NACKED_MASK 0x8UL
#define	_I2C_STATE_NACKED_DEFAULT 0x00000000UL
#define	I2C_STATE_NACKED_DEFAULT (_I2C_STATE_NACKED_DEFAULT << 3)
#define	I2C_STATE_BUSHOLD (0x1UL << 4)
#define	_I2C_STATE_BUSHOLD_SHIFT 4
#define	_I2C_STATE_BUSHOLD_MASK 0x10UL
#define	_I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL
#define	I2C_STATE_BUSHOLD_DEFAULT (_I2C_STATE_BUSHOLD_DEFAULT << 4)
#define	_I2C_STATE_STATE_SHIFT 5
#define	_I2C_STATE_STATE_MASK 0xE0UL
#define	_I2C_STATE_STATE_DEFAULT 0x00000000UL
#define	_I2C_STATE_STATE_IDLE 0x00000000UL
#define	_I2C_STATE_STATE_WAIT 0x00000001UL
#define	_I2C_STATE_STATE_START 0x00000002UL
#define	_I2C_STATE_STATE_ADDR 0x00000003UL
#define	_I2C_STATE_STATE_ADDRACK 0x00000004UL
#define	_I2C_STATE_STATE_DATA 0x00000005UL
#define	_I2C_STATE_STATE_DATAACK 0x00000006UL
#define	I2C_STATE_STATE_DEFAULT (_I2C_STATE_STATE_DEFAULT << 5)
#define	I2C_STATE_STATE_IDLE (_I2C_STATE_STATE_IDLE << 5)
#define	I2C_STATE_STATE_WAIT (_I2C_STATE_STATE_WAIT << 5)
#define	I2C_STATE_STATE_START (_I2C_STATE_STATE_START << 5)
#define	I2C_STATE_STATE_ADDR (_I2C_STATE_STATE_ADDR << 5)
#define	I2C_STATE_STATE_ADDRACK (_I2C_STATE_STATE_ADDRACK << 5)
#define	I2C_STATE_STATE_DATA (_I2C_STATE_STATE_DATA << 5)
#define	I2C_STATE_STATE_DATAACK (_I2C_STATE_STATE_DATAACK << 5)
#define	_I2C_STATUS_RESETVALUE 0x00000080UL
#define	_I2C_STATUS_MASK 0x000001FFUL
#define	I2C_STATUS_PSTART (0x1UL << 0)
#define	_I2C_STATUS_PSTART_SHIFT 0
#define	_I2C_STATUS_PSTART_MASK 0x1UL
#define	_I2C_STATUS_PSTART_DEFAULT 0x00000000UL
#define	I2C_STATUS_PSTART_DEFAULT (_I2C_STATUS_PSTART_DEFAULT << 0)
#define	I2C_STATUS_PSTOP (0x1UL << 1)
#define	_I2C_STATUS_PSTOP_SHIFT 1
#define	_I2C_STATUS_PSTOP_MASK 0x2UL
#define	_I2C_STATUS_PSTOP_DEFAULT 0x00000000UL
#define	I2C_STATUS_PSTOP_DEFAULT (_I2C_STATUS_PSTOP_DEFAULT << 1)
#define	I2C_STATUS_PACK (0x1UL << 2)
#define	_I2C_STATUS_PACK_SHIFT 2
#define	_I2C_STATUS_PACK_MASK 0x4UL
#define	_I2C_STATUS_PACK_DEFAULT 0x00000000UL
#define	I2C_STATUS_PACK_DEFAULT (_I2C_STATUS_PACK_DEFAULT << 2)
#define	I2C_STATUS_PNACK (0x1UL << 3)
#define	_I2C_STATUS_PNACK_SHIFT 3
#define	_I2C_STATUS_PNACK_MASK 0x8UL
#define	_I2C_STATUS_PNACK_DEFAULT 0x00000000UL
#define	I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3)
#define	I2C_STATUS_PCONT (0x1UL << 4)
#define	_I2C_STATUS_PCONT_SHIFT 4
#define	_I2C_STATUS_PCONT_MASK 0x10UL
#define	_I2C_STATUS_PCONT_DEFAULT 0x00000000UL
#define	I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4)
#define	I2C_STATUS_PABORT (0x1UL << 5)
#define	_I2C_STATUS_PABORT_SHIFT 5
#define	_I2C_STATUS_PABORT_MASK 0x20UL
#define	_I2C_STATUS_PABORT_DEFAULT 0x00000000UL
#define	I2C_STATUS_PABORT_DEFAULT (_I2C_STATUS_PABORT_DEFAULT << 5)
#define	I2C_STATUS_TXC (0x1UL << 6)
#define	_I2C_STATUS_TXC_SHIFT 6
#define	_I2C_STATUS_TXC_MASK 0x40UL
#define	_I2C_STATUS_TXC_DEFAULT 0x00000000UL
#define	I2C_STATUS_TXC_DEFAULT (_I2C_STATUS_TXC_DEFAULT << 6)
#define	I2C_STATUS_TXBL (0x1UL << 7)
#define	_I2C_STATUS_TXBL_SHIFT 7
#define	_I2C_STATUS_TXBL_MASK 0x80UL
#define	_I2C_STATUS_TXBL_DEFAULT 0x00000001UL
#define	I2C_STATUS_TXBL_DEFAULT (_I2C_STATUS_TXBL_DEFAULT << 7)
#define	I2C_STATUS_RXDATAV (0x1UL << 8)
#define	_I2C_STATUS_RXDATAV_SHIFT 8
#define	_I2C_STATUS_RXDATAV_MASK 0x100UL
#define	_I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL
#define	I2C_STATUS_RXDATAV_DEFAULT (_I2C_STATUS_RXDATAV_DEFAULT << 8)
#define	_I2C_CLKDIV_RESETVALUE 0x00000000UL
#define	_I2C_CLKDIV_MASK 0x000001FFUL
#define	_I2C_CLKDIV_DIV_SHIFT 0
#define	_I2C_CLKDIV_DIV_MASK 0x1FFUL
#define	_I2C_CLKDIV_DIV_DEFAULT 0x00000000UL
#define	I2C_CLKDIV_DIV_DEFAULT (_I2C_CLKDIV_DIV_DEFAULT << 0)
#define	_I2C_SADDR_RESETVALUE 0x00000000UL
#define	_I2C_SADDR_MASK 0x000000FEUL
#define	_I2C_SADDR_ADDR_SHIFT 1
#define	_I2C_SADDR_ADDR_MASK 0xFEUL
#define	_I2C_SADDR_ADDR_DEFAULT 0x00000000UL
#define	I2C_SADDR_ADDR_DEFAULT (_I2C_SADDR_ADDR_DEFAULT << 1)
#define	_I2C_SADDRMASK_RESETVALUE 0x00000000UL
#define	_I2C_SADDRMASK_MASK 0x000000FEUL
#define	_I2C_SADDRMASK_MASK_SHIFT 1
#define	_I2C_SADDRMASK_MASK_MASK 0xFEUL
#define	_I2C_SADDRMASK_MASK_DEFAULT 0x00000000UL
#define	I2C_SADDRMASK_MASK_DEFAULT (_I2C_SADDRMASK_MASK_DEFAULT << 1)
#define	_I2C_RXDATA_RESETVALUE 0x00000000UL
#define	_I2C_RXDATA_MASK 0x000000FFUL
#define	_I2C_RXDATA_RXDATA_SHIFT 0
#define	_I2C_RXDATA_RXDATA_MASK 0xFFUL
#define	_I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL
#define	I2C_RXDATA_RXDATA_DEFAULT (_I2C_RXDATA_RXDATA_DEFAULT << 0)
#define	_I2C_RXDATAP_RESETVALUE 0x00000000UL
#define	_I2C_RXDATAP_MASK 0x000000FFUL
#define	_I2C_RXDATAP_RXDATAP_SHIFT 0
#define	_I2C_RXDATAP_RXDATAP_MASK 0xFFUL
#define	_I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL
#define	I2C_RXDATAP_RXDATAP_DEFAULT (_I2C_RXDATAP_RXDATAP_DEFAULT << 0)
#define	_I2C_TXDATA_RESETVALUE 0x00000000UL
#define	_I2C_TXDATA_MASK 0x000000FFUL
#define	_I2C_TXDATA_TXDATA_SHIFT 0
#define	_I2C_TXDATA_TXDATA_MASK 0xFFUL
#define	_I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL
#define	I2C_TXDATA_TXDATA_DEFAULT (_I2C_TXDATA_TXDATA_DEFAULT << 0)
#define	_I2C_IF_RESETVALUE 0x00000010UL
#define	_I2C_IF_MASK 0x0001FFFFUL
#define	I2C_IF_START (0x1UL << 0)
#define	_I2C_IF_START_SHIFT 0
#define	_I2C_IF_START_MASK 0x1UL
#define	_I2C_IF_START_DEFAULT 0x00000000UL
#define	I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0)
#define	I2C_IF_RSTART (0x1UL << 1)
#define	_I2C_IF_RSTART_SHIFT 1
#define	_I2C_IF_RSTART_MASK 0x2UL
#define	_I2C_IF_RSTART_DEFAULT 0x00000000UL
#define	I2C_IF_RSTART_DEFAULT (_I2C_IF_RSTART_DEFAULT << 1)
#define	I2C_IF_ADDR (0x1UL << 2)
#define	_I2C_IF_ADDR_SHIFT 2
#define	_I2C_IF_ADDR_MASK 0x4UL
#define	_I2C_IF_ADDR_DEFAULT 0x00000000UL
#define	I2C_IF_ADDR_DEFAULT (_I2C_IF_ADDR_DEFAULT << 2)
#define	I2C_IF_TXC (0x1UL << 3)
#define	_I2C_IF_TXC_SHIFT 3
#define	_I2C_IF_TXC_MASK 0x8UL
#define	_I2C_IF_TXC_DEFAULT 0x00000000UL
#define	I2C_IF_TXC_DEFAULT (_I2C_IF_TXC_DEFAULT << 3)
#define	I2C_IF_TXBL (0x1UL << 4)
#define	_I2C_IF_TXBL_SHIFT 4
#define	_I2C_IF_TXBL_MASK 0x10UL
#define	_I2C_IF_TXBL_DEFAULT 0x00000000UL
#define	I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4)
#define	I2C_IF_RXDATAV (0x1UL << 5)
#define	_I2C_IF_RXDATAV_SHIFT 5
#define	_I2C_IF_RXDATAV_MASK 0x20UL
#define	_I2C_IF_RXDATAV_DEFAULT 0x00000000UL
#define	I2C_IF_RXDATAV_DEFAULT (_I2C_IF_RXDATAV_DEFAULT << 5)
#define	I2C_IF_ACK (0x1UL << 6)
#define	_I2C_IF_ACK_SHIFT 6
#define	_I2C_IF_ACK_MASK 0x40UL
#define	_I2C_IF_ACK_DEFAULT 0x00000000UL
#define	I2C_IF_ACK_DEFAULT (_I2C_IF_ACK_DEFAULT << 6)
#define	I2C_IF_NACK (0x1UL << 7)
#define	_I2C_IF_NACK_SHIFT 7
#define	_I2C_IF_NACK_MASK 0x80UL
#define	_I2C_IF_NACK_DEFAULT 0x00000000UL
#define	I2C_IF_NACK_DEFAULT (_I2C_IF_NACK_DEFAULT << 7)
#define	I2C_IF_MSTOP (0x1UL << 8)
#define	_I2C_IF_MSTOP_SHIFT 8
#define	_I2C_IF_MSTOP_MASK 0x100UL
#define	_I2C_IF_MSTOP_DEFAULT 0x00000000UL
#define	I2C_IF_MSTOP_DEFAULT (_I2C_IF_MSTOP_DEFAULT << 8)
#define	I2C_IF_ARBLOST (0x1UL << 9)
#define	_I2C_IF_ARBLOST_SHIFT 9
#define	_I2C_IF_ARBLOST_MASK 0x200UL
#define	_I2C_IF_ARBLOST_DEFAULT 0x00000000UL
#define	I2C_IF_ARBLOST_DEFAULT (_I2C_IF_ARBLOST_DEFAULT << 9)
#define	I2C_IF_BUSERR (0x1UL << 10)
#define	_I2C_IF_BUSERR_SHIFT 10
#define	_I2C_IF_BUSERR_MASK 0x400UL
#define	_I2C_IF_BUSERR_DEFAULT 0x00000000UL
#define	I2C_IF_BUSERR_DEFAULT (_I2C_IF_BUSERR_DEFAULT << 10)
#define	I2C_IF_BUSHOLD (0x1UL << 11)
#define	_I2C_IF_BUSHOLD_SHIFT 11
#define	_I2C_IF_BUSHOLD_MASK 0x800UL
#define	_I2C_IF_BUSHOLD_DEFAULT 0x00000000UL
#define	I2C_IF_BUSHOLD_DEFAULT (_I2C_IF_BUSHOLD_DEFAULT << 11)
#define	I2C_IF_TXOF (0x1UL << 12)
#define	_I2C_IF_TXOF_SHIFT 12
#define	_I2C_IF_TXOF_MASK 0x1000UL
#define	_I2C_IF_TXOF_DEFAULT 0x00000000UL
#define	I2C_IF_TXOF_DEFAULT (_I2C_IF_TXOF_DEFAULT << 12)
#define	I2C_IF_RXUF (0x1UL << 13)
#define	_I2C_IF_RXUF_SHIFT 13
#define	_I2C_IF_RXUF_MASK 0x2000UL
#define	_I2C_IF_RXUF_DEFAULT 0x00000000UL
#define	I2C_IF_RXUF_DEFAULT (_I2C_IF_RXUF_DEFAULT << 13)
#define	I2C_IF_BITO (0x1UL << 14)
#define	_I2C_IF_BITO_SHIFT 14
#define	_I2C_IF_BITO_MASK 0x4000UL
#define	_I2C_IF_BITO_DEFAULT 0x00000000UL
#define	I2C_IF_BITO_DEFAULT (_I2C_IF_BITO_DEFAULT << 14)
#define	I2C_IF_CLTO (0x1UL << 15)
#define	_I2C_IF_CLTO_SHIFT 15
#define	_I2C_IF_CLTO_MASK 0x8000UL
#define	_I2C_IF_CLTO_DEFAULT 0x00000000UL
#define	I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15)
#define	I2C_IF_SSTOP (0x1UL << 16)
#define	_I2C_IF_SSTOP_SHIFT 16
#define	_I2C_IF_SSTOP_MASK 0x10000UL
#define	_I2C_IF_SSTOP_DEFAULT 0x00000000UL
#define	I2C_IF_SSTOP_DEFAULT (_I2C_IF_SSTOP_DEFAULT << 16)
#define	_I2C_IFS_RESETVALUE 0x00000000UL
#define	_I2C_IFS_MASK 0x0001FFFFUL
#define	I2C_IFS_START (0x1UL << 0)
#define	_I2C_IFS_START_SHIFT 0
#define	_I2C_IFS_START_MASK 0x1UL
#define	_I2C_IFS_START_DEFAULT 0x00000000UL
#define	I2C_IFS_START_DEFAULT (_I2C_IFS_START_DEFAULT << 0)
#define	I2C_IFS_RSTART (0x1UL << 1)
#define	_I2C_IFS_RSTART_SHIFT 1
#define	_I2C_IFS_RSTART_MASK 0x2UL
#define	_I2C_IFS_RSTART_DEFAULT 0x00000000UL
#define	I2C_IFS_RSTART_DEFAULT (_I2C_IFS_RSTART_DEFAULT << 1)
#define	I2C_IFS_ADDR (0x1UL << 2)
#define	_I2C_IFS_ADDR_SHIFT 2
#define	_I2C_IFS_ADDR_MASK 0x4UL
#define	_I2C_IFS_ADDR_DEFAULT 0x00000000UL
#define	I2C_IFS_ADDR_DEFAULT (_I2C_IFS_ADDR_DEFAULT << 2)
#define	I2C_IFS_TXC (0x1UL << 3)
#define	_I2C_IFS_TXC_SHIFT 3
#define	_I2C_IFS_TXC_MASK 0x8UL
#define	_I2C_IFS_TXC_DEFAULT 0x00000000UL
#define	I2C_IFS_TXC_DEFAULT (_I2C_IFS_TXC_DEFAULT << 3)
#define	I2C_IFS_ACK (0x1UL << 6)
#define	_I2C_IFS_ACK_SHIFT 6
#define	_I2C_IFS_ACK_MASK 0x40UL
#define	_I2C_IFS_ACK_DEFAULT 0x00000000UL
#define	I2C_IFS_ACK_DEFAULT (_I2C_IFS_ACK_DEFAULT << 6)
#define	I2C_IFS_NACK (0x1UL << 7)
#define	_I2C_IFS_NACK_SHIFT 7
#define	_I2C_IFS_NACK_MASK 0x80UL
#define	_I2C_IFS_NACK_DEFAULT 0x00000000UL
#define	I2C_IFS_NACK_DEFAULT (_I2C_IFS_NACK_DEFAULT << 7)
#define	I2C_IFS_MSTOP (0x1UL << 8)
#define	_I2C_IFS_MSTOP_SHIFT 8
#define	_I2C_IFS_MSTOP_MASK 0x100UL
#define	_I2C_IFS_MSTOP_DEFAULT 0x00000000UL
#define	I2C_IFS_MSTOP_DEFAULT (_I2C_IFS_MSTOP_DEFAULT << 8)
#define	I2C_IFS_ARBLOST (0x1UL << 9)
#define	_I2C_IFS_ARBLOST_SHIFT 9
#define	_I2C_IFS_ARBLOST_MASK 0x200UL
#define	_I2C_IFS_ARBLOST_DEFAULT 0x00000000UL
#define	I2C_IFS_ARBLOST_DEFAULT (_I2C_IFS_ARBLOST_DEFAULT << 9)
#define	I2C_IFS_BUSERR (0x1UL << 10)
#define	_I2C_IFS_BUSERR_SHIFT 10
#define	_I2C_IFS_BUSERR_MASK 0x400UL
#define	_I2C_IFS_BUSERR_DEFAULT 0x00000000UL
#define	I2C_IFS_BUSERR_DEFAULT (_I2C_IFS_BUSERR_DEFAULT << 10)
#define	I2C_IFS_BUSHOLD (0x1UL << 11)
#define	_I2C_IFS_BUSHOLD_SHIFT 11
#define	_I2C_IFS_BUSHOLD_MASK 0x800UL
#define	_I2C_IFS_BUSHOLD_DEFAULT 0x00000000UL
#define	I2C_IFS_BUSHOLD_DEFAULT (_I2C_IFS_BUSHOLD_DEFAULT << 11)
#define	I2C_IFS_TXOF (0x1UL << 12)
#define	_I2C_IFS_TXOF_SHIFT 12
#define	_I2C_IFS_TXOF_MASK 0x1000UL
#define	_I2C_IFS_TXOF_DEFAULT 0x00000000UL
#define	I2C_IFS_TXOF_DEFAULT (_I2C_IFS_TXOF_DEFAULT << 12)
#define	I2C_IFS_RXUF (0x1UL << 13)
#define	_I2C_IFS_RXUF_SHIFT 13
#define	_I2C_IFS_RXUF_MASK 0x2000UL
#define	_I2C_IFS_RXUF_DEFAULT 0x00000000UL
#define	I2C_IFS_RXUF_DEFAULT (_I2C_IFS_RXUF_DEFAULT << 13)
#define	I2C_IFS_BITO (0x1UL << 14)
#define	_I2C_IFS_BITO_SHIFT 14
#define	_I2C_IFS_BITO_MASK 0x4000UL
#define	_I2C_IFS_BITO_DEFAULT 0x00000000UL
#define	I2C_IFS_BITO_DEFAULT (_I2C_IFS_BITO_DEFAULT << 14)
#define	I2C_IFS_CLTO (0x1UL << 15)
#define	_I2C_IFS_CLTO_SHIFT 15
#define	_I2C_IFS_CLTO_MASK 0x8000UL
#define	_I2C_IFS_CLTO_DEFAULT 0x00000000UL
#define	I2C_IFS_CLTO_DEFAULT (_I2C_IFS_CLTO_DEFAULT << 15)
#define	I2C_IFS_SSTOP (0x1UL << 16)
#define	_I2C_IFS_SSTOP_SHIFT 16
#define	_I2C_IFS_SSTOP_MASK 0x10000UL
#define	_I2C_IFS_SSTOP_DEFAULT 0x00000000UL
#define	I2C_IFS_SSTOP_DEFAULT (_I2C_IFS_SSTOP_DEFAULT << 16)
#define	_I2C_IFC_RESETVALUE 0x00000000UL
#define	_I2C_IFC_MASK 0x0001FFFFUL
#define	I2C_IFC_START (0x1UL << 0)
#define	_I2C_IFC_START_SHIFT 0
#define	_I2C_IFC_START_MASK 0x1UL
#define	_I2C_IFC_START_DEFAULT 0x00000000UL
#define	I2C_IFC_START_DEFAULT (_I2C_IFC_START_DEFAULT << 0)
#define	I2C_IFC_RSTART (0x1UL << 1)
#define	_I2C_IFC_RSTART_SHIFT 1
#define	_I2C_IFC_RSTART_MASK 0x2UL
#define	_I2C_IFC_RSTART_DEFAULT 0x00000000UL
#define	I2C_IFC_RSTART_DEFAULT (_I2C_IFC_RSTART_DEFAULT << 1)
#define	I2C_IFC_ADDR (0x1UL << 2)
#define	_I2C_IFC_ADDR_SHIFT 2
#define	_I2C_IFC_ADDR_MASK 0x4UL
#define	_I2C_IFC_ADDR_DEFAULT 0x00000000UL
#define	I2C_IFC_ADDR_DEFAULT (_I2C_IFC_ADDR_DEFAULT << 2)
#define	I2C_IFC_TXC (0x1UL << 3)
#define	_I2C_IFC_TXC_SHIFT 3
#define	_I2C_IFC_TXC_MASK 0x8UL
#define	_I2C_IFC_TXC_DEFAULT 0x00000000UL
#define	I2C_IFC_TXC_DEFAULT (_I2C_IFC_TXC_DEFAULT << 3)
#define	I2C_IFC_ACK (0x1UL << 6)
#define	_I2C_IFC_ACK_SHIFT 6
#define	_I2C_IFC_ACK_MASK 0x40UL
#define	_I2C_IFC_ACK_DEFAULT 0x00000000UL
#define	I2C_IFC_ACK_DEFAULT (_I2C_IFC_ACK_DEFAULT << 6)
#define	I2C_IFC_NACK (0x1UL << 7)
#define	_I2C_IFC_NACK_SHIFT 7
#define	_I2C_IFC_NACK_MASK 0x80UL
#define	_I2C_IFC_NACK_DEFAULT 0x00000000UL
#define	I2C_IFC_NACK_DEFAULT (_I2C_IFC_NACK_DEFAULT << 7)
#define	I2C_IFC_MSTOP (0x1UL << 8)
#define	_I2C_IFC_MSTOP_SHIFT 8
#define	_I2C_IFC_MSTOP_MASK 0x100UL
#define	_I2C_IFC_MSTOP_DEFAULT 0x00000000UL
#define	I2C_IFC_MSTOP_DEFAULT (_I2C_IFC_MSTOP_DEFAULT << 8)
#define	I2C_IFC_ARBLOST (0x1UL << 9)
#define	_I2C_IFC_ARBLOST_SHIFT 9
#define	_I2C_IFC_ARBLOST_MASK 0x200UL
#define	_I2C_IFC_ARBLOST_DEFAULT 0x00000000UL
#define	I2C_IFC_ARBLOST_DEFAULT (_I2C_IFC_ARBLOST_DEFAULT << 9)
#define	I2C_IFC_BUSERR (0x1UL << 10)
#define	_I2C_IFC_BUSERR_SHIFT 10
#define	_I2C_IFC_BUSERR_MASK 0x400UL
#define	_I2C_IFC_BUSERR_DEFAULT 0x00000000UL
#define	I2C_IFC_BUSERR_DEFAULT (_I2C_IFC_BUSERR_DEFAULT << 10)
#define	I2C_IFC_BUSHOLD (0x1UL << 11)
#define	_I2C_IFC_BUSHOLD_SHIFT 11
#define	_I2C_IFC_BUSHOLD_MASK 0x800UL
#define	_I2C_IFC_BUSHOLD_DEFAULT 0x00000000UL
#define	I2C_IFC_BUSHOLD_DEFAULT (_I2C_IFC_BUSHOLD_DEFAULT << 11)
#define	I2C_IFC_TXOF (0x1UL << 12)
#define	_I2C_IFC_TXOF_SHIFT 12
#define	_I2C_IFC_TXOF_MASK 0x1000UL
#define	_I2C_IFC_TXOF_DEFAULT 0x00000000UL
#define	I2C_IFC_TXOF_DEFAULT (_I2C_IFC_TXOF_DEFAULT << 12)
#define	I2C_IFC_RXUF (0x1UL << 13)
#define	_I2C_IFC_RXUF_SHIFT 13
#define	_I2C_IFC_RXUF_MASK 0x2000UL
#define	_I2C_IFC_RXUF_DEFAULT 0x00000000UL
#define	I2C_IFC_RXUF_DEFAULT (_I2C_IFC_RXUF_DEFAULT << 13)
#define	I2C_IFC_BITO (0x1UL << 14)
#define	_I2C_IFC_BITO_SHIFT 14
#define	_I2C_IFC_BITO_MASK 0x4000UL
#define	_I2C_IFC_BITO_DEFAULT 0x00000000UL
#define	I2C_IFC_BITO_DEFAULT (_I2C_IFC_BITO_DEFAULT << 14)
#define	I2C_IFC_CLTO (0x1UL << 15)
#define	_I2C_IFC_CLTO_SHIFT 15
#define	_I2C_IFC_CLTO_MASK 0x8000UL
#define	_I2C_IFC_CLTO_DEFAULT 0x00000000UL
#define	I2C_IFC_CLTO_DEFAULT (_I2C_IFC_CLTO_DEFAULT << 15)
#define	I2C_IFC_SSTOP (0x1UL << 16)
#define	_I2C_IFC_SSTOP_SHIFT 16
#define	_I2C_IFC_SSTOP_MASK 0x10000UL
#define	_I2C_IFC_SSTOP_DEFAULT 0x00000000UL
#define	I2C_IFC_SSTOP_DEFAULT (_I2C_IFC_SSTOP_DEFAULT << 16)
#define	_I2C_IEN_RESETVALUE 0x00000000UL
#define	_I2C_IEN_MASK 0x0001FFFFUL
#define	I2C_IEN_START (0x1UL << 0)
#define	_I2C_IEN_START_SHIFT 0
#define	_I2C_IEN_START_MASK 0x1UL
#define	_I2C_IEN_START_DEFAULT 0x00000000UL
#define	I2C_IEN_START_DEFAULT (_I2C_IEN_START_DEFAULT << 0)
#define	I2C_IEN_RSTART (0x1UL << 1)
#define	_I2C_IEN_RSTART_SHIFT 1
#define	_I2C_IEN_RSTART_MASK 0x2UL
#define	_I2C_IEN_RSTART_DEFAULT 0x00000000UL
#define	I2C_IEN_RSTART_DEFAULT (_I2C_IEN_RSTART_DEFAULT << 1)
#define	I2C_IEN_ADDR (0x1UL << 2)
#define	_I2C_IEN_ADDR_SHIFT 2
#define	_I2C_IEN_ADDR_MASK 0x4UL
#define	_I2C_IEN_ADDR_DEFAULT 0x00000000UL
#define	I2C_IEN_ADDR_DEFAULT (_I2C_IEN_ADDR_DEFAULT << 2)
#define	I2C_IEN_TXC (0x1UL << 3)
#define	_I2C_IEN_TXC_SHIFT 3
#define	_I2C_IEN_TXC_MASK 0x8UL
#define	_I2C_IEN_TXC_DEFAULT 0x00000000UL
#define	I2C_IEN_TXC_DEFAULT (_I2C_IEN_TXC_DEFAULT << 3)
#define	I2C_IEN_TXBL (0x1UL << 4)
#define	_I2C_IEN_TXBL_SHIFT 4
#define	_I2C_IEN_TXBL_MASK 0x10UL
#define	_I2C_IEN_TXBL_DEFAULT 0x00000000UL
#define	I2C_IEN_TXBL_DEFAULT (_I2C_IEN_TXBL_DEFAULT << 4)
#define	I2C_IEN_RXDATAV (0x1UL << 5)
#define	_I2C_IEN_RXDATAV_SHIFT 5
#define	_I2C_IEN_RXDATAV_MASK 0x20UL
#define	_I2C_IEN_RXDATAV_DEFAULT 0x00000000UL
#define	I2C_IEN_RXDATAV_DEFAULT (_I2C_IEN_RXDATAV_DEFAULT << 5)
#define	I2C_IEN_ACK (0x1UL << 6)
#define	_I2C_IEN_ACK_SHIFT 6
#define	_I2C_IEN_ACK_MASK 0x40UL
#define	_I2C_IEN_ACK_DEFAULT 0x00000000UL
#define	I2C_IEN_ACK_DEFAULT (_I2C_IEN_ACK_DEFAULT << 6)
#define	I2C_IEN_NACK (0x1UL << 7)
#define	_I2C_IEN_NACK_SHIFT 7
#define	_I2C_IEN_NACK_MASK 0x80UL
#define	_I2C_IEN_NACK_DEFAULT 0x00000000UL
#define	I2C_IEN_NACK_DEFAULT (_I2C_IEN_NACK_DEFAULT << 7)
#define	I2C_IEN_MSTOP (0x1UL << 8)
#define	_I2C_IEN_MSTOP_SHIFT 8
#define	_I2C_IEN_MSTOP_MASK 0x100UL
#define	_I2C_IEN_MSTOP_DEFAULT 0x00000000UL
#define	I2C_IEN_MSTOP_DEFAULT (_I2C_IEN_MSTOP_DEFAULT << 8)
#define	I2C_IEN_ARBLOST (0x1UL << 9)
#define	_I2C_IEN_ARBLOST_SHIFT 9
#define	_I2C_IEN_ARBLOST_MASK 0x200UL
#define	_I2C_IEN_ARBLOST_DEFAULT 0x00000000UL
#define	I2C_IEN_ARBLOST_DEFAULT (_I2C_IEN_ARBLOST_DEFAULT << 9)
#define	I2C_IEN_BUSERR (0x1UL << 10)
#define	_I2C_IEN_BUSERR_SHIFT 10
#define	_I2C_IEN_BUSERR_MASK 0x400UL
#define	_I2C_IEN_BUSERR_DEFAULT 0x00000000UL
#define	I2C_IEN_BUSERR_DEFAULT (_I2C_IEN_BUSERR_DEFAULT << 10)
#define	I2C_IEN_BUSHOLD (0x1UL << 11)
#define	_I2C_IEN_BUSHOLD_SHIFT 11
#define	_I2C_IEN_BUSHOLD_MASK 0x800UL
#define	_I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL
#define	I2C_IEN_BUSHOLD_DEFAULT (_I2C_IEN_BUSHOLD_DEFAULT << 11)
#define	I2C_IEN_TXOF (0x1UL << 12)
#define	_I2C_IEN_TXOF_SHIFT 12
#define	_I2C_IEN_TXOF_MASK 0x1000UL
#define	_I2C_IEN_TXOF_DEFAULT 0x00000000UL
#define	I2C_IEN_TXOF_DEFAULT (_I2C_IEN_TXOF_DEFAULT << 12)
#define	I2C_IEN_RXUF (0x1UL << 13)
#define	_I2C_IEN_RXUF_SHIFT 13
#define	_I2C_IEN_RXUF_MASK 0x2000UL
#define	_I2C_IEN_RXUF_DEFAULT 0x00000000UL
#define	I2C_IEN_RXUF_DEFAULT (_I2C_IEN_RXUF_DEFAULT << 13)
#define	I2C_IEN_BITO (0x1UL << 14)
#define	_I2C_IEN_BITO_SHIFT 14
#define	_I2C_IEN_BITO_MASK 0x4000UL
#define	_I2C_IEN_BITO_DEFAULT 0x00000000UL
#define	I2C_IEN_BITO_DEFAULT (_I2C_IEN_BITO_DEFAULT << 14)
#define	I2C_IEN_CLTO (0x1UL << 15)
#define	_I2C_IEN_CLTO_SHIFT 15
#define	_I2C_IEN_CLTO_MASK 0x8000UL
#define	_I2C_IEN_CLTO_DEFAULT 0x00000000UL
#define	I2C_IEN_CLTO_DEFAULT (_I2C_IEN_CLTO_DEFAULT << 15)
#define	I2C_IEN_SSTOP (0x1UL << 16)
#define	_I2C_IEN_SSTOP_SHIFT 16
#define	_I2C_IEN_SSTOP_MASK 0x10000UL
#define	_I2C_IEN_SSTOP_DEFAULT 0x00000000UL
#define	I2C_IEN_SSTOP_DEFAULT (_I2C_IEN_SSTOP_DEFAULT << 16)
#define	_I2C_ROUTE_RESETVALUE 0x00000000UL
#define	_I2C_ROUTE_MASK 0x00000303UL
#define	I2C_ROUTE_SDAPEN (0x1UL << 0)
#define	_I2C_ROUTE_SDAPEN_SHIFT 0
#define	_I2C_ROUTE_SDAPEN_MASK 0x1UL
#define	_I2C_ROUTE_SDAPEN_DEFAULT 0x00000000UL
#define	I2C_ROUTE_SDAPEN_DEFAULT (_I2C_ROUTE_SDAPEN_DEFAULT << 0)
#define	I2C_ROUTE_SCLPEN (0x1UL << 1)
#define	_I2C_ROUTE_SCLPEN_SHIFT 1
#define	_I2C_ROUTE_SCLPEN_MASK 0x2UL
#define	_I2C_ROUTE_SCLPEN_DEFAULT 0x00000000UL
#define	I2C_ROUTE_SCLPEN_DEFAULT (_I2C_ROUTE_SCLPEN_DEFAULT << 1)
#define	_I2C_ROUTE_LOCATION_SHIFT 8
#define	_I2C_ROUTE_LOCATION_MASK 0x300UL
#define	_I2C_ROUTE_LOCATION_DEFAULT 0x00000000UL
#define	_I2C_ROUTE_LOCATION_LOC0 0x00000000UL
#define	_I2C_ROUTE_LOCATION_LOC1 0x00000001UL
#define	_I2C_ROUTE_LOCATION_LOC2 0x00000002UL
#define	_I2C_ROUTE_LOCATION_LOC3 0x00000003UL
#define	I2C_ROUTE_LOCATION_DEFAULT (_I2C_ROUTE_LOCATION_DEFAULT << 8)
#define	I2C_ROUTE_LOCATION_LOC0 (_I2C_ROUTE_LOCATION_LOC0 << 8)
#define	I2C_ROUTE_LOCATION_LOC1 (_I2C_ROUTE_LOCATION_LOC1 << 8)
#define	I2C_ROUTE_LOCATION_LOC2 (_I2C_ROUTE_LOCATION_LOC2 << 8)
#define	I2C_ROUTE_LOCATION_LOC3 (_I2C_ROUTE_LOCATION_LOC3 << 8)
#define	_ADC_CTRL_RESETVALUE 0x001F0000UL
#define	_ADC_CTRL_MASK 0x0F1F7F3BUL
#define	_ADC_CTRL_WARMUPMODE_SHIFT 0
#define	_ADC_CTRL_WARMUPMODE_MASK 0x3UL
#define	_ADC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL
#define	_ADC_CTRL_WARMUPMODE_NORMAL 0x00000000UL
#define	_ADC_CTRL_WARMUPMODE_FASTBG 0x00000001UL
#define	_ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM 0x00000002UL
#define	_ADC_CTRL_WARMUPMODE_KEEPADCWARM 0x00000003UL
#define	ADC_CTRL_WARMUPMODE_DEFAULT (_ADC_CTRL_WARMUPMODE_DEFAULT << 0)
#define	ADC_CTRL_WARMUPMODE_NORMAL (_ADC_CTRL_WARMUPMODE_NORMAL << 0)
#define	ADC_CTRL_WARMUPMODE_FASTBG (_ADC_CTRL_WARMUPMODE_FASTBG << 0)
#define	ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM (_ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM << 0)
#define	ADC_CTRL_WARMUPMODE_KEEPADCWARM (_ADC_CTRL_WARMUPMODE_KEEPADCWARM << 0)
#define	ADC_CTRL_TAILGATE (0x1UL << 3)
#define	_ADC_CTRL_TAILGATE_SHIFT 3
#define	_ADC_CTRL_TAILGATE_MASK 0x8UL
#define	_ADC_CTRL_TAILGATE_DEFAULT 0x00000000UL
#define	ADC_CTRL_TAILGATE_DEFAULT (_ADC_CTRL_TAILGATE_DEFAULT << 3)
#define	_ADC_CTRL_LPFMODE_SHIFT 4
#define	_ADC_CTRL_LPFMODE_MASK 0x30UL
#define	_ADC_CTRL_LPFMODE_DEFAULT 0x00000000UL
#define	_ADC_CTRL_LPFMODE_BYPASS 0x00000000UL
#define	_ADC_CTRL_LPFMODE_DECAP 0x00000001UL
#define	_ADC_CTRL_LPFMODE_RCFILT 0x00000002UL
#define	ADC_CTRL_LPFMODE_DEFAULT (_ADC_CTRL_LPFMODE_DEFAULT << 4)
#define	ADC_CTRL_LPFMODE_BYPASS (_ADC_CTRL_LPFMODE_BYPASS << 4)
#define	ADC_CTRL_LPFMODE_DECAP (_ADC_CTRL_LPFMODE_DECAP << 4)
#define	ADC_CTRL_LPFMODE_RCFILT (_ADC_CTRL_LPFMODE_RCFILT << 4)
#define	_ADC_CTRL_PRESC_SHIFT 8
#define	_ADC_CTRL_PRESC_MASK 0x7F00UL
#define	_ADC_CTRL_PRESC_DEFAULT 0x00000000UL
#define	_ADC_CTRL_PRESC_NODIVISION 0x00000000UL
#define	ADC_CTRL_PRESC_DEFAULT (_ADC_CTRL_PRESC_DEFAULT << 8)
#define	ADC_CTRL_PRESC_NODIVISION (_ADC_CTRL_PRESC_NODIVISION << 8)
#define	_ADC_CTRL_TIMEBASE_SHIFT 16
#define	_ADC_CTRL_TIMEBASE_MASK 0x1F0000UL
#define	_ADC_CTRL_TIMEBASE_DEFAULT 0x0000001FUL
#define	ADC_CTRL_TIMEBASE_DEFAULT (_ADC_CTRL_TIMEBASE_DEFAULT << 16)
#define	_ADC_CTRL_OVSRSEL_SHIFT 24
#define	_ADC_CTRL_OVSRSEL_MASK 0xF000000UL
#define	_ADC_CTRL_OVSRSEL_DEFAULT 0x00000000UL
#define	_ADC_CTRL_OVSRSEL_X2 0x00000000UL
#define	_ADC_CTRL_OVSRSEL_X4 0x00000001UL
#define	_ADC_CTRL_OVSRSEL_X8 0x00000002UL
#define	_ADC_CTRL_OVSRSEL_X16 0x00000003UL
#define	_ADC_CTRL_OVSRSEL_X32 0x00000004UL
#define	_ADC_CTRL_OVSRSEL_X64 0x00000005UL
#define	_ADC_CTRL_OVSRSEL_X128 0x00000006UL
#define	_ADC_CTRL_OVSRSEL_X256 0x00000007UL
#define	_ADC_CTRL_OVSRSEL_X512 0x00000008UL
#define	_ADC_CTRL_OVSRSEL_X1024 0x00000009UL
#define	_ADC_CTRL_OVSRSEL_X2048 0x0000000AUL
#define	_ADC_CTRL_OVSRSEL_X4096 0x0000000BUL
#define	ADC_CTRL_OVSRSEL_DEFAULT (_ADC_CTRL_OVSRSEL_DEFAULT << 24)
#define	ADC_CTRL_OVSRSEL_X2 (_ADC_CTRL_OVSRSEL_X2 << 24)
#define	ADC_CTRL_OVSRSEL_X4 (_ADC_CTRL_OVSRSEL_X4 << 24)
#define	ADC_CTRL_OVSRSEL_X8 (_ADC_CTRL_OVSRSEL_X8 << 24)
#define	ADC_CTRL_OVSRSEL_X16 (_ADC_CTRL_OVSRSEL_X16 << 24)
#define	ADC_CTRL_OVSRSEL_X32 (_ADC_CTRL_OVSRSEL_X32 << 24)
#define	ADC_CTRL_OVSRSEL_X64 (_ADC_CTRL_OVSRSEL_X64 << 24)
#define	ADC_CTRL_OVSRSEL_X128 (_ADC_CTRL_OVSRSEL_X128 << 24)
#define	ADC_CTRL_OVSRSEL_X256 (_ADC_CTRL_OVSRSEL_X256 << 24)
#define	ADC_CTRL_OVSRSEL_X512 (_ADC_CTRL_OVSRSEL_X512 << 24)
#define	ADC_CTRL_OVSRSEL_X1024 (_ADC_CTRL_OVSRSEL_X1024 << 24)
#define	ADC_CTRL_OVSRSEL_X2048 (_ADC_CTRL_OVSRSEL_X2048 << 24)
#define	ADC_CTRL_OVSRSEL_X4096 (_ADC_CTRL_OVSRSEL_X4096 << 24)
#define	_ADC_CMD_RESETVALUE 0x00000000UL
#define	_ADC_CMD_MASK 0x0000000FUL
#define	ADC_CMD_SINGLESTART (0x1UL << 0)
#define	_ADC_CMD_SINGLESTART_SHIFT 0
#define	_ADC_CMD_SINGLESTART_MASK 0x1UL
#define	_ADC_CMD_SINGLESTART_DEFAULT 0x00000000UL
#define	ADC_CMD_SINGLESTART_DEFAULT (_ADC_CMD_SINGLESTART_DEFAULT << 0)
#define	ADC_CMD_SINGLESTOP (0x1UL << 1)
#define	_ADC_CMD_SINGLESTOP_SHIFT 1
#define	_ADC_CMD_SINGLESTOP_MASK 0x2UL
#define	_ADC_CMD_SINGLESTOP_DEFAULT 0x00000000UL
#define	ADC_CMD_SINGLESTOP_DEFAULT (_ADC_CMD_SINGLESTOP_DEFAULT << 1)
#define	ADC_CMD_SCANSTART (0x1UL << 2)
#define	_ADC_CMD_SCANSTART_SHIFT 2
#define	_ADC_CMD_SCANSTART_MASK 0x4UL
#define	_ADC_CMD_SCANSTART_DEFAULT 0x00000000UL
#define	ADC_CMD_SCANSTART_DEFAULT (_ADC_CMD_SCANSTART_DEFAULT << 2)
#define	ADC_CMD_SCANSTOP (0x1UL << 3)
#define	_ADC_CMD_SCANSTOP_SHIFT 3
#define	_ADC_CMD_SCANSTOP_MASK 0x8UL
#define	_ADC_CMD_SCANSTOP_DEFAULT 0x00000000UL
#define	ADC_CMD_SCANSTOP_DEFAULT (_ADC_CMD_SCANSTOP_DEFAULT << 3)
#define	_ADC_STATUS_RESETVALUE 0x00000000UL
#define	_ADC_STATUS_MASK 0x07031303UL
#define	ADC_STATUS_SINGLEACT (0x1UL << 0)
#define	_ADC_STATUS_SINGLEACT_SHIFT 0
#define	_ADC_STATUS_SINGLEACT_MASK 0x1UL
#define	_ADC_STATUS_SINGLEACT_DEFAULT 0x00000000UL
#define	ADC_STATUS_SINGLEACT_DEFAULT (_ADC_STATUS_SINGLEACT_DEFAULT << 0)
#define	ADC_STATUS_SCANACT (0x1UL << 1)
#define	_ADC_STATUS_SCANACT_SHIFT 1
#define	_ADC_STATUS_SCANACT_MASK 0x2UL
#define	_ADC_STATUS_SCANACT_DEFAULT 0x00000000UL
#define	ADC_STATUS_SCANACT_DEFAULT (_ADC_STATUS_SCANACT_DEFAULT << 1)
#define	ADC_STATUS_SINGLEREFWARM (0x1UL << 8)
#define	_ADC_STATUS_SINGLEREFWARM_SHIFT 8
#define	_ADC_STATUS_SINGLEREFWARM_MASK 0x100UL
#define	_ADC_STATUS_SINGLEREFWARM_DEFAULT 0x00000000UL
#define	ADC_STATUS_SINGLEREFWARM_DEFAULT (_ADC_STATUS_SINGLEREFWARM_DEFAULT << 8)
#define	ADC_STATUS_SCANREFWARM (0x1UL << 9)
#define	_ADC_STATUS_SCANREFWARM_SHIFT 9
#define	_ADC_STATUS_SCANREFWARM_MASK 0x200UL
#define	_ADC_STATUS_SCANREFWARM_DEFAULT 0x00000000UL
#define	ADC_STATUS_SCANREFWARM_DEFAULT (_ADC_STATUS_SCANREFWARM_DEFAULT << 9)
#define	ADC_STATUS_WARM (0x1UL << 12)
#define	_ADC_STATUS_WARM_SHIFT 12
#define	_ADC_STATUS_WARM_MASK 0x1000UL
#define	_ADC_STATUS_WARM_DEFAULT 0x00000000UL
#define	ADC_STATUS_WARM_DEFAULT (_ADC_STATUS_WARM_DEFAULT << 12)
#define	ADC_STATUS_SINGLEDV (0x1UL << 16)
#define	_ADC_STATUS_SINGLEDV_SHIFT 16
#define	_ADC_STATUS_SINGLEDV_MASK 0x10000UL
#define	_ADC_STATUS_SINGLEDV_DEFAULT 0x00000000UL
#define	ADC_STATUS_SINGLEDV_DEFAULT (_ADC_STATUS_SINGLEDV_DEFAULT << 16)
#define	ADC_STATUS_SCANDV (0x1UL << 17)
#define	_ADC_STATUS_SCANDV_SHIFT 17
#define	_ADC_STATUS_SCANDV_MASK 0x20000UL
#define	_ADC_STATUS_SCANDV_DEFAULT 0x00000000UL
#define	ADC_STATUS_SCANDV_DEFAULT (_ADC_STATUS_SCANDV_DEFAULT << 17)
#define	_ADC_STATUS_SCANDATASRC_SHIFT 24
#define	_ADC_STATUS_SCANDATASRC_MASK 0x7000000UL
#define	_ADC_STATUS_SCANDATASRC_DEFAULT 0x00000000UL
#define	_ADC_STATUS_SCANDATASRC_CH0 0x00000000UL
#define	_ADC_STATUS_SCANDATASRC_CH1 0x00000001UL
#define	_ADC_STATUS_SCANDATASRC_CH2 0x00000002UL
#define	_ADC_STATUS_SCANDATASRC_CH3 0x00000003UL
#define	_ADC_STATUS_SCANDATASRC_CH4 0x00000004UL
#define	_ADC_STATUS_SCANDATASRC_CH5 0x00000005UL
#define	_ADC_STATUS_SCANDATASRC_CH6 0x00000006UL
#define	_ADC_STATUS_SCANDATASRC_CH7 0x00000007UL
#define	ADC_STATUS_SCANDATASRC_DEFAULT (_ADC_STATUS_SCANDATASRC_DEFAULT << 24)
#define	ADC_STATUS_SCANDATASRC_CH0 (_ADC_STATUS_SCANDATASRC_CH0 << 24)
#define	ADC_STATUS_SCANDATASRC_CH1 (_ADC_STATUS_SCANDATASRC_CH1 << 24)
#define	ADC_STATUS_SCANDATASRC_CH2 (_ADC_STATUS_SCANDATASRC_CH2 << 24)
#define	ADC_STATUS_SCANDATASRC_CH3 (_ADC_STATUS_SCANDATASRC_CH3 << 24)
#define	ADC_STATUS_SCANDATASRC_CH4 (_ADC_STATUS_SCANDATASRC_CH4 << 24)
#define	ADC_STATUS_SCANDATASRC_CH5 (_ADC_STATUS_SCANDATASRC_CH5 << 24)
#define	ADC_STATUS_SCANDATASRC_CH6 (_ADC_STATUS_SCANDATASRC_CH6 << 24)
#define	ADC_STATUS_SCANDATASRC_CH7 (_ADC_STATUS_SCANDATASRC_CH7 << 24)
#define	_ADC_SINGLECTRL_RESETVALUE 0x00000000UL
#define	_ADC_SINGLECTRL_MASK 0x71F70F37UL
#define	ADC_SINGLECTRL_REP (0x1UL << 0)
#define	_ADC_SINGLECTRL_REP_SHIFT 0
#define	_ADC_SINGLECTRL_REP_MASK 0x1UL
#define	_ADC_SINGLECTRL_REP_DEFAULT 0x00000000UL
#define	ADC_SINGLECTRL_REP_DEFAULT (_ADC_SINGLECTRL_REP_DEFAULT << 0)
#define	ADC_SINGLECTRL_DIFF (0x1UL << 1)
#define	_ADC_SINGLECTRL_DIFF_SHIFT 1
#define	_ADC_SINGLECTRL_DIFF_MASK 0x2UL
#define	_ADC_SINGLECTRL_DIFF_DEFAULT 0x00000000UL
#define	ADC_SINGLECTRL_DIFF_DEFAULT (_ADC_SINGLECTRL_DIFF_DEFAULT << 1)
#define	ADC_SINGLECTRL_ADJ (0x1UL << 2)
#define	_ADC_SINGLECTRL_ADJ_SHIFT 2
#define	_ADC_SINGLECTRL_ADJ_MASK 0x4UL
#define	_ADC_SINGLECTRL_ADJ_DEFAULT 0x00000000UL
#define	_ADC_SINGLECTRL_ADJ_RIGHT 0x00000000UL
#define	_ADC_SINGLECTRL_ADJ_LEFT 0x00000001UL
#define	ADC_SINGLECTRL_ADJ_DEFAULT (_ADC_SINGLECTRL_ADJ_DEFAULT << 2)
#define	ADC_SINGLECTRL_ADJ_RIGHT (_ADC_SINGLECTRL_ADJ_RIGHT << 2)
#define	ADC_SINGLECTRL_ADJ_LEFT (_ADC_SINGLECTRL_ADJ_LEFT << 2)
#define	_ADC_SINGLECTRL_RES_SHIFT 4
#define	_ADC_SINGLECTRL_RES_MASK 0x30UL
#define	_ADC_SINGLECTRL_RES_DEFAULT 0x00000000UL
#define	_ADC_SINGLECTRL_RES_12BIT 0x00000000UL
#define	_ADC_SINGLECTRL_RES_8BIT 0x00000001UL
#define	_ADC_SINGLECTRL_RES_6BIT 0x00000002UL
#define	_ADC_SINGLECTRL_RES_OVS 0x00000003UL
#define	ADC_SINGLECTRL_RES_DEFAULT (_ADC_SINGLECTRL_RES_DEFAULT << 4)
#define	ADC_SINGLECTRL_RES_12BIT (_ADC_SINGLECTRL_RES_12BIT << 4)
#define	ADC_SINGLECTRL_RES_8BIT (_ADC_SINGLECTRL_RES_8BIT << 4)
#define	ADC_SINGLECTRL_RES_6BIT (_ADC_SINGLECTRL_RES_6BIT << 4)
#define	ADC_SINGLECTRL_RES_OVS (_ADC_SINGLECTRL_RES_OVS << 4)
#define	_ADC_SINGLECTRL_INPUTSEL_SHIFT 8
#define	_ADC_SINGLECTRL_INPUTSEL_MASK 0xF00UL
#define	_ADC_SINGLECTRL_INPUTSEL_DEFAULT 0x00000000UL
#define	_ADC_SINGLECTRL_INPUTSEL_CH0 0x00000000UL
#define	_ADC_SINGLECTRL_INPUTSEL_CH0CH1 0x00000000UL
#define	_ADC_SINGLECTRL_INPUTSEL_CH1 0x00000001UL
#define	_ADC_SINGLECTRL_INPUTSEL_CH2CH3 0x00000001UL
#define	_ADC_SINGLECTRL_INPUTSEL_CH2 0x00000002UL
#define	_ADC_SINGLECTRL_INPUTSEL_CH4CH5 0x00000002UL
#define	_ADC_SINGLECTRL_INPUTSEL_CH6CH7 0x00000003UL
#define	_ADC_SINGLECTRL_INPUTSEL_CH3 0x00000003UL
#define	_ADC_SINGLECTRL_INPUTSEL_CH4 0x00000004UL
#define	_ADC_SINGLECTRL_INPUTSEL_DIFF0 0x00000004UL
#define	_ADC_SINGLECTRL_INPUTSEL_CH5 0x00000005UL
#define	_ADC_SINGLECTRL_INPUTSEL_CH6 0x00000006UL
#define	_ADC_SINGLECTRL_INPUTSEL_CH7 0x00000007UL
#define	_ADC_SINGLECTRL_INPUTSEL_TEMP 0x00000008UL
#define	_ADC_SINGLECTRL_INPUTSEL_VDDDIV3 0x00000009UL
#define	_ADC_SINGLECTRL_INPUTSEL_VDD 0x0000000AUL
#define	_ADC_SINGLECTRL_INPUTSEL_VSS 0x0000000BUL
#define	_ADC_SINGLECTRL_INPUTSEL_VREFDIV2 0x0000000CUL
#define	_ADC_SINGLECTRL_INPUTSEL_DAC0OUT0 0x0000000DUL
#define	_ADC_SINGLECTRL_INPUTSEL_DAC0OUT1 0x0000000EUL
#define	ADC_SINGLECTRL_INPUTSEL_DEFAULT (_ADC_SINGLECTRL_INPUTSEL_DEFAULT << 8)
#define	ADC_SINGLECTRL_INPUTSEL_CH0 (_ADC_SINGLECTRL_INPUTSEL_CH0 << 8)
#define	ADC_SINGLECTRL_INPUTSEL_CH0CH1 (_ADC_SINGLECTRL_INPUTSEL_CH0CH1 << 8)
#define	ADC_SINGLECTRL_INPUTSEL_CH1 (_ADC_SINGLECTRL_INPUTSEL_CH1 << 8)
#define	ADC_SINGLECTRL_INPUTSEL_CH2CH3 (_ADC_SINGLECTRL_INPUTSEL_CH2CH3 << 8)
#define	ADC_SINGLECTRL_INPUTSEL_CH2 (_ADC_SINGLECTRL_INPUTSEL_CH2 << 8)
#define	ADC_SINGLECTRL_INPUTSEL_CH4CH5 (_ADC_SINGLECTRL_INPUTSEL_CH4CH5 << 8)
#define	ADC_SINGLECTRL_INPUTSEL_CH6CH7 (_ADC_SINGLECTRL_INPUTSEL_CH6CH7 << 8)
#define	ADC_SINGLECTRL_INPUTSEL_CH3 (_ADC_SINGLECTRL_INPUTSEL_CH3 << 8)
#define	ADC_SINGLECTRL_INPUTSEL_CH4 (_ADC_SINGLECTRL_INPUTSEL_CH4 << 8)
#define	ADC_SINGLECTRL_INPUTSEL_DIFF0 (_ADC_SINGLECTRL_INPUTSEL_DIFF0 << 8)
#define	ADC_SINGLECTRL_INPUTSEL_CH5 (_ADC_SINGLECTRL_INPUTSEL_CH5 << 8)
#define	ADC_SINGLECTRL_INPUTSEL_CH6 (_ADC_SINGLECTRL_INPUTSEL_CH6 << 8)
#define	ADC_SINGLECTRL_INPUTSEL_CH7 (_ADC_SINGLECTRL_INPUTSEL_CH7 << 8)
#define	ADC_SINGLECTRL_INPUTSEL_TEMP (_ADC_SINGLECTRL_INPUTSEL_TEMP << 8)
#define	ADC_SINGLECTRL_INPUTSEL_VDDDIV3 (_ADC_SINGLECTRL_INPUTSEL_VDDDIV3 << 8)
#define	ADC_SINGLECTRL_INPUTSEL_VDD (_ADC_SINGLECTRL_INPUTSEL_VDD << 8)
#define	ADC_SINGLECTRL_INPUTSEL_VSS (_ADC_SINGLECTRL_INPUTSEL_VSS << 8)
#define	ADC_SINGLECTRL_INPUTSEL_VREFDIV2 (_ADC_SINGLECTRL_INPUTSEL_VREFDIV2 << 8)
#define	ADC_SINGLECTRL_INPUTSEL_DAC0OUT0 (_ADC_SINGLECTRL_INPUTSEL_DAC0OUT0 << 8)
#define	ADC_SINGLECTRL_INPUTSEL_DAC0OUT1 (_ADC_SINGLECTRL_INPUTSEL_DAC0OUT1 << 8)
#define	_ADC_SINGLECTRL_REF_SHIFT 16
#define	_ADC_SINGLECTRL_REF_MASK 0x70000UL
#define	_ADC_SINGLECTRL_REF_DEFAULT 0x00000000UL
#define	_ADC_SINGLECTRL_REF_1V25 0x00000000UL
#define	_ADC_SINGLECTRL_REF_2V5 0x00000001UL
#define	_ADC_SINGLECTRL_REF_VDD 0x00000002UL
#define	_ADC_SINGLECTRL_REF_5VDIFF 0x00000003UL
#define	_ADC_SINGLECTRL_REF_EXTSINGLE 0x00000004UL
#define	_ADC_SINGLECTRL_REF_2XEXTDIFF 0x00000005UL
#define	_ADC_SINGLECTRL_REF_2XVDD 0x00000006UL
#define	ADC_SINGLECTRL_REF_DEFAULT (_ADC_SINGLECTRL_REF_DEFAULT << 16)
#define	ADC_SINGLECTRL_REF_1V25 (_ADC_SINGLECTRL_REF_1V25 << 16)
#define	ADC_SINGLECTRL_REF_2V5 (_ADC_SINGLECTRL_REF_2V5 << 16)
#define	ADC_SINGLECTRL_REF_VDD (_ADC_SINGLECTRL_REF_VDD << 16)
#define	ADC_SINGLECTRL_REF_5VDIFF (_ADC_SINGLECTRL_REF_5VDIFF << 16)
#define	ADC_SINGLECTRL_REF_EXTSINGLE (_ADC_SINGLECTRL_REF_EXTSINGLE << 16)
#define	ADC_SINGLECTRL_REF_2XEXTDIFF (_ADC_SINGLECTRL_REF_2XEXTDIFF << 16)
#define	ADC_SINGLECTRL_REF_2XVDD (_ADC_SINGLECTRL_REF_2XVDD << 16)
#define	_ADC_SINGLECTRL_AT_SHIFT 20
#define	_ADC_SINGLECTRL_AT_MASK 0xF00000UL
#define	_ADC_SINGLECTRL_AT_DEFAULT 0x00000000UL
#define	_ADC_SINGLECTRL_AT_1CYCLE 0x00000000UL
#define	_ADC_SINGLECTRL_AT_2CYCLES 0x00000001UL
#define	_ADC_SINGLECTRL_AT_4CYCLES 0x00000002UL
#define	_ADC_SINGLECTRL_AT_8CYCLES 0x00000003UL
#define	_ADC_SINGLECTRL_AT_16CYCLES 0x00000004UL
#define	_ADC_SINGLECTRL_AT_32CYCLES 0x00000005UL
#define	_ADC_SINGLECTRL_AT_64CYCLES 0x00000006UL
#define	_ADC_SINGLECTRL_AT_128CYCLES 0x00000007UL
#define	_ADC_SINGLECTRL_AT_256CYCLES 0x00000008UL
#define	ADC_SINGLECTRL_AT_DEFAULT (_ADC_SINGLECTRL_AT_DEFAULT << 20)
#define	ADC_SINGLECTRL_AT_1CYCLE (_ADC_SINGLECTRL_AT_1CYCLE << 20)
#define	ADC_SINGLECTRL_AT_2CYCLES (_ADC_SINGLECTRL_AT_2CYCLES << 20)
#define	ADC_SINGLECTRL_AT_4CYCLES (_ADC_SINGLECTRL_AT_4CYCLES << 20)
#define	ADC_SINGLECTRL_AT_8CYCLES (_ADC_SINGLECTRL_AT_8CYCLES << 20)
#define	ADC_SINGLECTRL_AT_16CYCLES (_ADC_SINGLECTRL_AT_16CYCLES << 20)
#define	ADC_SINGLECTRL_AT_32CYCLES (_ADC_SINGLECTRL_AT_32CYCLES << 20)
#define	ADC_SINGLECTRL_AT_64CYCLES (_ADC_SINGLECTRL_AT_64CYCLES << 20)
#define	ADC_SINGLECTRL_AT_128CYCLES (_ADC_SINGLECTRL_AT_128CYCLES << 20)
#define	ADC_SINGLECTRL_AT_256CYCLES (_ADC_SINGLECTRL_AT_256CYCLES << 20)
#define	ADC_SINGLECTRL_PRSEN (0x1UL << 24)
#define	_ADC_SINGLECTRL_PRSEN_SHIFT 24
#define	_ADC_SINGLECTRL_PRSEN_MASK 0x1000000UL
#define	_ADC_SINGLECTRL_PRSEN_DEFAULT 0x00000000UL
#define	ADC_SINGLECTRL_PRSEN_DEFAULT (_ADC_SINGLECTRL_PRSEN_DEFAULT << 24)
#define	_ADC_SINGLECTRL_PRSSEL_SHIFT 28
#define	_ADC_SINGLECTRL_PRSSEL_MASK 0x70000000UL
#define	_ADC_SINGLECTRL_PRSSEL_DEFAULT 0x00000000UL
#define	_ADC_SINGLECTRL_PRSSEL_PRSCH0 0x00000000UL
#define	_ADC_SINGLECTRL_PRSSEL_PRSCH1 0x00000001UL
#define	_ADC_SINGLECTRL_PRSSEL_PRSCH2 0x00000002UL
#define	_ADC_SINGLECTRL_PRSSEL_PRSCH3 0x00000003UL
#define	_ADC_SINGLECTRL_PRSSEL_PRSCH4 0x00000004UL
#define	_ADC_SINGLECTRL_PRSSEL_PRSCH5 0x00000005UL
#define	_ADC_SINGLECTRL_PRSSEL_PRSCH6 0x00000006UL
#define	_ADC_SINGLECTRL_PRSSEL_PRSCH7 0x00000007UL
#define	ADC_SINGLECTRL_PRSSEL_DEFAULT (_ADC_SINGLECTRL_PRSSEL_DEFAULT << 28)
#define	ADC_SINGLECTRL_PRSSEL_PRSCH0 (_ADC_SINGLECTRL_PRSSEL_PRSCH0 << 28)
#define	ADC_SINGLECTRL_PRSSEL_PRSCH1 (_ADC_SINGLECTRL_PRSSEL_PRSCH1 << 28)
#define	ADC_SINGLECTRL_PRSSEL_PRSCH2 (_ADC_SINGLECTRL_PRSSEL_PRSCH2 << 28)
#define	ADC_SINGLECTRL_PRSSEL_PRSCH3 (_ADC_SINGLECTRL_PRSSEL_PRSCH3 << 28)
#define	ADC_SINGLECTRL_PRSSEL_PRSCH4 (_ADC_SINGLECTRL_PRSSEL_PRSCH4 << 28)
#define	ADC_SINGLECTRL_PRSSEL_PRSCH5 (_ADC_SINGLECTRL_PRSSEL_PRSCH5 << 28)
#define	ADC_SINGLECTRL_PRSSEL_PRSCH6 (_ADC_SINGLECTRL_PRSSEL_PRSCH6 << 28)
#define	ADC_SINGLECTRL_PRSSEL_PRSCH7 (_ADC_SINGLECTRL_PRSSEL_PRSCH7 << 28)
#define	_ADC_SCANCTRL_RESETVALUE 0x00000000UL
#define	_ADC_SCANCTRL_MASK 0x71F7FF37UL
#define	ADC_SCANCTRL_REP (0x1UL << 0)
#define	_ADC_SCANCTRL_REP_SHIFT 0
#define	_ADC_SCANCTRL_REP_MASK 0x1UL
#define	_ADC_SCANCTRL_REP_DEFAULT 0x00000000UL
#define	ADC_SCANCTRL_REP_DEFAULT (_ADC_SCANCTRL_REP_DEFAULT << 0)
#define	ADC_SCANCTRL_DIFF (0x1UL << 1)
#define	_ADC_SCANCTRL_DIFF_SHIFT 1
#define	_ADC_SCANCTRL_DIFF_MASK 0x2UL
#define	_ADC_SCANCTRL_DIFF_DEFAULT 0x00000000UL
#define	ADC_SCANCTRL_DIFF_DEFAULT (_ADC_SCANCTRL_DIFF_DEFAULT << 1)
#define	ADC_SCANCTRL_ADJ (0x1UL << 2)
#define	_ADC_SCANCTRL_ADJ_SHIFT 2
#define	_ADC_SCANCTRL_ADJ_MASK 0x4UL
#define	_ADC_SCANCTRL_ADJ_DEFAULT 0x00000000UL
#define	_ADC_SCANCTRL_ADJ_RIGHT 0x00000000UL
#define	_ADC_SCANCTRL_ADJ_LEFT 0x00000001UL
#define	ADC_SCANCTRL_ADJ_DEFAULT (_ADC_SCANCTRL_ADJ_DEFAULT << 2)
#define	ADC_SCANCTRL_ADJ_RIGHT (_ADC_SCANCTRL_ADJ_RIGHT << 2)
#define	ADC_SCANCTRL_ADJ_LEFT (_ADC_SCANCTRL_ADJ_LEFT << 2)
#define	_ADC_SCANCTRL_RES_SHIFT 4
#define	_ADC_SCANCTRL_RES_MASK 0x30UL
#define	_ADC_SCANCTRL_RES_DEFAULT 0x00000000UL
#define	_ADC_SCANCTRL_RES_12BIT 0x00000000UL
#define	_ADC_SCANCTRL_RES_8BIT 0x00000001UL
#define	_ADC_SCANCTRL_RES_6BIT 0x00000002UL
#define	_ADC_SCANCTRL_RES_OVS 0x00000003UL
#define	ADC_SCANCTRL_RES_DEFAULT (_ADC_SCANCTRL_RES_DEFAULT << 4)
#define	ADC_SCANCTRL_RES_12BIT (_ADC_SCANCTRL_RES_12BIT << 4)
#define	ADC_SCANCTRL_RES_8BIT (_ADC_SCANCTRL_RES_8BIT << 4)
#define	ADC_SCANCTRL_RES_6BIT (_ADC_SCANCTRL_RES_6BIT << 4)
#define	ADC_SCANCTRL_RES_OVS (_ADC_SCANCTRL_RES_OVS << 4)
#define	_ADC_SCANCTRL_INPUTMASK_SHIFT 8
#define	_ADC_SCANCTRL_INPUTMASK_MASK 0xFF00UL
#define	_ADC_SCANCTRL_INPUTMASK_DEFAULT 0x00000000UL
#define	_ADC_SCANCTRL_INPUTMASK_CH0 0x00000001UL
#define	_ADC_SCANCTRL_INPUTMASK_CH0CH1 0x00000001UL
#define	_ADC_SCANCTRL_INPUTMASK_CH1 0x00000002UL
#define	_ADC_SCANCTRL_INPUTMASK_CH2CH3 0x00000002UL
#define	_ADC_SCANCTRL_INPUTMASK_CH2 0x00000004UL
#define	_ADC_SCANCTRL_INPUTMASK_CH4CH5 0x00000004UL
#define	_ADC_SCANCTRL_INPUTMASK_CH6CH7 0x00000008UL
#define	_ADC_SCANCTRL_INPUTMASK_CH3 0x00000008UL
#define	_ADC_SCANCTRL_INPUTMASK_CH4 0x00000010UL
#define	_ADC_SCANCTRL_INPUTMASK_CH5 0x00000020UL
#define	_ADC_SCANCTRL_INPUTMASK_CH6 0x00000040UL
#define	_ADC_SCANCTRL_INPUTMASK_CH7 0x00000080UL
#define	ADC_SCANCTRL_INPUTMASK_DEFAULT (_ADC_SCANCTRL_INPUTMASK_DEFAULT << 8)
#define	ADC_SCANCTRL_INPUTMASK_CH0 (_ADC_SCANCTRL_INPUTMASK_CH0 << 8)
#define	ADC_SCANCTRL_INPUTMASK_CH0CH1 (_ADC_SCANCTRL_INPUTMASK_CH0CH1 << 8)
#define	ADC_SCANCTRL_INPUTMASK_CH1 (_ADC_SCANCTRL_INPUTMASK_CH1 << 8)
#define	ADC_SCANCTRL_INPUTMASK_CH2CH3 (_ADC_SCANCTRL_INPUTMASK_CH2CH3 << 8)
#define	ADC_SCANCTRL_INPUTMASK_CH2 (_ADC_SCANCTRL_INPUTMASK_CH2 << 8)
#define	ADC_SCANCTRL_INPUTMASK_CH4CH5 (_ADC_SCANCTRL_INPUTMASK_CH4CH5 << 8)
#define	ADC_SCANCTRL_INPUTMASK_CH6CH7 (_ADC_SCANCTRL_INPUTMASK_CH6CH7 << 8)
#define	ADC_SCANCTRL_INPUTMASK_CH3 (_ADC_SCANCTRL_INPUTMASK_CH3 << 8)
#define	ADC_SCANCTRL_INPUTMASK_CH4 (_ADC_SCANCTRL_INPUTMASK_CH4 << 8)
#define	ADC_SCANCTRL_INPUTMASK_CH5 (_ADC_SCANCTRL_INPUTMASK_CH5 << 8)
#define	ADC_SCANCTRL_INPUTMASK_CH6 (_ADC_SCANCTRL_INPUTMASK_CH6 << 8)
#define	ADC_SCANCTRL_INPUTMASK_CH7 (_ADC_SCANCTRL_INPUTMASK_CH7 << 8)
#define	_ADC_SCANCTRL_REF_SHIFT 16
#define	_ADC_SCANCTRL_REF_MASK 0x70000UL
#define	_ADC_SCANCTRL_REF_DEFAULT 0x00000000UL
#define	_ADC_SCANCTRL_REF_1V25 0x00000000UL
#define	_ADC_SCANCTRL_REF_2V5 0x00000001UL
#define	_ADC_SCANCTRL_REF_VDD 0x00000002UL
#define	_ADC_SCANCTRL_REF_5VDIFF 0x00000003UL
#define	_ADC_SCANCTRL_REF_EXTSINGLE 0x00000004UL
#define	_ADC_SCANCTRL_REF_2XEXTDIFF 0x00000005UL
#define	_ADC_SCANCTRL_REF_2XVDD 0x00000006UL
#define	ADC_SCANCTRL_REF_DEFAULT (_ADC_SCANCTRL_REF_DEFAULT << 16)
#define	ADC_SCANCTRL_REF_1V25 (_ADC_SCANCTRL_REF_1V25 << 16)
#define	ADC_SCANCTRL_REF_2V5 (_ADC_SCANCTRL_REF_2V5 << 16)
#define	ADC_SCANCTRL_REF_VDD (_ADC_SCANCTRL_REF_VDD << 16)
#define	ADC_SCANCTRL_REF_5VDIFF (_ADC_SCANCTRL_REF_5VDIFF << 16)
#define	ADC_SCANCTRL_REF_EXTSINGLE (_ADC_SCANCTRL_REF_EXTSINGLE << 16)
#define	ADC_SCANCTRL_REF_2XEXTDIFF (_ADC_SCANCTRL_REF_2XEXTDIFF << 16)
#define	ADC_SCANCTRL_REF_2XVDD (_ADC_SCANCTRL_REF_2XVDD << 16)
#define	_ADC_SCANCTRL_AT_SHIFT 20
#define	_ADC_SCANCTRL_AT_MASK 0xF00000UL
#define	_ADC_SCANCTRL_AT_DEFAULT 0x00000000UL
#define	_ADC_SCANCTRL_AT_1CYCLE 0x00000000UL
#define	_ADC_SCANCTRL_AT_2CYCLES 0x00000001UL
#define	_ADC_SCANCTRL_AT_4CYCLES 0x00000002UL
#define	_ADC_SCANCTRL_AT_8CYCLES 0x00000003UL
#define	_ADC_SCANCTRL_AT_16CYCLES 0x00000004UL
#define	_ADC_SCANCTRL_AT_32CYCLES 0x00000005UL
#define	_ADC_SCANCTRL_AT_64CYCLES 0x00000006UL
#define	_ADC_SCANCTRL_AT_128CYCLES 0x00000007UL
#define	_ADC_SCANCTRL_AT_256CYCLES 0x00000008UL
#define	ADC_SCANCTRL_AT_DEFAULT (_ADC_SCANCTRL_AT_DEFAULT << 20)
#define	ADC_SCANCTRL_AT_1CYCLE (_ADC_SCANCTRL_AT_1CYCLE << 20)
#define	ADC_SCANCTRL_AT_2CYCLES (_ADC_SCANCTRL_AT_2CYCLES << 20)
#define	ADC_SCANCTRL_AT_4CYCLES (_ADC_SCANCTRL_AT_4CYCLES << 20)
#define	ADC_SCANCTRL_AT_8CYCLES (_ADC_SCANCTRL_AT_8CYCLES << 20)
#define	ADC_SCANCTRL_AT_16CYCLES (_ADC_SCANCTRL_AT_16CYCLES << 20)
#define	ADC_SCANCTRL_AT_32CYCLES (_ADC_SCANCTRL_AT_32CYCLES << 20)
#define	ADC_SCANCTRL_AT_64CYCLES (_ADC_SCANCTRL_AT_64CYCLES << 20)
#define	ADC_SCANCTRL_AT_128CYCLES (_ADC_SCANCTRL_AT_128CYCLES << 20)
#define	ADC_SCANCTRL_AT_256CYCLES (_ADC_SCANCTRL_AT_256CYCLES << 20)
#define	ADC_SCANCTRL_PRSEN (0x1UL << 24)
#define	_ADC_SCANCTRL_PRSEN_SHIFT 24
#define	_ADC_SCANCTRL_PRSEN_MASK 0x1000000UL
#define	_ADC_SCANCTRL_PRSEN_DEFAULT 0x00000000UL
#define	ADC_SCANCTRL_PRSEN_DEFAULT (_ADC_SCANCTRL_PRSEN_DEFAULT << 24)
#define	_ADC_SCANCTRL_PRSSEL_SHIFT 28
#define	_ADC_SCANCTRL_PRSSEL_MASK 0x70000000UL
#define	_ADC_SCANCTRL_PRSSEL_DEFAULT 0x00000000UL
#define	_ADC_SCANCTRL_PRSSEL_PRSCH0 0x00000000UL
#define	_ADC_SCANCTRL_PRSSEL_PRSCH1 0x00000001UL
#define	_ADC_SCANCTRL_PRSSEL_PRSCH2 0x00000002UL
#define	_ADC_SCANCTRL_PRSSEL_PRSCH3 0x00000003UL
#define	_ADC_SCANCTRL_PRSSEL_PRSCH4 0x00000004UL
#define	_ADC_SCANCTRL_PRSSEL_PRSCH5 0x00000005UL
#define	_ADC_SCANCTRL_PRSSEL_PRSCH6 0x00000006UL
#define	_ADC_SCANCTRL_PRSSEL_PRSCH7 0x00000007UL
#define	ADC_SCANCTRL_PRSSEL_DEFAULT (_ADC_SCANCTRL_PRSSEL_DEFAULT << 28)
#define	ADC_SCANCTRL_PRSSEL_PRSCH0 (_ADC_SCANCTRL_PRSSEL_PRSCH0 << 28)
#define	ADC_SCANCTRL_PRSSEL_PRSCH1 (_ADC_SCANCTRL_PRSSEL_PRSCH1 << 28)
#define	ADC_SCANCTRL_PRSSEL_PRSCH2 (_ADC_SCANCTRL_PRSSEL_PRSCH2 << 28)
#define	ADC_SCANCTRL_PRSSEL_PRSCH3 (_ADC_SCANCTRL_PRSSEL_PRSCH3 << 28)
#define	ADC_SCANCTRL_PRSSEL_PRSCH4 (_ADC_SCANCTRL_PRSSEL_PRSCH4 << 28)
#define	ADC_SCANCTRL_PRSSEL_PRSCH5 (_ADC_SCANCTRL_PRSSEL_PRSCH5 << 28)
#define	ADC_SCANCTRL_PRSSEL_PRSCH6 (_ADC_SCANCTRL_PRSSEL_PRSCH6 << 28)
#define	ADC_SCANCTRL_PRSSEL_PRSCH7 (_ADC_SCANCTRL_PRSSEL_PRSCH7 << 28)
#define	_ADC_IEN_RESETVALUE 0x00000000UL
#define	_ADC_IEN_MASK 0x00000303UL
#define	ADC_IEN_SINGLE (0x1UL << 0)
#define	_ADC_IEN_SINGLE_SHIFT 0
#define	_ADC_IEN_SINGLE_MASK 0x1UL
#define	_ADC_IEN_SINGLE_DEFAULT 0x00000000UL
#define	ADC_IEN_SINGLE_DEFAULT (_ADC_IEN_SINGLE_DEFAULT << 0)
#define	ADC_IEN_SCAN (0x1UL << 1)
#define	_ADC_IEN_SCAN_SHIFT 1
#define	_ADC_IEN_SCAN_MASK 0x2UL
#define	_ADC_IEN_SCAN_DEFAULT 0x00000000UL
#define	ADC_IEN_SCAN_DEFAULT (_ADC_IEN_SCAN_DEFAULT << 1)
#define	ADC_IEN_SINGLEOF (0x1UL << 8)
#define	_ADC_IEN_SINGLEOF_SHIFT 8
#define	_ADC_IEN_SINGLEOF_MASK 0x100UL
#define	_ADC_IEN_SINGLEOF_DEFAULT 0x00000000UL
#define	ADC_IEN_SINGLEOF_DEFAULT (_ADC_IEN_SINGLEOF_DEFAULT << 8)
#define	ADC_IEN_SCANOF (0x1UL << 9)
#define	_ADC_IEN_SCANOF_SHIFT 9
#define	_ADC_IEN_SCANOF_MASK 0x200UL
#define	_ADC_IEN_SCANOF_DEFAULT 0x00000000UL
#define	ADC_IEN_SCANOF_DEFAULT (_ADC_IEN_SCANOF_DEFAULT << 9)
#define	_ADC_IF_RESETVALUE 0x00000000UL
#define	_ADC_IF_MASK 0x00000303UL
#define	ADC_IF_SINGLE (0x1UL << 0)
#define	_ADC_IF_SINGLE_SHIFT 0
#define	_ADC_IF_SINGLE_MASK 0x1UL
#define	_ADC_IF_SINGLE_DEFAULT 0x00000000UL
#define	ADC_IF_SINGLE_DEFAULT (_ADC_IF_SINGLE_DEFAULT << 0)
#define	ADC_IF_SCAN (0x1UL << 1)
#define	_ADC_IF_SCAN_SHIFT 1
#define	_ADC_IF_SCAN_MASK 0x2UL
#define	_ADC_IF_SCAN_DEFAULT 0x00000000UL
#define	ADC_IF_SCAN_DEFAULT (_ADC_IF_SCAN_DEFAULT << 1)
#define	ADC_IF_SINGLEOF (0x1UL << 8)
#define	_ADC_IF_SINGLEOF_SHIFT 8
#define	_ADC_IF_SINGLEOF_MASK 0x100UL
#define	_ADC_IF_SINGLEOF_DEFAULT 0x00000000UL
#define	ADC_IF_SINGLEOF_DEFAULT (_ADC_IF_SINGLEOF_DEFAULT << 8)
#define	ADC_IF_SCANOF (0x1UL << 9)
#define	_ADC_IF_SCANOF_SHIFT 9
#define	_ADC_IF_SCANOF_MASK 0x200UL
#define	_ADC_IF_SCANOF_DEFAULT 0x00000000UL
#define	ADC_IF_SCANOF_DEFAULT (_ADC_IF_SCANOF_DEFAULT << 9)
#define	_ADC_IFS_RESETVALUE 0x00000000UL
#define	_ADC_IFS_MASK 0x00000303UL
#define	ADC_IFS_SINGLE (0x1UL << 0)
#define	_ADC_IFS_SINGLE_SHIFT 0
#define	_ADC_IFS_SINGLE_MASK 0x1UL
#define	_ADC_IFS_SINGLE_DEFAULT 0x00000000UL
#define	ADC_IFS_SINGLE_DEFAULT (_ADC_IFS_SINGLE_DEFAULT << 0)
#define	ADC_IFS_SCAN (0x1UL << 1)
#define	_ADC_IFS_SCAN_SHIFT 1
#define	_ADC_IFS_SCAN_MASK 0x2UL
#define	_ADC_IFS_SCAN_DEFAULT 0x00000000UL
#define	ADC_IFS_SCAN_DEFAULT (_ADC_IFS_SCAN_DEFAULT << 1)
#define	ADC_IFS_SINGLEOF (0x1UL << 8)
#define	_ADC_IFS_SINGLEOF_SHIFT 8
#define	_ADC_IFS_SINGLEOF_MASK 0x100UL
#define	_ADC_IFS_SINGLEOF_DEFAULT 0x00000000UL
#define	ADC_IFS_SINGLEOF_DEFAULT (_ADC_IFS_SINGLEOF_DEFAULT << 8)
#define	ADC_IFS_SCANOF (0x1UL << 9)
#define	_ADC_IFS_SCANOF_SHIFT 9
#define	_ADC_IFS_SCANOF_MASK 0x200UL
#define	_ADC_IFS_SCANOF_DEFAULT 0x00000000UL
#define	ADC_IFS_SCANOF_DEFAULT (_ADC_IFS_SCANOF_DEFAULT << 9)
#define	_ADC_IFC_RESETVALUE 0x00000000UL
#define	_ADC_IFC_MASK 0x00000303UL
#define	ADC_IFC_SINGLE (0x1UL << 0)
#define	_ADC_IFC_SINGLE_SHIFT 0
#define	_ADC_IFC_SINGLE_MASK 0x1UL
#define	_ADC_IFC_SINGLE_DEFAULT 0x00000000UL
#define	ADC_IFC_SINGLE_DEFAULT (_ADC_IFC_SINGLE_DEFAULT << 0)
#define	ADC_IFC_SCAN (0x1UL << 1)
#define	_ADC_IFC_SCAN_SHIFT 1
#define	_ADC_IFC_SCAN_MASK 0x2UL
#define	_ADC_IFC_SCAN_DEFAULT 0x00000000UL
#define	ADC_IFC_SCAN_DEFAULT (_ADC_IFC_SCAN_DEFAULT << 1)
#define	ADC_IFC_SINGLEOF (0x1UL << 8)
#define	_ADC_IFC_SINGLEOF_SHIFT 8
#define	_ADC_IFC_SINGLEOF_MASK 0x100UL
#define	_ADC_IFC_SINGLEOF_DEFAULT 0x00000000UL
#define	ADC_IFC_SINGLEOF_DEFAULT (_ADC_IFC_SINGLEOF_DEFAULT << 8)
#define	ADC_IFC_SCANOF (0x1UL << 9)
#define	_ADC_IFC_SCANOF_SHIFT 9
#define	_ADC_IFC_SCANOF_MASK 0x200UL
#define	_ADC_IFC_SCANOF_DEFAULT 0x00000000UL
#define	ADC_IFC_SCANOF_DEFAULT (_ADC_IFC_SCANOF_DEFAULT << 9)
#define	_ADC_SINGLEDATA_RESETVALUE 0x00000000UL
#define	_ADC_SINGLEDATA_MASK 0xFFFFFFFFUL
#define	_ADC_SINGLEDATA_DATA_SHIFT 0
#define	_ADC_SINGLEDATA_DATA_MASK 0xFFFFFFFFUL
#define	_ADC_SINGLEDATA_DATA_DEFAULT 0x00000000UL
#define	ADC_SINGLEDATA_DATA_DEFAULT (_ADC_SINGLEDATA_DATA_DEFAULT << 0)
#define	_ADC_SCANDATA_RESETVALUE 0x00000000UL
#define	_ADC_SCANDATA_MASK 0xFFFFFFFFUL
#define	_ADC_SCANDATA_DATA_SHIFT 0
#define	_ADC_SCANDATA_DATA_MASK 0xFFFFFFFFUL
#define	_ADC_SCANDATA_DATA_DEFAULT 0x00000000UL
#define	ADC_SCANDATA_DATA_DEFAULT (_ADC_SCANDATA_DATA_DEFAULT << 0)
#define	_ADC_SINGLEDATAP_RESETVALUE 0x00000000UL
#define	_ADC_SINGLEDATAP_MASK 0xFFFFFFFFUL
#define	_ADC_SINGLEDATAP_DATAP_SHIFT 0
#define	_ADC_SINGLEDATAP_DATAP_MASK 0xFFFFFFFFUL
#define	_ADC_SINGLEDATAP_DATAP_DEFAULT 0x00000000UL
#define	ADC_SINGLEDATAP_DATAP_DEFAULT (_ADC_SINGLEDATAP_DATAP_DEFAULT << 0)
#define	_ADC_SCANDATAP_RESETVALUE 0x00000000UL
#define	_ADC_SCANDATAP_MASK 0xFFFFFFFFUL
#define	_ADC_SCANDATAP_DATAP_SHIFT 0
#define	_ADC_SCANDATAP_DATAP_MASK 0xFFFFFFFFUL
#define	_ADC_SCANDATAP_DATAP_DEFAULT 0x00000000UL
#define	ADC_SCANDATAP_DATAP_DEFAULT (_ADC_SCANDATAP_DATAP_DEFAULT << 0)
#define	_ADC_CAL_RESETVALUE 0x3F003F00UL
#define	_ADC_CAL_MASK 0x7F7F7F7FUL
#define	_ADC_CAL_SINGLEOFFSET_SHIFT 0
#define	_ADC_CAL_SINGLEOFFSET_MASK 0x7FUL
#define	_ADC_CAL_SINGLEOFFSET_DEFAULT 0x00000000UL
#define	ADC_CAL_SINGLEOFFSET_DEFAULT (_ADC_CAL_SINGLEOFFSET_DEFAULT << 0)
#define	_ADC_CAL_SINGLEGAIN_SHIFT 8
#define	_ADC_CAL_SINGLEGAIN_MASK 0x7F00UL
#define	_ADC_CAL_SINGLEGAIN_DEFAULT 0x0000003FUL
#define	ADC_CAL_SINGLEGAIN_DEFAULT (_ADC_CAL_SINGLEGAIN_DEFAULT << 8)
#define	_ADC_CAL_SCANOFFSET_SHIFT 16
#define	_ADC_CAL_SCANOFFSET_MASK 0x7F0000UL
#define	_ADC_CAL_SCANOFFSET_DEFAULT 0x00000000UL
#define	ADC_CAL_SCANOFFSET_DEFAULT (_ADC_CAL_SCANOFFSET_DEFAULT << 16)
#define	_ADC_CAL_SCANGAIN_SHIFT 24
#define	_ADC_CAL_SCANGAIN_MASK 0x7F000000UL
#define	_ADC_CAL_SCANGAIN_DEFAULT 0x0000003FUL
#define	ADC_CAL_SCANGAIN_DEFAULT (_ADC_CAL_SCANGAIN_DEFAULT << 24)
#define	_ADC_BIASPROG_RESETVALUE 0x00000747UL
#define	_ADC_BIASPROG_MASK 0x00000F4FUL
#define	_ADC_BIASPROG_BIASPROG_SHIFT 0
#define	_ADC_BIASPROG_BIASPROG_MASK 0xFUL
#define	_ADC_BIASPROG_BIASPROG_DEFAULT 0x00000007UL
#define	ADC_BIASPROG_BIASPROG_DEFAULT (_ADC_BIASPROG_BIASPROG_DEFAULT << 0)
#define	ADC_BIASPROG_HALFBIAS (0x1UL << 6)
#define	_ADC_BIASPROG_HALFBIAS_SHIFT 6
#define	_ADC_BIASPROG_HALFBIAS_MASK 0x40UL
#define	_ADC_BIASPROG_HALFBIAS_DEFAULT 0x00000001UL
#define	ADC_BIASPROG_HALFBIAS_DEFAULT (_ADC_BIASPROG_HALFBIAS_DEFAULT << 6)
#define	_ADC_BIASPROG_COMPBIAS_SHIFT 8
#define	_ADC_BIASPROG_COMPBIAS_MASK 0xF00UL
#define	_ADC_BIASPROG_COMPBIAS_DEFAULT 0x00000007UL
#define	ADC_BIASPROG_COMPBIAS_DEFAULT (_ADC_BIASPROG_COMPBIAS_DEFAULT << 8)
#define	_DAC_CTRL_RESETVALUE 0x00000010UL
#define	_DAC_CTRL_MASK 0x0037D3FFUL
#define	DAC_CTRL_DIFF (0x1UL << 0)
#define	_DAC_CTRL_DIFF_SHIFT 0
#define	_DAC_CTRL_DIFF_MASK 0x1UL
#define	_DAC_CTRL_DIFF_DEFAULT 0x00000000UL
#define	DAC_CTRL_DIFF_DEFAULT (_DAC_CTRL_DIFF_DEFAULT << 0)
#define	DAC_CTRL_SINEMODE (0x1UL << 1)
#define	_DAC_CTRL_SINEMODE_SHIFT 1
#define	_DAC_CTRL_SINEMODE_MASK 0x2UL
#define	_DAC_CTRL_SINEMODE_DEFAULT 0x00000000UL
#define	DAC_CTRL_SINEMODE_DEFAULT (_DAC_CTRL_SINEMODE_DEFAULT << 1)
#define	_DAC_CTRL_CONVMODE_SHIFT 2
#define	_DAC_CTRL_CONVMODE_MASK 0xCUL
#define	_DAC_CTRL_CONVMODE_DEFAULT 0x00000000UL
#define	_DAC_CTRL_CONVMODE_CONTINUOUS 0x00000000UL
#define	_DAC_CTRL_CONVMODE_SAMPLEHOLD 0x00000001UL
#define	_DAC_CTRL_CONVMODE_SAMPLEOFF 0x00000002UL
#define	DAC_CTRL_CONVMODE_DEFAULT (_DAC_CTRL_CONVMODE_DEFAULT << 2)
#define	DAC_CTRL_CONVMODE_CONTINUOUS (_DAC_CTRL_CONVMODE_CONTINUOUS << 2)
#define	DAC_CTRL_CONVMODE_SAMPLEHOLD (_DAC_CTRL_CONVMODE_SAMPLEHOLD << 2)
#define	DAC_CTRL_CONVMODE_SAMPLEOFF (_DAC_CTRL_CONVMODE_SAMPLEOFF << 2)
#define	_DAC_CTRL_OUTMODE_SHIFT 4
#define	_DAC_CTRL_OUTMODE_MASK 0x30UL
#define	_DAC_CTRL_OUTMODE_DISABLE 0x00000000UL
#define	_DAC_CTRL_OUTMODE_DEFAULT 0x00000001UL
#define	_DAC_CTRL_OUTMODE_PIN 0x00000001UL
#define	_DAC_CTRL_OUTMODE_ADC 0x00000002UL
#define	_DAC_CTRL_OUTMODE_PINADC 0x00000003UL
#define	DAC_CTRL_OUTMODE_DISABLE (_DAC_CTRL_OUTMODE_DISABLE << 4)
#define	DAC_CTRL_OUTMODE_DEFAULT (_DAC_CTRL_OUTMODE_DEFAULT << 4)
#define	DAC_CTRL_OUTMODE_PIN (_DAC_CTRL_OUTMODE_PIN << 4)
#define	DAC_CTRL_OUTMODE_ADC (_DAC_CTRL_OUTMODE_ADC << 4)
#define	DAC_CTRL_OUTMODE_PINADC (_DAC_CTRL_OUTMODE_PINADC << 4)
#define	DAC_CTRL_OUTENPRS (0x1UL << 6)
#define	_DAC_CTRL_OUTENPRS_SHIFT 6
#define	_DAC_CTRL_OUTENPRS_MASK 0x40UL
#define	_DAC_CTRL_OUTENPRS_DEFAULT 0x00000000UL
#define	DAC_CTRL_OUTENPRS_DEFAULT (_DAC_CTRL_OUTENPRS_DEFAULT << 6)
#define	DAC_CTRL_CH0PRESCRST (0x1UL << 7)
#define	_DAC_CTRL_CH0PRESCRST_SHIFT 7
#define	_DAC_CTRL_CH0PRESCRST_MASK 0x80UL
#define	_DAC_CTRL_CH0PRESCRST_DEFAULT 0x00000000UL
#define	DAC_CTRL_CH0PRESCRST_DEFAULT (_DAC_CTRL_CH0PRESCRST_DEFAULT << 7)
#define	_DAC_CTRL_REFSEL_SHIFT 8
#define	_DAC_CTRL_REFSEL_MASK 0x300UL
#define	_DAC_CTRL_REFSEL_DEFAULT 0x00000000UL
#define	_DAC_CTRL_REFSEL_1V25 0x00000000UL
#define	_DAC_CTRL_REFSEL_2V5 0x00000001UL
#define	_DAC_CTRL_REFSEL_VDD 0x00000002UL
#define	DAC_CTRL_REFSEL_DEFAULT (_DAC_CTRL_REFSEL_DEFAULT << 8)
#define	DAC_CTRL_REFSEL_1V25 (_DAC_CTRL_REFSEL_1V25 << 8)
#define	DAC_CTRL_REFSEL_2V5 (_DAC_CTRL_REFSEL_2V5 << 8)
#define	DAC_CTRL_REFSEL_VDD (_DAC_CTRL_REFSEL_VDD << 8)
#define	DAC_CTRL_LPFEN (0x1UL << 12)
#define	_DAC_CTRL_LPFEN_SHIFT 12
#define	_DAC_CTRL_LPFEN_MASK 0x1000UL
#define	_DAC_CTRL_LPFEN_DEFAULT 0x00000000UL
#define	DAC_CTRL_LPFEN_DEFAULT (_DAC_CTRL_LPFEN_DEFAULT << 12)
#define	_DAC_CTRL_LPFFREQ_SHIFT 14
#define	_DAC_CTRL_LPFFREQ_MASK 0xC000UL
#define	_DAC_CTRL_LPFFREQ_DEFAULT 0x00000000UL
#define	_DAC_CTRL_LPFFREQ_FREQ0 0x00000000UL
#define	_DAC_CTRL_LPFFREQ_FREQ1 0x00000001UL
#define	_DAC_CTRL_LPFFREQ_FREQ2 0x00000002UL
#define	_DAC_CTRL_LPFFREQ_FREQ3 0x00000003UL
#define	DAC_CTRL_LPFFREQ_DEFAULT (_DAC_CTRL_LPFFREQ_DEFAULT << 14)
#define	DAC_CTRL_LPFFREQ_FREQ0 (_DAC_CTRL_LPFFREQ_FREQ0 << 14)
#define	DAC_CTRL_LPFFREQ_FREQ1 (_DAC_CTRL_LPFFREQ_FREQ1 << 14)
#define	DAC_CTRL_LPFFREQ_FREQ2 (_DAC_CTRL_LPFFREQ_FREQ2 << 14)
#define	DAC_CTRL_LPFFREQ_FREQ3 (_DAC_CTRL_LPFFREQ_FREQ3 << 14)
#define	_DAC_CTRL_PRESC_SHIFT 16
#define	_DAC_CTRL_PRESC_MASK 0x70000UL
#define	_DAC_CTRL_PRESC_DEFAULT 0x00000000UL
#define	_DAC_CTRL_PRESC_NODIVISION 0x00000000UL
#define	DAC_CTRL_PRESC_DEFAULT (_DAC_CTRL_PRESC_DEFAULT << 16)
#define	DAC_CTRL_PRESC_NODIVISION (_DAC_CTRL_PRESC_NODIVISION << 16)
#define	_DAC_CTRL_REFRSEL_SHIFT 20
#define	_DAC_CTRL_REFRSEL_MASK 0x300000UL
#define	_DAC_CTRL_REFRSEL_DEFAULT 0x00000000UL
#define	_DAC_CTRL_REFRSEL_8CYCLES 0x00000000UL
#define	_DAC_CTRL_REFRSEL_16CYCLES 0x00000001UL
#define	_DAC_CTRL_REFRSEL_32CYCLES 0x00000002UL
#define	_DAC_CTRL_REFRSEL_64CYCLES 0x00000003UL
#define	DAC_CTRL_REFRSEL_DEFAULT (_DAC_CTRL_REFRSEL_DEFAULT << 20)
#define	DAC_CTRL_REFRSEL_8CYCLES (_DAC_CTRL_REFRSEL_8CYCLES << 20)
#define	DAC_CTRL_REFRSEL_16CYCLES (_DAC_CTRL_REFRSEL_16CYCLES << 20)
#define	DAC_CTRL_REFRSEL_32CYCLES (_DAC_CTRL_REFRSEL_32CYCLES << 20)
#define	DAC_CTRL_REFRSEL_64CYCLES (_DAC_CTRL_REFRSEL_64CYCLES << 20)
#define	_DAC_STATUS_RESETVALUE 0x00000000UL
#define	_DAC_STATUS_MASK 0x00000003UL
#define	DAC_STATUS_CH0DV (0x1UL << 0)
#define	_DAC_STATUS_CH0DV_SHIFT 0
#define	_DAC_STATUS_CH0DV_MASK 0x1UL
#define	_DAC_STATUS_CH0DV_DEFAULT 0x00000000UL
#define	DAC_STATUS_CH0DV_DEFAULT (_DAC_STATUS_CH0DV_DEFAULT << 0)
#define	DAC_STATUS_CH1DV (0x1UL << 1)
#define	_DAC_STATUS_CH1DV_SHIFT 1
#define	_DAC_STATUS_CH1DV_MASK 0x2UL
#define	_DAC_STATUS_CH1DV_DEFAULT 0x00000000UL
#define	DAC_STATUS_CH1DV_DEFAULT (_DAC_STATUS_CH1DV_DEFAULT << 1)
#define	_DAC_CH0CTRL_RESETVALUE 0x00000000UL
#define	_DAC_CH0CTRL_MASK 0x00000077UL
#define	DAC_CH0CTRL_EN (0x1UL << 0)
#define	_DAC_CH0CTRL_EN_SHIFT 0
#define	_DAC_CH0CTRL_EN_MASK 0x1UL
#define	_DAC_CH0CTRL_EN_DEFAULT 0x00000000UL
#define	DAC_CH0CTRL_EN_DEFAULT (_DAC_CH0CTRL_EN_DEFAULT << 0)
#define	DAC_CH0CTRL_REFREN (0x1UL << 1)
#define	_DAC_CH0CTRL_REFREN_SHIFT 1
#define	_DAC_CH0CTRL_REFREN_MASK 0x2UL
#define	_DAC_CH0CTRL_REFREN_DEFAULT 0x00000000UL
#define	DAC_CH0CTRL_REFREN_DEFAULT (_DAC_CH0CTRL_REFREN_DEFAULT << 1)
#define	DAC_CH0CTRL_PRSEN (0x1UL << 2)
#define	_DAC_CH0CTRL_PRSEN_SHIFT 2
#define	_DAC_CH0CTRL_PRSEN_MASK 0x4UL
#define	_DAC_CH0CTRL_PRSEN_DEFAULT 0x00000000UL
#define	DAC_CH0CTRL_PRSEN_DEFAULT (_DAC_CH0CTRL_PRSEN_DEFAULT << 2)
#define	_DAC_CH0CTRL_PRSSEL_SHIFT 4
#define	_DAC_CH0CTRL_PRSSEL_MASK 0x70UL
#define	_DAC_CH0CTRL_PRSSEL_DEFAULT 0x00000000UL
#define	_DAC_CH0CTRL_PRSSEL_PRSCH0 0x00000000UL
#define	_DAC_CH0CTRL_PRSSEL_PRSCH1 0x00000001UL
#define	_DAC_CH0CTRL_PRSSEL_PRSCH2 0x00000002UL
#define	_DAC_CH0CTRL_PRSSEL_PRSCH3 0x00000003UL
#define	_DAC_CH0CTRL_PRSSEL_PRSCH4 0x00000004UL
#define	_DAC_CH0CTRL_PRSSEL_PRSCH5 0x00000005UL
#define	_DAC_CH0CTRL_PRSSEL_PRSCH6 0x00000006UL
#define	_DAC_CH0CTRL_PRSSEL_PRSCH7 0x00000007UL
#define	DAC_CH0CTRL_PRSSEL_DEFAULT (_DAC_CH0CTRL_PRSSEL_DEFAULT << 4)
#define	DAC_CH0CTRL_PRSSEL_PRSCH0 (_DAC_CH0CTRL_PRSSEL_PRSCH0 << 4)
#define	DAC_CH0CTRL_PRSSEL_PRSCH1 (_DAC_CH0CTRL_PRSSEL_PRSCH1 << 4)
#define	DAC_CH0CTRL_PRSSEL_PRSCH2 (_DAC_CH0CTRL_PRSSEL_PRSCH2 << 4)
#define	DAC_CH0CTRL_PRSSEL_PRSCH3 (_DAC_CH0CTRL_PRSSEL_PRSCH3 << 4)
#define	DAC_CH0CTRL_PRSSEL_PRSCH4 (_DAC_CH0CTRL_PRSSEL_PRSCH4 << 4)
#define	DAC_CH0CTRL_PRSSEL_PRSCH5 (_DAC_CH0CTRL_PRSSEL_PRSCH5 << 4)
#define	DAC_CH0CTRL_PRSSEL_PRSCH6 (_DAC_CH0CTRL_PRSSEL_PRSCH6 << 4)
#define	DAC_CH0CTRL_PRSSEL_PRSCH7 (_DAC_CH0CTRL_PRSSEL_PRSCH7 << 4)
#define	_DAC_CH1CTRL_RESETVALUE 0x00000000UL
#define	_DAC_CH1CTRL_MASK 0x00000077UL
#define	DAC_CH1CTRL_EN (0x1UL << 0)
#define	_DAC_CH1CTRL_EN_SHIFT 0
#define	_DAC_CH1CTRL_EN_MASK 0x1UL
#define	_DAC_CH1CTRL_EN_DEFAULT 0x00000000UL
#define	DAC_CH1CTRL_EN_DEFAULT (_DAC_CH1CTRL_EN_DEFAULT << 0)
#define	DAC_CH1CTRL_REFREN (0x1UL << 1)
#define	_DAC_CH1CTRL_REFREN_SHIFT 1
#define	_DAC_CH1CTRL_REFREN_MASK 0x2UL
#define	_DAC_CH1CTRL_REFREN_DEFAULT 0x00000000UL
#define	DAC_CH1CTRL_REFREN_DEFAULT (_DAC_CH1CTRL_REFREN_DEFAULT << 1)
#define	DAC_CH1CTRL_PRSEN (0x1UL << 2)
#define	_DAC_CH1CTRL_PRSEN_SHIFT 2
#define	_DAC_CH1CTRL_PRSEN_MASK 0x4UL
#define	_DAC_CH1CTRL_PRSEN_DEFAULT 0x00000000UL
#define	DAC_CH1CTRL_PRSEN_DEFAULT (_DAC_CH1CTRL_PRSEN_DEFAULT << 2)
#define	_DAC_CH1CTRL_PRSSEL_SHIFT 4
#define	_DAC_CH1CTRL_PRSSEL_MASK 0x70UL
#define	_DAC_CH1CTRL_PRSSEL_DEFAULT 0x00000000UL
#define	_DAC_CH1CTRL_PRSSEL_PRSCH0 0x00000000UL
#define	_DAC_CH1CTRL_PRSSEL_PRSCH1 0x00000001UL
#define	_DAC_CH1CTRL_PRSSEL_PRSCH2 0x00000002UL
#define	_DAC_CH1CTRL_PRSSEL_PRSCH3 0x00000003UL
#define	_DAC_CH1CTRL_PRSSEL_PRSCH4 0x00000004UL
#define	_DAC_CH1CTRL_PRSSEL_PRSCH5 0x00000005UL
#define	_DAC_CH1CTRL_PRSSEL_PRSCH6 0x00000006UL
#define	_DAC_CH1CTRL_PRSSEL_PRSCH7 0x00000007UL
#define	DAC_CH1CTRL_PRSSEL_DEFAULT (_DAC_CH1CTRL_PRSSEL_DEFAULT << 4)
#define	DAC_CH1CTRL_PRSSEL_PRSCH0 (_DAC_CH1CTRL_PRSSEL_PRSCH0 << 4)
#define	DAC_CH1CTRL_PRSSEL_PRSCH1 (_DAC_CH1CTRL_PRSSEL_PRSCH1 << 4)
#define	DAC_CH1CTRL_PRSSEL_PRSCH2 (_DAC_CH1CTRL_PRSSEL_PRSCH2 << 4)
#define	DAC_CH1CTRL_PRSSEL_PRSCH3 (_DAC_CH1CTRL_PRSSEL_PRSCH3 << 4)
#define	DAC_CH1CTRL_PRSSEL_PRSCH4 (_DAC_CH1CTRL_PRSSEL_PRSCH4 << 4)
#define	DAC_CH1CTRL_PRSSEL_PRSCH5 (_DAC_CH1CTRL_PRSSEL_PRSCH5 << 4)
#define	DAC_CH1CTRL_PRSSEL_PRSCH6 (_DAC_CH1CTRL_PRSSEL_PRSCH6 << 4)
#define	DAC_CH1CTRL_PRSSEL_PRSCH7 (_DAC_CH1CTRL_PRSSEL_PRSCH7 << 4)
#define	_DAC_IEN_RESETVALUE 0x00000000UL
#define	_DAC_IEN_MASK 0x00000033UL
#define	DAC_IEN_CH0 (0x1UL << 0)
#define	_DAC_IEN_CH0_SHIFT 0
#define	_DAC_IEN_CH0_MASK 0x1UL
#define	_DAC_IEN_CH0_DEFAULT 0x00000000UL
#define	DAC_IEN_CH0_DEFAULT (_DAC_IEN_CH0_DEFAULT << 0)
#define	DAC_IEN_CH1 (0x1UL << 1)
#define	_DAC_IEN_CH1_SHIFT 1
#define	_DAC_IEN_CH1_MASK 0x2UL
#define	_DAC_IEN_CH1_DEFAULT 0x00000000UL
#define	DAC_IEN_CH1_DEFAULT (_DAC_IEN_CH1_DEFAULT << 1)
#define	DAC_IEN_CH0UF (0x1UL << 4)
#define	_DAC_IEN_CH0UF_SHIFT 4
#define	_DAC_IEN_CH0UF_MASK 0x10UL
#define	_DAC_IEN_CH0UF_DEFAULT 0x00000000UL
#define	DAC_IEN_CH0UF_DEFAULT (_DAC_IEN_CH0UF_DEFAULT << 4)
#define	DAC_IEN_CH1UF (0x1UL << 5)
#define	_DAC_IEN_CH1UF_SHIFT 5
#define	_DAC_IEN_CH1UF_MASK 0x20UL
#define	_DAC_IEN_CH1UF_DEFAULT 0x00000000UL
#define	DAC_IEN_CH1UF_DEFAULT (_DAC_IEN_CH1UF_DEFAULT << 5)
#define	_DAC_IF_RESETVALUE 0x00000000UL
#define	_DAC_IF_MASK 0x00000033UL
#define	DAC_IF_CH0 (0x1UL << 0)
#define	_DAC_IF_CH0_SHIFT 0
#define	_DAC_IF_CH0_MASK 0x1UL
#define	_DAC_IF_CH0_DEFAULT 0x00000000UL
#define	DAC_IF_CH0_DEFAULT (_DAC_IF_CH0_DEFAULT << 0)
#define	DAC_IF_CH1 (0x1UL << 1)
#define	_DAC_IF_CH1_SHIFT 1
#define	_DAC_IF_CH1_MASK 0x2UL
#define	_DAC_IF_CH1_DEFAULT 0x00000000UL
#define	DAC_IF_CH1_DEFAULT (_DAC_IF_CH1_DEFAULT << 1)
#define	DAC_IF_CH0UF (0x1UL << 4)
#define	_DAC_IF_CH0UF_SHIFT 4
#define	_DAC_IF_CH0UF_MASK 0x10UL
#define	_DAC_IF_CH0UF_DEFAULT 0x00000000UL
#define	DAC_IF_CH0UF_DEFAULT (_DAC_IF_CH0UF_DEFAULT << 4)
#define	DAC_IF_CH1UF (0x1UL << 5)
#define	_DAC_IF_CH1UF_SHIFT 5
#define	_DAC_IF_CH1UF_MASK 0x20UL
#define	_DAC_IF_CH1UF_DEFAULT 0x00000000UL
#define	DAC_IF_CH1UF_DEFAULT (_DAC_IF_CH1UF_DEFAULT << 5)
#define	_DAC_IFS_RESETVALUE 0x00000000UL
#define	_DAC_IFS_MASK 0x00000033UL
#define	DAC_IFS_CH0 (0x1UL << 0)
#define	_DAC_IFS_CH0_SHIFT 0
#define	_DAC_IFS_CH0_MASK 0x1UL
#define	_DAC_IFS_CH0_DEFAULT 0x00000000UL
#define	DAC_IFS_CH0_DEFAULT (_DAC_IFS_CH0_DEFAULT << 0)
#define	DAC_IFS_CH1 (0x1UL << 1)
#define	_DAC_IFS_CH1_SHIFT 1
#define	_DAC_IFS_CH1_MASK 0x2UL
#define	_DAC_IFS_CH1_DEFAULT 0x00000000UL
#define	DAC_IFS_CH1_DEFAULT (_DAC_IFS_CH1_DEFAULT << 1)
#define	DAC_IFS_CH0UF (0x1UL << 4)
#define	_DAC_IFS_CH0UF_SHIFT 4
#define	_DAC_IFS_CH0UF_MASK 0x10UL
#define	_DAC_IFS_CH0UF_DEFAULT 0x00000000UL
#define	DAC_IFS_CH0UF_DEFAULT (_DAC_IFS_CH0UF_DEFAULT << 4)
#define	DAC_IFS_CH1UF (0x1UL << 5)
#define	_DAC_IFS_CH1UF_SHIFT 5
#define	_DAC_IFS_CH1UF_MASK 0x20UL
#define	_DAC_IFS_CH1UF_DEFAULT 0x00000000UL
#define	DAC_IFS_CH1UF_DEFAULT (_DAC_IFS_CH1UF_DEFAULT << 5)
#define	_DAC_IFC_RESETVALUE 0x00000000UL
#define	_DAC_IFC_MASK 0x00000033UL
#define	DAC_IFC_CH0 (0x1UL << 0)
#define	_DAC_IFC_CH0_SHIFT 0
#define	_DAC_IFC_CH0_MASK 0x1UL
#define	_DAC_IFC_CH0_DEFAULT 0x00000000UL
#define	DAC_IFC_CH0_DEFAULT (_DAC_IFC_CH0_DEFAULT << 0)
#define	DAC_IFC_CH1 (0x1UL << 1)
#define	_DAC_IFC_CH1_SHIFT 1
#define	_DAC_IFC_CH1_MASK 0x2UL
#define	_DAC_IFC_CH1_DEFAULT 0x00000000UL
#define	DAC_IFC_CH1_DEFAULT (_DAC_IFC_CH1_DEFAULT << 1)
#define	DAC_IFC_CH0UF (0x1UL << 4)
#define	_DAC_IFC_CH0UF_SHIFT 4
#define	_DAC_IFC_CH0UF_MASK 0x10UL
#define	_DAC_IFC_CH0UF_DEFAULT 0x00000000UL
#define	DAC_IFC_CH0UF_DEFAULT (_DAC_IFC_CH0UF_DEFAULT << 4)
#define	DAC_IFC_CH1UF (0x1UL << 5)
#define	_DAC_IFC_CH1UF_SHIFT 5
#define	_DAC_IFC_CH1UF_MASK 0x20UL
#define	_DAC_IFC_CH1UF_DEFAULT 0x00000000UL
#define	DAC_IFC_CH1UF_DEFAULT (_DAC_IFC_CH1UF_DEFAULT << 5)
#define	_DAC_CH0DATA_RESETVALUE 0x00000000UL
#define	_DAC_CH0DATA_MASK 0x00000FFFUL
#define	_DAC_CH0DATA_DATA_SHIFT 0
#define	_DAC_CH0DATA_DATA_MASK 0xFFFUL
#define	_DAC_CH0DATA_DATA_DEFAULT 0x00000000UL
#define	DAC_CH0DATA_DATA_DEFAULT (_DAC_CH0DATA_DATA_DEFAULT << 0)
#define	_DAC_CH1DATA_RESETVALUE 0x00000000UL
#define	_DAC_CH1DATA_MASK 0x00000FFFUL
#define	_DAC_CH1DATA_DATA_SHIFT 0
#define	_DAC_CH1DATA_DATA_MASK 0xFFFUL
#define	_DAC_CH1DATA_DATA_DEFAULT 0x00000000UL
#define	DAC_CH1DATA_DATA_DEFAULT (_DAC_CH1DATA_DATA_DEFAULT << 0)
#define	_DAC_COMBDATA_RESETVALUE 0x00000000UL
#define	_DAC_COMBDATA_MASK 0x0FFF0FFFUL
#define	_DAC_COMBDATA_CH0DATA_SHIFT 0
#define	_DAC_COMBDATA_CH0DATA_MASK 0xFFFUL
#define	_DAC_COMBDATA_CH0DATA_DEFAULT 0x00000000UL
#define	DAC_COMBDATA_CH0DATA_DEFAULT (_DAC_COMBDATA_CH0DATA_DEFAULT << 0)
#define	_DAC_COMBDATA_CH1DATA_SHIFT 16
#define	_DAC_COMBDATA_CH1DATA_MASK 0xFFF0000UL
#define	_DAC_COMBDATA_CH1DATA_DEFAULT 0x00000000UL
#define	DAC_COMBDATA_CH1DATA_DEFAULT (_DAC_COMBDATA_CH1DATA_DEFAULT << 16)
#define	_DAC_CAL_RESETVALUE 0x00400000UL
#define	_DAC_CAL_MASK 0x007F3F3FUL
#define	_DAC_CAL_CH0OFFSET_SHIFT 0
#define	_DAC_CAL_CH0OFFSET_MASK 0x3FUL
#define	_DAC_CAL_CH0OFFSET_DEFAULT 0x00000000UL
#define	DAC_CAL_CH0OFFSET_DEFAULT (_DAC_CAL_CH0OFFSET_DEFAULT << 0)
#define	_DAC_CAL_CH1OFFSET_SHIFT 8
#define	_DAC_CAL_CH1OFFSET_MASK 0x3F00UL
#define	_DAC_CAL_CH1OFFSET_DEFAULT 0x00000000UL
#define	DAC_CAL_CH1OFFSET_DEFAULT (_DAC_CAL_CH1OFFSET_DEFAULT << 8)
#define	_DAC_CAL_GAIN_SHIFT 16
#define	_DAC_CAL_GAIN_MASK 0x7F0000UL
#define	_DAC_CAL_GAIN_DEFAULT 0x00000040UL
#define	DAC_CAL_GAIN_DEFAULT (_DAC_CAL_GAIN_DEFAULT << 16)
#define	_DAC_BIASPROG_RESETVALUE 0x00000047UL
#define	_DAC_BIASPROG_MASK 0x0000004FUL
#define	_DAC_BIASPROG_BIASPROG_SHIFT 0
#define	_DAC_BIASPROG_BIASPROG_MASK 0xFUL
#define	_DAC_BIASPROG_BIASPROG_DEFAULT 0x00000007UL
#define	DAC_BIASPROG_BIASPROG_DEFAULT (_DAC_BIASPROG_BIASPROG_DEFAULT << 0)
#define	DAC_BIASPROG_HALFBIAS (0x1UL << 6)
#define	_DAC_BIASPROG_HALFBIAS_SHIFT 6
#define	_DAC_BIASPROG_HALFBIAS_MASK 0x40UL
#define	_DAC_BIASPROG_HALFBIAS_DEFAULT 0x00000001UL
#define	DAC_BIASPROG_HALFBIAS_DEFAULT (_DAC_BIASPROG_HALFBIAS_DEFAULT << 6)
#define	_ACMP_CTRL_RESETVALUE 0x47000000UL
#define	_ACMP_CTRL_MASK 0xCF03077FUL
#define	ACMP_CTRL_EN (0x1UL << 0)
#define	_ACMP_CTRL_EN_SHIFT 0
#define	_ACMP_CTRL_EN_MASK 0x1UL
#define	_ACMP_CTRL_EN_DEFAULT 0x00000000UL
#define	ACMP_CTRL_EN_DEFAULT (_ACMP_CTRL_EN_DEFAULT << 0)
#define	ACMP_CTRL_MUXEN (0x1UL << 1)
#define	_ACMP_CTRL_MUXEN_SHIFT 1
#define	_ACMP_CTRL_MUXEN_MASK 0x2UL
#define	_ACMP_CTRL_MUXEN_DEFAULT 0x00000000UL
#define	ACMP_CTRL_MUXEN_DEFAULT (_ACMP_CTRL_MUXEN_DEFAULT << 1)
#define	ACMP_CTRL_INACTVAL (0x1UL << 2)
#define	_ACMP_CTRL_INACTVAL_SHIFT 2
#define	_ACMP_CTRL_INACTVAL_MASK 0x4UL
#define	_ACMP_CTRL_INACTVAL_DEFAULT 0x00000000UL
#define	_ACMP_CTRL_INACTVAL_LOW 0x00000000UL
#define	_ACMP_CTRL_INACTVAL_HIGH 0x00000001UL
#define	ACMP_CTRL_INACTVAL_DEFAULT (_ACMP_CTRL_INACTVAL_DEFAULT << 2)
#define	ACMP_CTRL_INACTVAL_LOW (_ACMP_CTRL_INACTVAL_LOW << 2)
#define	ACMP_CTRL_INACTVAL_HIGH (_ACMP_CTRL_INACTVAL_HIGH << 2)
#define	ACMP_CTRL_GPIOINV (0x1UL << 3)
#define	_ACMP_CTRL_GPIOINV_SHIFT 3
#define	_ACMP_CTRL_GPIOINV_MASK 0x8UL
#define	_ACMP_CTRL_GPIOINV_DEFAULT 0x00000000UL
#define	_ACMP_CTRL_GPIOINV_NOTINV 0x00000000UL
#define	_ACMP_CTRL_GPIOINV_INV 0x00000001UL
#define	ACMP_CTRL_GPIOINV_DEFAULT (_ACMP_CTRL_GPIOINV_DEFAULT << 3)
#define	ACMP_CTRL_GPIOINV_NOTINV (_ACMP_CTRL_GPIOINV_NOTINV << 3)
#define	ACMP_CTRL_GPIOINV_INV (_ACMP_CTRL_GPIOINV_INV << 3)
#define	_ACMP_CTRL_HYSTSEL_SHIFT 4
#define	_ACMP_CTRL_HYSTSEL_MASK 0x70UL
#define	_ACMP_CTRL_HYSTSEL_DEFAULT 0x00000000UL
#define	_ACMP_CTRL_HYSTSEL_HYST0 0x00000000UL
#define	_ACMP_CTRL_HYSTSEL_HYST1 0x00000001UL
#define	_ACMP_CTRL_HYSTSEL_HYST2 0x00000002UL
#define	_ACMP_CTRL_HYSTSEL_HYST3 0x00000003UL
#define	_ACMP_CTRL_HYSTSEL_HYST4 0x00000004UL
#define	_ACMP_CTRL_HYSTSEL_HYST5 0x00000005UL
#define	_ACMP_CTRL_HYSTSEL_HYST6 0x00000006UL
#define	_ACMP_CTRL_HYSTSEL_HYST7 0x00000007UL
#define	ACMP_CTRL_HYSTSEL_DEFAULT (_ACMP_CTRL_HYSTSEL_DEFAULT << 4)
#define	ACMP_CTRL_HYSTSEL_HYST0 (_ACMP_CTRL_HYSTSEL_HYST0 << 4)
#define	ACMP_CTRL_HYSTSEL_HYST1 (_ACMP_CTRL_HYSTSEL_HYST1 << 4)
#define	ACMP_CTRL_HYSTSEL_HYST2 (_ACMP_CTRL_HYSTSEL_HYST2 << 4)
#define	ACMP_CTRL_HYSTSEL_HYST3 (_ACMP_CTRL_HYSTSEL_HYST3 << 4)
#define	ACMP_CTRL_HYSTSEL_HYST4 (_ACMP_CTRL_HYSTSEL_HYST4 << 4)
#define	ACMP_CTRL_HYSTSEL_HYST5 (_ACMP_CTRL_HYSTSEL_HYST5 << 4)
#define	ACMP_CTRL_HYSTSEL_HYST6 (_ACMP_CTRL_HYSTSEL_HYST6 << 4)
#define	ACMP_CTRL_HYSTSEL_HYST7 (_ACMP_CTRL_HYSTSEL_HYST7 << 4)
#define	_ACMP_CTRL_WARMTIME_SHIFT 8
#define	_ACMP_CTRL_WARMTIME_MASK 0x700UL
#define	_ACMP_CTRL_WARMTIME_DEFAULT 0x00000000UL
#define	_ACMP_CTRL_WARMTIME_4CYCLES 0x00000000UL
#define	_ACMP_CTRL_WARMTIME_8CYCLES 0x00000001UL
#define	_ACMP_CTRL_WARMTIME_16CYCLES 0x00000002UL
#define	_ACMP_CTRL_WARMTIME_32CYCLES 0x00000003UL
#define	_ACMP_CTRL_WARMTIME_64CYCLES 0x00000004UL
#define	_ACMP_CTRL_WARMTIME_128CYCLES 0x00000005UL
#define	_ACMP_CTRL_WARMTIME_256CYCLES 0x00000006UL
#define	_ACMP_CTRL_WARMTIME_512CYCLES 0x00000007UL
#define	ACMP_CTRL_WARMTIME_DEFAULT (_ACMP_CTRL_WARMTIME_DEFAULT << 8)
#define	ACMP_CTRL_WARMTIME_4CYCLES (_ACMP_CTRL_WARMTIME_4CYCLES << 8)
#define	ACMP_CTRL_WARMTIME_8CYCLES (_ACMP_CTRL_WARMTIME_8CYCLES << 8)
#define	ACMP_CTRL_WARMTIME_16CYCLES (_ACMP_CTRL_WARMTIME_16CYCLES << 8)
#define	ACMP_CTRL_WARMTIME_32CYCLES (_ACMP_CTRL_WARMTIME_32CYCLES << 8)
#define	ACMP_CTRL_WARMTIME_64CYCLES (_ACMP_CTRL_WARMTIME_64CYCLES << 8)
#define	ACMP_CTRL_WARMTIME_128CYCLES (_ACMP_CTRL_WARMTIME_128CYCLES << 8)
#define	ACMP_CTRL_WARMTIME_256CYCLES (_ACMP_CTRL_WARMTIME_256CYCLES << 8)
#define	ACMP_CTRL_WARMTIME_512CYCLES (_ACMP_CTRL_WARMTIME_512CYCLES << 8)
#define	ACMP_CTRL_IRISE (0x1UL << 16)
#define	_ACMP_CTRL_IRISE_SHIFT 16
#define	_ACMP_CTRL_IRISE_MASK 0x10000UL
#define	_ACMP_CTRL_IRISE_DEFAULT 0x00000000UL
#define	_ACMP_CTRL_IRISE_DISABLED 0x00000000UL
#define	_ACMP_CTRL_IRISE_ENABLED 0x00000001UL
#define	ACMP_CTRL_IRISE_DEFAULT (_ACMP_CTRL_IRISE_DEFAULT << 16)
#define	ACMP_CTRL_IRISE_DISABLED (_ACMP_CTRL_IRISE_DISABLED << 16)
#define	ACMP_CTRL_IRISE_ENABLED (_ACMP_CTRL_IRISE_ENABLED << 16)
#define	ACMP_CTRL_IFALL (0x1UL << 17)
#define	_ACMP_CTRL_IFALL_SHIFT 17
#define	_ACMP_CTRL_IFALL_MASK 0x20000UL
#define	_ACMP_CTRL_IFALL_DEFAULT 0x00000000UL
#define	_ACMP_CTRL_IFALL_DISABLED 0x00000000UL
#define	_ACMP_CTRL_IFALL_ENABLED 0x00000001UL
#define	ACMP_CTRL_IFALL_DEFAULT (_ACMP_CTRL_IFALL_DEFAULT << 17)
#define	ACMP_CTRL_IFALL_DISABLED (_ACMP_CTRL_IFALL_DISABLED << 17)
#define	ACMP_CTRL_IFALL_ENABLED (_ACMP_CTRL_IFALL_ENABLED << 17)
#define	_ACMP_CTRL_BIASPROG_SHIFT 24
#define	_ACMP_CTRL_BIASPROG_MASK 0xF000000UL
#define	_ACMP_CTRL_BIASPROG_DEFAULT 0x00000007UL
#define	ACMP_CTRL_BIASPROG_DEFAULT (_ACMP_CTRL_BIASPROG_DEFAULT << 24)
#define	ACMP_CTRL_HALFBIAS (0x1UL << 30)
#define	_ACMP_CTRL_HALFBIAS_SHIFT 30
#define	_ACMP_CTRL_HALFBIAS_MASK 0x40000000UL
#define	_ACMP_CTRL_HALFBIAS_DEFAULT 0x00000001UL
#define	ACMP_CTRL_HALFBIAS_DEFAULT (_ACMP_CTRL_HALFBIAS_DEFAULT << 30)
#define	ACMP_CTRL_FULLBIAS (0x1UL << 31)
#define	_ACMP_CTRL_FULLBIAS_SHIFT 31
#define	_ACMP_CTRL_FULLBIAS_MASK 0x80000000UL
#define	_ACMP_CTRL_FULLBIAS_DEFAULT 0x00000000UL
#define	ACMP_CTRL_FULLBIAS_DEFAULT (_ACMP_CTRL_FULLBIAS_DEFAULT << 31)
#define	_ACMP_INPUTSEL_RESETVALUE 0x00010080UL
#define	_ACMP_INPUTSEL_MASK 0x31013FF7UL
#define	_ACMP_INPUTSEL_POSSEL_SHIFT 0
#define	_ACMP_INPUTSEL_POSSEL_MASK 0x7UL
#define	_ACMP_INPUTSEL_POSSEL_DEFAULT 0x00000000UL
#define	_ACMP_INPUTSEL_POSSEL_CH0 0x00000000UL
#define	_ACMP_INPUTSEL_POSSEL_CH1 0x00000001UL
#define	_ACMP_INPUTSEL_POSSEL_CH2 0x00000002UL
#define	_ACMP_INPUTSEL_POSSEL_CH3 0x00000003UL
#define	_ACMP_INPUTSEL_POSSEL_CH4 0x00000004UL
#define	_ACMP_INPUTSEL_POSSEL_CH5 0x00000005UL
#define	_ACMP_INPUTSEL_POSSEL_CH6 0x00000006UL
#define	_ACMP_INPUTSEL_POSSEL_CH7 0x00000007UL
#define	ACMP_INPUTSEL_POSSEL_DEFAULT (_ACMP_INPUTSEL_POSSEL_DEFAULT << 0)
#define	ACMP_INPUTSEL_POSSEL_CH0 (_ACMP_INPUTSEL_POSSEL_CH0 << 0)
#define	ACMP_INPUTSEL_POSSEL_CH1 (_ACMP_INPUTSEL_POSSEL_CH1 << 0)
#define	ACMP_INPUTSEL_POSSEL_CH2 (_ACMP_INPUTSEL_POSSEL_CH2 << 0)
#define	ACMP_INPUTSEL_POSSEL_CH3 (_ACMP_INPUTSEL_POSSEL_CH3 << 0)
#define	ACMP_INPUTSEL_POSSEL_CH4 (_ACMP_INPUTSEL_POSSEL_CH4 << 0)
#define	ACMP_INPUTSEL_POSSEL_CH5 (_ACMP_INPUTSEL_POSSEL_CH5 << 0)
#define	ACMP_INPUTSEL_POSSEL_CH6 (_ACMP_INPUTSEL_POSSEL_CH6 << 0)
#define	ACMP_INPUTSEL_POSSEL_CH7 (_ACMP_INPUTSEL_POSSEL_CH7 << 0)
#define	_ACMP_INPUTSEL_NEGSEL_SHIFT 4
#define	_ACMP_INPUTSEL_NEGSEL_MASK 0xF0UL
#define	_ACMP_INPUTSEL_NEGSEL_CH0 0x00000000UL
#define	_ACMP_INPUTSEL_NEGSEL_CH1 0x00000001UL
#define	_ACMP_INPUTSEL_NEGSEL_CH2 0x00000002UL
#define	_ACMP_INPUTSEL_NEGSEL_CH3 0x00000003UL
#define	_ACMP_INPUTSEL_NEGSEL_CH4 0x00000004UL
#define	_ACMP_INPUTSEL_NEGSEL_CH5 0x00000005UL
#define	_ACMP_INPUTSEL_NEGSEL_CH6 0x00000006UL
#define	_ACMP_INPUTSEL_NEGSEL_CH7 0x00000007UL
#define	_ACMP_INPUTSEL_NEGSEL_DEFAULT 0x00000008UL
#define	_ACMP_INPUTSEL_NEGSEL_1V25 0x00000008UL
#define	_ACMP_INPUTSEL_NEGSEL_2V5 0x00000009UL
#define	_ACMP_INPUTSEL_NEGSEL_VDD 0x0000000AUL
#define	_ACMP_INPUTSEL_NEGSEL_CAPSENSE 0x0000000BUL
#define	ACMP_INPUTSEL_NEGSEL_CH0 (_ACMP_INPUTSEL_NEGSEL_CH0 << 4)
#define	ACMP_INPUTSEL_NEGSEL_CH1 (_ACMP_INPUTSEL_NEGSEL_CH1 << 4)
#define	ACMP_INPUTSEL_NEGSEL_CH2 (_ACMP_INPUTSEL_NEGSEL_CH2 << 4)
#define	ACMP_INPUTSEL_NEGSEL_CH3 (_ACMP_INPUTSEL_NEGSEL_CH3 << 4)
#define	ACMP_INPUTSEL_NEGSEL_CH4 (_ACMP_INPUTSEL_NEGSEL_CH4 << 4)
#define	ACMP_INPUTSEL_NEGSEL_CH5 (_ACMP_INPUTSEL_NEGSEL_CH5 << 4)
#define	ACMP_INPUTSEL_NEGSEL_CH6 (_ACMP_INPUTSEL_NEGSEL_CH6 << 4)
#define	ACMP_INPUTSEL_NEGSEL_CH7 (_ACMP_INPUTSEL_NEGSEL_CH7 << 4)
#define	ACMP_INPUTSEL_NEGSEL_DEFAULT (_ACMP_INPUTSEL_NEGSEL_DEFAULT << 4)
#define	ACMP_INPUTSEL_NEGSEL_1V25 (_ACMP_INPUTSEL_NEGSEL_1V25 << 4)
#define	ACMP_INPUTSEL_NEGSEL_2V5 (_ACMP_INPUTSEL_NEGSEL_2V5 << 4)
#define	ACMP_INPUTSEL_NEGSEL_VDD (_ACMP_INPUTSEL_NEGSEL_VDD << 4)
#define	ACMP_INPUTSEL_NEGSEL_CAPSENSE (_ACMP_INPUTSEL_NEGSEL_CAPSENSE << 4)
#define	_ACMP_INPUTSEL_VDDLEVEL_SHIFT 8
#define	_ACMP_INPUTSEL_VDDLEVEL_MASK 0x3F00UL
#define	_ACMP_INPUTSEL_VDDLEVEL_DEFAULT 0x00000000UL
#define	ACMP_INPUTSEL_VDDLEVEL_DEFAULT (_ACMP_INPUTSEL_VDDLEVEL_DEFAULT << 8)
#define	ACMP_INPUTSEL_LPREF (0x1UL << 16)
#define	_ACMP_INPUTSEL_LPREF_SHIFT 16
#define	_ACMP_INPUTSEL_LPREF_MASK 0x10000UL
#define	_ACMP_INPUTSEL_LPREF_DEFAULT 0x00000001UL
#define	ACMP_INPUTSEL_LPREF_DEFAULT (_ACMP_INPUTSEL_LPREF_DEFAULT << 16)
#define	ACMP_INPUTSEL_CSRESEN (0x1UL << 24)
#define	_ACMP_INPUTSEL_CSRESEN_SHIFT 24
#define	_ACMP_INPUTSEL_CSRESEN_MASK 0x1000000UL
#define	_ACMP_INPUTSEL_CSRESEN_DEFAULT 0x00000000UL
#define	ACMP_INPUTSEL_CSRESEN_DEFAULT (_ACMP_INPUTSEL_CSRESEN_DEFAULT << 24)
#define	_ACMP_INPUTSEL_CSRESSEL_SHIFT 28
#define	_ACMP_INPUTSEL_CSRESSEL_MASK 0x30000000UL
#define	_ACMP_INPUTSEL_CSRESSEL_DEFAULT 0x00000000UL
#define	_ACMP_INPUTSEL_CSRESSEL_RES0 0x00000000UL
#define	_ACMP_INPUTSEL_CSRESSEL_RES1 0x00000001UL
#define	_ACMP_INPUTSEL_CSRESSEL_RES2 0x00000002UL
#define	_ACMP_INPUTSEL_CSRESSEL_RES3 0x00000003UL
#define	ACMP_INPUTSEL_CSRESSEL_DEFAULT (_ACMP_INPUTSEL_CSRESSEL_DEFAULT << 28)
#define	ACMP_INPUTSEL_CSRESSEL_RES0 (_ACMP_INPUTSEL_CSRESSEL_RES0 << 28)
#define	ACMP_INPUTSEL_CSRESSEL_RES1 (_ACMP_INPUTSEL_CSRESSEL_RES1 << 28)
#define	ACMP_INPUTSEL_CSRESSEL_RES2 (_ACMP_INPUTSEL_CSRESSEL_RES2 << 28)
#define	ACMP_INPUTSEL_CSRESSEL_RES3 (_ACMP_INPUTSEL_CSRESSEL_RES3 << 28)
#define	_ACMP_STATUS_RESETVALUE 0x00000000UL
#define	_ACMP_STATUS_MASK 0x00000003UL
#define	ACMP_STATUS_ACMPACT (0x1UL << 0)
#define	_ACMP_STATUS_ACMPACT_SHIFT 0
#define	_ACMP_STATUS_ACMPACT_MASK 0x1UL
#define	_ACMP_STATUS_ACMPACT_DEFAULT 0x00000000UL
#define	ACMP_STATUS_ACMPACT_DEFAULT (_ACMP_STATUS_ACMPACT_DEFAULT << 0)
#define	ACMP_STATUS_ACMPOUT (0x1UL << 1)
#define	_ACMP_STATUS_ACMPOUT_SHIFT 1
#define	_ACMP_STATUS_ACMPOUT_MASK 0x2UL
#define	_ACMP_STATUS_ACMPOUT_DEFAULT 0x00000000UL
#define	ACMP_STATUS_ACMPOUT_DEFAULT (_ACMP_STATUS_ACMPOUT_DEFAULT << 1)
#define	_ACMP_IEN_RESETVALUE 0x00000000UL
#define	_ACMP_IEN_MASK 0x00000003UL
#define	ACMP_IEN_EDGE (0x1UL << 0)
#define	_ACMP_IEN_EDGE_SHIFT 0
#define	_ACMP_IEN_EDGE_MASK 0x1UL
#define	_ACMP_IEN_EDGE_DEFAULT 0x00000000UL
#define	ACMP_IEN_EDGE_DEFAULT (_ACMP_IEN_EDGE_DEFAULT << 0)
#define	ACMP_IEN_WARMUP (0x1UL << 1)
#define	_ACMP_IEN_WARMUP_SHIFT 1
#define	_ACMP_IEN_WARMUP_MASK 0x2UL
#define	_ACMP_IEN_WARMUP_DEFAULT 0x00000000UL
#define	ACMP_IEN_WARMUP_DEFAULT (_ACMP_IEN_WARMUP_DEFAULT << 1)
#define	_ACMP_IF_RESETVALUE 0x00000000UL
#define	_ACMP_IF_MASK 0x00000003UL
#define	ACMP_IF_EDGE (0x1UL << 0)
#define	_ACMP_IF_EDGE_SHIFT 0
#define	_ACMP_IF_EDGE_MASK 0x1UL
#define	_ACMP_IF_EDGE_DEFAULT 0x00000000UL
#define	ACMP_IF_EDGE_DEFAULT (_ACMP_IF_EDGE_DEFAULT << 0)
#define	ACMP_IF_WARMUP (0x1UL << 1)
#define	_ACMP_IF_WARMUP_SHIFT 1
#define	_ACMP_IF_WARMUP_MASK 0x2UL
#define	_ACMP_IF_WARMUP_DEFAULT 0x00000000UL
#define	ACMP_IF_WARMUP_DEFAULT (_ACMP_IF_WARMUP_DEFAULT << 1)
#define	_ACMP_IFS_RESETVALUE 0x00000000UL
#define	_ACMP_IFS_MASK 0x00000003UL
#define	ACMP_IFS_EDGE (0x1UL << 0)
#define	_ACMP_IFS_EDGE_SHIFT 0
#define	_ACMP_IFS_EDGE_MASK 0x1UL
#define	_ACMP_IFS_EDGE_DEFAULT 0x00000000UL
#define	ACMP_IFS_EDGE_DEFAULT (_ACMP_IFS_EDGE_DEFAULT << 0)
#define	ACMP_IFS_WARMUP (0x1UL << 1)
#define	_ACMP_IFS_WARMUP_SHIFT 1
#define	_ACMP_IFS_WARMUP_MASK 0x2UL
#define	_ACMP_IFS_WARMUP_DEFAULT 0x00000000UL
#define	ACMP_IFS_WARMUP_DEFAULT (_ACMP_IFS_WARMUP_DEFAULT << 1)
#define	_ACMP_IFC_RESETVALUE 0x00000000UL
#define	_ACMP_IFC_MASK 0x00000003UL
#define	ACMP_IFC_EDGE (0x1UL << 0)
#define	_ACMP_IFC_EDGE_SHIFT 0
#define	_ACMP_IFC_EDGE_MASK 0x1UL
#define	_ACMP_IFC_EDGE_DEFAULT 0x00000000UL
#define	ACMP_IFC_EDGE_DEFAULT (_ACMP_IFC_EDGE_DEFAULT << 0)
#define	ACMP_IFC_WARMUP (0x1UL << 1)
#define	_ACMP_IFC_WARMUP_SHIFT 1
#define	_ACMP_IFC_WARMUP_MASK 0x2UL
#define	_ACMP_IFC_WARMUP_DEFAULT 0x00000000UL
#define	ACMP_IFC_WARMUP_DEFAULT (_ACMP_IFC_WARMUP_DEFAULT << 1)
#define	_ACMP_ROUTE_RESETVALUE 0x00000000UL
#define	_ACMP_ROUTE_MASK 0x00000301UL
#define	ACMP_ROUTE_ACMPPEN (0x1UL << 0)
#define	_ACMP_ROUTE_ACMPPEN_SHIFT 0
#define	_ACMP_ROUTE_ACMPPEN_MASK 0x1UL
#define	_ACMP_ROUTE_ACMPPEN_DEFAULT 0x00000000UL
#define	ACMP_ROUTE_ACMPPEN_DEFAULT (_ACMP_ROUTE_ACMPPEN_DEFAULT << 0)
#define	_ACMP_ROUTE_LOCATION_SHIFT 8
#define	_ACMP_ROUTE_LOCATION_MASK 0x300UL
#define	_ACMP_ROUTE_LOCATION_DEFAULT 0x00000000UL
#define	_ACMP_ROUTE_LOCATION_LOC0 0x00000000UL
#define	_ACMP_ROUTE_LOCATION_LOC1 0x00000001UL
#define	_ACMP_ROUTE_LOCATION_LOC2 0x00000002UL
#define	_ACMP_ROUTE_LOCATION_LOC3 0x00000003UL
#define	ACMP_ROUTE_LOCATION_DEFAULT (_ACMP_ROUTE_LOCATION_DEFAULT << 8)
#define	ACMP_ROUTE_LOCATION_LOC0 (_ACMP_ROUTE_LOCATION_LOC0 << 8)
#define	ACMP_ROUTE_LOCATION_LOC1 (_ACMP_ROUTE_LOCATION_LOC1 << 8)
#define	ACMP_ROUTE_LOCATION_LOC2 (_ACMP_ROUTE_LOCATION_LOC2 << 8)
#define	ACMP_ROUTE_LOCATION_LOC3 (_ACMP_ROUTE_LOCATION_LOC3 << 8)
#define	_MSC_CTRL_RESETVALUE 0x00000001UL
#define	_MSC_CTRL_MASK 0x00000001UL
#define	MSC_CTRL_BUSFAULT (0x1UL << 0)
#define	_MSC_CTRL_BUSFAULT_SHIFT 0
#define	_MSC_CTRL_BUSFAULT_MASK 0x1UL
#define	_MSC_CTRL_BUSFAULT_GENERATE 0x00000000UL
#define	_MSC_CTRL_BUSFAULT_DEFAULT 0x00000001UL
#define	_MSC_CTRL_BUSFAULT_IGNORE 0x00000001UL
#define	MSC_CTRL_BUSFAULT_GENERATE (_MSC_CTRL_BUSFAULT_GENERATE << 0)
#define	MSC_CTRL_BUSFAULT_DEFAULT (_MSC_CTRL_BUSFAULT_DEFAULT << 0)
#define	MSC_CTRL_BUSFAULT_IGNORE (_MSC_CTRL_BUSFAULT_IGNORE << 0)
#define	_MSC_READCTRL_RESETVALUE 0x00000001UL
#define	_MSC_READCTRL_MASK 0x00000007UL
#define	_MSC_READCTRL_MODE_SHIFT 0
#define	_MSC_READCTRL_MODE_MASK 0x7UL
#define	_MSC_READCTRL_MODE_WS0 0x00000000UL
#define	_MSC_READCTRL_MODE_DEFAULT 0x00000001UL
#define	_MSC_READCTRL_MODE_WS1 0x00000001UL
#define	_MSC_READCTRL_MODE_WS0SCBTP 0x00000002UL
#define	_MSC_READCTRL_MODE_WS1SCBTP 0x00000003UL
#define	MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 0)
#define	MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 0)
#define	MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 0)
#define	MSC_READCTRL_MODE_WS0SCBTP (_MSC_READCTRL_MODE_WS0SCBTP << 0)
#define	MSC_READCTRL_MODE_WS1SCBTP (_MSC_READCTRL_MODE_WS1SCBTP << 0)
#define	_MSC_WRITECTRL_RESETVALUE 0x00000000UL
#define	_MSC_WRITECTRL_MASK 0x00000003UL
#define	MSC_WRITECTRL_WREN (0x1UL << 0)
#define	_MSC_WRITECTRL_WREN_SHIFT 0
#define	_MSC_WRITECTRL_WREN_MASK 0x1UL
#define	_MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL
#define	MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0)
#define	MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1)
#define	_MSC_WRITECTRL_IRQERASEABORT_SHIFT 1
#define	_MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL
#define	_MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL
#define	MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1)
#define	_MSC_WRITECMD_RESETVALUE 0x00000000UL
#define	_MSC_WRITECMD_MASK 0x0000001FUL
#define	MSC_WRITECMD_LADDRIM (0x1UL << 0)
#define	_MSC_WRITECMD_LADDRIM_SHIFT 0
#define	_MSC_WRITECMD_LADDRIM_MASK 0x1UL
#define	_MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL
#define	MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0)
#define	MSC_WRITECMD_ERASEPAGE (0x1UL << 1)
#define	_MSC_WRITECMD_ERASEPAGE_SHIFT 1
#define	_MSC_WRITECMD_ERASEPAGE_MASK 0x2UL
#define	_MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL
#define	MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1)
#define	MSC_WRITECMD_WRITEEND (0x1UL << 2)
#define	_MSC_WRITECMD_WRITEEND_SHIFT 2
#define	_MSC_WRITECMD_WRITEEND_MASK 0x4UL
#define	_MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL
#define	MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2)
#define	MSC_WRITECMD_WRITEONCE (0x1UL << 3)
#define	_MSC_WRITECMD_WRITEONCE_SHIFT 3
#define	_MSC_WRITECMD_WRITEONCE_MASK 0x8UL
#define	_MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL
#define	MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3)
#define	MSC_WRITECMD_WRITETRIG (0x1UL << 4)
#define	_MSC_WRITECMD_WRITETRIG_SHIFT 4
#define	_MSC_WRITECMD_WRITETRIG_MASK 0x10UL
#define	_MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL
#define	MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4)
#define	_MSC_ADDRB_RESETVALUE 0x00000000UL
#define	_MSC_ADDRB_MASK 0xFFFFFFFFUL
#define	_MSC_ADDRB_ADDRB_SHIFT 0
#define	_MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL
#define	_MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL
#define	MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0)
#define	_MSC_WDATA_RESETVALUE 0x00000000UL
#define	_MSC_WDATA_MASK 0xFFFFFFFFUL
#define	_MSC_WDATA_WDATA_SHIFT 0
#define	_MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL
#define	_MSC_WDATA_WDATA_DEFAULT 0x00000000UL
#define	MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0)
#define	_MSC_STATUS_RESETVALUE 0x00000008UL
#define	_MSC_STATUS_MASK 0x0000003FUL
#define	MSC_STATUS_BUSY (0x1UL << 0)
#define	_MSC_STATUS_BUSY_SHIFT 0
#define	_MSC_STATUS_BUSY_MASK 0x1UL
#define	_MSC_STATUS_BUSY_DEFAULT 0x00000000UL
#define	MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0)
#define	MSC_STATUS_LOCKED (0x1UL << 1)
#define	_MSC_STATUS_LOCKED_SHIFT 1
#define	_MSC_STATUS_LOCKED_MASK 0x2UL
#define	_MSC_STATUS_LOCKED_DEFAULT 0x00000000UL
#define	MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1)
#define	MSC_STATUS_INVADDR (0x1UL << 2)
#define	_MSC_STATUS_INVADDR_SHIFT 2
#define	_MSC_STATUS_INVADDR_MASK 0x4UL
#define	_MSC_STATUS_INVADDR_DEFAULT 0x00000000UL
#define	MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2)
#define	MSC_STATUS_WDATAREADY (0x1UL << 3)
#define	_MSC_STATUS_WDATAREADY_SHIFT 3
#define	_MSC_STATUS_WDATAREADY_MASK 0x8UL
#define	_MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL
#define	MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3)
#define	MSC_STATUS_WORDTIMEOUT (0x1UL << 4)
#define	_MSC_STATUS_WORDTIMEOUT_SHIFT 4
#define	_MSC_STATUS_WORDTIMEOUT_MASK 0x10UL
#define	_MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL
#define	MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4)
#define	MSC_STATUS_ERASEABORTED (0x1UL << 5)
#define	_MSC_STATUS_ERASEABORTED_SHIFT 5
#define	_MSC_STATUS_ERASEABORTED_MASK 0x20UL
#define	_MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL
#define	MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5)
#define	_MSC_IF_RESETVALUE 0x00000000UL
#define	_MSC_IF_MASK 0x00000003UL
#define	MSC_IF_ERASE (0x1UL << 0)
#define	_MSC_IF_ERASE_SHIFT 0
#define	_MSC_IF_ERASE_MASK 0x1UL
#define	_MSC_IF_ERASE_DEFAULT 0x00000000UL
#define	MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0)
#define	MSC_IF_WRITE (0x1UL << 1)
#define	_MSC_IF_WRITE_SHIFT 1
#define	_MSC_IF_WRITE_MASK 0x2UL
#define	_MSC_IF_WRITE_DEFAULT 0x00000000UL
#define	MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1)
#define	_MSC_IFS_RESETVALUE 0x00000000UL
#define	_MSC_IFS_MASK 0x00000003UL
#define	MSC_IFS_ERASE (0x1UL << 0)
#define	_MSC_IFS_ERASE_SHIFT 0
#define	_MSC_IFS_ERASE_MASK 0x1UL
#define	_MSC_IFS_ERASE_DEFAULT 0x00000000UL
#define	MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0)
#define	MSC_IFS_WRITE (0x1UL << 1)
#define	_MSC_IFS_WRITE_SHIFT 1
#define	_MSC_IFS_WRITE_MASK 0x2UL
#define	_MSC_IFS_WRITE_DEFAULT 0x00000000UL
#define	MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1)
#define	_MSC_IFC_RESETVALUE 0x00000000UL
#define	_MSC_IFC_MASK 0x00000003UL
#define	MSC_IFC_ERASE (0x1UL << 0)
#define	_MSC_IFC_ERASE_SHIFT 0
#define	_MSC_IFC_ERASE_MASK 0x1UL
#define	_MSC_IFC_ERASE_DEFAULT 0x00000000UL
#define	MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0)
#define	MSC_IFC_WRITE (0x1UL << 1)
#define	_MSC_IFC_WRITE_SHIFT 1
#define	_MSC_IFC_WRITE_MASK 0x2UL
#define	_MSC_IFC_WRITE_DEFAULT 0x00000000UL
#define	MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1)
#define	_MSC_IEN_RESETVALUE 0x00000000UL
#define	_MSC_IEN_MASK 0x00000003UL
#define	MSC_IEN_ERASE (0x1UL << 0)
#define	_MSC_IEN_ERASE_SHIFT 0
#define	_MSC_IEN_ERASE_MASK 0x1UL
#define	_MSC_IEN_ERASE_DEFAULT 0x00000000UL
#define	MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0)
#define	MSC_IEN_WRITE (0x1UL << 1)
#define	_MSC_IEN_WRITE_SHIFT 1
#define	_MSC_IEN_WRITE_MASK 0x2UL
#define	_MSC_IEN_WRITE_DEFAULT 0x00000000UL
#define	MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1)
#define	_MSC_LOCK_RESETVALUE 0x00000000UL
#define	_MSC_LOCK_MASK 0x0000FFFFUL
#define	_MSC_LOCK_LOCKKEY_SHIFT 0
#define	_MSC_LOCK_LOCKKEY_MASK 0xFFFFUL
#define	_MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL
#define	_MSC_LOCK_LOCKKEY_LOCK 0x00000000UL
#define	_MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL
#define	_MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL
#define	_MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL
#define	MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0)
#define	MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0)
#define	MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0)
#define	MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0)
#define	MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0)
#define	_EMU_CTRL_RESETVALUE 0x00000000UL
#define	_EMU_CTRL_MASK 0x0000000FUL
#define	EMU_CTRL_EMVREG (0x1UL << 0)
#define	_EMU_CTRL_EMVREG_SHIFT 0
#define	_EMU_CTRL_EMVREG_MASK 0x1UL
#define	_EMU_CTRL_EMVREG_DEFAULT 0x00000000UL
#define	_EMU_CTRL_EMVREG_REDUCED 0x00000000UL
#define	_EMU_CTRL_EMVREG_FULL 0x00000001UL
#define	EMU_CTRL_EMVREG_DEFAULT (_EMU_CTRL_EMVREG_DEFAULT << 0)
#define	EMU_CTRL_EMVREG_REDUCED (_EMU_CTRL_EMVREG_REDUCED << 0)
#define	EMU_CTRL_EMVREG_FULL (_EMU_CTRL_EMVREG_FULL << 0)
#define	EMU_CTRL_EM2BLOCK (0x1UL << 1)
#define	_EMU_CTRL_EM2BLOCK_SHIFT 1
#define	_EMU_CTRL_EM2BLOCK_MASK 0x2UL
#define	_EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL
#define	EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1)
#define	_EMU_CTRL_EM4CTRL_SHIFT 2
#define	_EMU_CTRL_EM4CTRL_MASK 0xCUL
#define	_EMU_CTRL_EM4CTRL_DEFAULT 0x00000000UL
#define	EMU_CTRL_EM4CTRL_DEFAULT (_EMU_CTRL_EM4CTRL_DEFAULT << 2)
#define	_EMU_MEMCTRL_RESETVALUE 0x00000000UL
#define	_EMU_MEMCTRL_MASK 0x00000007UL
#define	_EMU_MEMCTRL_POWERDOWN_SHIFT 0
#define	_EMU_MEMCTRL_POWERDOWN_MASK 0x7UL
#define	_EMU_MEMCTRL_POWERDOWN_DEFAULT 0x00000000UL
#define	_EMU_MEMCTRL_POWERDOWN_BLK3 0x00000004UL
#define	_EMU_MEMCTRL_POWERDOWN_BLK23 0x00000006UL
#define	_EMU_MEMCTRL_POWERDOWN_BLK123 0x00000007UL
#define	EMU_MEMCTRL_POWERDOWN_DEFAULT (_EMU_MEMCTRL_POWERDOWN_DEFAULT << 0)
#define	EMU_MEMCTRL_POWERDOWN_BLK3 (_EMU_MEMCTRL_POWERDOWN_BLK3 << 0)
#define	EMU_MEMCTRL_POWERDOWN_BLK23 (_EMU_MEMCTRL_POWERDOWN_BLK23 << 0)
#define	EMU_MEMCTRL_POWERDOWN_BLK123 (_EMU_MEMCTRL_POWERDOWN_BLK123 << 0)
#define	_EMU_LOCK_RESETVALUE 0x00000000UL
#define	_EMU_LOCK_MASK 0x0000FFFFUL
#define	_EMU_LOCK_LOCKKEY_SHIFT 0
#define	_EMU_LOCK_LOCKKEY_MASK 0xFFFFUL
#define	_EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL
#define	_EMU_LOCK_LOCKKEY_LOCK 0x00000000UL
#define	_EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL
#define	_EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL
#define	_EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL
#define	EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0)
#define	EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0)
#define	EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0)
#define	EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0)
#define	EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0)
#define	_EMU_AUXCTRL_RESETVALUE 0x00000000UL
#define	_EMU_AUXCTRL_MASK 0x00000001UL
#define	EMU_AUXCTRL_HRCCLR (0x1UL << 0)
#define	_EMU_AUXCTRL_HRCCLR_SHIFT 0
#define	_EMU_AUXCTRL_HRCCLR_MASK 0x1UL
#define	_EMU_AUXCTRL_HRCCLR_DEFAULT 0x00000000UL
#define	EMU_AUXCTRL_HRCCLR_DEFAULT (_EMU_AUXCTRL_HRCCLR_DEFAULT << 0)
#define	_RMU_CTRL_RESETVALUE 0x00000000UL
#define	_RMU_CTRL_MASK 0x00000001UL
#define	RMU_CTRL_LOCKUPRDIS (0x1UL << 0)
#define	_RMU_CTRL_LOCKUPRDIS_SHIFT 0
#define	_RMU_CTRL_LOCKUPRDIS_MASK 0x1UL
#define	_RMU_CTRL_LOCKUPRDIS_DEFAULT 0x00000000UL
#define	RMU_CTRL_LOCKUPRDIS_DEFAULT (_RMU_CTRL_LOCKUPRDIS_DEFAULT << 0)
#define	_RMU_RSTCAUSE_RESETVALUE 0x00000000UL
#define	_RMU_RSTCAUSE_MASK 0x0000007FUL
#define	RMU_RSTCAUSE_PORST (0x1UL << 0)
#define	_RMU_RSTCAUSE_PORST_SHIFT 0
#define	_RMU_RSTCAUSE_PORST_MASK 0x1UL
#define	_RMU_RSTCAUSE_PORST_DEFAULT 0x00000000UL
#define	RMU_RSTCAUSE_PORST_DEFAULT (_RMU_RSTCAUSE_PORST_DEFAULT << 0)
#define	RMU_RSTCAUSE_BODUNREGRST (0x1UL << 1)
#define	_RMU_RSTCAUSE_BODUNREGRST_SHIFT 1
#define	_RMU_RSTCAUSE_BODUNREGRST_MASK 0x2UL
#define	_RMU_RSTCAUSE_BODUNREGRST_DEFAULT 0x00000000UL
#define	RMU_RSTCAUSE_BODUNREGRST_DEFAULT (_RMU_RSTCAUSE_BODUNREGRST_DEFAULT << 1)
#define	RMU_RSTCAUSE_BODREGRST (0x1UL << 2)
#define	_RMU_RSTCAUSE_BODREGRST_SHIFT 2
#define	_RMU_RSTCAUSE_BODREGRST_MASK 0x4UL
#define	_RMU_RSTCAUSE_BODREGRST_DEFAULT 0x00000000UL
#define	RMU_RSTCAUSE_BODREGRST_DEFAULT (_RMU_RSTCAUSE_BODREGRST_DEFAULT << 2)
#define	RMU_RSTCAUSE_EXTRST (0x1UL << 3)
#define	_RMU_RSTCAUSE_EXTRST_SHIFT 3
#define	_RMU_RSTCAUSE_EXTRST_MASK 0x8UL
#define	_RMU_RSTCAUSE_EXTRST_DEFAULT 0x00000000UL
#define	RMU_RSTCAUSE_EXTRST_DEFAULT (_RMU_RSTCAUSE_EXTRST_DEFAULT << 3)
#define	RMU_RSTCAUSE_WDOGRST (0x1UL << 4)
#define	_RMU_RSTCAUSE_WDOGRST_SHIFT 4
#define	_RMU_RSTCAUSE_WDOGRST_MASK 0x10UL
#define	_RMU_RSTCAUSE_WDOGRST_DEFAULT 0x00000000UL
#define	RMU_RSTCAUSE_WDOGRST_DEFAULT (_RMU_RSTCAUSE_WDOGRST_DEFAULT << 4)
#define	RMU_RSTCAUSE_LOCKUPRST (0x1UL << 5)
#define	_RMU_RSTCAUSE_LOCKUPRST_SHIFT 5
#define	_RMU_RSTCAUSE_LOCKUPRST_MASK 0x20UL
#define	_RMU_RSTCAUSE_LOCKUPRST_DEFAULT 0x00000000UL
#define	RMU_RSTCAUSE_LOCKUPRST_DEFAULT (_RMU_RSTCAUSE_LOCKUPRST_DEFAULT << 5)
#define	RMU_RSTCAUSE_SYSREQRST (0x1UL << 6)
#define	_RMU_RSTCAUSE_SYSREQRST_SHIFT 6
#define	_RMU_RSTCAUSE_SYSREQRST_MASK 0x40UL
#define	_RMU_RSTCAUSE_SYSREQRST_DEFAULT 0x00000000UL
#define	RMU_RSTCAUSE_SYSREQRST_DEFAULT (_RMU_RSTCAUSE_SYSREQRST_DEFAULT << 6)
#define	_RMU_CMD_RESETVALUE 0x00000000UL
#define	_RMU_CMD_MASK 0x00000001UL
#define	RMU_CMD_RCCLR (0x1UL << 0)
#define	_RMU_CMD_RCCLR_SHIFT 0
#define	_RMU_CMD_RCCLR_MASK 0x1UL
#define	_RMU_CMD_RCCLR_DEFAULT 0x00000000UL
#define	RMU_CMD_RCCLR_DEFAULT (_RMU_CMD_RCCLR_DEFAULT << 0)
#define	_CMU_CTRL_RESETVALUE 0x000C262CUL
#define	_CMU_CTRL_MASK 0x00FE3EEFUL
#define	_CMU_CTRL_HFXOMODE_SHIFT 0
#define	_CMU_CTRL_HFXOMODE_MASK 0x3UL
#define	_CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL
#define	_CMU_CTRL_HFXOMODE_XTAL 0x00000000UL
#define	_CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL
#define	_CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL
#define	CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0)
#define	CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0)
#define	CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0)
#define	CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0)
#define	_CMU_CTRL_HFXOBOOST_SHIFT 2
#define	_CMU_CTRL_HFXOBOOST_MASK 0xCUL
#define	_CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL
#define	_CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL
#define	_CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL
#define	_CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL
#define	_CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL
#define	CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2)
#define	CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2)
#define	CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2)
#define	CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2)
#define	CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2)
#define	_CMU_CTRL_HFXOBUFCUR_SHIFT 5
#define	_CMU_CTRL_HFXOBUFCUR_MASK 0x60UL
#define	_CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL
#define	CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5)
#define	CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7)
#define	_CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7
#define	_CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL
#define	_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL
#define	CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7)
#define	_CMU_CTRL_HFXOTIMEOUT_SHIFT 9
#define	_CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL
#define	_CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL
#define	_CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL
#define	_CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL
#define	_CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL
#define	_CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL
#define	CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9)
#define	CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9)
#define	CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9)
#define	CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9)
#define	CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9)
#define	_CMU_CTRL_LFXOMODE_SHIFT 11
#define	_CMU_CTRL_LFXOMODE_MASK 0x1800UL
#define	_CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL
#define	_CMU_CTRL_LFXOMODE_XTAL 0x00000000UL
#define	_CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL
#define	_CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL
#define	CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11)
#define	CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11)
#define	CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11)
#define	CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11)
#define	CMU_CTRL_LFXOBOOST (0x1UL << 13)
#define	_CMU_CTRL_LFXOBOOST_SHIFT 13
#define	_CMU_CTRL_LFXOBOOST_MASK 0x2000UL
#define	_CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL
#define	_CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL
#define	_CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL
#define	CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13)
#define	CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13)
#define	CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13)
#define	CMU_CTRL_LFXOBUFCUR (0x1UL << 17)
#define	_CMU_CTRL_LFXOBUFCUR_SHIFT 17
#define	_CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL
#define	_CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL
#define	CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17)
#define	_CMU_CTRL_LFXOTIMEOUT_SHIFT 18
#define	_CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL
#define	_CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL
#define	_CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL
#define	_CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL
#define	_CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL
#define	_CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL
#define	CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18)
#define	CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18)
#define	CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18)
#define	CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18)
#define	CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18)
#define	_CMU_CTRL_CLKOUTSEL0_SHIFT 20
#define	_CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL
#define	_CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL
#define	_CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL
#define	_CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL
#define	_CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL
#define	_CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL
#define	_CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL
#define	_CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL
#define	_CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL
#define	CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20)
#define	CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20)
#define	CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20)
#define	CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20)
#define	CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20)
#define	CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20)
#define	CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20)
#define	CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20)
#define	CMU_CTRL_CLKOUTSEL1 (0x1UL << 23)
#define	_CMU_CTRL_CLKOUTSEL1_SHIFT 23
#define	_CMU_CTRL_CLKOUTSEL1_MASK 0x800000UL
#define	_CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL
#define	_CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL
#define	_CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL
#define	CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23)
#define	CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23)
#define	CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23)
#define	_CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL
#define	_CMU_HFCORECLKDIV_MASK 0x0000000FUL
#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0
#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL
#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL
#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL
#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL
#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL
#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL
#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL
#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL
#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL
#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL
#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL
#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL
#define	CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0)
#define	CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0)
#define	CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0)
#define	CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0)
#define	CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0)
#define	CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0)
#define	CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0)
#define	CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0)
#define	CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0)
#define	CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0)
#define	CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0)
#define	_CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL
#define	_CMU_HFPERCLKDIV_MASK 0x0000010FUL
#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0
#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL
#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL
#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL
#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL
#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL
#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL
#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL
#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL
#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL
#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL
#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL
#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL
#define	CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0)
#define	CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0)
#define	CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0)
#define	CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0)
#define	CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0)
#define	CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0)
#define	CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0)
#define	CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0)
#define	CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0)
#define	CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0)
#define	CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0)
#define	CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8)
#define	_CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8
#define	_CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL
#define	_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL
#define	CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8)
#define	_CMU_HFRCOCTRL_RESETVALUE 0x00000380UL
#define	_CMU_HFRCOCTRL_MASK 0x0001F7FFUL
#define	_CMU_HFRCOCTRL_TUNING_SHIFT 0
#define	_CMU_HFRCOCTRL_TUNING_MASK 0xFFUL
#define	_CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL
#define	CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0)
#define	_CMU_HFRCOCTRL_BAND_SHIFT 8
#define	_CMU_HFRCOCTRL_BAND_MASK 0x700UL
#define	_CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL
#define	_CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL
#define	_CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL
#define	_CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL
#define	_CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL
#define	_CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL
#define	_CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL
#define	CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8)
#define	CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8)
#define	CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8)
#define	CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8)
#define	CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8)
#define	CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8)
#define	CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8)
#define	_CMU_HFRCOCTRL_SUDELAY_SHIFT 12
#define	_CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL
#define	_CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL
#define	CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12)
#define	_CMU_LFRCOCTRL_RESETVALUE 0x00000040UL
#define	_CMU_LFRCOCTRL_MASK 0x0000007FUL
#define	_CMU_LFRCOCTRL_TUNING_SHIFT 0
#define	_CMU_LFRCOCTRL_TUNING_MASK 0x7FUL
#define	_CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL
#define	CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0)
#define	_CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL
#define	_CMU_AUXHFRCOCTRL_MASK 0x000000FFUL
#define	_CMU_AUXHFRCOCTRL_TUNING_SHIFT 0
#define	_CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL
#define	_CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL
#define	CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0)
#define	_CMU_CALCTRL_RESETVALUE 0x00000000UL
#define	_CMU_CALCTRL_MASK 0x00000007UL
#define	_CMU_CALCTRL_REFSEL_SHIFT 0
#define	_CMU_CALCTRL_REFSEL_MASK 0x7UL
#define	_CMU_CALCTRL_REFSEL_DEFAULT 0x00000000UL
#define	_CMU_CALCTRL_REFSEL_HFXO 0x00000000UL
#define	_CMU_CALCTRL_REFSEL_LFXO 0x00000001UL
#define	_CMU_CALCTRL_REFSEL_HFRCO 0x00000002UL
#define	_CMU_CALCTRL_REFSEL_LFRCO 0x00000003UL
#define	_CMU_CALCTRL_REFSEL_AUXHFRCO 0x00000004UL
#define	CMU_CALCTRL_REFSEL_DEFAULT (_CMU_CALCTRL_REFSEL_DEFAULT << 0)
#define	CMU_CALCTRL_REFSEL_HFXO (_CMU_CALCTRL_REFSEL_HFXO << 0)
#define	CMU_CALCTRL_REFSEL_LFXO (_CMU_CALCTRL_REFSEL_LFXO << 0)
#define	CMU_CALCTRL_REFSEL_HFRCO (_CMU_CALCTRL_REFSEL_HFRCO << 0)
#define	CMU_CALCTRL_REFSEL_LFRCO (_CMU_CALCTRL_REFSEL_LFRCO << 0)
#define	CMU_CALCTRL_REFSEL_AUXHFRCO (_CMU_CALCTRL_REFSEL_AUXHFRCO << 0)
#define	_CMU_CALCNT_RESETVALUE 0x00000000UL
#define	_CMU_CALCNT_MASK 0x000FFFFFUL
#define	_CMU_CALCNT_CALCNT_SHIFT 0
#define	_CMU_CALCNT_CALCNT_MASK 0xFFFFFUL
#define	_CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL
#define	CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0)
#define	_CMU_OSCENCMD_RESETVALUE 0x00000000UL
#define	_CMU_OSCENCMD_MASK 0x000003FFUL
#define	CMU_OSCENCMD_HFRCOEN (0x1UL << 0)
#define	_CMU_OSCENCMD_HFRCOEN_SHIFT 0
#define	_CMU_OSCENCMD_HFRCOEN_MASK 0x1UL
#define	_CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL
#define	CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0)
#define	CMU_OSCENCMD_HFRCODIS (0x1UL << 1)
#define	_CMU_OSCENCMD_HFRCODIS_SHIFT 1
#define	_CMU_OSCENCMD_HFRCODIS_MASK 0x2UL
#define	_CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL
#define	CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1)
#define	CMU_OSCENCMD_HFXOEN (0x1UL << 2)
#define	_CMU_OSCENCMD_HFXOEN_SHIFT 2
#define	_CMU_OSCENCMD_HFXOEN_MASK 0x4UL
#define	_CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL
#define	CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2)
#define	CMU_OSCENCMD_HFXODIS (0x1UL << 3)
#define	_CMU_OSCENCMD_HFXODIS_SHIFT 3
#define	_CMU_OSCENCMD_HFXODIS_MASK 0x8UL
#define	_CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL
#define	CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3)
#define	CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4)
#define	_CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4
#define	_CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL
#define	_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL
#define	CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4)
#define	CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5)
#define	_CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5
#define	_CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL
#define	_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL
#define	CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5)
#define	CMU_OSCENCMD_LFRCOEN (0x1UL << 6)
#define	_CMU_OSCENCMD_LFRCOEN_SHIFT 6
#define	_CMU_OSCENCMD_LFRCOEN_MASK 0x40UL
#define	_CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL
#define	CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6)
#define	CMU_OSCENCMD_LFRCODIS (0x1UL << 7)
#define	_CMU_OSCENCMD_LFRCODIS_SHIFT 7
#define	_CMU_OSCENCMD_LFRCODIS_MASK 0x80UL
#define	_CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL
#define	CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7)
#define	CMU_OSCENCMD_LFXOEN (0x1UL << 8)
#define	_CMU_OSCENCMD_LFXOEN_SHIFT 8
#define	_CMU_OSCENCMD_LFXOEN_MASK 0x100UL
#define	_CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL
#define	CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8)
#define	CMU_OSCENCMD_LFXODIS (0x1UL << 9)
#define	_CMU_OSCENCMD_LFXODIS_SHIFT 9
#define	_CMU_OSCENCMD_LFXODIS_MASK 0x200UL
#define	_CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL
#define	CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9)
#define	_CMU_CMD_RESETVALUE 0x00000000UL
#define	_CMU_CMD_MASK 0x0000000FUL
#define	_CMU_CMD_HFCLKSEL_SHIFT 0
#define	_CMU_CMD_HFCLKSEL_MASK 0x7UL
#define	_CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL
#define	_CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL
#define	_CMU_CMD_HFCLKSEL_HFXO 0x00000002UL
#define	_CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL
#define	_CMU_CMD_HFCLKSEL_LFXO 0x00000004UL
#define	CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0)
#define	CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0)
#define	CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0)
#define	CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0)
#define	CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0)
#define	CMU_CMD_CALSTART (0x1UL << 3)
#define	_CMU_CMD_CALSTART_SHIFT 3
#define	_CMU_CMD_CALSTART_MASK 0x8UL
#define	_CMU_CMD_CALSTART_DEFAULT 0x00000000UL
#define	CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3)
#define	_CMU_LFCLKSEL_RESETVALUE 0x00000005UL
#define	_CMU_LFCLKSEL_MASK 0x0000000FUL
#define	_CMU_LFCLKSEL_LFA_SHIFT 0
#define	_CMU_LFCLKSEL_LFA_MASK 0x3UL
#define	_CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL
#define	_CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL
#define	_CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL
#define	_CMU_LFCLKSEL_LFA_LFXO 0x00000002UL
#define	_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL
#define	CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0)
#define	CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0)
#define	CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0)
#define	CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0)
#define	CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0)
#define	_CMU_LFCLKSEL_LFB_SHIFT 2
#define	_CMU_LFCLKSEL_LFB_MASK 0xCUL
#define	_CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL
#define	_CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL
#define	_CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL
#define	_CMU_LFCLKSEL_LFB_LFXO 0x00000002UL
#define	_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL
#define	CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2)
#define	CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2)
#define	CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2)
#define	CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2)
#define	CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2)
#define	_CMU_STATUS_RESETVALUE 0x00000403UL
#define	_CMU_STATUS_MASK 0x00007FFFUL
#define	CMU_STATUS_HFRCOENS (0x1UL << 0)
#define	_CMU_STATUS_HFRCOENS_SHIFT 0
#define	_CMU_STATUS_HFRCOENS_MASK 0x1UL
#define	_CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL
#define	CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0)
#define	CMU_STATUS_HFRCORDY (0x1UL << 1)
#define	_CMU_STATUS_HFRCORDY_SHIFT 1
#define	_CMU_STATUS_HFRCORDY_MASK 0x2UL
#define	_CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL
#define	CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1)
#define	CMU_STATUS_HFXOENS (0x1UL << 2)
#define	_CMU_STATUS_HFXOENS_SHIFT 2
#define	_CMU_STATUS_HFXOENS_MASK 0x4UL
#define	_CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL
#define	CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2)
#define	CMU_STATUS_HFXORDY (0x1UL << 3)
#define	_CMU_STATUS_HFXORDY_SHIFT 3
#define	_CMU_STATUS_HFXORDY_MASK 0x8UL
#define	_CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL
#define	CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3)
#define	CMU_STATUS_AUXHFRCOENS (0x1UL << 4)
#define	_CMU_STATUS_AUXHFRCOENS_SHIFT 4
#define	_CMU_STATUS_AUXHFRCOENS_MASK 0x10UL
#define	_CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL
#define	CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4)
#define	CMU_STATUS_AUXHFRCORDY (0x1UL << 5)
#define	_CMU_STATUS_AUXHFRCORDY_SHIFT 5
#define	_CMU_STATUS_AUXHFRCORDY_MASK 0x20UL
#define	_CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL
#define	CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5)
#define	CMU_STATUS_LFRCOENS (0x1UL << 6)
#define	_CMU_STATUS_LFRCOENS_SHIFT 6
#define	_CMU_STATUS_LFRCOENS_MASK 0x40UL
#define	_CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL
#define	CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6)
#define	CMU_STATUS_LFRCORDY (0x1UL << 7)
#define	_CMU_STATUS_LFRCORDY_SHIFT 7
#define	_CMU_STATUS_LFRCORDY_MASK 0x80UL
#define	_CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL
#define	CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7)
#define	CMU_STATUS_LFXOENS (0x1UL << 8)
#define	_CMU_STATUS_LFXOENS_SHIFT 8
#define	_CMU_STATUS_LFXOENS_MASK 0x100UL
#define	_CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL
#define	CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8)
#define	CMU_STATUS_LFXORDY (0x1UL << 9)
#define	_CMU_STATUS_LFXORDY_SHIFT 9
#define	_CMU_STATUS_LFXORDY_MASK 0x200UL
#define	_CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL
#define	CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9)
#define	CMU_STATUS_HFRCOSEL (0x1UL << 10)
#define	_CMU_STATUS_HFRCOSEL_SHIFT 10
#define	_CMU_STATUS_HFRCOSEL_MASK 0x400UL
#define	_CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL
#define	CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10)
#define	CMU_STATUS_HFXOSEL (0x1UL << 11)
#define	_CMU_STATUS_HFXOSEL_SHIFT 11
#define	_CMU_STATUS_HFXOSEL_MASK 0x800UL
#define	_CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL
#define	CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11)
#define	CMU_STATUS_LFRCOSEL (0x1UL << 12)
#define	_CMU_STATUS_LFRCOSEL_SHIFT 12
#define	_CMU_STATUS_LFRCOSEL_MASK 0x1000UL
#define	_CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL
#define	CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12)
#define	CMU_STATUS_LFXOSEL (0x1UL << 13)
#define	_CMU_STATUS_LFXOSEL_SHIFT 13
#define	_CMU_STATUS_LFXOSEL_MASK 0x2000UL
#define	_CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL
#define	CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13)
#define	CMU_STATUS_CALBSY (0x1UL << 14)
#define	_CMU_STATUS_CALBSY_SHIFT 14
#define	_CMU_STATUS_CALBSY_MASK 0x4000UL
#define	_CMU_STATUS_CALBSY_DEFAULT 0x00000000UL
#define	CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14)
#define	_CMU_IF_RESETVALUE 0x00000001UL
#define	_CMU_IF_MASK 0x0000003FUL
#define	CMU_IF_HFRCORDY (0x1UL << 0)
#define	_CMU_IF_HFRCORDY_SHIFT 0
#define	_CMU_IF_HFRCORDY_MASK 0x1UL
#define	_CMU_IF_HFRCORDY_DEFAULT 0x00000001UL
#define	CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0)
#define	CMU_IF_HFXORDY (0x1UL << 1)
#define	_CMU_IF_HFXORDY_SHIFT 1
#define	_CMU_IF_HFXORDY_MASK 0x2UL
#define	_CMU_IF_HFXORDY_DEFAULT 0x00000000UL
#define	CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1)
#define	CMU_IF_LFRCORDY (0x1UL << 2)
#define	_CMU_IF_LFRCORDY_SHIFT 2
#define	_CMU_IF_LFRCORDY_MASK 0x4UL
#define	_CMU_IF_LFRCORDY_DEFAULT 0x00000000UL
#define	CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2)
#define	CMU_IF_LFXORDY (0x1UL << 3)
#define	_CMU_IF_LFXORDY_SHIFT 3
#define	_CMU_IF_LFXORDY_MASK 0x8UL
#define	_CMU_IF_LFXORDY_DEFAULT 0x00000000UL
#define	CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3)
#define	CMU_IF_AUXHFRCORDY (0x1UL << 4)
#define	_CMU_IF_AUXHFRCORDY_SHIFT 4
#define	_CMU_IF_AUXHFRCORDY_MASK 0x10UL
#define	_CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL
#define	CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4)
#define	CMU_IF_CALRDY (0x1UL << 5)
#define	_CMU_IF_CALRDY_SHIFT 5
#define	_CMU_IF_CALRDY_MASK 0x20UL
#define	_CMU_IF_CALRDY_DEFAULT 0x00000000UL
#define	CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5)
#define	_CMU_IFS_RESETVALUE 0x00000000UL
#define	_CMU_IFS_MASK 0x0000003FUL
#define	CMU_IFS_HFRCORDY (0x1UL << 0)
#define	_CMU_IFS_HFRCORDY_SHIFT 0
#define	_CMU_IFS_HFRCORDY_MASK 0x1UL
#define	_CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL
#define	CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0)
#define	CMU_IFS_HFXORDY (0x1UL << 1)
#define	_CMU_IFS_HFXORDY_SHIFT 1
#define	_CMU_IFS_HFXORDY_MASK 0x2UL
#define	_CMU_IFS_HFXORDY_DEFAULT 0x00000000UL
#define	CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1)
#define	CMU_IFS_LFRCORDY (0x1UL << 2)
#define	_CMU_IFS_LFRCORDY_SHIFT 2
#define	_CMU_IFS_LFRCORDY_MASK 0x4UL
#define	_CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL
#define	CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2)
#define	CMU_IFS_LFXORDY (0x1UL << 3)
#define	_CMU_IFS_LFXORDY_SHIFT 3
#define	_CMU_IFS_LFXORDY_MASK 0x8UL
#define	_CMU_IFS_LFXORDY_DEFAULT 0x00000000UL
#define	CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3)
#define	CMU_IFS_AUXHFRCORDY (0x1UL << 4)
#define	_CMU_IFS_AUXHFRCORDY_SHIFT 4
#define	_CMU_IFS_AUXHFRCORDY_MASK 0x10UL
#define	_CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL
#define	CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4)
#define	CMU_IFS_CALRDY (0x1UL << 5)
#define	_CMU_IFS_CALRDY_SHIFT 5
#define	_CMU_IFS_CALRDY_MASK 0x20UL
#define	_CMU_IFS_CALRDY_DEFAULT 0x00000000UL
#define	CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5)
#define	_CMU_IFC_RESETVALUE 0x00000000UL
#define	_CMU_IFC_MASK 0x0000003FUL
#define	CMU_IFC_HFRCORDY (0x1UL << 0)
#define	_CMU_IFC_HFRCORDY_SHIFT 0
#define	_CMU_IFC_HFRCORDY_MASK 0x1UL
#define	_CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL
#define	CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0)
#define	CMU_IFC_HFXORDY (0x1UL << 1)
#define	_CMU_IFC_HFXORDY_SHIFT 1
#define	_CMU_IFC_HFXORDY_MASK 0x2UL
#define	_CMU_IFC_HFXORDY_DEFAULT 0x00000000UL
#define	CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1)
#define	CMU_IFC_LFRCORDY (0x1UL << 2)
#define	_CMU_IFC_LFRCORDY_SHIFT 2
#define	_CMU_IFC_LFRCORDY_MASK 0x4UL
#define	_CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL
#define	CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2)
#define	CMU_IFC_LFXORDY (0x1UL << 3)
#define	_CMU_IFC_LFXORDY_SHIFT 3
#define	_CMU_IFC_LFXORDY_MASK 0x8UL
#define	_CMU_IFC_LFXORDY_DEFAULT 0x00000000UL
#define	CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3)
#define	CMU_IFC_AUXHFRCORDY (0x1UL << 4)
#define	_CMU_IFC_AUXHFRCORDY_SHIFT 4
#define	_CMU_IFC_AUXHFRCORDY_MASK 0x10UL
#define	_CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL
#define	CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4)
#define	CMU_IFC_CALRDY (0x1UL << 5)
#define	_CMU_IFC_CALRDY_SHIFT 5
#define	_CMU_IFC_CALRDY_MASK 0x20UL
#define	_CMU_IFC_CALRDY_DEFAULT 0x00000000UL
#define	CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5)
#define	_CMU_IEN_RESETVALUE 0x00000000UL
#define	_CMU_IEN_MASK 0x0000003FUL
#define	CMU_IEN_HFRCORDY (0x1UL << 0)
#define	_CMU_IEN_HFRCORDY_SHIFT 0
#define	_CMU_IEN_HFRCORDY_MASK 0x1UL
#define	_CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL
#define	CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0)
#define	CMU_IEN_HFXORDY (0x1UL << 1)
#define	_CMU_IEN_HFXORDY_SHIFT 1
#define	_CMU_IEN_HFXORDY_MASK 0x2UL
#define	_CMU_IEN_HFXORDY_DEFAULT 0x00000000UL
#define	CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1)
#define	CMU_IEN_LFRCORDY (0x1UL << 2)
#define	_CMU_IEN_LFRCORDY_SHIFT 2
#define	_CMU_IEN_LFRCORDY_MASK 0x4UL
#define	_CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL
#define	CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2)
#define	CMU_IEN_LFXORDY (0x1UL << 3)
#define	_CMU_IEN_LFXORDY_SHIFT 3
#define	_CMU_IEN_LFXORDY_MASK 0x8UL
#define	_CMU_IEN_LFXORDY_DEFAULT 0x00000000UL
#define	CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3)
#define	CMU_IEN_AUXHFRCORDY (0x1UL << 4)
#define	_CMU_IEN_AUXHFRCORDY_SHIFT 4
#define	_CMU_IEN_AUXHFRCORDY_MASK 0x10UL
#define	_CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL
#define	CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4)
#define	CMU_IEN_CALRDY (0x1UL << 5)
#define	_CMU_IEN_CALRDY_SHIFT 5
#define	_CMU_IEN_CALRDY_MASK 0x20UL
#define	_CMU_IEN_CALRDY_DEFAULT 0x00000000UL
#define	CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5)
#define	_CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL
#define	_CMU_HFCORECLKEN0_MASK 0x0000000FUL
#define	CMU_HFCORECLKEN0_AES (0x1UL << 0)
#define	_CMU_HFCORECLKEN0_AES_SHIFT 0
#define	_CMU_HFCORECLKEN0_AES_MASK 0x1UL
#define	_CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL
#define	CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 0)
#define	CMU_HFCORECLKEN0_DMA (0x1UL << 1)
#define	_CMU_HFCORECLKEN0_DMA_SHIFT 1
#define	_CMU_HFCORECLKEN0_DMA_MASK 0x2UL
#define	_CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL
#define	CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 1)
#define	CMU_HFCORECLKEN0_LE (0x1UL << 2)
#define	_CMU_HFCORECLKEN0_LE_SHIFT 2
#define	_CMU_HFCORECLKEN0_LE_MASK 0x4UL
#define	_CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL
#define	CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 2)
#define	CMU_HFCORECLKEN0_EBI (0x1UL << 3)
#define	_CMU_HFCORECLKEN0_EBI_SHIFT 3
#define	_CMU_HFCORECLKEN0_EBI_MASK 0x8UL
#define	_CMU_HFCORECLKEN0_EBI_DEFAULT 0x00000000UL
#define	CMU_HFCORECLKEN0_EBI_DEFAULT (_CMU_HFCORECLKEN0_EBI_DEFAULT << 3)
#define	_CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL
#define	_CMU_HFPERCLKEN0_MASK 0x0000FFFFUL
#define	CMU_HFPERCLKEN0_USART0 (0x1UL << 0)
#define	_CMU_HFPERCLKEN0_USART0_SHIFT 0
#define	_CMU_HFPERCLKEN0_USART0_MASK 0x1UL
#define	_CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL
#define	CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0)
#define	CMU_HFPERCLKEN0_USART1 (0x1UL << 1)
#define	_CMU_HFPERCLKEN0_USART1_SHIFT 1
#define	_CMU_HFPERCLKEN0_USART1_MASK 0x2UL
#define	_CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL
#define	CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1)
#define	CMU_HFPERCLKEN0_USART2 (0x1UL << 2)
#define	_CMU_HFPERCLKEN0_USART2_SHIFT 2
#define	_CMU_HFPERCLKEN0_USART2_MASK 0x4UL
#define	_CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL
#define	CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2)
#define	CMU_HFPERCLKEN0_UART0 (0x1UL << 3)
#define	_CMU_HFPERCLKEN0_UART0_SHIFT 3
#define	_CMU_HFPERCLKEN0_UART0_MASK 0x8UL
#define	_CMU_HFPERCLKEN0_UART0_DEFAULT 0x00000000UL
#define	CMU_HFPERCLKEN0_UART0_DEFAULT (_CMU_HFPERCLKEN0_UART0_DEFAULT << 3)
#define	CMU_HFPERCLKEN0_TIMER0 (0x1UL << 4)
#define	_CMU_HFPERCLKEN0_TIMER0_SHIFT 4
#define	_CMU_HFPERCLKEN0_TIMER0_MASK 0x10UL
#define	_CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL
#define	CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 4)
#define	CMU_HFPERCLKEN0_TIMER1 (0x1UL << 5)
#define	_CMU_HFPERCLKEN0_TIMER1_SHIFT 5
#define	_CMU_HFPERCLKEN0_TIMER1_MASK 0x20UL
#define	_CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL
#define	CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 5)
#define	CMU_HFPERCLKEN0_TIMER2 (0x1UL << 6)
#define	_CMU_HFPERCLKEN0_TIMER2_SHIFT 6
#define	_CMU_HFPERCLKEN0_TIMER2_MASK 0x40UL
#define	_CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL
#define	CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 6)
#define	CMU_HFPERCLKEN0_ACMP0 (0x1UL << 7)
#define	_CMU_HFPERCLKEN0_ACMP0_SHIFT 7
#define	_CMU_HFPERCLKEN0_ACMP0_MASK 0x80UL
#define	_CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL
#define	CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 7)
#define	CMU_HFPERCLKEN0_ACMP1 (0x1UL << 8)
#define	_CMU_HFPERCLKEN0_ACMP1_SHIFT 8
#define	_CMU_HFPERCLKEN0_ACMP1_MASK 0x100UL
#define	_CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL
#define	CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 8)
#define	CMU_HFPERCLKEN0_PRS (0x1UL << 10)
#define	_CMU_HFPERCLKEN0_PRS_SHIFT 10
#define	_CMU_HFPERCLKEN0_PRS_MASK 0x400UL
#define	_CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL
#define	CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 10)
#define	CMU_HFPERCLKEN0_DAC0 (0x1UL << 11)
#define	_CMU_HFPERCLKEN0_DAC0_SHIFT 11
#define	_CMU_HFPERCLKEN0_DAC0_MASK 0x800UL
#define	_CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL
#define	CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 11)
#define	CMU_HFPERCLKEN0_GPIO (0x1UL << 12)
#define	_CMU_HFPERCLKEN0_GPIO_SHIFT 12
#define	_CMU_HFPERCLKEN0_GPIO_MASK 0x1000UL
#define	_CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL
#define	CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 12)
#define	CMU_HFPERCLKEN0_VCMP (0x1UL << 13)
#define	_CMU_HFPERCLKEN0_VCMP_SHIFT 13
#define	_CMU_HFPERCLKEN0_VCMP_MASK 0x2000UL
#define	_CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL
#define	CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 13)
#define	CMU_HFPERCLKEN0_ADC0 (0x1UL << 14)
#define	_CMU_HFPERCLKEN0_ADC0_SHIFT 14
#define	_CMU_HFPERCLKEN0_ADC0_MASK 0x4000UL
#define	_CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL
#define	CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 14)
#define	CMU_HFPERCLKEN0_I2C0 (0x1UL << 15)
#define	_CMU_HFPERCLKEN0_I2C0_SHIFT 15
#define	_CMU_HFPERCLKEN0_I2C0_MASK 0x8000UL
#define	_CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL
#define	CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 15)
#define	_CMU_SYNCBUSY_RESETVALUE 0x00000000UL
#define	_CMU_SYNCBUSY_MASK 0x00000055UL
#define	CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0)
#define	_CMU_SYNCBUSY_LFACLKEN0_SHIFT 0
#define	_CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL
#define	_CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL
#define	CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0)
#define	CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2)
#define	_CMU_SYNCBUSY_LFAPRESC0_SHIFT 2
#define	_CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL
#define	_CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL
#define	CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2)
#define	CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4)
#define	_CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4
#define	_CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL
#define	_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL
#define	CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4)
#define	CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6)
#define	_CMU_SYNCBUSY_LFBPRESC0_SHIFT 6
#define	_CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL
#define	_CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL
#define	CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6)
#define	_CMU_FREEZE_RESETVALUE 0x00000000UL
#define	_CMU_FREEZE_MASK 0x00000001UL
#define	CMU_FREEZE_REGFREEZE (0x1UL << 0)
#define	_CMU_FREEZE_REGFREEZE_SHIFT 0
#define	_CMU_FREEZE_REGFREEZE_MASK 0x1UL
#define	_CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL
#define	_CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL
#define	_CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL
#define	CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0)
#define	CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0)
#define	CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0)
#define	_CMU_LFACLKEN0_RESETVALUE 0x00000000UL
#define	_CMU_LFACLKEN0_MASK 0x00000007UL
#define	CMU_LFACLKEN0_RTC (0x1UL << 0)
#define	_CMU_LFACLKEN0_RTC_SHIFT 0
#define	_CMU_LFACLKEN0_RTC_MASK 0x1UL
#define	_CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL
#define	CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 0)
#define	CMU_LFACLKEN0_LETIMER0 (0x1UL << 1)
#define	_CMU_LFACLKEN0_LETIMER0_SHIFT 1
#define	_CMU_LFACLKEN0_LETIMER0_MASK 0x2UL
#define	_CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL
#define	CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 1)
#define	CMU_LFACLKEN0_LCD (0x1UL << 2)
#define	_CMU_LFACLKEN0_LCD_SHIFT 2
#define	_CMU_LFACLKEN0_LCD_MASK 0x4UL
#define	_CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL
#define	CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 2)
#define	_CMU_LFBCLKEN0_RESETVALUE 0x00000000UL
#define	_CMU_LFBCLKEN0_MASK 0x00000003UL
#define	CMU_LFBCLKEN0_LEUART0 (0x1UL << 0)
#define	_CMU_LFBCLKEN0_LEUART0_SHIFT 0
#define	_CMU_LFBCLKEN0_LEUART0_MASK 0x1UL
#define	_CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL
#define	CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0)
#define	CMU_LFBCLKEN0_LEUART1 (0x1UL << 1)
#define	_CMU_LFBCLKEN0_LEUART1_SHIFT 1
#define	_CMU_LFBCLKEN0_LEUART1_MASK 0x2UL
#define	_CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL
#define	CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1)
#define	_CMU_LFAPRESC0_RESETVALUE 0x00000000UL
#define	_CMU_LFAPRESC0_MASK 0x000003FFUL
#define	_CMU_LFAPRESC0_RTC_SHIFT 0
#define	_CMU_LFAPRESC0_RTC_MASK 0xFUL
#define	_CMU_LFAPRESC0_RTC_DIV1 0x00000000UL
#define	_CMU_LFAPRESC0_RTC_DIV2 0x00000001UL
#define	_CMU_LFAPRESC0_RTC_DIV4 0x00000002UL
#define	_CMU_LFAPRESC0_RTC_DIV8 0x00000003UL
#define	_CMU_LFAPRESC0_RTC_DIV16 0x00000004UL
#define	_CMU_LFAPRESC0_RTC_DIV32 0x00000005UL
#define	_CMU_LFAPRESC0_RTC_DIV64 0x00000006UL
#define	_CMU_LFAPRESC0_RTC_DIV128 0x00000007UL
#define	_CMU_LFAPRESC0_RTC_DIV256 0x00000008UL
#define	_CMU_LFAPRESC0_RTC_DIV512 0x00000009UL
#define	_CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL
#define	_CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL
#define	_CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL
#define	_CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL
#define	_CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL
#define	_CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL
#define	CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 0)
#define	CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 0)
#define	CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 0)
#define	CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 0)
#define	CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 0)
#define	CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 0)
#define	CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 0)
#define	CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 0)
#define	CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 0)
#define	CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 0)
#define	CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 0)
#define	CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 0)
#define	CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 0)
#define	CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 0)
#define	CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 0)
#define	CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 0)
#define	_CMU_LFAPRESC0_LETIMER0_SHIFT 4
#define	_CMU_LFAPRESC0_LETIMER0_MASK 0xF0UL
#define	_CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL
#define	_CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL
#define	_CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL
#define	_CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL
#define	_CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL
#define	_CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL
#define	_CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL
#define	_CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL
#define	_CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL
#define	_CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL
#define	_CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL
#define	_CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL
#define	_CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL
#define	_CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL
#define	_CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL
#define	_CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL
#define	CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 4)
#define	CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 4)
#define	CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 4)
#define	CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 4)
#define	CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 4)
#define	CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 4)
#define	CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 4)
#define	CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 4)
#define	CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 4)
#define	CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 4)
#define	CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 4)
#define	CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 4)
#define	CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 4)
#define	CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 4)
#define	CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 4)
#define	CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 4)
#define	_CMU_LFAPRESC0_LCD_SHIFT 8
#define	_CMU_LFAPRESC0_LCD_MASK 0x300UL
#define	_CMU_LFAPRESC0_LCD_DIV16 0x00000000UL
#define	_CMU_LFAPRESC0_LCD_DIV32 0x00000001UL
#define	_CMU_LFAPRESC0_LCD_DIV64 0x00000002UL
#define	_CMU_LFAPRESC0_LCD_DIV128 0x00000003UL
#define	CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 8)
#define	CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 8)
#define	CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 8)
#define	CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 8)
#define	_CMU_LFBPRESC0_RESETVALUE 0x00000000UL
#define	_CMU_LFBPRESC0_MASK 0x00000033UL
#define	_CMU_LFBPRESC0_LEUART0_SHIFT 0
#define	_CMU_LFBPRESC0_LEUART0_MASK 0x3UL
#define	_CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL
#define	_CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL
#define	_CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL
#define	_CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL
#define	CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0)
#define	CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0)
#define	CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0)
#define	CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0)
#define	_CMU_LFBPRESC0_LEUART1_SHIFT 4
#define	_CMU_LFBPRESC0_LEUART1_MASK 0x30UL
#define	_CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL
#define	_CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL
#define	_CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL
#define	_CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL
#define	CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4)
#define	CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4)
#define	CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4)
#define	CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4)
#define	_CMU_PCNTCTRL_RESETVALUE 0x00000000UL
#define	_CMU_PCNTCTRL_MASK 0x0000003FUL
#define	CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0)
#define	_CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0
#define	_CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL
#define	_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL
#define	CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0)
#define	CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1)
#define	_CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1
#define	_CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL
#define	_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL
#define	_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL
#define	_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL
#define	CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1)
#define	CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1)
#define	CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1)
#define	CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2)
#define	_CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2
#define	_CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL
#define	_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL
#define	CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2)
#define	CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3)
#define	_CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3
#define	_CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL
#define	_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL
#define	_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL
#define	_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL
#define	CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3)
#define	CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3)
#define	CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3)
#define	CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4)
#define	_CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4
#define	_CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL
#define	_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL
#define	CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4)
#define	CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5)
#define	_CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5
#define	_CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL
#define	_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL
#define	_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL
#define	_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL
#define	CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5)
#define	CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5)
#define	CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5)
#define	_CMU_LCDCTRL_RESETVALUE 0x00000020UL
#define	_CMU_LCDCTRL_MASK 0x0000007FUL
#define	_CMU_LCDCTRL_FDIV_SHIFT 0
#define	_CMU_LCDCTRL_FDIV_MASK 0x7UL
#define	_CMU_LCDCTRL_FDIV_DEFAULT 0x00000000UL
#define	CMU_LCDCTRL_FDIV_DEFAULT (_CMU_LCDCTRL_FDIV_DEFAULT << 0)
#define	CMU_LCDCTRL_VBOOSTEN (0x1UL << 3)
#define	_CMU_LCDCTRL_VBOOSTEN_SHIFT 3
#define	_CMU_LCDCTRL_VBOOSTEN_MASK 0x8UL
#define	_CMU_LCDCTRL_VBOOSTEN_DEFAULT 0x00000000UL
#define	CMU_LCDCTRL_VBOOSTEN_DEFAULT (_CMU_LCDCTRL_VBOOSTEN_DEFAULT << 3)
#define	_CMU_LCDCTRL_VBFDIV_SHIFT 4
#define	_CMU_LCDCTRL_VBFDIV_MASK 0x70UL
#define	_CMU_LCDCTRL_VBFDIV_DIV1 0x00000000UL
#define	_CMU_LCDCTRL_VBFDIV_DIV2 0x00000001UL
#define	_CMU_LCDCTRL_VBFDIV_DEFAULT 0x00000002UL
#define	_CMU_LCDCTRL_VBFDIV_DIV4 0x00000002UL
#define	_CMU_LCDCTRL_VBFDIV_DIV8 0x00000003UL
#define	_CMU_LCDCTRL_VBFDIV_DIV16 0x00000004UL
#define	_CMU_LCDCTRL_VBFDIV_DIV32 0x00000005UL
#define	_CMU_LCDCTRL_VBFDIV_DIV64 0x00000006UL
#define	_CMU_LCDCTRL_VBFDIV_DIV128 0x00000007UL
#define	CMU_LCDCTRL_VBFDIV_DIV1 (_CMU_LCDCTRL_VBFDIV_DIV1 << 4)
#define	CMU_LCDCTRL_VBFDIV_DIV2 (_CMU_LCDCTRL_VBFDIV_DIV2 << 4)
#define	CMU_LCDCTRL_VBFDIV_DEFAULT (_CMU_LCDCTRL_VBFDIV_DEFAULT << 4)
#define	CMU_LCDCTRL_VBFDIV_DIV4 (_CMU_LCDCTRL_VBFDIV_DIV4 << 4)
#define	CMU_LCDCTRL_VBFDIV_DIV8 (_CMU_LCDCTRL_VBFDIV_DIV8 << 4)
#define	CMU_LCDCTRL_VBFDIV_DIV16 (_CMU_LCDCTRL_VBFDIV_DIV16 << 4)
#define	CMU_LCDCTRL_VBFDIV_DIV32 (_CMU_LCDCTRL_VBFDIV_DIV32 << 4)
#define	CMU_LCDCTRL_VBFDIV_DIV64 (_CMU_LCDCTRL_VBFDIV_DIV64 << 4)
#define	CMU_LCDCTRL_VBFDIV_DIV128 (_CMU_LCDCTRL_VBFDIV_DIV128 << 4)
#define	_CMU_ROUTE_RESETVALUE 0x00000000UL
#define	_CMU_ROUTE_MASK 0x00000007UL
#define	CMU_ROUTE_CLKOUT0PEN (0x1UL << 0)
#define	_CMU_ROUTE_CLKOUT0PEN_SHIFT 0
#define	_CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL
#define	_CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL
#define	CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0)
#define	CMU_ROUTE_CLKOUT1PEN (0x1UL << 1)
#define	_CMU_ROUTE_CLKOUT1PEN_SHIFT 1
#define	_CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL
#define	_CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL
#define	CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1)
#define	CMU_ROUTE_LOCATION (0x1UL << 2)
#define	_CMU_ROUTE_LOCATION_SHIFT 2
#define	_CMU_ROUTE_LOCATION_MASK 0x4UL
#define	_CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL
#define	_CMU_ROUTE_LOCATION_LOC0 0x00000000UL
#define	_CMU_ROUTE_LOCATION_LOC1 0x00000001UL
#define	CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2)
#define	CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2)
#define	CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2)
#define	_CMU_LOCK_RESETVALUE 0x00000000UL
#define	_CMU_LOCK_MASK 0x0000FFFFUL
#define	_CMU_LOCK_LOCKKEY_SHIFT 0
#define	_CMU_LOCK_LOCKKEY_MASK 0xFFFFUL
#define	_CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL
#define	_CMU_LOCK_LOCKKEY_LOCK 0x00000000UL
#define	_CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL
#define	_CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL
#define	_CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL
#define	CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0)
#define	CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0)
#define	CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0)
#define	CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0)
#define	CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0)
#define	_AES_CTRL_RESETVALUE 0x00000000UL
#define	_AES_CTRL_MASK 0x00000037UL
#define	AES_CTRL_DECRYPT (0x1UL << 0)
#define	_AES_CTRL_DECRYPT_SHIFT 0
#define	_AES_CTRL_DECRYPT_MASK 0x1UL
#define	_AES_CTRL_DECRYPT_DEFAULT 0x00000000UL
#define	AES_CTRL_DECRYPT_DEFAULT (_AES_CTRL_DECRYPT_DEFAULT << 0)
#define	AES_CTRL_AES256 (0x1UL << 1)
#define	_AES_CTRL_AES256_SHIFT 1
#define	_AES_CTRL_AES256_MASK 0x2UL
#define	_AES_CTRL_AES256_DEFAULT 0x00000000UL
#define	AES_CTRL_AES256_DEFAULT (_AES_CTRL_AES256_DEFAULT << 1)
#define	AES_CTRL_KEYBUFEN (0x1UL << 2)
#define	_AES_CTRL_KEYBUFEN_SHIFT 2
#define	_AES_CTRL_KEYBUFEN_MASK 0x4UL
#define	_AES_CTRL_KEYBUFEN_DEFAULT 0x00000000UL
#define	AES_CTRL_KEYBUFEN_DEFAULT (_AES_CTRL_KEYBUFEN_DEFAULT << 2)
#define	AES_CTRL_DATASTART (0x1UL << 4)
#define	_AES_CTRL_DATASTART_SHIFT 4
#define	_AES_CTRL_DATASTART_MASK 0x10UL
#define	_AES_CTRL_DATASTART_DEFAULT 0x00000000UL
#define	AES_CTRL_DATASTART_DEFAULT (_AES_CTRL_DATASTART_DEFAULT << 4)
#define	AES_CTRL_XORSTART (0x1UL << 5)
#define	_AES_CTRL_XORSTART_SHIFT 5
#define	_AES_CTRL_XORSTART_MASK 0x20UL
#define	_AES_CTRL_XORSTART_DEFAULT 0x00000000UL
#define	AES_CTRL_XORSTART_DEFAULT (_AES_CTRL_XORSTART_DEFAULT << 5)
#define	_AES_CMD_RESETVALUE 0x00000000UL
#define	_AES_CMD_MASK 0x00000003UL
#define	AES_CMD_START (0x1UL << 0)
#define	_AES_CMD_START_SHIFT 0
#define	_AES_CMD_START_MASK 0x1UL
#define	_AES_CMD_START_DEFAULT 0x00000000UL
#define	AES_CMD_START_DEFAULT (_AES_CMD_START_DEFAULT << 0)
#define	AES_CMD_STOP (0x1UL << 1)
#define	_AES_CMD_STOP_SHIFT 1
#define	_AES_CMD_STOP_MASK 0x2UL
#define	_AES_CMD_STOP_DEFAULT 0x00000000UL
#define	AES_CMD_STOP_DEFAULT (_AES_CMD_STOP_DEFAULT << 1)
#define	_AES_STATUS_RESETVALUE 0x00000000UL
#define	_AES_STATUS_MASK 0x00000001UL
#define	AES_STATUS_RUNNING (0x1UL << 0)
#define	_AES_STATUS_RUNNING_SHIFT 0
#define	_AES_STATUS_RUNNING_MASK 0x1UL
#define	_AES_STATUS_RUNNING_DEFAULT 0x00000000UL
#define	AES_STATUS_RUNNING_DEFAULT (_AES_STATUS_RUNNING_DEFAULT << 0)
#define	_AES_IEN_RESETVALUE 0x00000000UL
#define	_AES_IEN_MASK 0x00000001UL
#define	AES_IEN_DONE (0x1UL << 0)
#define	_AES_IEN_DONE_SHIFT 0
#define	_AES_IEN_DONE_MASK 0x1UL
#define	_AES_IEN_DONE_DEFAULT 0x00000000UL
#define	AES_IEN_DONE_DEFAULT (_AES_IEN_DONE_DEFAULT << 0)
#define	_AES_IF_RESETVALUE 0x00000000UL
#define	_AES_IF_MASK 0x00000001UL
#define	AES_IF_DONE (0x1UL << 0)
#define	_AES_IF_DONE_SHIFT 0
#define	_AES_IF_DONE_MASK 0x1UL
#define	_AES_IF_DONE_DEFAULT 0x00000000UL
#define	AES_IF_DONE_DEFAULT (_AES_IF_DONE_DEFAULT << 0)
#define	_AES_IFS_RESETVALUE 0x00000000UL
#define	_AES_IFS_MASK 0x00000001UL
#define	AES_IFS_DONE (0x1UL << 0)
#define	_AES_IFS_DONE_SHIFT 0
#define	_AES_IFS_DONE_MASK 0x1UL
#define	_AES_IFS_DONE_DEFAULT 0x00000000UL
#define	AES_IFS_DONE_DEFAULT (_AES_IFS_DONE_DEFAULT << 0)
#define	_AES_IFC_RESETVALUE 0x00000000UL
#define	_AES_IFC_MASK 0x00000001UL
#define	AES_IFC_DONE (0x1UL << 0)
#define	_AES_IFC_DONE_SHIFT 0
#define	_AES_IFC_DONE_MASK 0x1UL
#define	_AES_IFC_DONE_DEFAULT 0x00000000UL
#define	AES_IFC_DONE_DEFAULT (_AES_IFC_DONE_DEFAULT << 0)
#define	_AES_DATA_RESETVALUE 0x00000000UL
#define	_AES_DATA_MASK 0xFFFFFFFFUL
#define	_AES_DATA_DATA_SHIFT 0
#define	_AES_DATA_DATA_MASK 0xFFFFFFFFUL
#define	_AES_DATA_DATA_DEFAULT 0x00000000UL
#define	AES_DATA_DATA_DEFAULT (_AES_DATA_DATA_DEFAULT << 0)
#define	_AES_XORDATA_RESETVALUE 0x00000000UL
#define	_AES_XORDATA_MASK 0xFFFFFFFFUL
#define	_AES_XORDATA_XORDATA_SHIFT 0
#define	_AES_XORDATA_XORDATA_MASK 0xFFFFFFFFUL
#define	_AES_XORDATA_XORDATA_DEFAULT 0x00000000UL
#define	AES_XORDATA_XORDATA_DEFAULT (_AES_XORDATA_XORDATA_DEFAULT << 0)
#define	_AES_KEYLA_RESETVALUE 0x00000000UL
#define	_AES_KEYLA_MASK 0xFFFFFFFFUL
#define	_AES_KEYLA_KEYLA_SHIFT 0
#define	_AES_KEYLA_KEYLA_MASK 0xFFFFFFFFUL
#define	_AES_KEYLA_KEYLA_DEFAULT 0x00000000UL
#define	AES_KEYLA_KEYLA_DEFAULT (_AES_KEYLA_KEYLA_DEFAULT << 0)
#define	_AES_KEYLB_RESETVALUE 0x00000000UL
#define	_AES_KEYLB_MASK 0xFFFFFFFFUL
#define	_AES_KEYLB_KEYLB_SHIFT 0
#define	_AES_KEYLB_KEYLB_MASK 0xFFFFFFFFUL
#define	_AES_KEYLB_KEYLB_DEFAULT 0x00000000UL
#define	AES_KEYLB_KEYLB_DEFAULT (_AES_KEYLB_KEYLB_DEFAULT << 0)
#define	_AES_KEYLC_RESETVALUE 0x00000000UL
#define	_AES_KEYLC_MASK 0xFFFFFFFFUL
#define	_AES_KEYLC_KEYLC_SHIFT 0
#define	_AES_KEYLC_KEYLC_MASK 0xFFFFFFFFUL
#define	_AES_KEYLC_KEYLC_DEFAULT 0x00000000UL
#define	AES_KEYLC_KEYLC_DEFAULT (_AES_KEYLC_KEYLC_DEFAULT << 0)
#define	_AES_KEYLD_RESETVALUE 0x00000000UL
#define	_AES_KEYLD_MASK 0xFFFFFFFFUL
#define	_AES_KEYLD_KEYLD_SHIFT 0
#define	_AES_KEYLD_KEYLD_MASK 0xFFFFFFFFUL
#define	_AES_KEYLD_KEYLD_DEFAULT 0x00000000UL
#define	AES_KEYLD_KEYLD_DEFAULT (_AES_KEYLD_KEYLD_DEFAULT << 0)
#define	_AES_KEYHA_RESETVALUE 0x00000000UL
#define	_AES_KEYHA_MASK 0xFFFFFFFFUL
#define	_AES_KEYHA_KEYHA_SHIFT 0
#define	_AES_KEYHA_KEYHA_MASK 0xFFFFFFFFUL
#define	_AES_KEYHA_KEYHA_DEFAULT 0x00000000UL
#define	AES_KEYHA_KEYHA_DEFAULT (_AES_KEYHA_KEYHA_DEFAULT << 0)
#define	_AES_KEYHB_RESETVALUE 0x00000000UL
#define	_AES_KEYHB_MASK 0xFFFFFFFFUL
#define	_AES_KEYHB_KEYHB_SHIFT 0
#define	_AES_KEYHB_KEYHB_MASK 0xFFFFFFFFUL
#define	_AES_KEYHB_KEYHB_DEFAULT 0x00000000UL
#define	AES_KEYHB_KEYHB_DEFAULT (_AES_KEYHB_KEYHB_DEFAULT << 0)
#define	_AES_KEYHC_RESETVALUE 0x00000000UL
#define	_AES_KEYHC_MASK 0xFFFFFFFFUL
#define	_AES_KEYHC_KEYHC_SHIFT 0
#define	_AES_KEYHC_KEYHC_MASK 0xFFFFFFFFUL
#define	_AES_KEYHC_KEYHC_DEFAULT 0x00000000UL
#define	AES_KEYHC_KEYHC_DEFAULT (_AES_KEYHC_KEYHC_DEFAULT << 0)
#define	_AES_KEYHD_RESETVALUE 0x00000000UL
#define	_AES_KEYHD_MASK 0xFFFFFFFFUL
#define	_AES_KEYHD_KEYHD_SHIFT 0
#define	_AES_KEYHD_KEYHD_MASK 0xFFFFFFFFUL
#define	_AES_KEYHD_KEYHD_DEFAULT 0x00000000UL
#define	AES_KEYHD_KEYHD_DEFAULT (_AES_KEYHD_KEYHD_DEFAULT << 0)
#define	_EBI_CTRL_RESETVALUE 0x00000000UL
#define	_EBI_CTRL_MASK 0x00030F07UL
#define	_EBI_CTRL_MODE_SHIFT 0
#define	_EBI_CTRL_MODE_MASK 0x7UL
#define	_EBI_CTRL_MODE_DEFAULT 0x00000000UL
#define	_EBI_CTRL_MODE_D8A8 0x00000000UL
#define	_EBI_CTRL_MODE_D16A16ALE 0x00000001UL
#define	_EBI_CTRL_MODE_D8A24ALE 0x00000002UL
#define	EBI_CTRL_MODE_DEFAULT (_EBI_CTRL_MODE_DEFAULT << 0)
#define	EBI_CTRL_MODE_D8A8 (_EBI_CTRL_MODE_D8A8 << 0)
#define	EBI_CTRL_MODE_D16A16ALE (_EBI_CTRL_MODE_D16A16ALE << 0)
#define	EBI_CTRL_MODE_D8A24ALE (_EBI_CTRL_MODE_D8A24ALE << 0)
#define	EBI_CTRL_BANK0EN (0x1UL << 8)
#define	_EBI_CTRL_BANK0EN_SHIFT 8
#define	_EBI_CTRL_BANK0EN_MASK 0x100UL
#define	_EBI_CTRL_BANK0EN_DEFAULT 0x00000000UL
#define	EBI_CTRL_BANK0EN_DEFAULT (_EBI_CTRL_BANK0EN_DEFAULT << 8)
#define	EBI_CTRL_BANK1EN (0x1UL << 9)
#define	_EBI_CTRL_BANK1EN_SHIFT 9
#define	_EBI_CTRL_BANK1EN_MASK 0x200UL
#define	_EBI_CTRL_BANK1EN_DEFAULT 0x00000000UL
#define	EBI_CTRL_BANK1EN_DEFAULT (_EBI_CTRL_BANK1EN_DEFAULT << 9)
#define	EBI_CTRL_BANK2EN (0x1UL << 10)
#define	_EBI_CTRL_BANK2EN_SHIFT 10
#define	_EBI_CTRL_BANK2EN_MASK 0x400UL
#define	_EBI_CTRL_BANK2EN_DEFAULT 0x00000000UL
#define	EBI_CTRL_BANK2EN_DEFAULT (_EBI_CTRL_BANK2EN_DEFAULT << 10)
#define	EBI_CTRL_BANK3EN (0x1UL << 11)
#define	_EBI_CTRL_BANK3EN_SHIFT 11
#define	_EBI_CTRL_BANK3EN_MASK 0x800UL
#define	_EBI_CTRL_BANK3EN_DEFAULT 0x00000000UL
#define	EBI_CTRL_BANK3EN_DEFAULT (_EBI_CTRL_BANK3EN_DEFAULT << 11)
#define	EBI_CTRL_ARDYEN (0x1UL << 16)
#define	_EBI_CTRL_ARDYEN_SHIFT 16
#define	_EBI_CTRL_ARDYEN_MASK 0x10000UL
#define	_EBI_CTRL_ARDYEN_DEFAULT 0x00000000UL
#define	EBI_CTRL_ARDYEN_DEFAULT (_EBI_CTRL_ARDYEN_DEFAULT << 16)
#define	EBI_CTRL_ARDYTODIS (0x1UL << 17)
#define	_EBI_CTRL_ARDYTODIS_SHIFT 17
#define	_EBI_CTRL_ARDYTODIS_MASK 0x20000UL
#define	_EBI_CTRL_ARDYTODIS_DEFAULT 0x00000000UL
#define	EBI_CTRL_ARDYTODIS_DEFAULT (_EBI_CTRL_ARDYTODIS_DEFAULT << 17)
#define	_EBI_ADDRTIMING_RESETVALUE 0x00000100UL
#define	_EBI_ADDRTIMING_MASK 0x00000303UL
#define	_EBI_ADDRTIMING_ADDRSETUP_SHIFT 0
#define	_EBI_ADDRTIMING_ADDRSETUP_MASK 0x3UL
#define	_EBI_ADDRTIMING_ADDRSETUP_DEFAULT 0x00000000UL
#define	EBI_ADDRTIMING_ADDRSETUP_DEFAULT (_EBI_ADDRTIMING_ADDRSETUP_DEFAULT << 0)
#define	_EBI_ADDRTIMING_ADDRHOLD_SHIFT 8
#define	_EBI_ADDRTIMING_ADDRHOLD_MASK 0x300UL
#define	_EBI_ADDRTIMING_ADDRHOLD_DEFAULT 0x00000001UL
#define	EBI_ADDRTIMING_ADDRHOLD_DEFAULT (_EBI_ADDRTIMING_ADDRHOLD_DEFAULT << 8)
#define	_EBI_RDTIMING_RESETVALUE 0x00000000UL
#define	_EBI_RDTIMING_MASK 0x00030F03UL
#define	_EBI_RDTIMING_RDSETUP_SHIFT 0
#define	_EBI_RDTIMING_RDSETUP_MASK 0x3UL
#define	_EBI_RDTIMING_RDSETUP_DEFAULT 0x00000000UL
#define	EBI_RDTIMING_RDSETUP_DEFAULT (_EBI_RDTIMING_RDSETUP_DEFAULT << 0)
#define	_EBI_RDTIMING_RDSTRB_SHIFT 8
#define	_EBI_RDTIMING_RDSTRB_MASK 0xF00UL
#define	_EBI_RDTIMING_RDSTRB_DEFAULT 0x00000000UL
#define	EBI_RDTIMING_RDSTRB_DEFAULT (_EBI_RDTIMING_RDSTRB_DEFAULT << 8)
#define	_EBI_RDTIMING_RDHOLD_SHIFT 16
#define	_EBI_RDTIMING_RDHOLD_MASK 0x30000UL
#define	_EBI_RDTIMING_RDHOLD_DEFAULT 0x00000000UL
#define	EBI_RDTIMING_RDHOLD_DEFAULT (_EBI_RDTIMING_RDHOLD_DEFAULT << 16)
#define	_EBI_WRTIMING_RESETVALUE 0x00010000UL
#define	_EBI_WRTIMING_MASK 0x00030F03UL
#define	_EBI_WRTIMING_WRSETUP_SHIFT 0
#define	_EBI_WRTIMING_WRSETUP_MASK 0x3UL
#define	_EBI_WRTIMING_WRSETUP_DEFAULT 0x00000000UL
#define	EBI_WRTIMING_WRSETUP_DEFAULT (_EBI_WRTIMING_WRSETUP_DEFAULT << 0)
#define	_EBI_WRTIMING_WRSTRB_SHIFT 8
#define	_EBI_WRTIMING_WRSTRB_MASK 0xF00UL
#define	_EBI_WRTIMING_WRSTRB_DEFAULT 0x00000000UL
#define	EBI_WRTIMING_WRSTRB_DEFAULT (_EBI_WRTIMING_WRSTRB_DEFAULT << 8)
#define	_EBI_WRTIMING_WRHOLD_SHIFT 16
#define	_EBI_WRTIMING_WRHOLD_MASK 0x30000UL
#define	_EBI_WRTIMING_WRHOLD_DEFAULT 0x00000001UL
#define	EBI_WRTIMING_WRHOLD_DEFAULT (_EBI_WRTIMING_WRHOLD_DEFAULT << 16)
#define	_EBI_POLARITY_RESETVALUE 0x00000000UL
#define	_EBI_POLARITY_MASK 0x0000001FUL
#define	EBI_POLARITY_CSPOL (0x1UL << 0)
#define	_EBI_POLARITY_CSPOL_SHIFT 0
#define	_EBI_POLARITY_CSPOL_MASK 0x1UL
#define	_EBI_POLARITY_CSPOL_DEFAULT 0x00000000UL
#define	_EBI_POLARITY_CSPOL_ACTIVELOW 0x00000000UL
#define	_EBI_POLARITY_CSPOL_ACTIVEHIGH 0x00000001UL
#define	EBI_POLARITY_CSPOL_DEFAULT (_EBI_POLARITY_CSPOL_DEFAULT << 0)
#define	EBI_POLARITY_CSPOL_ACTIVELOW (_EBI_POLARITY_CSPOL_ACTIVELOW << 0)
#define	EBI_POLARITY_CSPOL_ACTIVEHIGH (_EBI_POLARITY_CSPOL_ACTIVEHIGH << 0)
#define	EBI_POLARITY_REPOL (0x1UL << 1)
#define	_EBI_POLARITY_REPOL_SHIFT 1
#define	_EBI_POLARITY_REPOL_MASK 0x2UL
#define	_EBI_POLARITY_REPOL_DEFAULT 0x00000000UL
#define	_EBI_POLARITY_REPOL_ACTIVELOW 0x00000000UL
#define	_EBI_POLARITY_REPOL_ACTIVEHIGH 0x00000001UL
#define	EBI_POLARITY_REPOL_DEFAULT (_EBI_POLARITY_REPOL_DEFAULT << 1)
#define	EBI_POLARITY_REPOL_ACTIVELOW (_EBI_POLARITY_REPOL_ACTIVELOW << 1)
#define	EBI_POLARITY_REPOL_ACTIVEHIGH (_EBI_POLARITY_REPOL_ACTIVEHIGH << 1)
#define	EBI_POLARITY_WEPOL (0x1UL << 2)
#define	_EBI_POLARITY_WEPOL_SHIFT 2
#define	_EBI_POLARITY_WEPOL_MASK 0x4UL
#define	_EBI_POLARITY_WEPOL_DEFAULT 0x00000000UL
#define	_EBI_POLARITY_WEPOL_ACTIVELOW 0x00000000UL
#define	_EBI_POLARITY_WEPOL_ACTIVEHIGH 0x00000001UL
#define	EBI_POLARITY_WEPOL_DEFAULT (_EBI_POLARITY_WEPOL_DEFAULT << 2)
#define	EBI_POLARITY_WEPOL_ACTIVELOW (_EBI_POLARITY_WEPOL_ACTIVELOW << 2)
#define	EBI_POLARITY_WEPOL_ACTIVEHIGH (_EBI_POLARITY_WEPOL_ACTIVEHIGH << 2)
#define	EBI_POLARITY_ALEPOL (0x1UL << 3)
#define	_EBI_POLARITY_ALEPOL_SHIFT 3
#define	_EBI_POLARITY_ALEPOL_MASK 0x8UL
#define	_EBI_POLARITY_ALEPOL_DEFAULT 0x00000000UL
#define	_EBI_POLARITY_ALEPOL_ACTIVELOW 0x00000000UL
#define	_EBI_POLARITY_ALEPOL_ACTIVEHIGH 0x00000001UL
#define	EBI_POLARITY_ALEPOL_DEFAULT (_EBI_POLARITY_ALEPOL_DEFAULT << 3)
#define	EBI_POLARITY_ALEPOL_ACTIVELOW (_EBI_POLARITY_ALEPOL_ACTIVELOW << 3)
#define	EBI_POLARITY_ALEPOL_ACTIVEHIGH (_EBI_POLARITY_ALEPOL_ACTIVEHIGH << 3)
#define	EBI_POLARITY_ARDYPOL (0x1UL << 4)
#define	_EBI_POLARITY_ARDYPOL_SHIFT 4
#define	_EBI_POLARITY_ARDYPOL_MASK 0x10UL
#define	_EBI_POLARITY_ARDYPOL_DEFAULT 0x00000000UL
#define	_EBI_POLARITY_ARDYPOL_ACTIVELOW 0x00000000UL
#define	_EBI_POLARITY_ARDYPOL_ACTIVEHIGH 0x00000001UL
#define	EBI_POLARITY_ARDYPOL_DEFAULT (_EBI_POLARITY_ARDYPOL_DEFAULT << 4)
#define	EBI_POLARITY_ARDYPOL_ACTIVELOW (_EBI_POLARITY_ARDYPOL_ACTIVELOW << 4)
#define	EBI_POLARITY_ARDYPOL_ACTIVEHIGH (_EBI_POLARITY_ARDYPOL_ACTIVEHIGH << 4)
#define	_EBI_ROUTE_RESETVALUE 0x00000000UL
#define	_EBI_ROUTE_MASK 0x0000007FUL
#define	EBI_ROUTE_EBIPEN (0x1UL << 0)
#define	_EBI_ROUTE_EBIPEN_SHIFT 0
#define	_EBI_ROUTE_EBIPEN_MASK 0x1UL
#define	_EBI_ROUTE_EBIPEN_DEFAULT 0x00000000UL
#define	EBI_ROUTE_EBIPEN_DEFAULT (_EBI_ROUTE_EBIPEN_DEFAULT << 0)
#define	EBI_ROUTE_CS0PEN (0x1UL << 1)
#define	_EBI_ROUTE_CS0PEN_SHIFT 1
#define	_EBI_ROUTE_CS0PEN_MASK 0x2UL
#define	_EBI_ROUTE_CS0PEN_DEFAULT 0x00000000UL
#define	EBI_ROUTE_CS0PEN_DEFAULT (_EBI_ROUTE_CS0PEN_DEFAULT << 1)
#define	EBI_ROUTE_CS1PEN (0x1UL << 2)
#define	_EBI_ROUTE_CS1PEN_SHIFT 2
#define	_EBI_ROUTE_CS1PEN_MASK 0x4UL
#define	_EBI_ROUTE_CS1PEN_DEFAULT 0x00000000UL
#define	EBI_ROUTE_CS1PEN_DEFAULT (_EBI_ROUTE_CS1PEN_DEFAULT << 2)
#define	EBI_ROUTE_CS2PEN (0x1UL << 3)
#define	_EBI_ROUTE_CS2PEN_SHIFT 3
#define	_EBI_ROUTE_CS2PEN_MASK 0x8UL
#define	_EBI_ROUTE_CS2PEN_DEFAULT 0x00000000UL
#define	EBI_ROUTE_CS2PEN_DEFAULT (_EBI_ROUTE_CS2PEN_DEFAULT << 3)
#define	EBI_ROUTE_CS3PEN (0x1UL << 4)
#define	_EBI_ROUTE_CS3PEN_SHIFT 4
#define	_EBI_ROUTE_CS3PEN_MASK 0x10UL
#define	_EBI_ROUTE_CS3PEN_DEFAULT 0x00000000UL
#define	EBI_ROUTE_CS3PEN_DEFAULT (_EBI_ROUTE_CS3PEN_DEFAULT << 4)
#define	EBI_ROUTE_ALEPEN (0x1UL << 5)
#define	_EBI_ROUTE_ALEPEN_SHIFT 5
#define	_EBI_ROUTE_ALEPEN_MASK 0x20UL
#define	_EBI_ROUTE_ALEPEN_DEFAULT 0x00000000UL
#define	EBI_ROUTE_ALEPEN_DEFAULT (_EBI_ROUTE_ALEPEN_DEFAULT << 5)
#define	EBI_ROUTE_ARDYPEN (0x1UL << 6)
#define	_EBI_ROUTE_ARDYPEN_SHIFT 6
#define	_EBI_ROUTE_ARDYPEN_MASK 0x40UL
#define	_EBI_ROUTE_ARDYPEN_DEFAULT 0x00000000UL
#define	EBI_ROUTE_ARDYPEN_DEFAULT (_EBI_ROUTE_ARDYPEN_DEFAULT << 6)
#define	_GPIO_P_CTRL_RESETVALUE 0x00000000UL
#define	_GPIO_P_CTRL_MASK 0x00000003UL
#define	_GPIO_P_CTRL_DRIVEMODE_SHIFT 0
#define	_GPIO_P_CTRL_DRIVEMODE_MASK 0x3UL
#define	_GPIO_P_CTRL_DRIVEMODE_DEFAULT 0x00000000UL
#define	_GPIO_P_CTRL_DRIVEMODE_STANDARD 0x00000000UL
#define	_GPIO_P_CTRL_DRIVEMODE_LOWEST 0x00000001UL
#define	_GPIO_P_CTRL_DRIVEMODE_HIGH 0x00000002UL
#define	_GPIO_P_CTRL_DRIVEMODE_LOW 0x00000003UL
#define	GPIO_P_CTRL_DRIVEMODE_DEFAULT (_GPIO_P_CTRL_DRIVEMODE_DEFAULT << 0)
#define	GPIO_P_CTRL_DRIVEMODE_STANDARD (_GPIO_P_CTRL_DRIVEMODE_STANDARD << 0)
#define	GPIO_P_CTRL_DRIVEMODE_LOWEST (_GPIO_P_CTRL_DRIVEMODE_LOWEST << 0)
#define	GPIO_P_CTRL_DRIVEMODE_HIGH (_GPIO_P_CTRL_DRIVEMODE_HIGH << 0)
#define	GPIO_P_CTRL_DRIVEMODE_LOW (_GPIO_P_CTRL_DRIVEMODE_LOW << 0)
#define	_GPIO_P_MODEL_RESETVALUE 0x00000000UL
#define	_GPIO_P_MODEL_MASK 0xFFFFFFFFUL
#define	_GPIO_P_MODEL_MODE0_SHIFT 0
#define	_GPIO_P_MODEL_MODE0_MASK 0xFUL
#define	_GPIO_P_MODEL_MODE0_DEFAULT 0x00000000UL
#define	_GPIO_P_MODEL_MODE0_DISABLED 0x00000000UL
#define	_GPIO_P_MODEL_MODE0_INPUT 0x00000001UL
#define	_GPIO_P_MODEL_MODE0_INPUTPULL 0x00000002UL
#define	_GPIO_P_MODEL_MODE0_INPUTPULLFILTER 0x00000003UL
#define	_GPIO_P_MODEL_MODE0_PUSHPULL 0x00000004UL
#define	_GPIO_P_MODEL_MODE0_PUSHPULLDRIVE 0x00000005UL
#define	_GPIO_P_MODEL_MODE0_WIREDOR 0x00000006UL
#define	_GPIO_P_MODEL_MODE0_WIREDORPULLDOWN 0x00000007UL
#define	_GPIO_P_MODEL_MODE0_WIREDAND 0x00000008UL
#define	_GPIO_P_MODEL_MODE0_WIREDANDFILTER 0x00000009UL
#define	_GPIO_P_MODEL_MODE0_WIREDANDPULLUP 0x0000000AUL
#define	_GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL
#define	_GPIO_P_MODEL_MODE0_WIREDANDDRIVE 0x0000000CUL
#define	_GPIO_P_MODEL_MODE0_WIREDANDDRIVEFILTER 0x0000000DUL
#define	_GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUP 0x0000000EUL
#define	_GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL
#define	GPIO_P_MODEL_MODE0_DEFAULT (_GPIO_P_MODEL_MODE0_DEFAULT << 0)
#define	GPIO_P_MODEL_MODE0_DISABLED (_GPIO_P_MODEL_MODE0_DISABLED << 0)
#define	GPIO_P_MODEL_MODE0_INPUT (_GPIO_P_MODEL_MODE0_INPUT << 0)
#define	GPIO_P_MODEL_MODE0_INPUTPULL (_GPIO_P_MODEL_MODE0_INPUTPULL << 0)
#define	GPIO_P_MODEL_MODE0_INPUTPULLFILTER (_GPIO_P_MODEL_MODE0_INPUTPULLFILTER << 0)
#define	GPIO_P_MODEL_MODE0_PUSHPULL (_GPIO_P_MODEL_MODE0_PUSHPULL << 0)
#define	GPIO_P_MODEL_MODE0_PUSHPULLDRIVE (_GPIO_P_MODEL_MODE0_PUSHPULLDRIVE << 0)
#define	GPIO_P_MODEL_MODE0_WIREDOR (_GPIO_P_MODEL_MODE0_WIREDOR << 0)
#define	GPIO_P_MODEL_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE0_WIREDORPULLDOWN << 0)
#define	GPIO_P_MODEL_MODE0_WIREDAND (_GPIO_P_MODEL_MODE0_WIREDAND << 0)
#define	GPIO_P_MODEL_MODE0_WIREDANDFILTER (_GPIO_P_MODEL_MODE0_WIREDANDFILTER << 0)
#define	GPIO_P_MODEL_MODE0_WIREDANDPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDPULLUP << 0)
#define	GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER << 0)
#define	GPIO_P_MODEL_MODE0_WIREDANDDRIVE (_GPIO_P_MODEL_MODE0_WIREDANDDRIVE << 0)
#define	GPIO_P_MODEL_MODE0_WIREDANDDRIVEFILTER (_GPIO_P_MODEL_MODE0_WIREDANDDRIVEFILTER << 0)
#define	GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUP << 0)
#define	GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUPFILTER << 0)
#define	_GPIO_P_MODEL_MODE1_SHIFT 4
#define	_GPIO_P_MODEL_MODE1_MASK 0xF0UL
#define	_GPIO_P_MODEL_MODE1_DEFAULT 0x00000000UL
#define	_GPIO_P_MODEL_MODE1_DISABLED 0x00000000UL
#define	_GPIO_P_MODEL_MODE1_INPUT 0x00000001UL
#define	_GPIO_P_MODEL_MODE1_INPUTPULL 0x00000002UL
#define	_GPIO_P_MODEL_MODE1_INPUTPULLFILTER 0x00000003UL
#define	_GPIO_P_MODEL_MODE1_PUSHPULL 0x00000004UL
#define	_GPIO_P_MODEL_MODE1_PUSHPULLDRIVE 0x00000005UL
#define	_GPIO_P_MODEL_MODE1_WIREDOR 0x00000006UL
#define	_GPIO_P_MODEL_MODE1_WIREDORPULLDOWN 0x00000007UL
#define	_GPIO_P_MODEL_MODE1_WIREDAND 0x00000008UL
#define	_GPIO_P_MODEL_MODE1_WIREDANDFILTER 0x00000009UL
#define	_GPIO_P_MODEL_MODE1_WIREDANDPULLUP 0x0000000AUL
#define	_GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER 0x0000000BUL
#define	_GPIO_P_MODEL_MODE1_WIREDANDDRIVE 0x0000000CUL
#define	_GPIO_P_MODEL_MODE1_WIREDANDDRIVEFILTER 0x0000000DUL
#define	_GPIO_P_MODEL_MODE1_WIREDANDDRIVEPULLUP 0x0000000EUL
#define	_GPIO_P_MODEL_MODE1_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL
#define	GPIO_P_MODEL_MODE1_DEFAULT (_GPIO_P_MODEL_MODE1_DEFAULT << 4)
#define	GPIO_P_MODEL_MODE1_DISABLED (_GPIO_P_MODEL_MODE1_DISABLED << 4)
#define	GPIO_P_MODEL_MODE1_INPUT (_GPIO_P_MODEL_MODE1_INPUT << 4)
#define	GPIO_P_MODEL_MODE1_INPUTPULL (_GPIO_P_MODEL_MODE1_INPUTPULL << 4)
#define	GPIO_P_MODEL_MODE1_INPUTPULLFILTER (_GPIO_P_MODEL_MODE1_INPUTPULLFILTER << 4)
#define	GPIO_P_MODEL_MODE1_PUSHPULL (_GPIO_P_MODEL_MODE1_PUSHPULL << 4)
#define	GPIO_P_MODEL_MODE1_PUSHPULLDRIVE (_GPIO_P_MODEL_MODE1_PUSHPULLDRIVE << 4)
#define	GPIO_P_MODEL_MODE1_WIREDOR (_GPIO_P_MODEL_MODE1_WIREDOR << 4)
#define	GPIO_P_MODEL_MODE1_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE1_WIREDORPULLDOWN << 4)
#define	GPIO_P_MODEL_MODE1_WIREDAND (_GPIO_P_MODEL_MODE1_WIREDAND << 4)
#define	GPIO_P_MODEL_MODE1_WIREDANDFILTER (_GPIO_P_MODEL_MODE1_WIREDANDFILTER << 4)
#define	GPIO_P_MODEL_MODE1_WIREDANDPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDPULLUP << 4)
#define	GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER << 4)
#define	GPIO_P_MODEL_MODE1_WIREDANDDRIVE (_GPIO_P_MODEL_MODE1_WIREDANDDRIVE << 4)
#define	GPIO_P_MODEL_MODE1_WIREDANDDRIVEFILTER (_GPIO_P_MODEL_MODE1_WIREDANDDRIVEFILTER << 4)
#define	GPIO_P_MODEL_MODE1_WIREDANDDRIVEPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDDRIVEPULLUP << 4)
#define	GPIO_P_MODEL_MODE1_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDDRIVEPULLUPFILTER << 4)
#define	_GPIO_P_MODEL_MODE2_SHIFT 8
#define	_GPIO_P_MODEL_MODE2_MASK 0xF00UL
#define	_GPIO_P_MODEL_MODE2_DEFAULT 0x00000000UL
#define	_GPIO_P_MODEL_MODE2_DISABLED 0x00000000UL
#define	_GPIO_P_MODEL_MODE2_INPUT 0x00000001UL
#define	_GPIO_P_MODEL_MODE2_INPUTPULL 0x00000002UL
#define	_GPIO_P_MODEL_MODE2_INPUTPULLFILTER 0x00000003UL
#define	_GPIO_P_MODEL_MODE2_PUSHPULL 0x00000004UL
#define	_GPIO_P_MODEL_MODE2_PUSHPULLDRIVE 0x00000005UL
#define	_GPIO_P_MODEL_MODE2_WIREDOR 0x00000006UL
#define	_GPIO_P_MODEL_MODE2_WIREDORPULLDOWN 0x00000007UL
#define	_GPIO_P_MODEL_MODE2_WIREDAND 0x00000008UL
#define	_GPIO_P_MODEL_MODE2_WIREDANDFILTER 0x00000009UL
#define	_GPIO_P_MODEL_MODE2_WIREDANDPULLUP 0x0000000AUL
#define	_GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER 0x0000000BUL
#define	_GPIO_P_MODEL_MODE2_WIREDANDDRIVE 0x0000000CUL
#define	_GPIO_P_MODEL_MODE2_WIREDANDDRIVEFILTER 0x0000000DUL
#define	_GPIO_P_MODEL_MODE2_WIREDANDDRIVEPULLUP 0x0000000EUL
#define	_GPIO_P_MODEL_MODE2_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL
#define	GPIO_P_MODEL_MODE2_DEFAULT (_GPIO_P_MODEL_MODE2_DEFAULT << 8)
#define	GPIO_P_MODEL_MODE2_DISABLED (_GPIO_P_MODEL_MODE2_DISABLED << 8)
#define	GPIO_P_MODEL_MODE2_INPUT (_GPIO_P_MODEL_MODE2_INPUT << 8)
#define	GPIO_P_MODEL_MODE2_INPUTPULL (_GPIO_P_MODEL_MODE2_INPUTPULL << 8)
#define	GPIO_P_MODEL_MODE2_INPUTPULLFILTER (_GPIO_P_MODEL_MODE2_INPUTPULLFILTER << 8)
#define	GPIO_P_MODEL_MODE2_PUSHPULL (_GPIO_P_MODEL_MODE2_PUSHPULL << 8)
#define	GPIO_P_MODEL_MODE2_PUSHPULLDRIVE (_GPIO_P_MODEL_MODE2_PUSHPULLDRIVE << 8)
#define	GPIO_P_MODEL_MODE2_WIREDOR (_GPIO_P_MODEL_MODE2_WIREDOR << 8)
#define	GPIO_P_MODEL_MODE2_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE2_WIREDORPULLDOWN << 8)
#define	GPIO_P_MODEL_MODE2_WIREDAND (_GPIO_P_MODEL_MODE2_WIREDAND << 8)
#define	GPIO_P_MODEL_MODE2_WIREDANDFILTER (_GPIO_P_MODEL_MODE2_WIREDANDFILTER << 8)
#define	GPIO_P_MODEL_MODE2_WIREDANDPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDPULLUP << 8)
#define	GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER << 8)
#define	GPIO_P_MODEL_MODE2_WIREDANDDRIVE (_GPIO_P_MODEL_MODE2_WIREDANDDRIVE << 8)
#define	GPIO_P_MODEL_MODE2_WIREDANDDRIVEFILTER (_GPIO_P_MODEL_MODE2_WIREDANDDRIVEFILTER << 8)
#define	GPIO_P_MODEL_MODE2_WIREDANDDRIVEPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDDRIVEPULLUP << 8)
#define	GPIO_P_MODEL_MODE2_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDDRIVEPULLUPFILTER << 8)
#define	_GPIO_P_MODEL_MODE3_SHIFT 12
#define	_GPIO_P_MODEL_MODE3_MASK 0xF000UL
#define	_GPIO_P_MODEL_MODE3_DEFAULT 0x00000000UL
#define	_GPIO_P_MODEL_MODE3_DISABLED 0x00000000UL
#define	_GPIO_P_MODEL_MODE3_INPUT 0x00000001UL
#define	_GPIO_P_MODEL_MODE3_INPUTPULL 0x00000002UL
#define	_GPIO_P_MODEL_MODE3_INPUTPULLFILTER 0x00000003UL
#define	_GPIO_P_MODEL_MODE3_PUSHPULL 0x00000004UL
#define	_GPIO_P_MODEL_MODE3_PUSHPULLDRIVE 0x00000005UL
#define	_GPIO_P_MODEL_MODE3_WIREDOR 0x00000006UL
#define	_GPIO_P_MODEL_MODE3_WIREDORPULLDOWN 0x00000007UL
#define	_GPIO_P_MODEL_MODE3_WIREDAND 0x00000008UL
#define	_GPIO_P_MODEL_MODE3_WIREDANDFILTER 0x00000009UL
#define	_GPIO_P_MODEL_MODE3_WIREDANDPULLUP 0x0000000AUL
#define	_GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER 0x0000000BUL
#define	_GPIO_P_MODEL_MODE3_WIREDANDDRIVE 0x0000000CUL
#define	_GPIO_P_MODEL_MODE3_WIREDANDDRIVEFILTER 0x0000000DUL
#define	_GPIO_P_MODEL_MODE3_WIREDANDDRIVEPULLUP 0x0000000EUL
#define	_GPIO_P_MODEL_MODE3_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL
#define	GPIO_P_MODEL_MODE3_DEFAULT (_GPIO_P_MODEL_MODE3_DEFAULT << 12)
#define	GPIO_P_MODEL_MODE3_DISABLED (_GPIO_P_MODEL_MODE3_DISABLED << 12)
#define	GPIO_P_MODEL_MODE3_INPUT (_GPIO_P_MODEL_MODE3_INPUT << 12)
#define	GPIO_P_MODEL_MODE3_INPUTPULL (_GPIO_P_MODEL_MODE3_INPUTPULL << 12)
#define	GPIO_P_MODEL_MODE3_INPUTPULLFILTER (_GPIO_P_MODEL_MODE3_INPUTPULLFILTER << 12)
#define	GPIO_P_MODEL_MODE3_PUSHPULL (_GPIO_P_MODEL_MODE3_PUSHPULL << 12)
#define	GPIO_P_MODEL_MODE3_PUSHPULLDRIVE (_GPIO_P_MODEL_MODE3_PUSHPULLDRIVE << 12)
#define	GPIO_P_MODEL_MODE3_WIREDOR (_GPIO_P_MODEL_MODE3_WIREDOR << 12)
#define	GPIO_P_MODEL_MODE3_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE3_WIREDORPULLDOWN << 12)
#define	GPIO_P_MODEL_MODE3_WIREDAND (_GPIO_P_MODEL_MODE3_WIREDAND << 12)
#define	GPIO_P_MODEL_MODE3_WIREDANDFILTER (_GPIO_P_MODEL_MODE3_WIREDANDFILTER << 12)
#define	GPIO_P_MODEL_MODE3_WIREDANDPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDPULLUP << 12)
#define	GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER << 12)
#define	GPIO_P_MODEL_MODE3_WIREDANDDRIVE (_GPIO_P_MODEL_MODE3_WIREDANDDRIVE << 12)
#define	GPIO_P_MODEL_MODE3_WIREDANDDRIVEFILTER (_GPIO_P_MODEL_MODE3_WIREDANDDRIVEFILTER << 12)
#define	GPIO_P_MODEL_MODE3_WIREDANDDRIVEPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDDRIVEPULLUP << 12)
#define	GPIO_P_MODEL_MODE3_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDDRIVEPULLUPFILTER << 12)
#define	_GPIO_P_MODEL_MODE4_SHIFT 16
#define	_GPIO_P_MODEL_MODE4_MASK 0xF0000UL
#define	_GPIO_P_MODEL_MODE4_DEFAULT 0x00000000UL
#define	_GPIO_P_MODEL_MODE4_DISABLED 0x00000000UL
#define	_GPIO_P_MODEL_MODE4_INPUT 0x00000001UL
#define	_GPIO_P_MODEL_MODE4_INPUTPULL 0x00000002UL
#define	_GPIO_P_MODEL_MODE4_INPUTPULLFILTER 0x00000003UL
#define	_GPIO_P_MODEL_MODE4_PUSHPULL 0x00000004UL
#define	_GPIO_P_MODEL_MODE4_PUSHPULLDRIVE 0x00000005UL
#define	_GPIO_P_MODEL_MODE4_WIREDOR 0x00000006UL
#define	_GPIO_P_MODEL_MODE4_WIREDORPULLDOWN 0x00000007UL
#define	_GPIO_P_MODEL_MODE4_WIREDAND 0x00000008UL
#define	_GPIO_P_MODEL_MODE4_WIREDANDFILTER 0x00000009UL
#define	_GPIO_P_MODEL_MODE4_WIREDANDPULLUP 0x0000000AUL
#define	_GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER 0x0000000BUL
#define	_GPIO_P_MODEL_MODE4_WIREDANDDRIVE 0x0000000CUL
#define	_GPIO_P_MODEL_MODE4_WIREDANDDRIVEFILTER 0x0000000DUL
#define	_GPIO_P_MODEL_MODE4_WIREDANDDRIVEPULLUP 0x0000000EUL
#define	_GPIO_P_MODEL_MODE4_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL
#define	GPIO_P_MODEL_MODE4_DEFAULT (_GPIO_P_MODEL_MODE4_DEFAULT << 16)
#define	GPIO_P_MODEL_MODE4_DISABLED (_GPIO_P_MODEL_MODE4_DISABLED << 16)
#define	GPIO_P_MODEL_MODE4_INPUT (_GPIO_P_MODEL_MODE4_INPUT << 16)
#define	GPIO_P_MODEL_MODE4_INPUTPULL (_GPIO_P_MODEL_MODE4_INPUTPULL << 16)
#define	GPIO_P_MODEL_MODE4_INPUTPULLFILTER (_GPIO_P_MODEL_MODE4_INPUTPULLFILTER << 16)
#define	GPIO_P_MODEL_MODE4_PUSHPULL (_GPIO_P_MODEL_MODE4_PUSHPULL << 16)
#define	GPIO_P_MODEL_MODE4_PUSHPULLDRIVE (_GPIO_P_MODEL_MODE4_PUSHPULLDRIVE << 16)
#define	GPIO_P_MODEL_MODE4_WIREDOR (_GPIO_P_MODEL_MODE4_WIREDOR << 16)
#define	GPIO_P_MODEL_MODE4_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE4_WIREDORPULLDOWN << 16)
#define	GPIO_P_MODEL_MODE4_WIREDAND (_GPIO_P_MODEL_MODE4_WIREDAND << 16)
#define	GPIO_P_MODEL_MODE4_WIREDANDFILTER (_GPIO_P_MODEL_MODE4_WIREDANDFILTER << 16)
#define	GPIO_P_MODEL_MODE4_WIREDANDPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDPULLUP << 16)
#define	GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER << 16)
#define	GPIO_P_MODEL_MODE4_WIREDANDDRIVE (_GPIO_P_MODEL_MODE4_WIREDANDDRIVE << 16)
#define	GPIO_P_MODEL_MODE4_WIREDANDDRIVEFILTER (_GPIO_P_MODEL_MODE4_WIREDANDDRIVEFILTER << 16)
#define	GPIO_P_MODEL_MODE4_WIREDANDDRIVEPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDDRIVEPULLUP << 16)
#define	GPIO_P_MODEL_MODE4_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDDRIVEPULLUPFILTER << 16)
#define	_GPIO_P_MODEL_MODE5_SHIFT 20
#define	_GPIO_P_MODEL_MODE5_MASK 0xF00000UL
#define	_GPIO_P_MODEL_MODE5_DEFAULT 0x00000000UL
#define	_GPIO_P_MODEL_MODE5_DISABLED 0x00000000UL
#define	_GPIO_P_MODEL_MODE5_INPUT 0x00000001UL
#define	_GPIO_P_MODEL_MODE5_INPUTPULL 0x00000002UL
#define	_GPIO_P_MODEL_MODE5_INPUTPULLFILTER 0x00000003UL
#define	_GPIO_P_MODEL_MODE5_PUSHPULL 0x00000004UL
#define	_GPIO_P_MODEL_MODE5_PUSHPULLDRIVE 0x00000005UL
#define	_GPIO_P_MODEL_MODE5_WIREDOR 0x00000006UL
#define	_GPIO_P_MODEL_MODE5_WIREDORPULLDOWN 0x00000007UL
#define	_GPIO_P_MODEL_MODE5_WIREDAND 0x00000008UL
#define	_GPIO_P_MODEL_MODE5_WIREDANDFILTER 0x00000009UL
#define	_GPIO_P_MODEL_MODE5_WIREDANDPULLUP 0x0000000AUL
#define	_GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER 0x0000000BUL
#define	_GPIO_P_MODEL_MODE5_WIREDANDDRIVE 0x0000000CUL
#define	_GPIO_P_MODEL_MODE5_WIREDANDDRIVEFILTER 0x0000000DUL
#define	_GPIO_P_MODEL_MODE5_WIREDANDDRIVEPULLUP 0x0000000EUL
#define	_GPIO_P_MODEL_MODE5_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL
#define	GPIO_P_MODEL_MODE5_DEFAULT (_GPIO_P_MODEL_MODE5_DEFAULT << 20)
#define	GPIO_P_MODEL_MODE5_DISABLED (_GPIO_P_MODEL_MODE5_DISABLED << 20)
#define	GPIO_P_MODEL_MODE5_INPUT (_GPIO_P_MODEL_MODE5_INPUT << 20)
#define	GPIO_P_MODEL_MODE5_INPUTPULL (_GPIO_P_MODEL_MODE5_INPUTPULL << 20)
#define	GPIO_P_MODEL_MODE5_INPUTPULLFILTER (_GPIO_P_MODEL_MODE5_INPUTPULLFILTER << 20)
#define	GPIO_P_MODEL_MODE5_PUSHPULL (_GPIO_P_MODEL_MODE5_PUSHPULL << 20)
#define	GPIO_P_MODEL_MODE5_PUSHPULLDRIVE (_GPIO_P_MODEL_MODE5_PUSHPULLDRIVE << 20)
#define	GPIO_P_MODEL_MODE5_WIREDOR (_GPIO_P_MODEL_MODE5_WIREDOR << 20)
#define	GPIO_P_MODEL_MODE5_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE5_WIREDORPULLDOWN << 20)
#define	GPIO_P_MODEL_MODE5_WIREDAND (_GPIO_P_MODEL_MODE5_WIREDAND << 20)
#define	GPIO_P_MODEL_MODE5_WIREDANDFILTER (_GPIO_P_MODEL_MODE5_WIREDANDFILTER << 20)
#define	GPIO_P_MODEL_MODE5_WIREDANDPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDPULLUP << 20)
#define	GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER << 20)
#define	GPIO_P_MODEL_MODE5_WIREDANDDRIVE (_GPIO_P_MODEL_MODE5_WIREDANDDRIVE << 20)
#define	GPIO_P_MODEL_MODE5_WIREDANDDRIVEFILTER (_GPIO_P_MODEL_MODE5_WIREDANDDRIVEFILTER << 20)
#define	GPIO_P_MODEL_MODE5_WIREDANDDRIVEPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDDRIVEPULLUP << 20)
#define	GPIO_P_MODEL_MODE5_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDDRIVEPULLUPFILTER << 20)
#define	_GPIO_P_MODEL_MODE6_SHIFT 24
#define	_GPIO_P_MODEL_MODE6_MASK 0xF000000UL
#define	_GPIO_P_MODEL_MODE6_DEFAULT 0x00000000UL
#define	_GPIO_P_MODEL_MODE6_DISABLED 0x00000000UL
#define	_GPIO_P_MODEL_MODE6_INPUT 0x00000001UL
#define	_GPIO_P_MODEL_MODE6_INPUTPULL 0x00000002UL
#define	_GPIO_P_MODEL_MODE6_INPUTPULLFILTER 0x00000003UL
#define	_GPIO_P_MODEL_MODE6_PUSHPULL 0x00000004UL
#define	_GPIO_P_MODEL_MODE6_PUSHPULLDRIVE 0x00000005UL
#define	_GPIO_P_MODEL_MODE6_WIREDOR 0x00000006UL
#define	_GPIO_P_MODEL_MODE6_WIREDORPULLDOWN 0x00000007UL
#define	_GPIO_P_MODEL_MODE6_WIREDAND 0x00000008UL
#define	_GPIO_P_MODEL_MODE6_WIREDANDFILTER 0x00000009UL
#define	_GPIO_P_MODEL_MODE6_WIREDANDPULLUP 0x0000000AUL
#define	_GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER 0x0000000BUL
#define	_GPIO_P_MODEL_MODE6_WIREDANDDRIVE 0x0000000CUL
#define	_GPIO_P_MODEL_MODE6_WIREDANDDRIVEFILTER 0x0000000DUL
#define	_GPIO_P_MODEL_MODE6_WIREDANDDRIVEPULLUP 0x0000000EUL
#define	_GPIO_P_MODEL_MODE6_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL
#define	GPIO_P_MODEL_MODE6_DEFAULT (_GPIO_P_MODEL_MODE6_DEFAULT << 24)
#define	GPIO_P_MODEL_MODE6_DISABLED (_GPIO_P_MODEL_MODE6_DISABLED << 24)
#define	GPIO_P_MODEL_MODE6_INPUT (_GPIO_P_MODEL_MODE6_INPUT << 24)
#define	GPIO_P_MODEL_MODE6_INPUTPULL (_GPIO_P_MODEL_MODE6_INPUTPULL << 24)
#define	GPIO_P_MODEL_MODE6_INPUTPULLFILTER (_GPIO_P_MODEL_MODE6_INPUTPULLFILTER << 24)
#define	GPIO_P_MODEL_MODE6_PUSHPULL (_GPIO_P_MODEL_MODE6_PUSHPULL << 24)
#define	GPIO_P_MODEL_MODE6_PUSHPULLDRIVE (_GPIO_P_MODEL_MODE6_PUSHPULLDRIVE << 24)
#define	GPIO_P_MODEL_MODE6_WIREDOR (_GPIO_P_MODEL_MODE6_WIREDOR << 24)
#define	GPIO_P_MODEL_MODE6_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE6_WIREDORPULLDOWN << 24)
#define	GPIO_P_MODEL_MODE6_WIREDAND (_GPIO_P_MODEL_MODE6_WIREDAND << 24)
#define	GPIO_P_MODEL_MODE6_WIREDANDFILTER (_GPIO_P_MODEL_MODE6_WIREDANDFILTER << 24)
#define	GPIO_P_MODEL_MODE6_WIREDANDPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDPULLUP << 24)
#define	GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER << 24)
#define	GPIO_P_MODEL_MODE6_WIREDANDDRIVE (_GPIO_P_MODEL_MODE6_WIREDANDDRIVE << 24)
#define	GPIO_P_MODEL_MODE6_WIREDANDDRIVEFILTER (_GPIO_P_MODEL_MODE6_WIREDANDDRIVEFILTER << 24)
#define	GPIO_P_MODEL_MODE6_WIREDANDDRIVEPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDDRIVEPULLUP << 24)
#define	GPIO_P_MODEL_MODE6_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDDRIVEPULLUPFILTER << 24)
#define	_GPIO_P_MODEL_MODE7_SHIFT 28
#define	_GPIO_P_MODEL_MODE7_MASK 0xF0000000UL
#define	_GPIO_P_MODEL_MODE7_DEFAULT 0x00000000UL
#define	_GPIO_P_MODEL_MODE7_DISABLED 0x00000000UL
#define	_GPIO_P_MODEL_MODE7_INPUT 0x00000001UL
#define	_GPIO_P_MODEL_MODE7_INPUTPULL 0x00000002UL
#define	_GPIO_P_MODEL_MODE7_INPUTPULLFILTER 0x00000003UL
#define	_GPIO_P_MODEL_MODE7_PUSHPULL 0x00000004UL
#define	_GPIO_P_MODEL_MODE7_PUSHPULLDRIVE 0x00000005UL
#define	_GPIO_P_MODEL_MODE7_WIREDOR 0x00000006UL
#define	_GPIO_P_MODEL_MODE7_WIREDORPULLDOWN 0x00000007UL
#define	_GPIO_P_MODEL_MODE7_WIREDAND 0x00000008UL
#define	_GPIO_P_MODEL_MODE7_WIREDANDFILTER 0x00000009UL
#define	_GPIO_P_MODEL_MODE7_WIREDANDPULLUP 0x0000000AUL
#define	_GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER 0x0000000BUL
#define	_GPIO_P_MODEL_MODE7_WIREDANDDRIVE 0x0000000CUL
#define	_GPIO_P_MODEL_MODE7_WIREDANDDRIVEFILTER 0x0000000DUL
#define	_GPIO_P_MODEL_MODE7_WIREDANDDRIVEPULLUP 0x0000000EUL
#define	_GPIO_P_MODEL_MODE7_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL
#define	GPIO_P_MODEL_MODE7_DEFAULT (_GPIO_P_MODEL_MODE7_DEFAULT << 28)
#define	GPIO_P_MODEL_MODE7_DISABLED (_GPIO_P_MODEL_MODE7_DISABLED << 28)
#define	GPIO_P_MODEL_MODE7_INPUT (_GPIO_P_MODEL_MODE7_INPUT << 28)
#define	GPIO_P_MODEL_MODE7_INPUTPULL (_GPIO_P_MODEL_MODE7_INPUTPULL << 28)
#define	GPIO_P_MODEL_MODE7_INPUTPULLFILTER (_GPIO_P_MODEL_MODE7_INPUTPULLFILTER << 28)
#define	GPIO_P_MODEL_MODE7_PUSHPULL (_GPIO_P_MODEL_MODE7_PUSHPULL << 28)
#define	GPIO_P_MODEL_MODE7_PUSHPULLDRIVE (_GPIO_P_MODEL_MODE7_PUSHPULLDRIVE << 28)
#define	GPIO_P_MODEL_MODE7_WIREDOR (_GPIO_P_MODEL_MODE7_WIREDOR << 28)
#define	GPIO_P_MODEL_MODE7_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE7_WIREDORPULLDOWN << 28)
#define	GPIO_P_MODEL_MODE7_WIREDAND (_GPIO_P_MODEL_MODE7_WIREDAND << 28)
#define	GPIO_P_MODEL_MODE7_WIREDANDFILTER (_GPIO_P_MODEL_MODE7_WIREDANDFILTER << 28)
#define	GPIO_P_MODEL_MODE7_WIREDANDPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDPULLUP << 28)
#define	GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER << 28)
#define	GPIO_P_MODEL_MODE7_WIREDANDDRIVE (_GPIO_P_MODEL_MODE7_WIREDANDDRIVE << 28)
#define	GPIO_P_MODEL_MODE7_WIREDANDDRIVEFILTER (_GPIO_P_MODEL_MODE7_WIREDANDDRIVEFILTER << 28)
#define	GPIO_P_MODEL_MODE7_WIREDANDDRIVEPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDDRIVEPULLUP << 28)
#define	GPIO_P_MODEL_MODE7_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDDRIVEPULLUPFILTER << 28)
#define	_GPIO_P_MODEH_RESETVALUE 0x00000000UL
#define	_GPIO_P_MODEH_MASK 0xFFFFFFFFUL
#define	_GPIO_P_MODEH_MODE8_SHIFT 0
#define	_GPIO_P_MODEH_MODE8_MASK 0xFUL
#define	_GPIO_P_MODEH_MODE8_DEFAULT 0x00000000UL
#define	_GPIO_P_MODEH_MODE8_DISABLED 0x00000000UL
#define	_GPIO_P_MODEH_MODE8_INPUT 0x00000001UL
#define	_GPIO_P_MODEH_MODE8_INPUTPULL 0x00000002UL
#define	_GPIO_P_MODEH_MODE8_INPUTPULLFILTER 0x00000003UL
#define	_GPIO_P_MODEH_MODE8_PUSHPULL 0x00000004UL
#define	_GPIO_P_MODEH_MODE8_PUSHPULLDRIVE 0x00000005UL
#define	_GPIO_P_MODEH_MODE8_WIREDOR 0x00000006UL
#define	_GPIO_P_MODEH_MODE8_WIREDORPULLDOWN 0x00000007UL
#define	_GPIO_P_MODEH_MODE8_WIREDAND 0x00000008UL
#define	_GPIO_P_MODEH_MODE8_WIREDANDFILTER 0x00000009UL
#define	_GPIO_P_MODEH_MODE8_WIREDANDPULLUP 0x0000000AUL
#define	_GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER 0x0000000BUL
#define	_GPIO_P_MODEH_MODE8_WIREDANDDRIVE 0x0000000CUL
#define	_GPIO_P_MODEH_MODE8_WIREDANDDRIVEFILTER 0x0000000DUL
#define	_GPIO_P_MODEH_MODE8_WIREDANDDRIVEPULLUP 0x0000000EUL
#define	_GPIO_P_MODEH_MODE8_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL
#define	GPIO_P_MODEH_MODE8_DEFAULT (_GPIO_P_MODEH_MODE8_DEFAULT << 0)
#define	GPIO_P_MODEH_MODE8_DISABLED (_GPIO_P_MODEH_MODE8_DISABLED << 0)
#define	GPIO_P_MODEH_MODE8_INPUT (_GPIO_P_MODEH_MODE8_INPUT << 0)
#define	GPIO_P_MODEH_MODE8_INPUTPULL (_GPIO_P_MODEH_MODE8_INPUTPULL << 0)
#define	GPIO_P_MODEH_MODE8_INPUTPULLFILTER (_GPIO_P_MODEH_MODE8_INPUTPULLFILTER << 0)
#define	GPIO_P_MODEH_MODE8_PUSHPULL (_GPIO_P_MODEH_MODE8_PUSHPULL << 0)
#define	GPIO_P_MODEH_MODE8_PUSHPULLDRIVE (_GPIO_P_MODEH_MODE8_PUSHPULLDRIVE << 0)
#define	GPIO_P_MODEH_MODE8_WIREDOR (_GPIO_P_MODEH_MODE8_WIREDOR << 0)
#define	GPIO_P_MODEH_MODE8_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE8_WIREDORPULLDOWN << 0)
#define	GPIO_P_MODEH_MODE8_WIREDAND (_GPIO_P_MODEH_MODE8_WIREDAND << 0)
#define	GPIO_P_MODEH_MODE8_WIREDANDFILTER (_GPIO_P_MODEH_MODE8_WIREDANDFILTER << 0)
#define	GPIO_P_MODEH_MODE8_WIREDANDPULLUP (_GPIO_P_MODEH_MODE8_WIREDANDPULLUP << 0)
#define	GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER << 0)
#define	GPIO_P_MODEH_MODE8_WIREDANDDRIVE (_GPIO_P_MODEH_MODE8_WIREDANDDRIVE << 0)
#define	GPIO_P_MODEH_MODE8_WIREDANDDRIVEFILTER (_GPIO_P_MODEH_MODE8_WIREDANDDRIVEFILTER << 0)
#define	GPIO_P_MODEH_MODE8_WIREDANDDRIVEPULLUP (_GPIO_P_MODEH_MODE8_WIREDANDDRIVEPULLUP << 0)
#define	GPIO_P_MODEH_MODE8_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEH_MODE8_WIREDANDDRIVEPULLUPFILTER << 0)
#define	_GPIO_P_MODEH_MODE9_SHIFT 4
#define	_GPIO_P_MODEH_MODE9_MASK 0xF0UL
#define	_GPIO_P_MODEH_MODE9_DEFAULT 0x00000000UL
#define	_GPIO_P_MODEH_MODE9_DISABLED 0x00000000UL
#define	_GPIO_P_MODEH_MODE9_INPUT 0x00000001UL
#define	_GPIO_P_MODEH_MODE9_INPUTPULL 0x00000002UL
#define	_GPIO_P_MODEH_MODE9_INPUTPULLFILTER 0x00000003UL
#define	_GPIO_P_MODEH_MODE9_PUSHPULL 0x00000004UL
#define	_GPIO_P_MODEH_MODE9_PUSHPULLDRIVE 0x00000005UL
#define	_GPIO_P_MODEH_MODE9_WIREDOR 0x00000006UL
#define	_GPIO_P_MODEH_MODE9_WIREDORPULLDOWN 0x00000007UL
#define	_GPIO_P_MODEH_MODE9_WIREDAND 0x00000008UL
#define	_GPIO_P_MODEH_MODE9_WIREDANDFILTER 0x00000009UL
#define	_GPIO_P_MODEH_MODE9_WIREDANDPULLUP 0x0000000AUL
#define	_GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER 0x0000000BUL
#define	_GPIO_P_MODEH_MODE9_WIREDANDDRIVE 0x0000000CUL
#define	_GPIO_P_MODEH_MODE9_WIREDANDDRIVEFILTER 0x0000000DUL
#define	_GPIO_P_MODEH_MODE9_WIREDANDDRIVEPULLUP 0x0000000EUL
#define	_GPIO_P_MODEH_MODE9_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL
#define	GPIO_P_MODEH_MODE9_DEFAULT (_GPIO_P_MODEH_MODE9_DEFAULT << 4)
#define	GPIO_P_MODEH_MODE9_DISABLED (_GPIO_P_MODEH_MODE9_DISABLED << 4)
#define	GPIO_P_MODEH_MODE9_INPUT (_GPIO_P_MODEH_MODE9_INPUT << 4)
#define	GPIO_P_MODEH_MODE9_INPUTPULL (_GPIO_P_MODEH_MODE9_INPUTPULL << 4)
#define	GPIO_P_MODEH_MODE9_INPUTPULLFILTER (_GPIO_P_MODEH_MODE9_INPUTPULLFILTER << 4)
#define	GPIO_P_MODEH_MODE9_PUSHPULL (_GPIO_P_MODEH_MODE9_PUSHPULL << 4)
#define	GPIO_P_MODEH_MODE9_PUSHPULLDRIVE (_GPIO_P_MODEH_MODE9_PUSHPULLDRIVE << 4)
#define	GPIO_P_MODEH_MODE9_WIREDOR (_GPIO_P_MODEH_MODE9_WIREDOR << 4)
#define	GPIO_P_MODEH_MODE9_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE9_WIREDORPULLDOWN << 4)
#define	GPIO_P_MODEH_MODE9_WIREDAND (_GPIO_P_MODEH_MODE9_WIREDAND << 4)
#define	GPIO_P_MODEH_MODE9_WIREDANDFILTER (_GPIO_P_MODEH_MODE9_WIREDANDFILTER << 4)
#define	GPIO_P_MODEH_MODE9_WIREDANDPULLUP (_GPIO_P_MODEH_MODE9_WIREDANDPULLUP << 4)
#define	GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER << 4)
#define	GPIO_P_MODEH_MODE9_WIREDANDDRIVE (_GPIO_P_MODEH_MODE9_WIREDANDDRIVE << 4)
#define	GPIO_P_MODEH_MODE9_WIREDANDDRIVEFILTER (_GPIO_P_MODEH_MODE9_WIREDANDDRIVEFILTER << 4)
#define	GPIO_P_MODEH_MODE9_WIREDANDDRIVEPULLUP (_GPIO_P_MODEH_MODE9_WIREDANDDRIVEPULLUP << 4)
#define	GPIO_P_MODEH_MODE9_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEH_MODE9_WIREDANDDRIVEPULLUPFILTER << 4)
#define	_GPIO_P_MODEH_MODE10_SHIFT 8
#define	_GPIO_P_MODEH_MODE10_MASK 0xF00UL
#define	_GPIO_P_MODEH_MODE10_DEFAULT 0x00000000UL
#define	_GPIO_P_MODEH_MODE10_DISABLED 0x00000000UL
#define	_GPIO_P_MODEH_MODE10_INPUT 0x00000001UL
#define	_GPIO_P_MODEH_MODE10_INPUTPULL 0x00000002UL
#define	_GPIO_P_MODEH_MODE10_INPUTPULLFILTER 0x00000003UL
#define	_GPIO_P_MODEH_MODE10_PUSHPULL 0x00000004UL
#define	_GPIO_P_MODEH_MODE10_PUSHPULLDRIVE 0x00000005UL
#define	_GPIO_P_MODEH_MODE10_WIREDOR 0x00000006UL
#define	_GPIO_P_MODEH_MODE10_WIREDORPULLDOWN 0x00000007UL
#define	_GPIO_P_MODEH_MODE10_WIREDAND 0x00000008UL
#define	_GPIO_P_MODEH_MODE10_WIREDANDFILTER 0x00000009UL
#define	_GPIO_P_MODEH_MODE10_WIREDANDPULLUP 0x0000000AUL
#define	_GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER 0x0000000BUL
#define	_GPIO_P_MODEH_MODE10_WIREDANDDRIVE 0x0000000CUL
#define	_GPIO_P_MODEH_MODE10_WIREDANDDRIVEFILTER 0x0000000DUL
#define	_GPIO_P_MODEH_MODE10_WIREDANDDRIVEPULLUP 0x0000000EUL
#define	_GPIO_P_MODEH_MODE10_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL
#define	GPIO_P_MODEH_MODE10_DEFAULT (_GPIO_P_MODEH_MODE10_DEFAULT << 8)
#define	GPIO_P_MODEH_MODE10_DISABLED (_GPIO_P_MODEH_MODE10_DISABLED << 8)
#define	GPIO_P_MODEH_MODE10_INPUT (_GPIO_P_MODEH_MODE10_INPUT << 8)
#define	GPIO_P_MODEH_MODE10_INPUTPULL (_GPIO_P_MODEH_MODE10_INPUTPULL << 8)
#define	GPIO_P_MODEH_MODE10_INPUTPULLFILTER (_GPIO_P_MODEH_MODE10_INPUTPULLFILTER << 8)
#define	GPIO_P_MODEH_MODE10_PUSHPULL (_GPIO_P_MODEH_MODE10_PUSHPULL << 8)
#define	GPIO_P_MODEH_MODE10_PUSHPULLDRIVE (_GPIO_P_MODEH_MODE10_PUSHPULLDRIVE << 8)
#define	GPIO_P_MODEH_MODE10_WIREDOR (_GPIO_P_MODEH_MODE10_WIREDOR << 8)
#define	GPIO_P_MODEH_MODE10_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE10_WIREDORPULLDOWN << 8)
#define	GPIO_P_MODEH_MODE10_WIREDAND (_GPIO_P_MODEH_MODE10_WIREDAND << 8)
#define	GPIO_P_MODEH_MODE10_WIREDANDFILTER (_GPIO_P_MODEH_MODE10_WIREDANDFILTER << 8)
#define	GPIO_P_MODEH_MODE10_WIREDANDPULLUP (_GPIO_P_MODEH_MODE10_WIREDANDPULLUP << 8)
#define	GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER << 8)
#define	GPIO_P_MODEH_MODE10_WIREDANDDRIVE (_GPIO_P_MODEH_MODE10_WIREDANDDRIVE << 8)
#define	GPIO_P_MODEH_MODE10_WIREDANDDRIVEFILTER (_GPIO_P_MODEH_MODE10_WIREDANDDRIVEFILTER << 8)
#define	GPIO_P_MODEH_MODE10_WIREDANDDRIVEPULLUP (_GPIO_P_MODEH_MODE10_WIREDANDDRIVEPULLUP << 8)
#define	GPIO_P_MODEH_MODE10_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEH_MODE10_WIREDANDDRIVEPULLUPFILTER << 8)
#define	_GPIO_P_MODEH_MODE11_SHIFT 12
#define	_GPIO_P_MODEH_MODE11_MASK 0xF000UL
#define	_GPIO_P_MODEH_MODE11_DEFAULT 0x00000000UL
#define	_GPIO_P_MODEH_MODE11_DISABLED 0x00000000UL
#define	_GPIO_P_MODEH_MODE11_INPUT 0x00000001UL
#define	_GPIO_P_MODEH_MODE11_INPUTPULL 0x00000002UL
#define	_GPIO_P_MODEH_MODE11_INPUTPULLFILTER 0x00000003UL
#define	_GPIO_P_MODEH_MODE11_PUSHPULL 0x00000004UL
#define	_GPIO_P_MODEH_MODE11_PUSHPULLDRIVE 0x00000005UL
#define	_GPIO_P_MODEH_MODE11_WIREDOR 0x00000006UL
#define	_GPIO_P_MODEH_MODE11_WIREDORPULLDOWN 0x00000007UL
#define	_GPIO_P_MODEH_MODE11_WIREDAND 0x00000008UL
#define	_GPIO_P_MODEH_MODE11_WIREDANDFILTER 0x00000009UL
#define	_GPIO_P_MODEH_MODE11_WIREDANDPULLUP 0x0000000AUL
#define	_GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER 0x0000000BUL
#define	_GPIO_P_MODEH_MODE11_WIREDANDDRIVE 0x0000000CUL
#define	_GPIO_P_MODEH_MODE11_WIREDANDDRIVEFILTER 0x0000000DUL
#define	_GPIO_P_MODEH_MODE11_WIREDANDDRIVEPULLUP 0x0000000EUL
#define	_GPIO_P_MODEH_MODE11_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL
#define	GPIO_P_MODEH_MODE11_DEFAULT (_GPIO_P_MODEH_MODE11_DEFAULT << 12)
#define	GPIO_P_MODEH_MODE11_DISABLED (_GPIO_P_MODEH_MODE11_DISABLED << 12)
#define	GPIO_P_MODEH_MODE11_INPUT (_GPIO_P_MODEH_MODE11_INPUT << 12)
#define	GPIO_P_MODEH_MODE11_INPUTPULL (_GPIO_P_MODEH_MODE11_INPUTPULL << 12)
#define	GPIO_P_MODEH_MODE11_INPUTPULLFILTER (_GPIO_P_MODEH_MODE11_INPUTPULLFILTER << 12)
#define	GPIO_P_MODEH_MODE11_PUSHPULL (_GPIO_P_MODEH_MODE11_PUSHPULL << 12)
#define	GPIO_P_MODEH_MODE11_PUSHPULLDRIVE (_GPIO_P_MODEH_MODE11_PUSHPULLDRIVE << 12)
#define	GPIO_P_MODEH_MODE11_WIREDOR (_GPIO_P_MODEH_MODE11_WIREDOR << 12)
#define	GPIO_P_MODEH_MODE11_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE11_WIREDORPULLDOWN << 12)
#define	GPIO_P_MODEH_MODE11_WIREDAND (_GPIO_P_MODEH_MODE11_WIREDAND << 12)
#define	GPIO_P_MODEH_MODE11_WIREDANDFILTER (_GPIO_P_MODEH_MODE11_WIREDANDFILTER << 12)
#define	GPIO_P_MODEH_MODE11_WIREDANDPULLUP (_GPIO_P_MODEH_MODE11_WIREDANDPULLUP << 12)
#define	GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER << 12)
#define	GPIO_P_MODEH_MODE11_WIREDANDDRIVE (_GPIO_P_MODEH_MODE11_WIREDANDDRIVE << 12)
#define	GPIO_P_MODEH_MODE11_WIREDANDDRIVEFILTER (_GPIO_P_MODEH_MODE11_WIREDANDDRIVEFILTER << 12)
#define	GPIO_P_MODEH_MODE11_WIREDANDDRIVEPULLUP (_GPIO_P_MODEH_MODE11_WIREDANDDRIVEPULLUP << 12)
#define	GPIO_P_MODEH_MODE11_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEH_MODE11_WIREDANDDRIVEPULLUPFILTER << 12)
#define	_GPIO_P_MODEH_MODE12_SHIFT 16
#define	_GPIO_P_MODEH_MODE12_MASK 0xF0000UL
#define	_GPIO_P_MODEH_MODE12_DEFAULT 0x00000000UL
#define	_GPIO_P_MODEH_MODE12_DISABLED 0x00000000UL
#define	_GPIO_P_MODEH_MODE12_INPUT 0x00000001UL
#define	_GPIO_P_MODEH_MODE12_INPUTPULL 0x00000002UL
#define	_GPIO_P_MODEH_MODE12_INPUTPULLFILTER 0x00000003UL
#define	_GPIO_P_MODEH_MODE12_PUSHPULL 0x00000004UL
#define	_GPIO_P_MODEH_MODE12_PUSHPULLDRIVE 0x00000005UL
#define	_GPIO_P_MODEH_MODE12_WIREDOR 0x00000006UL
#define	_GPIO_P_MODEH_MODE12_WIREDORPULLDOWN 0x00000007UL
#define	_GPIO_P_MODEH_MODE12_WIREDAND 0x00000008UL
#define	_GPIO_P_MODEH_MODE12_WIREDANDFILTER 0x00000009UL
#define	_GPIO_P_MODEH_MODE12_WIREDANDPULLUP 0x0000000AUL
#define	_GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER 0x0000000BUL
#define	_GPIO_P_MODEH_MODE12_WIREDANDDRIVE 0x0000000CUL
#define	_GPIO_P_MODEH_MODE12_WIREDANDDRIVEFILTER 0x0000000DUL
#define	_GPIO_P_MODEH_MODE12_WIREDANDDRIVEPULLUP 0x0000000EUL
#define	_GPIO_P_MODEH_MODE12_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL
#define	GPIO_P_MODEH_MODE12_DEFAULT (_GPIO_P_MODEH_MODE12_DEFAULT << 16)
#define	GPIO_P_MODEH_MODE12_DISABLED (_GPIO_P_MODEH_MODE12_DISABLED << 16)
#define	GPIO_P_MODEH_MODE12_INPUT (_GPIO_P_MODEH_MODE12_INPUT << 16)
#define	GPIO_P_MODEH_MODE12_INPUTPULL (_GPIO_P_MODEH_MODE12_INPUTPULL << 16)
#define	GPIO_P_MODEH_MODE12_INPUTPULLFILTER (_GPIO_P_MODEH_MODE12_INPUTPULLFILTER << 16)
#define	GPIO_P_MODEH_MODE12_PUSHPULL (_GPIO_P_MODEH_MODE12_PUSHPULL << 16)
#define	GPIO_P_MODEH_MODE12_PUSHPULLDRIVE (_GPIO_P_MODEH_MODE12_PUSHPULLDRIVE << 16)
#define	GPIO_P_MODEH_MODE12_WIREDOR (_GPIO_P_MODEH_MODE12_WIREDOR << 16)
#define	GPIO_P_MODEH_MODE12_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE12_WIREDORPULLDOWN << 16)
#define	GPIO_P_MODEH_MODE12_WIREDAND (_GPIO_P_MODEH_MODE12_WIREDAND << 16)
#define	GPIO_P_MODEH_MODE12_WIREDANDFILTER (_GPIO_P_MODEH_MODE12_WIREDANDFILTER << 16)
#define	GPIO_P_MODEH_MODE12_WIREDANDPULLUP (_GPIO_P_MODEH_MODE12_WIREDANDPULLUP << 16)
#define	GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER << 16)
#define	GPIO_P_MODEH_MODE12_WIREDANDDRIVE (_GPIO_P_MODEH_MODE12_WIREDANDDRIVE << 16)
#define	GPIO_P_MODEH_MODE12_WIREDANDDRIVEFILTER (_GPIO_P_MODEH_MODE12_WIREDANDDRIVEFILTER << 16)
#define	GPIO_P_MODEH_MODE12_WIREDANDDRIVEPULLUP (_GPIO_P_MODEH_MODE12_WIREDANDDRIVEPULLUP << 16)
#define	GPIO_P_MODEH_MODE12_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEH_MODE12_WIREDANDDRIVEPULLUPFILTER << 16)
#define	_GPIO_P_MODEH_MODE13_SHIFT 20
#define	_GPIO_P_MODEH_MODE13_MASK 0xF00000UL
#define	_GPIO_P_MODEH_MODE13_DEFAULT 0x00000000UL
#define	_GPIO_P_MODEH_MODE13_DISABLED 0x00000000UL
#define	_GPIO_P_MODEH_MODE13_INPUT 0x00000001UL
#define	_GPIO_P_MODEH_MODE13_INPUTPULL 0x00000002UL
#define	_GPIO_P_MODEH_MODE13_INPUTPULLFILTER 0x00000003UL
#define	_GPIO_P_MODEH_MODE13_PUSHPULL 0x00000004UL
#define	_GPIO_P_MODEH_MODE13_PUSHPULLDRIVE 0x00000005UL
#define	_GPIO_P_MODEH_MODE13_WIREDOR 0x00000006UL
#define	_GPIO_P_MODEH_MODE13_WIREDORPULLDOWN 0x00000007UL
#define	_GPIO_P_MODEH_MODE13_WIREDAND 0x00000008UL
#define	_GPIO_P_MODEH_MODE13_WIREDANDFILTER 0x00000009UL
#define	_GPIO_P_MODEH_MODE13_WIREDANDPULLUP 0x0000000AUL
#define	_GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER 0x0000000BUL
#define	_GPIO_P_MODEH_MODE13_WIREDANDDRIVE 0x0000000CUL
#define	_GPIO_P_MODEH_MODE13_WIREDANDDRIVEFILTER 0x0000000DUL
#define	_GPIO_P_MODEH_MODE13_WIREDANDDRIVEPULLUP 0x0000000EUL
#define	_GPIO_P_MODEH_MODE13_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL
#define	GPIO_P_MODEH_MODE13_DEFAULT (_GPIO_P_MODEH_MODE13_DEFAULT << 20)
#define	GPIO_P_MODEH_MODE13_DISABLED (_GPIO_P_MODEH_MODE13_DISABLED << 20)
#define	GPIO_P_MODEH_MODE13_INPUT (_GPIO_P_MODEH_MODE13_INPUT << 20)
#define	GPIO_P_MODEH_MODE13_INPUTPULL (_GPIO_P_MODEH_MODE13_INPUTPULL << 20)
#define	GPIO_P_MODEH_MODE13_INPUTPULLFILTER (_GPIO_P_MODEH_MODE13_INPUTPULLFILTER << 20)
#define	GPIO_P_MODEH_MODE13_PUSHPULL (_GPIO_P_MODEH_MODE13_PUSHPULL << 20)
#define	GPIO_P_MODEH_MODE13_PUSHPULLDRIVE (_GPIO_P_MODEH_MODE13_PUSHPULLDRIVE << 20)
#define	GPIO_P_MODEH_MODE13_WIREDOR (_GPIO_P_MODEH_MODE13_WIREDOR << 20)
#define	GPIO_P_MODEH_MODE13_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE13_WIREDORPULLDOWN << 20)
#define	GPIO_P_MODEH_MODE13_WIREDAND (_GPIO_P_MODEH_MODE13_WIREDAND << 20)
#define	GPIO_P_MODEH_MODE13_WIREDANDFILTER (_GPIO_P_MODEH_MODE13_WIREDANDFILTER << 20)
#define	GPIO_P_MODEH_MODE13_WIREDANDPULLUP (_GPIO_P_MODEH_MODE13_WIREDANDPULLUP << 20)
#define	GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER << 20)
#define	GPIO_P_MODEH_MODE13_WIREDANDDRIVE (_GPIO_P_MODEH_MODE13_WIREDANDDRIVE << 20)
#define	GPIO_P_MODEH_MODE13_WIREDANDDRIVEFILTER (_GPIO_P_MODEH_MODE13_WIREDANDDRIVEFILTER << 20)
#define	GPIO_P_MODEH_MODE13_WIREDANDDRIVEPULLUP (_GPIO_P_MODEH_MODE13_WIREDANDDRIVEPULLUP << 20)
#define	GPIO_P_MODEH_MODE13_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEH_MODE13_WIREDANDDRIVEPULLUPFILTER << 20)
#define	_GPIO_P_MODEH_MODE14_SHIFT 24
#define	_GPIO_P_MODEH_MODE14_MASK 0xF000000UL
#define	_GPIO_P_MODEH_MODE14_DEFAULT 0x00000000UL
#define	_GPIO_P_MODEH_MODE14_DISABLED 0x00000000UL
#define	_GPIO_P_MODEH_MODE14_INPUT 0x00000001UL
#define	_GPIO_P_MODEH_MODE14_INPUTPULL 0x00000002UL
#define	_GPIO_P_MODEH_MODE14_INPUTPULLFILTER 0x00000003UL
#define	_GPIO_P_MODEH_MODE14_PUSHPULL 0x00000004UL
#define	_GPIO_P_MODEH_MODE14_PUSHPULLDRIVE 0x00000005UL
#define	_GPIO_P_MODEH_MODE14_WIREDOR 0x00000006UL
#define	_GPIO_P_MODEH_MODE14_WIREDORPULLDOWN 0x00000007UL
#define	_GPIO_P_MODEH_MODE14_WIREDAND 0x00000008UL
#define	_GPIO_P_MODEH_MODE14_WIREDANDFILTER 0x00000009UL
#define	_GPIO_P_MODEH_MODE14_WIREDANDPULLUP 0x0000000AUL
#define	_GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER 0x0000000BUL
#define	_GPIO_P_MODEH_MODE14_WIREDANDDRIVE 0x0000000CUL
#define	_GPIO_P_MODEH_MODE14_WIREDANDDRIVEFILTER 0x0000000DUL
#define	_GPIO_P_MODEH_MODE14_WIREDANDDRIVEPULLUP 0x0000000EUL
#define	_GPIO_P_MODEH_MODE14_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL
#define	GPIO_P_MODEH_MODE14_DEFAULT (_GPIO_P_MODEH_MODE14_DEFAULT << 24)
#define	GPIO_P_MODEH_MODE14_DISABLED (_GPIO_P_MODEH_MODE14_DISABLED << 24)
#define	GPIO_P_MODEH_MODE14_INPUT (_GPIO_P_MODEH_MODE14_INPUT << 24)
#define	GPIO_P_MODEH_MODE14_INPUTPULL (_GPIO_P_MODEH_MODE14_INPUTPULL << 24)
#define	GPIO_P_MODEH_MODE14_INPUTPULLFILTER (_GPIO_P_MODEH_MODE14_INPUTPULLFILTER << 24)
#define	GPIO_P_MODEH_MODE14_PUSHPULL (_GPIO_P_MODEH_MODE14_PUSHPULL << 24)
#define	GPIO_P_MODEH_MODE14_PUSHPULLDRIVE (_GPIO_P_MODEH_MODE14_PUSHPULLDRIVE << 24)
#define	GPIO_P_MODEH_MODE14_WIREDOR (_GPIO_P_MODEH_MODE14_WIREDOR << 24)
#define	GPIO_P_MODEH_MODE14_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE14_WIREDORPULLDOWN << 24)
#define	GPIO_P_MODEH_MODE14_WIREDAND (_GPIO_P_MODEH_MODE14_WIREDAND << 24)
#define	GPIO_P_MODEH_MODE14_WIREDANDFILTER (_GPIO_P_MODEH_MODE14_WIREDANDFILTER << 24)
#define	GPIO_P_MODEH_MODE14_WIREDANDPULLUP (_GPIO_P_MODEH_MODE14_WIREDANDPULLUP << 24)
#define	GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER << 24)
#define	GPIO_P_MODEH_MODE14_WIREDANDDRIVE (_GPIO_P_MODEH_MODE14_WIREDANDDRIVE << 24)
#define	GPIO_P_MODEH_MODE14_WIREDANDDRIVEFILTER (_GPIO_P_MODEH_MODE14_WIREDANDDRIVEFILTER << 24)
#define	GPIO_P_MODEH_MODE14_WIREDANDDRIVEPULLUP (_GPIO_P_MODEH_MODE14_WIREDANDDRIVEPULLUP << 24)
#define	GPIO_P_MODEH_MODE14_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEH_MODE14_WIREDANDDRIVEPULLUPFILTER << 24)
#define	_GPIO_P_MODEH_MODE15_SHIFT 28
#define	_GPIO_P_MODEH_MODE15_MASK 0xF0000000UL
#define	_GPIO_P_MODEH_MODE15_DEFAULT 0x00000000UL
#define	_GPIO_P_MODEH_MODE15_DISABLED 0x00000000UL
#define	_GPIO_P_MODEH_MODE15_INPUT 0x00000001UL
#define	_GPIO_P_MODEH_MODE15_INPUTPULL 0x00000002UL
#define	_GPIO_P_MODEH_MODE15_INPUTPULLFILTER 0x00000003UL
#define	_GPIO_P_MODEH_MODE15_PUSHPULL 0x00000004UL
#define	_GPIO_P_MODEH_MODE15_PUSHPULLDRIVE 0x00000005UL
#define	_GPIO_P_MODEH_MODE15_WIREDOR 0x00000006UL
#define	_GPIO_P_MODEH_MODE15_WIREDORPULLDOWN 0x00000007UL
#define	_GPIO_P_MODEH_MODE15_WIREDAND 0x00000008UL
#define	_GPIO_P_MODEH_MODE15_WIREDANDFILTER 0x00000009UL
#define	_GPIO_P_MODEH_MODE15_WIREDANDPULLUP 0x0000000AUL
#define	_GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER 0x0000000BUL
#define	_GPIO_P_MODEH_MODE15_WIREDANDDRIVE 0x0000000CUL
#define	_GPIO_P_MODEH_MODE15_WIREDANDDRIVEFILTER 0x0000000DUL
#define	_GPIO_P_MODEH_MODE15_WIREDANDDRIVEPULLUP 0x0000000EUL
#define	_GPIO_P_MODEH_MODE15_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL
#define	GPIO_P_MODEH_MODE15_DEFAULT (_GPIO_P_MODEH_MODE15_DEFAULT << 28)
#define	GPIO_P_MODEH_MODE15_DISABLED (_GPIO_P_MODEH_MODE15_DISABLED << 28)
#define	GPIO_P_MODEH_MODE15_INPUT (_GPIO_P_MODEH_MODE15_INPUT << 28)
#define	GPIO_P_MODEH_MODE15_INPUTPULL (_GPIO_P_MODEH_MODE15_INPUTPULL << 28)
#define	GPIO_P_MODEH_MODE15_INPUTPULLFILTER (_GPIO_P_MODEH_MODE15_INPUTPULLFILTER << 28)
#define	GPIO_P_MODEH_MODE15_PUSHPULL (_GPIO_P_MODEH_MODE15_PUSHPULL << 28)
#define	GPIO_P_MODEH_MODE15_PUSHPULLDRIVE (_GPIO_P_MODEH_MODE15_PUSHPULLDRIVE << 28)
#define	GPIO_P_MODEH_MODE15_WIREDOR (_GPIO_P_MODEH_MODE15_WIREDOR << 28)
#define	GPIO_P_MODEH_MODE15_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE15_WIREDORPULLDOWN << 28)
#define	GPIO_P_MODEH_MODE15_WIREDAND (_GPIO_P_MODEH_MODE15_WIREDAND << 28)
#define	GPIO_P_MODEH_MODE15_WIREDANDFILTER (_GPIO_P_MODEH_MODE15_WIREDANDFILTER << 28)
#define	GPIO_P_MODEH_MODE15_WIREDANDPULLUP (_GPIO_P_MODEH_MODE15_WIREDANDPULLUP << 28)
#define	GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER << 28)
#define	GPIO_P_MODEH_MODE15_WIREDANDDRIVE (_GPIO_P_MODEH_MODE15_WIREDANDDRIVE << 28)
#define	GPIO_P_MODEH_MODE15_WIREDANDDRIVEFILTER (_GPIO_P_MODEH_MODE15_WIREDANDDRIVEFILTER << 28)
#define	GPIO_P_MODEH_MODE15_WIREDANDDRIVEPULLUP (_GPIO_P_MODEH_MODE15_WIREDANDDRIVEPULLUP << 28)
#define	GPIO_P_MODEH_MODE15_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEH_MODE15_WIREDANDDRIVEPULLUPFILTER << 28)
#define	_GPIO_P_DOUT_RESETVALUE 0x00000000UL
#define	_GPIO_P_DOUT_MASK 0x0000FFFFUL
#define	_GPIO_P_DOUT_DOUT_SHIFT 0
#define	_GPIO_P_DOUT_DOUT_MASK 0xFFFFUL
#define	_GPIO_P_DOUT_DOUT_DEFAULT 0x00000000UL
#define	GPIO_P_DOUT_DOUT_DEFAULT (_GPIO_P_DOUT_DOUT_DEFAULT << 0)
#define	_GPIO_P_DOUTSET_RESETVALUE 0x00000000UL
#define	_GPIO_P_DOUTSET_MASK 0x0000FFFFUL
#define	_GPIO_P_DOUTSET_DOUTSET_SHIFT 0
#define	_GPIO_P_DOUTSET_DOUTSET_MASK 0xFFFFUL
#define	_GPIO_P_DOUTSET_DOUTSET_DEFAULT 0x00000000UL
#define	GPIO_P_DOUTSET_DOUTSET_DEFAULT (_GPIO_P_DOUTSET_DOUTSET_DEFAULT << 0)
#define	_GPIO_P_DOUTCLR_RESETVALUE 0x00000000UL
#define	_GPIO_P_DOUTCLR_MASK 0x0000FFFFUL
#define	_GPIO_P_DOUTCLR_DOUTCLR_SHIFT 0
#define	_GPIO_P_DOUTCLR_DOUTCLR_MASK 0xFFFFUL
#define	_GPIO_P_DOUTCLR_DOUTCLR_DEFAULT 0x00000000UL
#define	GPIO_P_DOUTCLR_DOUTCLR_DEFAULT (_GPIO_P_DOUTCLR_DOUTCLR_DEFAULT << 0)
#define	_GPIO_P_DOUTTGL_RESETVALUE 0x00000000UL
#define	_GPIO_P_DOUTTGL_MASK 0x0000FFFFUL
#define	_GPIO_P_DOUTTGL_DOUTTGL_SHIFT 0
#define	_GPIO_P_DOUTTGL_DOUTTGL_MASK 0xFFFFUL
#define	_GPIO_P_DOUTTGL_DOUTTGL_DEFAULT 0x00000000UL
#define	GPIO_P_DOUTTGL_DOUTTGL_DEFAULT (_GPIO_P_DOUTTGL_DOUTTGL_DEFAULT << 0)
#define	_GPIO_P_DIN_RESETVALUE 0x00000000UL
#define	_GPIO_P_DIN_MASK 0x0000FFFFUL
#define	_GPIO_P_DIN_DIN_SHIFT 0
#define	_GPIO_P_DIN_DIN_MASK 0xFFFFUL
#define	_GPIO_P_DIN_DIN_DEFAULT 0x00000000UL
#define	GPIO_P_DIN_DIN_DEFAULT (_GPIO_P_DIN_DIN_DEFAULT << 0)
#define	_GPIO_P_PINLOCKN_RESETVALUE 0x0000FFFFUL
#define	_GPIO_P_PINLOCKN_MASK 0x0000FFFFUL
#define	_GPIO_P_PINLOCKN_PINLOCKN_SHIFT 0
#define	_GPIO_P_PINLOCKN_PINLOCKN_MASK 0xFFFFUL
#define	_GPIO_P_PINLOCKN_PINLOCKN_DEFAULT 0x0000FFFFUL
#define	GPIO_P_PINLOCKN_PINLOCKN_DEFAULT (_GPIO_P_PINLOCKN_PINLOCKN_DEFAULT << 0)
#define	_GPIO_EXTIPSELL_RESETVALUE 0x00000000UL
#define	_GPIO_EXTIPSELL_MASK 0x77777777UL
#define	_GPIO_EXTIPSELL_EXTIPSEL0_SHIFT 0
#define	_GPIO_EXTIPSELL_EXTIPSEL0_MASK 0x7UL
#define	_GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT 0x00000000UL
#define	_GPIO_EXTIPSELL_EXTIPSEL0_PORTA 0x00000000UL
#define	_GPIO_EXTIPSELL_EXTIPSEL0_PORTB 0x00000001UL
#define	_GPIO_EXTIPSELL_EXTIPSEL0_PORTC 0x00000002UL
#define	_GPIO_EXTIPSELL_EXTIPSEL0_PORTD 0x00000003UL
#define	_GPIO_EXTIPSELL_EXTIPSEL0_PORTE 0x00000004UL
#define	_GPIO_EXTIPSELL_EXTIPSEL0_PORTF 0x00000005UL
#define	GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT << 0)
#define	GPIO_EXTIPSELL_EXTIPSEL0_PORTA (_GPIO_EXTIPSELL_EXTIPSEL0_PORTA << 0)
#define	GPIO_EXTIPSELL_EXTIPSEL0_PORTB (_GPIO_EXTIPSELL_EXTIPSEL0_PORTB << 0)
#define	GPIO_EXTIPSELL_EXTIPSEL0_PORTC (_GPIO_EXTIPSELL_EXTIPSEL0_PORTC << 0)
#define	GPIO_EXTIPSELL_EXTIPSEL0_PORTD (_GPIO_EXTIPSELL_EXTIPSEL0_PORTD << 0)
#define	GPIO_EXTIPSELL_EXTIPSEL0_PORTE (_GPIO_EXTIPSELL_EXTIPSEL0_PORTE << 0)
#define	GPIO_EXTIPSELL_EXTIPSEL0_PORTF (_GPIO_EXTIPSELL_EXTIPSEL0_PORTF << 0)
#define	_GPIO_EXTIPSELL_EXTIPSEL1_SHIFT 4
#define	_GPIO_EXTIPSELL_EXTIPSEL1_MASK 0x70UL
#define	_GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT 0x00000000UL
#define	_GPIO_EXTIPSELL_EXTIPSEL1_PORTA 0x00000000UL
#define	_GPIO_EXTIPSELL_EXTIPSEL1_PORTB 0x00000001UL
#define	_GPIO_EXTIPSELL_EXTIPSEL1_PORTC 0x00000002UL
#define	_GPIO_EXTIPSELL_EXTIPSEL1_PORTD 0x00000003UL
#define	_GPIO_EXTIPSELL_EXTIPSEL1_PORTE 0x00000004UL
#define	_GPIO_EXTIPSELL_EXTIPSEL1_PORTF 0x00000005UL
#define	GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT << 4)
#define	GPIO_EXTIPSELL_EXTIPSEL1_PORTA (_GPIO_EXTIPSELL_EXTIPSEL1_PORTA << 4)
#define	GPIO_EXTIPSELL_EXTIPSEL1_PORTB (_GPIO_EXTIPSELL_EXTIPSEL1_PORTB << 4)
#define	GPIO_EXTIPSELL_EXTIPSEL1_PORTC (_GPIO_EXTIPSELL_EXTIPSEL1_PORTC << 4)
#define	GPIO_EXTIPSELL_EXTIPSEL1_PORTD (_GPIO_EXTIPSELL_EXTIPSEL1_PORTD << 4)
#define	GPIO_EXTIPSELL_EXTIPSEL1_PORTE (_GPIO_EXTIPSELL_EXTIPSEL1_PORTE << 4)
#define	GPIO_EXTIPSELL_EXTIPSEL1_PORTF (_GPIO_EXTIPSELL_EXTIPSEL1_PORTF << 4)
#define	_GPIO_EXTIPSELL_EXTIPSEL2_SHIFT 8
#define	_GPIO_EXTIPSELL_EXTIPSEL2_MASK 0x700UL
#define	_GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT 0x00000000UL
#define	_GPIO_EXTIPSELL_EXTIPSEL2_PORTA 0x00000000UL
#define	_GPIO_EXTIPSELL_EXTIPSEL2_PORTB 0x00000001UL
#define	_GPIO_EXTIPSELL_EXTIPSEL2_PORTC 0x00000002UL
#define	_GPIO_EXTIPSELL_EXTIPSEL2_PORTD 0x00000003UL
#define	_GPIO_EXTIPSELL_EXTIPSEL2_PORTE 0x00000004UL
#define	_GPIO_EXTIPSELL_EXTIPSEL2_PORTF 0x00000005UL
#define	GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT << 8)
#define	GPIO_EXTIPSELL_EXTIPSEL2_PORTA (_GPIO_EXTIPSELL_EXTIPSEL2_PORTA << 8)
#define	GPIO_EXTIPSELL_EXTIPSEL2_PORTB (_GPIO_EXTIPSELL_EXTIPSEL2_PORTB << 8)
#define	GPIO_EXTIPSELL_EXTIPSEL2_PORTC (_GPIO_EXTIPSELL_EXTIPSEL2_PORTC << 8)
#define	GPIO_EXTIPSELL_EXTIPSEL2_PORTD (_GPIO_EXTIPSELL_EXTIPSEL2_PORTD << 8)
#define	GPIO_EXTIPSELL_EXTIPSEL2_PORTE (_GPIO_EXTIPSELL_EXTIPSEL2_PORTE << 8)
#define	GPIO_EXTIPSELL_EXTIPSEL2_PORTF (_GPIO_EXTIPSELL_EXTIPSEL2_PORTF << 8)
#define	_GPIO_EXTIPSELL_EXTIPSEL3_SHIFT 12
#define	_GPIO_EXTIPSELL_EXTIPSEL3_MASK 0x7000UL
#define	_GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT 0x00000000UL
#define	_GPIO_EXTIPSELL_EXTIPSEL3_PORTA 0x00000000UL
#define	_GPIO_EXTIPSELL_EXTIPSEL3_PORTB 0x00000001UL
#define	_GPIO_EXTIPSELL_EXTIPSEL3_PORTC 0x00000002UL
#define	_GPIO_EXTIPSELL_EXTIPSEL3_PORTD 0x00000003UL
#define	_GPIO_EXTIPSELL_EXTIPSEL3_PORTE 0x00000004UL
#define	_GPIO_EXTIPSELL_EXTIPSEL3_PORTF 0x00000005UL
#define	GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT << 12)
#define	GPIO_EXTIPSELL_EXTIPSEL3_PORTA (_GPIO_EXTIPSELL_EXTIPSEL3_PORTA << 12)
#define	GPIO_EXTIPSELL_EXTIPSEL3_PORTB (_GPIO_EXTIPSELL_EXTIPSEL3_PORTB << 12)
#define	GPIO_EXTIPSELL_EXTIPSEL3_PORTC (_GPIO_EXTIPSELL_EXTIPSEL3_PORTC << 12)
#define	GPIO_EXTIPSELL_EXTIPSEL3_PORTD (_GPIO_EXTIPSELL_EXTIPSEL3_PORTD << 12)
#define	GPIO_EXTIPSELL_EXTIPSEL3_PORTE (_GPIO_EXTIPSELL_EXTIPSEL3_PORTE << 12)
#define	GPIO_EXTIPSELL_EXTIPSEL3_PORTF (_GPIO_EXTIPSELL_EXTIPSEL3_PORTF << 12)
#define	_GPIO_EXTIPSELL_EXTIPSEL4_SHIFT 16
#define	_GPIO_EXTIPSELL_EXTIPSEL4_MASK 0x70000UL
#define	_GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT 0x00000000UL
#define	_GPIO_EXTIPSELL_EXTIPSEL4_PORTA 0x00000000UL
#define	_GPIO_EXTIPSELL_EXTIPSEL4_PORTB 0x00000001UL
#define	_GPIO_EXTIPSELL_EXTIPSEL4_PORTC 0x00000002UL
#define	_GPIO_EXTIPSELL_EXTIPSEL4_PORTD 0x00000003UL
#define	_GPIO_EXTIPSELL_EXTIPSEL4_PORTE 0x00000004UL
#define	_GPIO_EXTIPSELL_EXTIPSEL4_PORTF 0x00000005UL
#define	GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT << 16)
#define	GPIO_EXTIPSELL_EXTIPSEL4_PORTA (_GPIO_EXTIPSELL_EXTIPSEL4_PORTA << 16)
#define	GPIO_EXTIPSELL_EXTIPSEL4_PORTB (_GPIO_EXTIPSELL_EXTIPSEL4_PORTB << 16)
#define	GPIO_EXTIPSELL_EXTIPSEL4_PORTC (_GPIO_EXTIPSELL_EXTIPSEL4_PORTC << 16)
#define	GPIO_EXTIPSELL_EXTIPSEL4_PORTD (_GPIO_EXTIPSELL_EXTIPSEL4_PORTD << 16)
#define	GPIO_EXTIPSELL_EXTIPSEL4_PORTE (_GPIO_EXTIPSELL_EXTIPSEL4_PORTE << 16)
#define	GPIO_EXTIPSELL_EXTIPSEL4_PORTF (_GPIO_EXTIPSELL_EXTIPSEL4_PORTF << 16)
#define	_GPIO_EXTIPSELL_EXTIPSEL5_SHIFT 20
#define	_GPIO_EXTIPSELL_EXTIPSEL5_MASK 0x700000UL
#define	_GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT 0x00000000UL
#define	_GPIO_EXTIPSELL_EXTIPSEL5_PORTA 0x00000000UL
#define	_GPIO_EXTIPSELL_EXTIPSEL5_PORTB 0x00000001UL
#define	_GPIO_EXTIPSELL_EXTIPSEL5_PORTC 0x00000002UL
#define	_GPIO_EXTIPSELL_EXTIPSEL5_PORTD 0x00000003UL
#define	_GPIO_EXTIPSELL_EXTIPSEL5_PORTE 0x00000004UL
#define	_GPIO_EXTIPSELL_EXTIPSEL5_PORTF 0x00000005UL
#define	GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT << 20)
#define	GPIO_EXTIPSELL_EXTIPSEL5_PORTA (_GPIO_EXTIPSELL_EXTIPSEL5_PORTA << 20)
#define	GPIO_EXTIPSELL_EXTIPSEL5_PORTB (_GPIO_EXTIPSELL_EXTIPSEL5_PORTB << 20)
#define	GPIO_EXTIPSELL_EXTIPSEL5_PORTC (_GPIO_EXTIPSELL_EXTIPSEL5_PORTC << 20)
#define	GPIO_EXTIPSELL_EXTIPSEL5_PORTD (_GPIO_EXTIPSELL_EXTIPSEL5_PORTD << 20)
#define	GPIO_EXTIPSELL_EXTIPSEL5_PORTE (_GPIO_EXTIPSELL_EXTIPSEL5_PORTE << 20)
#define	GPIO_EXTIPSELL_EXTIPSEL5_PORTF (_GPIO_EXTIPSELL_EXTIPSEL5_PORTF << 20)
#define	_GPIO_EXTIPSELL_EXTIPSEL6_SHIFT 24
#define	_GPIO_EXTIPSELL_EXTIPSEL6_MASK 0x7000000UL
#define	_GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT 0x00000000UL
#define	_GPIO_EXTIPSELL_EXTIPSEL6_PORTA 0x00000000UL
#define	_GPIO_EXTIPSELL_EXTIPSEL6_PORTB 0x00000001UL
#define	_GPIO_EXTIPSELL_EXTIPSEL6_PORTC 0x00000002UL
#define	_GPIO_EXTIPSELL_EXTIPSEL6_PORTD 0x00000003UL
#define	_GPIO_EXTIPSELL_EXTIPSEL6_PORTE 0x00000004UL
#define	_GPIO_EXTIPSELL_EXTIPSEL6_PORTF 0x00000005UL
#define	GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT << 24)
#define	GPIO_EXTIPSELL_EXTIPSEL6_PORTA (_GPIO_EXTIPSELL_EXTIPSEL6_PORTA << 24)
#define	GPIO_EXTIPSELL_EXTIPSEL6_PORTB (_GPIO_EXTIPSELL_EXTIPSEL6_PORTB << 24)
#define	GPIO_EXTIPSELL_EXTIPSEL6_PORTC (_GPIO_EXTIPSELL_EXTIPSEL6_PORTC << 24)
#define	GPIO_EXTIPSELL_EXTIPSEL6_PORTD (_GPIO_EXTIPSELL_EXTIPSEL6_PORTD << 24)
#define	GPIO_EXTIPSELL_EXTIPSEL6_PORTE (_GPIO_EXTIPSELL_EXTIPSEL6_PORTE << 24)
#define	GPIO_EXTIPSELL_EXTIPSEL6_PORTF (_GPIO_EXTIPSELL_EXTIPSEL6_PORTF << 24)
#define	_GPIO_EXTIPSELL_EXTIPSEL7_SHIFT 28
#define	_GPIO_EXTIPSELL_EXTIPSEL7_MASK 0x70000000UL
#define	_GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT 0x00000000UL
#define	_GPIO_EXTIPSELL_EXTIPSEL7_PORTA 0x00000000UL
#define	_GPIO_EXTIPSELL_EXTIPSEL7_PORTB 0x00000001UL
#define	_GPIO_EXTIPSELL_EXTIPSEL7_PORTC 0x00000002UL
#define	_GPIO_EXTIPSELL_EXTIPSEL7_PORTD 0x00000003UL
#define	_GPIO_EXTIPSELL_EXTIPSEL7_PORTE 0x00000004UL
#define	_GPIO_EXTIPSELL_EXTIPSEL7_PORTF 0x00000005UL
#define	GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT << 28)
#define	GPIO_EXTIPSELL_EXTIPSEL7_PORTA (_GPIO_EXTIPSELL_EXTIPSEL7_PORTA << 28)
#define	GPIO_EXTIPSELL_EXTIPSEL7_PORTB (_GPIO_EXTIPSELL_EXTIPSEL7_PORTB << 28)
#define	GPIO_EXTIPSELL_EXTIPSEL7_PORTC (_GPIO_EXTIPSELL_EXTIPSEL7_PORTC << 28)
#define	GPIO_EXTIPSELL_EXTIPSEL7_PORTD (_GPIO_EXTIPSELL_EXTIPSEL7_PORTD << 28)
#define	GPIO_EXTIPSELL_EXTIPSEL7_PORTE (_GPIO_EXTIPSELL_EXTIPSEL7_PORTE << 28)
#define	GPIO_EXTIPSELL_EXTIPSEL7_PORTF (_GPIO_EXTIPSELL_EXTIPSEL7_PORTF << 28)
#define	_GPIO_EXTIPSELH_RESETVALUE 0x00000000UL
#define	_GPIO_EXTIPSELH_MASK 0x77777777UL
#define	_GPIO_EXTIPSELH_EXTIPSEL8_SHIFT 0
#define	_GPIO_EXTIPSELH_EXTIPSEL8_MASK 0x7UL
#define	_GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT 0x00000000UL
#define	_GPIO_EXTIPSELH_EXTIPSEL8_PORTA 0x00000000UL
#define	_GPIO_EXTIPSELH_EXTIPSEL8_PORTB 0x00000001UL
#define	_GPIO_EXTIPSELH_EXTIPSEL8_PORTC 0x00000002UL
#define	_GPIO_EXTIPSELH_EXTIPSEL8_PORTD 0x00000003UL
#define	_GPIO_EXTIPSELH_EXTIPSEL8_PORTE 0x00000004UL
#define	_GPIO_EXTIPSELH_EXTIPSEL8_PORTF 0x00000005UL
#define	GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT << 0)
#define	GPIO_EXTIPSELH_EXTIPSEL8_PORTA (_GPIO_EXTIPSELH_EXTIPSEL8_PORTA << 0)
#define	GPIO_EXTIPSELH_EXTIPSEL8_PORTB (_GPIO_EXTIPSELH_EXTIPSEL8_PORTB << 0)
#define	GPIO_EXTIPSELH_EXTIPSEL8_PORTC (_GPIO_EXTIPSELH_EXTIPSEL8_PORTC << 0)
#define	GPIO_EXTIPSELH_EXTIPSEL8_PORTD (_GPIO_EXTIPSELH_EXTIPSEL8_PORTD << 0)
#define	GPIO_EXTIPSELH_EXTIPSEL8_PORTE (_GPIO_EXTIPSELH_EXTIPSEL8_PORTE << 0)
#define	GPIO_EXTIPSELH_EXTIPSEL8_PORTF (_GPIO_EXTIPSELH_EXTIPSEL8_PORTF << 0)
#define	_GPIO_EXTIPSELH_EXTIPSEL9_SHIFT 4
#define	_GPIO_EXTIPSELH_EXTIPSEL9_MASK 0x70UL
#define	_GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT 0x00000000UL
#define	_GPIO_EXTIPSELH_EXTIPSEL9_PORTA 0x00000000UL
#define	_GPIO_EXTIPSELH_EXTIPSEL9_PORTB 0x00000001UL
#define	_GPIO_EXTIPSELH_EXTIPSEL9_PORTC 0x00000002UL
#define	_GPIO_EXTIPSELH_EXTIPSEL9_PORTD 0x00000003UL
#define	_GPIO_EXTIPSELH_EXTIPSEL9_PORTE 0x00000004UL
#define	_GPIO_EXTIPSELH_EXTIPSEL9_PORTF 0x00000005UL
#define	GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT << 4)
#define	GPIO_EXTIPSELH_EXTIPSEL9_PORTA (_GPIO_EXTIPSELH_EXTIPSEL9_PORTA << 4)
#define	GPIO_EXTIPSELH_EXTIPSEL9_PORTB (_GPIO_EXTIPSELH_EXTIPSEL9_PORTB << 4)
#define	GPIO_EXTIPSELH_EXTIPSEL9_PORTC (_GPIO_EXTIPSELH_EXTIPSEL9_PORTC << 4)
#define	GPIO_EXTIPSELH_EXTIPSEL9_PORTD (_GPIO_EXTIPSELH_EXTIPSEL9_PORTD << 4)
#define	GPIO_EXTIPSELH_EXTIPSEL9_PORTE (_GPIO_EXTIPSELH_EXTIPSEL9_PORTE << 4)
#define	GPIO_EXTIPSELH_EXTIPSEL9_PORTF (_GPIO_EXTIPSELH_EXTIPSEL9_PORTF << 4)
#define	_GPIO_EXTIPSELH_EXTIPSEL10_SHIFT 8
#define	_GPIO_EXTIPSELH_EXTIPSEL10_MASK 0x700UL
#define	_GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT 0x00000000UL
#define	_GPIO_EXTIPSELH_EXTIPSEL10_PORTA 0x00000000UL
#define	_GPIO_EXTIPSELH_EXTIPSEL10_PORTB 0x00000001UL
#define	_GPIO_EXTIPSELH_EXTIPSEL10_PORTC 0x00000002UL
#define	_GPIO_EXTIPSELH_EXTIPSEL10_PORTD 0x00000003UL
#define	_GPIO_EXTIPSELH_EXTIPSEL10_PORTE 0x00000004UL
#define	_GPIO_EXTIPSELH_EXTIPSEL10_PORTF 0x00000005UL
#define	GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT << 8)
#define	GPIO_EXTIPSELH_EXTIPSEL10_PORTA (_GPIO_EXTIPSELH_EXTIPSEL10_PORTA << 8)
#define	GPIO_EXTIPSELH_EXTIPSEL10_PORTB (_GPIO_EXTIPSELH_EXTIPSEL10_PORTB << 8)
#define	GPIO_EXTIPSELH_EXTIPSEL10_PORTC (_GPIO_EXTIPSELH_EXTIPSEL10_PORTC << 8)
#define	GPIO_EXTIPSELH_EXTIPSEL10_PORTD (_GPIO_EXTIPSELH_EXTIPSEL10_PORTD << 8)
#define	GPIO_EXTIPSELH_EXTIPSEL10_PORTE (_GPIO_EXTIPSELH_EXTIPSEL10_PORTE << 8)
#define	GPIO_EXTIPSELH_EXTIPSEL10_PORTF (_GPIO_EXTIPSELH_EXTIPSEL10_PORTF << 8)
#define	_GPIO_EXTIPSELH_EXTIPSEL11_SHIFT 12
#define	_GPIO_EXTIPSELH_EXTIPSEL11_MASK 0x7000UL
#define	_GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT 0x00000000UL
#define	_GPIO_EXTIPSELH_EXTIPSEL11_PORTA 0x00000000UL
#define	_GPIO_EXTIPSELH_EXTIPSEL11_PORTB 0x00000001UL
#define	_GPIO_EXTIPSELH_EXTIPSEL11_PORTC 0x00000002UL
#define	_GPIO_EXTIPSELH_EXTIPSEL11_PORTD 0x00000003UL
#define	_GPIO_EXTIPSELH_EXTIPSEL11_PORTE 0x00000004UL
#define	_GPIO_EXTIPSELH_EXTIPSEL11_PORTF 0x00000005UL
#define	GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT << 12)
#define	GPIO_EXTIPSELH_EXTIPSEL11_PORTA (_GPIO_EXTIPSELH_EXTIPSEL11_PORTA << 12)
#define	GPIO_EXTIPSELH_EXTIPSEL11_PORTB (_GPIO_EXTIPSELH_EXTIPSEL11_PORTB << 12)
#define	GPIO_EXTIPSELH_EXTIPSEL11_PORTC (_GPIO_EXTIPSELH_EXTIPSEL11_PORTC << 12)
#define	GPIO_EXTIPSELH_EXTIPSEL11_PORTD (_GPIO_EXTIPSELH_EXTIPSEL11_PORTD << 12)
#define	GPIO_EXTIPSELH_EXTIPSEL11_PORTE (_GPIO_EXTIPSELH_EXTIPSEL11_PORTE << 12)
#define	GPIO_EXTIPSELH_EXTIPSEL11_PORTF (_GPIO_EXTIPSELH_EXTIPSEL11_PORTF << 12)
#define	_GPIO_EXTIPSELH_EXTIPSEL12_SHIFT 16
#define	_GPIO_EXTIPSELH_EXTIPSEL12_MASK 0x70000UL
#define	_GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT 0x00000000UL
#define	_GPIO_EXTIPSELH_EXTIPSEL12_PORTA 0x00000000UL
#define	_GPIO_EXTIPSELH_EXTIPSEL12_PORTB 0x00000001UL
#define	_GPIO_EXTIPSELH_EXTIPSEL12_PORTC 0x00000002UL
#define	_GPIO_EXTIPSELH_EXTIPSEL12_PORTD 0x00000003UL
#define	_GPIO_EXTIPSELH_EXTIPSEL12_PORTE 0x00000004UL
#define	_GPIO_EXTIPSELH_EXTIPSEL12_PORTF 0x00000005UL
#define	GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT << 16)
#define	GPIO_EXTIPSELH_EXTIPSEL12_PORTA (_GPIO_EXTIPSELH_EXTIPSEL12_PORTA << 16)
#define	GPIO_EXTIPSELH_EXTIPSEL12_PORTB (_GPIO_EXTIPSELH_EXTIPSEL12_PORTB << 16)
#define	GPIO_EXTIPSELH_EXTIPSEL12_PORTC (_GPIO_EXTIPSELH_EXTIPSEL12_PORTC << 16)
#define	GPIO_EXTIPSELH_EXTIPSEL12_PORTD (_GPIO_EXTIPSELH_EXTIPSEL12_PORTD << 16)
#define	GPIO_EXTIPSELH_EXTIPSEL12_PORTE (_GPIO_EXTIPSELH_EXTIPSEL12_PORTE << 16)
#define	GPIO_EXTIPSELH_EXTIPSEL12_PORTF (_GPIO_EXTIPSELH_EXTIPSEL12_PORTF << 16)
#define	_GPIO_EXTIPSELH_EXTIPSEL13_SHIFT 20
#define	_GPIO_EXTIPSELH_EXTIPSEL13_MASK 0x700000UL
#define	_GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT 0x00000000UL
#define	_GPIO_EXTIPSELH_EXTIPSEL13_PORTA 0x00000000UL
#define	_GPIO_EXTIPSELH_EXTIPSEL13_PORTB 0x00000001UL
#define	_GPIO_EXTIPSELH_EXTIPSEL13_PORTC 0x00000002UL
#define	_GPIO_EXTIPSELH_EXTIPSEL13_PORTD 0x00000003UL
#define	_GPIO_EXTIPSELH_EXTIPSEL13_PORTE 0x00000004UL
#define	_GPIO_EXTIPSELH_EXTIPSEL13_PORTF 0x00000005UL
#define	GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT << 20)
#define	GPIO_EXTIPSELH_EXTIPSEL13_PORTA (_GPIO_EXTIPSELH_EXTIPSEL13_PORTA << 20)
#define	GPIO_EXTIPSELH_EXTIPSEL13_PORTB (_GPIO_EXTIPSELH_EXTIPSEL13_PORTB << 20)
#define	GPIO_EXTIPSELH_EXTIPSEL13_PORTC (_GPIO_EXTIPSELH_EXTIPSEL13_PORTC << 20)
#define	GPIO_EXTIPSELH_EXTIPSEL13_PORTD (_GPIO_EXTIPSELH_EXTIPSEL13_PORTD << 20)
#define	GPIO_EXTIPSELH_EXTIPSEL13_PORTE (_GPIO_EXTIPSELH_EXTIPSEL13_PORTE << 20)
#define	GPIO_EXTIPSELH_EXTIPSEL13_PORTF (_GPIO_EXTIPSELH_EXTIPSEL13_PORTF << 20)
#define	_GPIO_EXTIPSELH_EXTIPSEL14_SHIFT 24
#define	_GPIO_EXTIPSELH_EXTIPSEL14_MASK 0x7000000UL
#define	_GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT 0x00000000UL
#define	_GPIO_EXTIPSELH_EXTIPSEL14_PORTA 0x00000000UL
#define	_GPIO_EXTIPSELH_EXTIPSEL14_PORTB 0x00000001UL
#define	_GPIO_EXTIPSELH_EXTIPSEL14_PORTC 0x00000002UL
#define	_GPIO_EXTIPSELH_EXTIPSEL14_PORTD 0x00000003UL
#define	_GPIO_EXTIPSELH_EXTIPSEL14_PORTE 0x00000004UL
#define	_GPIO_EXTIPSELH_EXTIPSEL14_PORTF 0x00000005UL
#define	GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT << 24)
#define	GPIO_EXTIPSELH_EXTIPSEL14_PORTA (_GPIO_EXTIPSELH_EXTIPSEL14_PORTA << 24)
#define	GPIO_EXTIPSELH_EXTIPSEL14_PORTB (_GPIO_EXTIPSELH_EXTIPSEL14_PORTB << 24)
#define	GPIO_EXTIPSELH_EXTIPSEL14_PORTC (_GPIO_EXTIPSELH_EXTIPSEL14_PORTC << 24)
#define	GPIO_EXTIPSELH_EXTIPSEL14_PORTD (_GPIO_EXTIPSELH_EXTIPSEL14_PORTD << 24)
#define	GPIO_EXTIPSELH_EXTIPSEL14_PORTE (_GPIO_EXTIPSELH_EXTIPSEL14_PORTE << 24)
#define	GPIO_EXTIPSELH_EXTIPSEL14_PORTF (_GPIO_EXTIPSELH_EXTIPSEL14_PORTF << 24)
#define	_GPIO_EXTIPSELH_EXTIPSEL15_SHIFT 28
#define	_GPIO_EXTIPSELH_EXTIPSEL15_MASK 0x70000000UL
#define	_GPIO_EXTIPSELH_EXTIPSEL15_DEFAULT 0x00000000UL
#define	_GPIO_EXTIPSELH_EXTIPSEL15_PORTA 0x00000000UL
#define	_GPIO_EXTIPSELH_EXTIPSEL15_PORTB 0x00000001UL
#define	_GPIO_EXTIPSELH_EXTIPSEL15_PORTC 0x00000002UL
#define	_GPIO_EXTIPSELH_EXTIPSEL15_PORTD 0x00000003UL
#define	_GPIO_EXTIPSELH_EXTIPSEL15_PORTE 0x00000004UL
#define	_GPIO_EXTIPSELH_EXTIPSEL15_PORTF 0x00000005UL
#define	GPIO_EXTIPSELH_EXTIPSEL15_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL15_DEFAULT << 28)
#define	GPIO_EXTIPSELH_EXTIPSEL15_PORTA (_GPIO_EXTIPSELH_EXTIPSEL15_PORTA << 28)
#define	GPIO_EXTIPSELH_EXTIPSEL15_PORTB (_GPIO_EXTIPSELH_EXTIPSEL15_PORTB << 28)
#define	GPIO_EXTIPSELH_EXTIPSEL15_PORTC (_GPIO_EXTIPSELH_EXTIPSEL15_PORTC << 28)
#define	GPIO_EXTIPSELH_EXTIPSEL15_PORTD (_GPIO_EXTIPSELH_EXTIPSEL15_PORTD << 28)
#define	GPIO_EXTIPSELH_EXTIPSEL15_PORTE (_GPIO_EXTIPSELH_EXTIPSEL15_PORTE << 28)
#define	GPIO_EXTIPSELH_EXTIPSEL15_PORTF (_GPIO_EXTIPSELH_EXTIPSEL15_PORTF << 28)
#define	_GPIO_EXTIRISE_RESETVALUE 0x00000000UL
#define	_GPIO_EXTIRISE_MASK 0x0000FFFFUL
#define	_GPIO_EXTIRISE_EXTIRISE_SHIFT 0
#define	_GPIO_EXTIRISE_EXTIRISE_MASK 0xFFFFUL
#define	_GPIO_EXTIRISE_EXTIRISE_DEFAULT 0x00000000UL
#define	GPIO_EXTIRISE_EXTIRISE_DEFAULT (_GPIO_EXTIRISE_EXTIRISE_DEFAULT << 0)
#define	_GPIO_EXTIFALL_RESETVALUE 0x00000000UL
#define	_GPIO_EXTIFALL_MASK 0x0000FFFFUL
#define	_GPIO_EXTIFALL_EXTIFALL_SHIFT 0
#define	_GPIO_EXTIFALL_EXTIFALL_MASK 0xFFFFUL
#define	_GPIO_EXTIFALL_EXTIFALL_DEFAULT 0x00000000UL
#define	GPIO_EXTIFALL_EXTIFALL_DEFAULT (_GPIO_EXTIFALL_EXTIFALL_DEFAULT << 0)
#define	_GPIO_IEN_RESETVALUE 0x00000000UL
#define	_GPIO_IEN_MASK 0x0000FFFFUL
#define	_GPIO_IEN_EXT_SHIFT 0
#define	_GPIO_IEN_EXT_MASK 0xFFFFUL
#define	_GPIO_IEN_EXT_DEFAULT 0x00000000UL
#define	GPIO_IEN_EXT_DEFAULT (_GPIO_IEN_EXT_DEFAULT << 0)
#define	_GPIO_IF_RESETVALUE 0x00000000UL
#define	_GPIO_IF_MASK 0x0000FFFFUL
#define	_GPIO_IF_EXT_SHIFT 0
#define	_GPIO_IF_EXT_MASK 0xFFFFUL
#define	_GPIO_IF_EXT_DEFAULT 0x00000000UL
#define	GPIO_IF_EXT_DEFAULT (_GPIO_IF_EXT_DEFAULT << 0)
#define	_GPIO_IFS_RESETVALUE 0x00000000UL
#define	_GPIO_IFS_MASK 0x0000FFFFUL
#define	_GPIO_IFS_EXT_SHIFT 0
#define	_GPIO_IFS_EXT_MASK 0xFFFFUL
#define	_GPIO_IFS_EXT_DEFAULT 0x00000000UL
#define	GPIO_IFS_EXT_DEFAULT (_GPIO_IFS_EXT_DEFAULT << 0)
#define	_GPIO_IFC_RESETVALUE 0x00000000UL
#define	_GPIO_IFC_MASK 0x0000FFFFUL
#define	_GPIO_IFC_EXT_SHIFT 0
#define	_GPIO_IFC_EXT_MASK 0xFFFFUL
#define	_GPIO_IFC_EXT_DEFAULT 0x00000000UL
#define	GPIO_IFC_EXT_DEFAULT (_GPIO_IFC_EXT_DEFAULT << 0)
#define	_GPIO_ROUTE_RESETVALUE 0x00000003UL
#define	_GPIO_ROUTE_MASK 0x00000307UL
#define	GPIO_ROUTE_SWCLKPEN (0x1UL << 0)
#define	_GPIO_ROUTE_SWCLKPEN_SHIFT 0
#define	_GPIO_ROUTE_SWCLKPEN_MASK 0x1UL
#define	_GPIO_ROUTE_SWCLKPEN_DEFAULT 0x00000001UL
#define	GPIO_ROUTE_SWCLKPEN_DEFAULT (_GPIO_ROUTE_SWCLKPEN_DEFAULT << 0)
#define	GPIO_ROUTE_SWDIOPEN (0x1UL << 1)
#define	_GPIO_ROUTE_SWDIOPEN_SHIFT 1
#define	_GPIO_ROUTE_SWDIOPEN_MASK 0x2UL
#define	_GPIO_ROUTE_SWDIOPEN_DEFAULT 0x00000001UL
#define	GPIO_ROUTE_SWDIOPEN_DEFAULT (_GPIO_ROUTE_SWDIOPEN_DEFAULT << 1)
#define	GPIO_ROUTE_SWOPEN (0x1UL << 2)
#define	_GPIO_ROUTE_SWOPEN_SHIFT 2
#define	_GPIO_ROUTE_SWOPEN_MASK 0x4UL
#define	_GPIO_ROUTE_SWOPEN_DEFAULT 0x00000000UL
#define	GPIO_ROUTE_SWOPEN_DEFAULT (_GPIO_ROUTE_SWOPEN_DEFAULT << 2)
#define	_GPIO_ROUTE_SWLOCATION_SHIFT 8
#define	_GPIO_ROUTE_SWLOCATION_MASK 0x300UL
#define	_GPIO_ROUTE_SWLOCATION_DEFAULT 0x00000000UL
#define	_GPIO_ROUTE_SWLOCATION_LOC0 0x00000000UL
#define	_GPIO_ROUTE_SWLOCATION_LOC1 0x00000001UL
#define	_GPIO_ROUTE_SWLOCATION_LOC2 0x00000002UL
#define	_GPIO_ROUTE_SWLOCATION_LOC3 0x00000003UL
#define	GPIO_ROUTE_SWLOCATION_DEFAULT (_GPIO_ROUTE_SWLOCATION_DEFAULT << 8)
#define	GPIO_ROUTE_SWLOCATION_LOC0 (_GPIO_ROUTE_SWLOCATION_LOC0 << 8)
#define	GPIO_ROUTE_SWLOCATION_LOC1 (_GPIO_ROUTE_SWLOCATION_LOC1 << 8)
#define	GPIO_ROUTE_SWLOCATION_LOC2 (_GPIO_ROUTE_SWLOCATION_LOC2 << 8)
#define	GPIO_ROUTE_SWLOCATION_LOC3 (_GPIO_ROUTE_SWLOCATION_LOC3 << 8)
#define	_GPIO_INSENSE_RESETVALUE 0x00000003UL
#define	_GPIO_INSENSE_MASK 0x00000003UL
#define	GPIO_INSENSE_INT (0x1UL << 0)
#define	_GPIO_INSENSE_INT_SHIFT 0
#define	_GPIO_INSENSE_INT_MASK 0x1UL
#define	_GPIO_INSENSE_INT_DEFAULT 0x00000001UL
#define	GPIO_INSENSE_INT_DEFAULT (_GPIO_INSENSE_INT_DEFAULT << 0)
#define	GPIO_INSENSE_PRS (0x1UL << 1)
#define	_GPIO_INSENSE_PRS_SHIFT 1
#define	_GPIO_INSENSE_PRS_MASK 0x2UL
#define	_GPIO_INSENSE_PRS_DEFAULT 0x00000001UL
#define	GPIO_INSENSE_PRS_DEFAULT (_GPIO_INSENSE_PRS_DEFAULT << 1)
#define	_GPIO_LOCK_RESETVALUE 0x00000000UL
#define	_GPIO_LOCK_MASK 0x0000FFFFUL
#define	_GPIO_LOCK_LOCKKEY_SHIFT 0
#define	_GPIO_LOCK_LOCKKEY_MASK 0xFFFFUL
#define	_GPIO_LOCK_LOCKKEY_DEFAULT 0x00000000UL
#define	_GPIO_LOCK_LOCKKEY_LOCK 0x00000000UL
#define	_GPIO_LOCK_LOCKKEY_UNLOCKED 0x00000000UL
#define	_GPIO_LOCK_LOCKKEY_LOCKED 0x00000001UL
#define	_GPIO_LOCK_LOCKKEY_UNLOCK 0x0000A534UL
#define	GPIO_LOCK_LOCKKEY_DEFAULT (_GPIO_LOCK_LOCKKEY_DEFAULT << 0)
#define	GPIO_LOCK_LOCKKEY_LOCK (_GPIO_LOCK_LOCKKEY_LOCK << 0)
#define	GPIO_LOCK_LOCKKEY_UNLOCKED (_GPIO_LOCK_LOCKKEY_UNLOCKED << 0)
#define	GPIO_LOCK_LOCKKEY_LOCKED (_GPIO_LOCK_LOCKKEY_LOCKED << 0)
#define	GPIO_LOCK_LOCKKEY_UNLOCK (_GPIO_LOCK_LOCKKEY_UNLOCK << 0)
#define	_PRS_SWPULSE_RESETVALUE 0x00000000UL
#define	_PRS_SWPULSE_MASK 0x000000FFUL
#define	PRS_SWPULSE_CH0PULSE (0x1UL << 0)
#define	_PRS_SWPULSE_CH0PULSE_SHIFT 0
#define	_PRS_SWPULSE_CH0PULSE_MASK 0x1UL
#define	_PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL
#define	PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0)
#define	PRS_SWPULSE_CH1PULSE (0x1UL << 1)
#define	_PRS_SWPULSE_CH1PULSE_SHIFT 1
#define	_PRS_SWPULSE_CH1PULSE_MASK 0x2UL
#define	_PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL
#define	PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1)
#define	PRS_SWPULSE_CH2PULSE (0x1UL << 2)
#define	_PRS_SWPULSE_CH2PULSE_SHIFT 2
#define	_PRS_SWPULSE_CH2PULSE_MASK 0x4UL
#define	_PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL
#define	PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2)
#define	PRS_SWPULSE_CH3PULSE (0x1UL << 3)
#define	_PRS_SWPULSE_CH3PULSE_SHIFT 3
#define	_PRS_SWPULSE_CH3PULSE_MASK 0x8UL
#define	_PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL
#define	PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3)
#define	PRS_SWPULSE_CH4PULSE (0x1UL << 4)
#define	_PRS_SWPULSE_CH4PULSE_SHIFT 4
#define	_PRS_SWPULSE_CH4PULSE_MASK 0x10UL
#define	_PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL
#define	PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4)
#define	PRS_SWPULSE_CH5PULSE (0x1UL << 5)
#define	_PRS_SWPULSE_CH5PULSE_SHIFT 5
#define	_PRS_SWPULSE_CH5PULSE_MASK 0x20UL
#define	_PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL
#define	PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5)
#define	PRS_SWPULSE_CH6PULSE (0x1UL << 6)
#define	_PRS_SWPULSE_CH6PULSE_SHIFT 6
#define	_PRS_SWPULSE_CH6PULSE_MASK 0x40UL
#define	_PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL
#define	PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6)
#define	PRS_SWPULSE_CH7PULSE (0x1UL << 7)
#define	_PRS_SWPULSE_CH7PULSE_SHIFT 7
#define	_PRS_SWPULSE_CH7PULSE_MASK 0x80UL
#define	_PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL
#define	PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7)
#define	_PRS_SWLEVEL_RESETVALUE 0x00000000UL
#define	_PRS_SWLEVEL_MASK 0x000000FFUL
#define	PRS_SWLEVEL_CH0LEVEL (0x1UL << 0)
#define	_PRS_SWLEVEL_CH0LEVEL_SHIFT 0
#define	_PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL
#define	_PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL
#define	PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0)
#define	PRS_SWLEVEL_CH1LEVEL (0x1UL << 1)
#define	_PRS_SWLEVEL_CH1LEVEL_SHIFT 1
#define	_PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL
#define	_PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL
#define	PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1)
#define	PRS_SWLEVEL_CH2LEVEL (0x1UL << 2)
#define	_PRS_SWLEVEL_CH2LEVEL_SHIFT 2
#define	_PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL
#define	_PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL
#define	PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2)
#define	PRS_SWLEVEL_CH3LEVEL (0x1UL << 3)
#define	_PRS_SWLEVEL_CH3LEVEL_SHIFT 3
#define	_PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL
#define	_PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL
#define	PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3)
#define	PRS_SWLEVEL_CH4LEVEL (0x1UL << 4)
#define	_PRS_SWLEVEL_CH4LEVEL_SHIFT 4
#define	_PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL
#define	_PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL
#define	PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4)
#define	PRS_SWLEVEL_CH5LEVEL (0x1UL << 5)
#define	_PRS_SWLEVEL_CH5LEVEL_SHIFT 5
#define	_PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL
#define	_PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL
#define	PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5)
#define	PRS_SWLEVEL_CH6LEVEL (0x1UL << 6)
#define	_PRS_SWLEVEL_CH6LEVEL_SHIFT 6
#define	_PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL
#define	_PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL
#define	PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6)
#define	PRS_SWLEVEL_CH7LEVEL (0x1UL << 7)
#define	_PRS_SWLEVEL_CH7LEVEL_SHIFT 7
#define	_PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL
#define	_PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL
#define	PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7)
#define	_PRS_CH_CTRL_RESETVALUE 0x00000000UL
#define	_PRS_CH_CTRL_MASK 0x033F0007UL
#define	_PRS_CH_CTRL_SIGSEL_SHIFT 0
#define	_PRS_CH_CTRL_SIGSEL_MASK 0x7UL
#define	_PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL
#define	_PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL
#define	_PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL
#define	_PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL
#define	_PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL
#define	_PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL
#define	_PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL
#define	_PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL
#define	_PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL
#define	_PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL
#define	_PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL
#define	_PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL
#define	_PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL
#define	_PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL
#define	_PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL
#define	_PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL
#define	_PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL
#define	_PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL
#define	_PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL
#define	_PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL
#define	_PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL
#define	_PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL
#define	_PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL
#define	_PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL
#define	_PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL
#define	_PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL
#define	_PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL
#define	_PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL
#define	_PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL
#define	_PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL
#define	_PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL
#define	_PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL
#define	_PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL
#define	_PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL
#define	_PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL
#define	_PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL
#define	_PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL
#define	_PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL
#define	_PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL
#define	_PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL
#define	_PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL
#define	_PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL
#define	_PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL
#define	_PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL
#define	_PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL
#define	_PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL
#define	_PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL
#define	_PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL
#define	_PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL
#define	_PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL
#define	PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0)
#define	PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0)
#define	PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0)
#define	PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0)
#define	PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0)
#define	PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0)
#define	PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0)
#define	PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0)
#define	PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0)
#define	PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0)
#define	PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0)
#define	PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0)
#define	PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0)
#define	PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0)
#define	PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0)
#define	PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0)
#define	PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0)
#define	PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0)
#define	PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0)
#define	PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0)
#define	PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0)
#define	PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0)
#define	PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0)
#define	PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0)
#define	PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0)
#define	PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0)
#define	PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0)
#define	PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0)
#define	PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0)
#define	PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0)
#define	PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0)
#define	PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0)
#define	PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0)
#define	PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0)
#define	PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0)
#define	PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0)
#define	PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0)
#define	PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0)
#define	PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0)
#define	PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0)
#define	PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0)
#define	PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0)
#define	PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0)
#define	PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0)
#define	PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0)
#define	PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0)
#define	PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0)
#define	PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0)
#define	PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0)
#define	PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0)
#define	_PRS_CH_CTRL_SOURCESEL_SHIFT 16
#define	_PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL
#define	_PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL
#define	_PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL
#define	_PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL
#define	_PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL
#define	_PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL
#define	_PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL
#define	_PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL
#define	_PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL
#define	_PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL
#define	_PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL
#define	_PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL
#define	_PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL
#define	_PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL
#define	_PRS_CH_CTRL_SOURCESEL_UART0 0x00000029UL
#define	_PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL
#define	_PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL
#define	PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16)
#define	PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16)
#define	PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16)
#define	PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16)
#define	PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16)
#define	PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16)
#define	PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16)
#define	PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16)
#define	PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16)
#define	PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16)
#define	PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16)
#define	PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16)
#define	PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16)
#define	PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 16)
#define	PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16)
#define	PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16)
#define	_PRS_CH_CTRL_EDSEL_SHIFT 24
#define	_PRS_CH_CTRL_EDSEL_MASK 0x3000000UL
#define	_PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL
#define	_PRS_CH_CTRL_EDSEL_OFF 0x00000000UL
#define	_PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL
#define	_PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL
#define	_PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL
#define	PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24)
#define	PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24)
#define	PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24)
#define	PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24)
#define	PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24)
#define	_DMA_STATUS_RESETVALUE 0x10070000UL
#define	_DMA_STATUS_MASK 0xF01F00F1UL
#define	DMA_STATUS_EN (0x1UL << 0)
#define	_DMA_STATUS_EN_SHIFT 0
#define	_DMA_STATUS_EN_MASK 0x1UL
#define	_DMA_STATUS_EN_DEFAULT 0x00000000UL
#define	DMA_STATUS_EN_DEFAULT (_DMA_STATUS_EN_DEFAULT << 0)
#define	_DMA_STATUS_STATE_SHIFT 4
#define	_DMA_STATUS_STATE_MASK 0xF0UL
#define	_DMA_STATUS_STATE_DEFAULT 0x00000000UL
#define	_DMA_STATUS_STATE_IDLE 0x00000000UL
#define	_DMA_STATUS_STATE_RDCHCTRLDATA 0x00000001UL
#define	_DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL
#define	_DMA_STATUS_STATE_RDDSTENDPTR 0x00000003UL
#define	_DMA_STATUS_STATE_RDSRCDATA 0x00000004UL
#define	_DMA_STATUS_STATE_WRDSTDATA 0x00000005UL
#define	_DMA_STATUS_STATE_WAITREQCLR 0x00000006UL
#define	_DMA_STATUS_STATE_WRCHCTRLDATA 0x00000007UL
#define	_DMA_STATUS_STATE_STALLED 0x00000008UL
#define	_DMA_STATUS_STATE_DONE 0x00000009UL
#define	_DMA_STATUS_STATE_PERSCATTRANS 0x0000000AUL
#define	DMA_STATUS_STATE_DEFAULT (_DMA_STATUS_STATE_DEFAULT << 4)
#define	DMA_STATUS_STATE_IDLE (_DMA_STATUS_STATE_IDLE << 4)
#define	DMA_STATUS_STATE_RDCHCTRLDATA (_DMA_STATUS_STATE_RDCHCTRLDATA << 4)
#define	DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4)
#define	DMA_STATUS_STATE_RDDSTENDPTR (_DMA_STATUS_STATE_RDDSTENDPTR << 4)
#define	DMA_STATUS_STATE_RDSRCDATA (_DMA_STATUS_STATE_RDSRCDATA << 4)
#define	DMA_STATUS_STATE_WRDSTDATA (_DMA_STATUS_STATE_WRDSTDATA << 4)
#define	DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4)
#define	DMA_STATUS_STATE_WRCHCTRLDATA (_DMA_STATUS_STATE_WRCHCTRLDATA << 4)
#define	DMA_STATUS_STATE_STALLED (_DMA_STATUS_STATE_STALLED << 4)
#define	DMA_STATUS_STATE_DONE (_DMA_STATUS_STATE_DONE << 4)
#define	DMA_STATUS_STATE_PERSCATTRANS (_DMA_STATUS_STATE_PERSCATTRANS << 4)
#define	_DMA_STATUS_CHNUM_SHIFT 16
#define	_DMA_STATUS_CHNUM_MASK 0x1F0000UL
#define	_DMA_STATUS_CHNUM_DEFAULT 0x00000007UL
#define	DMA_STATUS_CHNUM_DEFAULT (_DMA_STATUS_CHNUM_DEFAULT << 16)
#define	_DMA_CONFIG_RESETVALUE 0x00000000UL
#define	_DMA_CONFIG_MASK 0x00000021UL
#define	DMA_CONFIG_EN (0x1UL << 0)
#define	_DMA_CONFIG_EN_SHIFT 0
#define	_DMA_CONFIG_EN_MASK 0x1UL
#define	_DMA_CONFIG_EN_DEFAULT 0x00000000UL
#define	DMA_CONFIG_EN_DEFAULT (_DMA_CONFIG_EN_DEFAULT << 0)
#define	DMA_CONFIG_CHPROT (0x1UL << 5)
#define	_DMA_CONFIG_CHPROT_SHIFT 5
#define	_DMA_CONFIG_CHPROT_MASK 0x20UL
#define	_DMA_CONFIG_CHPROT_DEFAULT 0x00000000UL
#define	DMA_CONFIG_CHPROT_DEFAULT (_DMA_CONFIG_CHPROT_DEFAULT << 5)
#define	_DMA_CTRLBASE_RESETVALUE 0x00000000UL
#define	_DMA_CTRLBASE_MASK 0xFFFFFFFFUL
#define	_DMA_CTRLBASE_CTRLBASE_SHIFT 0
#define	_DMA_CTRLBASE_CTRLBASE_MASK 0xFFFFFFFFUL
#define	_DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL
#define	DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0)
#define	_DMA_ALTCTRLBASE_RESETVALUE 0x00000080UL
#define	_DMA_ALTCTRLBASE_MASK 0xFFFFFFFFUL
#define	_DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT 0
#define	_DMA_ALTCTRLBASE_ALTCTRLBASE_MASK 0xFFFFFFFFUL
#define	_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT 0x00000080UL
#define	DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0)
#define	_DMA_CHWAITSTATUS_RESETVALUE 0x000000FFUL
#define	_DMA_CHWAITSTATUS_MASK 0x000000FFUL
#define	DMA_CHWAITSTATUS_CH0WAITSTATUS (0x1UL << 0)
#define	_DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT 0
#define	_DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK 0x1UL
#define	_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT 0x00000001UL
#define	DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0)
#define	DMA_CHWAITSTATUS_CH1WAITSTATUS (0x1UL << 1)
#define	_DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT 1
#define	_DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK 0x2UL
#define	_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT 0x00000001UL
#define	DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1)
#define	DMA_CHWAITSTATUS_CH2WAITSTATUS (0x1UL << 2)
#define	_DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT 2
#define	_DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK 0x4UL
#define	_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT 0x00000001UL
#define	DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2)
#define	DMA_CHWAITSTATUS_CH3WAITSTATUS (0x1UL << 3)
#define	_DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT 3
#define	_DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK 0x8UL
#define	_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT 0x00000001UL
#define	DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3)
#define	DMA_CHWAITSTATUS_CH4WAITSTATUS (0x1UL << 4)
#define	_DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT 4
#define	_DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK 0x10UL
#define	_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT 0x00000001UL
#define	DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4)
#define	DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5)
#define	_DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT 5
#define	_DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK 0x20UL
#define	_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT 0x00000001UL
#define	DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5)
#define	DMA_CHWAITSTATUS_CH6WAITSTATUS (0x1UL << 6)
#define	_DMA_CHWAITSTATUS_CH6WAITSTATUS_SHIFT 6
#define	_DMA_CHWAITSTATUS_CH6WAITSTATUS_MASK 0x40UL
#define	_DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT 0x00000001UL
#define	DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT << 6)
#define	DMA_CHWAITSTATUS_CH7WAITSTATUS (0x1UL << 7)
#define	_DMA_CHWAITSTATUS_CH7WAITSTATUS_SHIFT 7
#define	_DMA_CHWAITSTATUS_CH7WAITSTATUS_MASK 0x80UL
#define	_DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT 0x00000001UL
#define	DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT << 7)
#define	_DMA_CHSWREQ_RESETVALUE 0x00000000UL
#define	_DMA_CHSWREQ_MASK 0x000000FFUL
#define	DMA_CHSWREQ_CH0SWREQ (0x1UL << 0)
#define	_DMA_CHSWREQ_CH0SWREQ_SHIFT 0
#define	_DMA_CHSWREQ_CH0SWREQ_MASK 0x1UL
#define	_DMA_CHSWREQ_CH0SWREQ_DEFAULT 0x00000000UL
#define	DMA_CHSWREQ_CH0SWREQ_DEFAULT (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0)
#define	DMA_CHSWREQ_CH1SWREQ (0x1UL << 1)
#define	_DMA_CHSWREQ_CH1SWREQ_SHIFT 1
#define	_DMA_CHSWREQ_CH1SWREQ_MASK 0x2UL
#define	_DMA_CHSWREQ_CH1SWREQ_DEFAULT 0x00000000UL
#define	DMA_CHSWREQ_CH1SWREQ_DEFAULT (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1)
#define	DMA_CHSWREQ_CH2SWREQ (0x1UL << 2)
#define	_DMA_CHSWREQ_CH2SWREQ_SHIFT 2
#define	_DMA_CHSWREQ_CH2SWREQ_MASK 0x4UL
#define	_DMA_CHSWREQ_CH2SWREQ_DEFAULT 0x00000000UL
#define	DMA_CHSWREQ_CH2SWREQ_DEFAULT (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2)
#define	DMA_CHSWREQ_CH3SWREQ (0x1UL << 3)
#define	_DMA_CHSWREQ_CH3SWREQ_SHIFT 3
#define	_DMA_CHSWREQ_CH3SWREQ_MASK 0x8UL
#define	_DMA_CHSWREQ_CH3SWREQ_DEFAULT 0x00000000UL
#define	DMA_CHSWREQ_CH3SWREQ_DEFAULT (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3)
#define	DMA_CHSWREQ_CH4SWREQ (0x1UL << 4)
#define	_DMA_CHSWREQ_CH4SWREQ_SHIFT 4
#define	_DMA_CHSWREQ_CH4SWREQ_MASK 0x10UL
#define	_DMA_CHSWREQ_CH4SWREQ_DEFAULT 0x00000000UL
#define	DMA_CHSWREQ_CH4SWREQ_DEFAULT (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4)
#define	DMA_CHSWREQ_CH5SWREQ (0x1UL << 5)
#define	_DMA_CHSWREQ_CH5SWREQ_SHIFT 5
#define	_DMA_CHSWREQ_CH5SWREQ_MASK 0x20UL
#define	_DMA_CHSWREQ_CH5SWREQ_DEFAULT 0x00000000UL
#define	DMA_CHSWREQ_CH5SWREQ_DEFAULT (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5)
#define	DMA_CHSWREQ_CH6SWREQ (0x1UL << 6)
#define	_DMA_CHSWREQ_CH6SWREQ_SHIFT 6
#define	_DMA_CHSWREQ_CH6SWREQ_MASK 0x40UL
#define	_DMA_CHSWREQ_CH6SWREQ_DEFAULT 0x00000000UL
#define	DMA_CHSWREQ_CH6SWREQ_DEFAULT (_DMA_CHSWREQ_CH6SWREQ_DEFAULT << 6)
#define	DMA_CHSWREQ_CH7SWREQ (0x1UL << 7)
#define	_DMA_CHSWREQ_CH7SWREQ_SHIFT 7
#define	_DMA_CHSWREQ_CH7SWREQ_MASK 0x80UL
#define	_DMA_CHSWREQ_CH7SWREQ_DEFAULT 0x00000000UL
#define	DMA_CHSWREQ_CH7SWREQ_DEFAULT (_DMA_CHSWREQ_CH7SWREQ_DEFAULT << 7)
#define	_DMA_CHUSEBURSTS_RESETVALUE 0x00000000UL
#define	_DMA_CHUSEBURSTS_MASK 0x000000FFUL
#define	DMA_CHUSEBURSTS_CH0USEBURSTS (0x1UL << 0)
#define	_DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT 0
#define	_DMA_CHUSEBURSTS_CH0USEBURSTS_MASK 0x1UL
#define	_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT 0x00000000UL
#define	_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST 0x00000000UL
#define	_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY 0x00000001UL
#define	DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0)
#define	DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0)
#define	DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0)
#define	DMA_CHUSEBURSTS_CH1USEBURSTS (0x1UL << 1)
#define	_DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT 1
#define	_DMA_CHUSEBURSTS_CH1USEBURSTS_MASK 0x2UL
#define	_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT 0x00000000UL
#define	DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1)
#define	DMA_CHUSEBURSTS_CH2USEBURSTS (0x1UL << 2)
#define	_DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT 2
#define	_DMA_CHUSEBURSTS_CH2USEBURSTS_MASK 0x4UL
#define	_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT 0x00000000UL
#define	DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2)
#define	DMA_CHUSEBURSTS_CH3USEBURSTS (0x1UL << 3)
#define	_DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT 3
#define	_DMA_CHUSEBURSTS_CH3USEBURSTS_MASK 0x8UL
#define	_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT 0x00000000UL
#define	DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3)
#define	DMA_CHUSEBURSTS_CH4USEBURSTS (0x1UL << 4)
#define	_DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT 4
#define	_DMA_CHUSEBURSTS_CH4USEBURSTS_MASK 0x10UL
#define	_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT 0x00000000UL
#define	DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4)
#define	DMA_CHUSEBURSTS_CH5USEBURSTS (0x1UL << 5)
#define	_DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT 5
#define	_DMA_CHUSEBURSTS_CH5USEBURSTS_MASK 0x20UL
#define	_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT 0x00000000UL
#define	DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5)
#define	DMA_CHUSEBURSTS_CH6USEBURSTS (0x1UL << 6)
#define	_DMA_CHUSEBURSTS_CH6USEBURSTS_SHIFT 6
#define	_DMA_CHUSEBURSTS_CH6USEBURSTS_MASK 0x40UL
#define	_DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT 0x00000000UL
#define	DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT << 6)
#define	DMA_CHUSEBURSTS_CH7USEBURSTS (0x1UL << 7)
#define	_DMA_CHUSEBURSTS_CH7USEBURSTS_SHIFT 7
#define	_DMA_CHUSEBURSTS_CH7USEBURSTS_MASK 0x80UL
#define	_DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT 0x00000000UL
#define	DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT << 7)
#define	_DMA_CHUSEBURSTC_RESETVALUE 0x00000000UL
#define	_DMA_CHUSEBURSTC_MASK 0x000000FFUL
#define	DMA_CHUSEBURSTC_CH0USEBURSTC (0x1UL << 0)
#define	_DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT 0
#define	_DMA_CHUSEBURSTC_CH0USEBURSTC_MASK 0x1UL
#define	_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT 0x00000000UL
#define	DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0)
#define	DMA_CHUSEBURSTC_CH1USEBURSTC (0x1UL << 1)
#define	_DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT 1
#define	_DMA_CHUSEBURSTC_CH1USEBURSTC_MASK 0x2UL
#define	_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT 0x00000000UL
#define	DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1)
#define	DMA_CHUSEBURSTC_CH2USEBURSTC (0x1UL << 2)
#define	_DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT 2
#define	_DMA_CHUSEBURSTC_CH2USEBURSTC_MASK 0x4UL
#define	_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT 0x00000000UL
#define	DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2)
#define	DMA_CHUSEBURSTC_CH3USEBURSTC (0x1UL << 3)
#define	_DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT 3
#define	_DMA_CHUSEBURSTC_CH3USEBURSTC_MASK 0x8UL
#define	_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT 0x00000000UL
#define	DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3)
#define	DMA_CHUSEBURSTC_CH4USEBURSTC (0x1UL << 4)
#define	_DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT 4
#define	_DMA_CHUSEBURSTC_CH4USEBURSTC_MASK 0x10UL
#define	_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT 0x00000000UL
#define	DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4)
#define	DMA_CHUSEBURSTC_CH5USEBURSTC (0x1UL << 5)
#define	_DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT 5
#define	_DMA_CHUSEBURSTC_CH5USEBURSTC_MASK 0x20UL
#define	_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT 0x00000000UL
#define	DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5)
#define	DMA_CHUSEBURSTC_CH6USEBURSTC (0x1UL << 6)
#define	_DMA_CHUSEBURSTC_CH6USEBURSTC_SHIFT 6
#define	_DMA_CHUSEBURSTC_CH6USEBURSTC_MASK 0x40UL
#define	_DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT 0x00000000UL
#define	DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT << 6)
#define	DMA_CHUSEBURSTC_CH7USEBURSTC (0x1UL << 7)
#define	_DMA_CHUSEBURSTC_CH7USEBURSTC_SHIFT 7
#define	_DMA_CHUSEBURSTC_CH7USEBURSTC_MASK 0x80UL
#define	_DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT 0x00000000UL
#define	DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT << 7)
#define	_DMA_CHREQMASKS_RESETVALUE 0x00000000UL
#define	_DMA_CHREQMASKS_MASK 0x000000FFUL
#define	DMA_CHREQMASKS_CH0REQMASKS (0x1UL << 0)
#define	_DMA_CHREQMASKS_CH0REQMASKS_SHIFT 0
#define	_DMA_CHREQMASKS_CH0REQMASKS_MASK 0x1UL
#define	_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT 0x00000000UL
#define	DMA_CHREQMASKS_CH0REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0)
#define	DMA_CHREQMASKS_CH1REQMASKS (0x1UL << 1)
#define	_DMA_CHREQMASKS_CH1REQMASKS_SHIFT 1
#define	_DMA_CHREQMASKS_CH1REQMASKS_MASK 0x2UL
#define	_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT 0x00000000UL
#define	DMA_CHREQMASKS_CH1REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1)
#define	DMA_CHREQMASKS_CH2REQMASKS (0x1UL << 2)
#define	_DMA_CHREQMASKS_CH2REQMASKS_SHIFT 2
#define	_DMA_CHREQMASKS_CH2REQMASKS_MASK 0x4UL
#define	_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT 0x00000000UL
#define	DMA_CHREQMASKS_CH2REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2)
#define	DMA_CHREQMASKS_CH3REQMASKS (0x1UL << 3)
#define	_DMA_CHREQMASKS_CH3REQMASKS_SHIFT 3
#define	_DMA_CHREQMASKS_CH3REQMASKS_MASK 0x8UL
#define	_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT 0x00000000UL
#define	DMA_CHREQMASKS_CH3REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3)
#define	DMA_CHREQMASKS_CH4REQMASKS (0x1UL << 4)
#define	_DMA_CHREQMASKS_CH4REQMASKS_SHIFT 4
#define	_DMA_CHREQMASKS_CH4REQMASKS_MASK 0x10UL
#define	_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT 0x00000000UL
#define	DMA_CHREQMASKS_CH4REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4)
#define	DMA_CHREQMASKS_CH5REQMASKS (0x1UL << 5)
#define	_DMA_CHREQMASKS_CH5REQMASKS_SHIFT 5
#define	_DMA_CHREQMASKS_CH5REQMASKS_MASK 0x20UL
#define	_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT 0x00000000UL
#define	DMA_CHREQMASKS_CH5REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5)
#define	DMA_CHREQMASKS_CH6REQMASKS (0x1UL << 6)
#define	_DMA_CHREQMASKS_CH6REQMASKS_SHIFT 6
#define	_DMA_CHREQMASKS_CH6REQMASKS_MASK 0x40UL
#define	_DMA_CHREQMASKS_CH6REQMASKS_DEFAULT 0x00000000UL
#define	DMA_CHREQMASKS_CH6REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH6REQMASKS_DEFAULT << 6)
#define	DMA_CHREQMASKS_CH7REQMASKS (0x1UL << 7)
#define	_DMA_CHREQMASKS_CH7REQMASKS_SHIFT 7
#define	_DMA_CHREQMASKS_CH7REQMASKS_MASK 0x80UL
#define	_DMA_CHREQMASKS_CH7REQMASKS_DEFAULT 0x00000000UL
#define	DMA_CHREQMASKS_CH7REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH7REQMASKS_DEFAULT << 7)
#define	_DMA_CHREQMASKC_RESETVALUE 0x00000000UL
#define	_DMA_CHREQMASKC_MASK 0x000000FFUL
#define	DMA_CHREQMASKC_CH0REQMASKC (0x1UL << 0)
#define	_DMA_CHREQMASKC_CH0REQMASKC_SHIFT 0
#define	_DMA_CHREQMASKC_CH0REQMASKC_MASK 0x1UL
#define	_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT 0x00000000UL
#define	DMA_CHREQMASKC_CH0REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0)
#define	DMA_CHREQMASKC_CH1REQMASKC (0x1UL << 1)
#define	_DMA_CHREQMASKC_CH1REQMASKC_SHIFT 1
#define	_DMA_CHREQMASKC_CH1REQMASKC_MASK 0x2UL
#define	_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT 0x00000000UL
#define	DMA_CHREQMASKC_CH1REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1)
#define	DMA_CHREQMASKC_CH2REQMASKC (0x1UL << 2)
#define	_DMA_CHREQMASKC_CH2REQMASKC_SHIFT 2
#define	_DMA_CHREQMASKC_CH2REQMASKC_MASK 0x4UL
#define	_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT 0x00000000UL
#define	DMA_CHREQMASKC_CH2REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2)
#define	DMA_CHREQMASKC_CH3REQMASKC (0x1UL << 3)
#define	_DMA_CHREQMASKC_CH3REQMASKC_SHIFT 3
#define	_DMA_CHREQMASKC_CH3REQMASKC_MASK 0x8UL
#define	_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT 0x00000000UL
#define	DMA_CHREQMASKC_CH3REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3)
#define	DMA_CHREQMASKC_CH4REQMASKC (0x1UL << 4)
#define	_DMA_CHREQMASKC_CH4REQMASKC_SHIFT 4
#define	_DMA_CHREQMASKC_CH4REQMASKC_MASK 0x10UL
#define	_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT 0x00000000UL
#define	DMA_CHREQMASKC_CH4REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4)
#define	DMA_CHREQMASKC_CH5REQMASKC (0x1UL << 5)
#define	_DMA_CHREQMASKC_CH5REQMASKC_SHIFT 5
#define	_DMA_CHREQMASKC_CH5REQMASKC_MASK 0x20UL
#define	_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT 0x00000000UL
#define	DMA_CHREQMASKC_CH5REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5)
#define	DMA_CHREQMASKC_CH6REQMASKC (0x1UL << 6)
#define	_DMA_CHREQMASKC_CH6REQMASKC_SHIFT 6
#define	_DMA_CHREQMASKC_CH6REQMASKC_MASK 0x40UL
#define	_DMA_CHREQMASKC_CH6REQMASKC_DEFAULT 0x00000000UL
#define	DMA_CHREQMASKC_CH6REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH6REQMASKC_DEFAULT << 6)
#define	DMA_CHREQMASKC_CH7REQMASKC (0x1UL << 7)
#define	_DMA_CHREQMASKC_CH7REQMASKC_SHIFT 7
#define	_DMA_CHREQMASKC_CH7REQMASKC_MASK 0x80UL
#define	_DMA_CHREQMASKC_CH7REQMASKC_DEFAULT 0x00000000UL
#define	DMA_CHREQMASKC_CH7REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH7REQMASKC_DEFAULT << 7)
#define	_DMA_CHENS_RESETVALUE 0x00000000UL
#define	_DMA_CHENS_MASK 0x000000FFUL
#define	DMA_CHENS_CH0ENS (0x1UL << 0)
#define	_DMA_CHENS_CH0ENS_SHIFT 0
#define	_DMA_CHENS_CH0ENS_MASK 0x1UL
#define	_DMA_CHENS_CH0ENS_DEFAULT 0x00000000UL
#define	DMA_CHENS_CH0ENS_DEFAULT (_DMA_CHENS_CH0ENS_DEFAULT << 0)
#define	DMA_CHENS_CH1ENS (0x1UL << 1)
#define	_DMA_CHENS_CH1ENS_SHIFT 1
#define	_DMA_CHENS_CH1ENS_MASK 0x2UL
#define	_DMA_CHENS_CH1ENS_DEFAULT 0x00000000UL
#define	DMA_CHENS_CH1ENS_DEFAULT (_DMA_CHENS_CH1ENS_DEFAULT << 1)
#define	DMA_CHENS_CH2ENS (0x1UL << 2)
#define	_DMA_CHENS_CH2ENS_SHIFT 2
#define	_DMA_CHENS_CH2ENS_MASK 0x4UL
#define	_DMA_CHENS_CH2ENS_DEFAULT 0x00000000UL
#define	DMA_CHENS_CH2ENS_DEFAULT (_DMA_CHENS_CH2ENS_DEFAULT << 2)
#define	DMA_CHENS_CH3ENS (0x1UL << 3)
#define	_DMA_CHENS_CH3ENS_SHIFT 3
#define	_DMA_CHENS_CH3ENS_MASK 0x8UL
#define	_DMA_CHENS_CH3ENS_DEFAULT 0x00000000UL
#define	DMA_CHENS_CH3ENS_DEFAULT (_DMA_CHENS_CH3ENS_DEFAULT << 3)
#define	DMA_CHENS_CH4ENS (0x1UL << 4)
#define	_DMA_CHENS_CH4ENS_SHIFT 4
#define	_DMA_CHENS_CH4ENS_MASK 0x10UL
#define	_DMA_CHENS_CH4ENS_DEFAULT 0x00000000UL
#define	DMA_CHENS_CH4ENS_DEFAULT (_DMA_CHENS_CH4ENS_DEFAULT << 4)
#define	DMA_CHENS_CH5ENS (0x1UL << 5)
#define	_DMA_CHENS_CH5ENS_SHIFT 5
#define	_DMA_CHENS_CH5ENS_MASK 0x20UL
#define	_DMA_CHENS_CH5ENS_DEFAULT 0x00000000UL
#define	DMA_CHENS_CH5ENS_DEFAULT (_DMA_CHENS_CH5ENS_DEFAULT << 5)
#define	DMA_CHENS_CH6ENS (0x1UL << 6)
#define	_DMA_CHENS_CH6ENS_SHIFT 6
#define	_DMA_CHENS_CH6ENS_MASK 0x40UL
#define	_DMA_CHENS_CH6ENS_DEFAULT 0x00000000UL
#define	DMA_CHENS_CH6ENS_DEFAULT (_DMA_CHENS_CH6ENS_DEFAULT << 6)
#define	DMA_CHENS_CH7ENS (0x1UL << 7)
#define	_DMA_CHENS_CH7ENS_SHIFT 7
#define	_DMA_CHENS_CH7ENS_MASK 0x80UL
#define	_DMA_CHENS_CH7ENS_DEFAULT 0x00000000UL
#define	DMA_CHENS_CH7ENS_DEFAULT (_DMA_CHENS_CH7ENS_DEFAULT << 7)
#define	_DMA_CHENC_RESETVALUE 0x00000000UL
#define	_DMA_CHENC_MASK 0x000000FFUL
#define	DMA_CHENC_CH0ENC (0x1UL << 0)
#define	_DMA_CHENC_CH0ENC_SHIFT 0
#define	_DMA_CHENC_CH0ENC_MASK 0x1UL
#define	_DMA_CHENC_CH0ENC_DEFAULT 0x00000000UL
#define	DMA_CHENC_CH0ENC_DEFAULT (_DMA_CHENC_CH0ENC_DEFAULT << 0)
#define	DMA_CHENC_CH1ENC (0x1UL << 1)
#define	_DMA_CHENC_CH1ENC_SHIFT 1
#define	_DMA_CHENC_CH1ENC_MASK 0x2UL
#define	_DMA_CHENC_CH1ENC_DEFAULT 0x00000000UL
#define	DMA_CHENC_CH1ENC_DEFAULT (_DMA_CHENC_CH1ENC_DEFAULT << 1)
#define	DMA_CHENC_CH2ENC (0x1UL << 2)
#define	_DMA_CHENC_CH2ENC_SHIFT 2
#define	_DMA_CHENC_CH2ENC_MASK 0x4UL
#define	_DMA_CHENC_CH2ENC_DEFAULT 0x00000000UL
#define	DMA_CHENC_CH2ENC_DEFAULT (_DMA_CHENC_CH2ENC_DEFAULT << 2)
#define	DMA_CHENC_CH3ENC (0x1UL << 3)
#define	_DMA_CHENC_CH3ENC_SHIFT 3
#define	_DMA_CHENC_CH3ENC_MASK 0x8UL
#define	_DMA_CHENC_CH3ENC_DEFAULT 0x00000000UL
#define	DMA_CHENC_CH3ENC_DEFAULT (_DMA_CHENC_CH3ENC_DEFAULT << 3)
#define	DMA_CHENC_CH4ENC (0x1UL << 4)
#define	_DMA_CHENC_CH4ENC_SHIFT 4
#define	_DMA_CHENC_CH4ENC_MASK 0x10UL
#define	_DMA_CHENC_CH4ENC_DEFAULT 0x00000000UL
#define	DMA_CHENC_CH4ENC_DEFAULT (_DMA_CHENC_CH4ENC_DEFAULT << 4)
#define	DMA_CHENC_CH5ENC (0x1UL << 5)
#define	_DMA_CHENC_CH5ENC_SHIFT 5
#define	_DMA_CHENC_CH5ENC_MASK 0x20UL
#define	_DMA_CHENC_CH5ENC_DEFAULT 0x00000000UL
#define	DMA_CHENC_CH5ENC_DEFAULT (_DMA_CHENC_CH5ENC_DEFAULT << 5)
#define	DMA_CHENC_CH6ENC (0x1UL << 6)
#define	_DMA_CHENC_CH6ENC_SHIFT 6
#define	_DMA_CHENC_CH6ENC_MASK 0x40UL
#define	_DMA_CHENC_CH6ENC_DEFAULT 0x00000000UL
#define	DMA_CHENC_CH6ENC_DEFAULT (_DMA_CHENC_CH6ENC_DEFAULT << 6)
#define	DMA_CHENC_CH7ENC (0x1UL << 7)
#define	_DMA_CHENC_CH7ENC_SHIFT 7
#define	_DMA_CHENC_CH7ENC_MASK 0x80UL
#define	_DMA_CHENC_CH7ENC_DEFAULT 0x00000000UL
#define	DMA_CHENC_CH7ENC_DEFAULT (_DMA_CHENC_CH7ENC_DEFAULT << 7)
#define	_DMA_CHALTS_RESETVALUE 0x00000000UL
#define	_DMA_CHALTS_MASK 0x000000FFUL
#define	DMA_CHALTS_CH0ALTS (0x1UL << 0)
#define	_DMA_CHALTS_CH0ALTS_SHIFT 0
#define	_DMA_CHALTS_CH0ALTS_MASK 0x1UL
#define	_DMA_CHALTS_CH0ALTS_DEFAULT 0x00000000UL
#define	DMA_CHALTS_CH0ALTS_DEFAULT (_DMA_CHALTS_CH0ALTS_DEFAULT << 0)
#define	DMA_CHALTS_CH1ALTS (0x1UL << 1)
#define	_DMA_CHALTS_CH1ALTS_SHIFT 1
#define	_DMA_CHALTS_CH1ALTS_MASK 0x2UL
#define	_DMA_CHALTS_CH1ALTS_DEFAULT 0x00000000UL
#define	DMA_CHALTS_CH1ALTS_DEFAULT (_DMA_CHALTS_CH1ALTS_DEFAULT << 1)
#define	DMA_CHALTS_CH2ALTS (0x1UL << 2)
#define	_DMA_CHALTS_CH2ALTS_SHIFT 2
#define	_DMA_CHALTS_CH2ALTS_MASK 0x4UL
#define	_DMA_CHALTS_CH2ALTS_DEFAULT 0x00000000UL
#define	DMA_CHALTS_CH2ALTS_DEFAULT (_DMA_CHALTS_CH2ALTS_DEFAULT << 2)
#define	DMA_CHALTS_CH3ALTS (0x1UL << 3)
#define	_DMA_CHALTS_CH3ALTS_SHIFT 3
#define	_DMA_CHALTS_CH3ALTS_MASK 0x8UL
#define	_DMA_CHALTS_CH3ALTS_DEFAULT 0x00000000UL
#define	DMA_CHALTS_CH3ALTS_DEFAULT (_DMA_CHALTS_CH3ALTS_DEFAULT << 3)
#define	DMA_CHALTS_CH4ALTS (0x1UL << 4)
#define	_DMA_CHALTS_CH4ALTS_SHIFT 4
#define	_DMA_CHALTS_CH4ALTS_MASK 0x10UL
#define	_DMA_CHALTS_CH4ALTS_DEFAULT 0x00000000UL
#define	DMA_CHALTS_CH4ALTS_DEFAULT (_DMA_CHALTS_CH4ALTS_DEFAULT << 4)
#define	DMA_CHALTS_CH5ALTS (0x1UL << 5)
#define	_DMA_CHALTS_CH5ALTS_SHIFT 5
#define	_DMA_CHALTS_CH5ALTS_MASK 0x20UL
#define	_DMA_CHALTS_CH5ALTS_DEFAULT 0x00000000UL
#define	DMA_CHALTS_CH5ALTS_DEFAULT (_DMA_CHALTS_CH5ALTS_DEFAULT << 5)
#define	DMA_CHALTS_CH6ALTS (0x1UL << 6)
#define	_DMA_CHALTS_CH6ALTS_SHIFT 6
#define	_DMA_CHALTS_CH6ALTS_MASK 0x40UL
#define	_DMA_CHALTS_CH6ALTS_DEFAULT 0x00000000UL
#define	DMA_CHALTS_CH6ALTS_DEFAULT (_DMA_CHALTS_CH6ALTS_DEFAULT << 6)
#define	DMA_CHALTS_CH7ALTS (0x1UL << 7)
#define	_DMA_CHALTS_CH7ALTS_SHIFT 7
#define	_DMA_CHALTS_CH7ALTS_MASK 0x80UL
#define	_DMA_CHALTS_CH7ALTS_DEFAULT 0x00000000UL
#define	DMA_CHALTS_CH7ALTS_DEFAULT (_DMA_CHALTS_CH7ALTS_DEFAULT << 7)
#define	_DMA_CHALTC_RESETVALUE 0x00000000UL
#define	_DMA_CHALTC_MASK 0x000000FFUL
#define	DMA_CHALTC_CH0ALTC (0x1UL << 0)
#define	_DMA_CHALTC_CH0ALTC_SHIFT 0
#define	_DMA_CHALTC_CH0ALTC_MASK 0x1UL
#define	_DMA_CHALTC_CH0ALTC_DEFAULT 0x00000000UL
#define	DMA_CHALTC_CH0ALTC_DEFAULT (_DMA_CHALTC_CH0ALTC_DEFAULT << 0)
#define	DMA_CHALTC_CH1ALTC (0x1UL << 1)
#define	_DMA_CHALTC_CH1ALTC_SHIFT 1
#define	_DMA_CHALTC_CH1ALTC_MASK 0x2UL
#define	_DMA_CHALTC_CH1ALTC_DEFAULT 0x00000000UL
#define	DMA_CHALTC_CH1ALTC_DEFAULT (_DMA_CHALTC_CH1ALTC_DEFAULT << 1)
#define	DMA_CHALTC_CH2ALTC (0x1UL << 2)
#define	_DMA_CHALTC_CH2ALTC_SHIFT 2
#define	_DMA_CHALTC_CH2ALTC_MASK 0x4UL
#define	_DMA_CHALTC_CH2ALTC_DEFAULT 0x00000000UL
#define	DMA_CHALTC_CH2ALTC_DEFAULT (_DMA_CHALTC_CH2ALTC_DEFAULT << 2)
#define	DMA_CHALTC_CH3ALTC (0x1UL << 3)
#define	_DMA_CHALTC_CH3ALTC_SHIFT 3
#define	_DMA_CHALTC_CH3ALTC_MASK 0x8UL
#define	_DMA_CHALTC_CH3ALTC_DEFAULT 0x00000000UL
#define	DMA_CHALTC_CH3ALTC_DEFAULT (_DMA_CHALTC_CH3ALTC_DEFAULT << 3)
#define	DMA_CHALTC_CH4ALTC (0x1UL << 4)
#define	_DMA_CHALTC_CH4ALTC_SHIFT 4
#define	_DMA_CHALTC_CH4ALTC_MASK 0x10UL
#define	_DMA_CHALTC_CH4ALTC_DEFAULT 0x00000000UL
#define	DMA_CHALTC_CH4ALTC_DEFAULT (_DMA_CHALTC_CH4ALTC_DEFAULT << 4)
#define	DMA_CHALTC_CH5ALTC (0x1UL << 5)
#define	_DMA_CHALTC_CH5ALTC_SHIFT 5
#define	_DMA_CHALTC_CH5ALTC_MASK 0x20UL
#define	_DMA_CHALTC_CH5ALTC_DEFAULT 0x00000000UL
#define	DMA_CHALTC_CH5ALTC_DEFAULT (_DMA_CHALTC_CH5ALTC_DEFAULT << 5)
#define	DMA_CHALTC_CH6ALTC (0x1UL << 6)
#define	_DMA_CHALTC_CH6ALTC_SHIFT 6
#define	_DMA_CHALTC_CH6ALTC_MASK 0x40UL
#define	_DMA_CHALTC_CH6ALTC_DEFAULT 0x00000000UL
#define	DMA_CHALTC_CH6ALTC_DEFAULT (_DMA_CHALTC_CH6ALTC_DEFAULT << 6)
#define	DMA_CHALTC_CH7ALTC (0x1UL << 7)
#define	_DMA_CHALTC_CH7ALTC_SHIFT 7
#define	_DMA_CHALTC_CH7ALTC_MASK 0x80UL
#define	_DMA_CHALTC_CH7ALTC_DEFAULT 0x00000000UL
#define	DMA_CHALTC_CH7ALTC_DEFAULT (_DMA_CHALTC_CH7ALTC_DEFAULT << 7)
#define	_DMA_CHPRIS_RESETVALUE 0x00000000UL
#define	_DMA_CHPRIS_MASK 0x000000FFUL
#define	DMA_CHPRIS_CH0PRIS (0x1UL << 0)
#define	_DMA_CHPRIS_CH0PRIS_SHIFT 0
#define	_DMA_CHPRIS_CH0PRIS_MASK 0x1UL
#define	_DMA_CHPRIS_CH0PRIS_DEFAULT 0x00000000UL
#define	DMA_CHPRIS_CH0PRIS_DEFAULT (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0)
#define	DMA_CHPRIS_CH1PRIS (0x1UL << 1)
#define	_DMA_CHPRIS_CH1PRIS_SHIFT 1
#define	_DMA_CHPRIS_CH1PRIS_MASK 0x2UL
#define	_DMA_CHPRIS_CH1PRIS_DEFAULT 0x00000000UL
#define	DMA_CHPRIS_CH1PRIS_DEFAULT (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1)
#define	DMA_CHPRIS_CH2PRIS (0x1UL << 2)
#define	_DMA_CHPRIS_CH2PRIS_SHIFT 2
#define	_DMA_CHPRIS_CH2PRIS_MASK 0x4UL
#define	_DMA_CHPRIS_CH2PRIS_DEFAULT 0x00000000UL
#define	DMA_CHPRIS_CH2PRIS_DEFAULT (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2)
#define	DMA_CHPRIS_CH3PRIS (0x1UL << 3)
#define	_DMA_CHPRIS_CH3PRIS_SHIFT 3
#define	_DMA_CHPRIS_CH3PRIS_MASK 0x8UL
#define	_DMA_CHPRIS_CH3PRIS_DEFAULT 0x00000000UL
#define	DMA_CHPRIS_CH3PRIS_DEFAULT (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3)
#define	DMA_CHPRIS_CH4PRIS (0x1UL << 4)
#define	_DMA_CHPRIS_CH4PRIS_SHIFT 4
#define	_DMA_CHPRIS_CH4PRIS_MASK 0x10UL
#define	_DMA_CHPRIS_CH4PRIS_DEFAULT 0x00000000UL
#define	DMA_CHPRIS_CH4PRIS_DEFAULT (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4)
#define	DMA_CHPRIS_CH5PRIS (0x1UL << 5)
#define	_DMA_CHPRIS_CH5PRIS_SHIFT 5
#define	_DMA_CHPRIS_CH5PRIS_MASK 0x20UL
#define	_DMA_CHPRIS_CH5PRIS_DEFAULT 0x00000000UL
#define	DMA_CHPRIS_CH5PRIS_DEFAULT (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5)
#define	DMA_CHPRIS_CH6PRIS (0x1UL << 6)
#define	_DMA_CHPRIS_CH6PRIS_SHIFT 6
#define	_DMA_CHPRIS_CH6PRIS_MASK 0x40UL
#define	_DMA_CHPRIS_CH6PRIS_DEFAULT 0x00000000UL
#define	DMA_CHPRIS_CH6PRIS_DEFAULT (_DMA_CHPRIS_CH6PRIS_DEFAULT << 6)
#define	DMA_CHPRIS_CH7PRIS (0x1UL << 7)
#define	_DMA_CHPRIS_CH7PRIS_SHIFT 7
#define	_DMA_CHPRIS_CH7PRIS_MASK 0x80UL
#define	_DMA_CHPRIS_CH7PRIS_DEFAULT 0x00000000UL
#define	DMA_CHPRIS_CH7PRIS_DEFAULT (_DMA_CHPRIS_CH7PRIS_DEFAULT << 7)
#define	_DMA_CHPRIC_RESETVALUE 0x00000000UL
#define	_DMA_CHPRIC_MASK 0x000000FFUL
#define	DMA_CHPRIC_CH0PRIC (0x1UL << 0)
#define	_DMA_CHPRIC_CH0PRIC_SHIFT 0
#define	_DMA_CHPRIC_CH0PRIC_MASK 0x1UL
#define	_DMA_CHPRIC_CH0PRIC_DEFAULT 0x00000000UL
#define	DMA_CHPRIC_CH0PRIC_DEFAULT (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0)
#define	DMA_CHPRIC_CH1PRIC (0x1UL << 1)
#define	_DMA_CHPRIC_CH1PRIC_SHIFT 1
#define	_DMA_CHPRIC_CH1PRIC_MASK 0x2UL
#define	_DMA_CHPRIC_CH1PRIC_DEFAULT 0x00000000UL
#define	DMA_CHPRIC_CH1PRIC_DEFAULT (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1)
#define	DMA_CHPRIC_CH2PRIC (0x1UL << 2)
#define	_DMA_CHPRIC_CH2PRIC_SHIFT 2
#define	_DMA_CHPRIC_CH2PRIC_MASK 0x4UL
#define	_DMA_CHPRIC_CH2PRIC_DEFAULT 0x00000000UL
#define	DMA_CHPRIC_CH2PRIC_DEFAULT (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2)
#define	DMA_CHPRIC_CH3PRIC (0x1UL << 3)
#define	_DMA_CHPRIC_CH3PRIC_SHIFT 3
#define	_DMA_CHPRIC_CH3PRIC_MASK 0x8UL
#define	_DMA_CHPRIC_CH3PRIC_DEFAULT 0x00000000UL
#define	DMA_CHPRIC_CH3PRIC_DEFAULT (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3)
#define	DMA_CHPRIC_CH4PRIC (0x1UL << 4)
#define	_DMA_CHPRIC_CH4PRIC_SHIFT 4
#define	_DMA_CHPRIC_CH4PRIC_MASK 0x10UL
#define	_DMA_CHPRIC_CH4PRIC_DEFAULT 0x00000000UL
#define	DMA_CHPRIC_CH4PRIC_DEFAULT (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4)
#define	DMA_CHPRIC_CH5PRIC (0x1UL << 5)
#define	_DMA_CHPRIC_CH5PRIC_SHIFT 5
#define	_DMA_CHPRIC_CH5PRIC_MASK 0x20UL
#define	_DMA_CHPRIC_CH5PRIC_DEFAULT 0x00000000UL
#define	DMA_CHPRIC_CH5PRIC_DEFAULT (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5)
#define	DMA_CHPRIC_CH6PRIC (0x1UL << 6)
#define	_DMA_CHPRIC_CH6PRIC_SHIFT 6
#define	_DMA_CHPRIC_CH6PRIC_MASK 0x40UL
#define	_DMA_CHPRIC_CH6PRIC_DEFAULT 0x00000000UL
#define	DMA_CHPRIC_CH6PRIC_DEFAULT (_DMA_CHPRIC_CH6PRIC_DEFAULT << 6)
#define	DMA_CHPRIC_CH7PRIC (0x1UL << 7)
#define	_DMA_CHPRIC_CH7PRIC_SHIFT 7
#define	_DMA_CHPRIC_CH7PRIC_MASK 0x80UL
#define	_DMA_CHPRIC_CH7PRIC_DEFAULT 0x00000000UL
#define	DMA_CHPRIC_CH7PRIC_DEFAULT (_DMA_CHPRIC_CH7PRIC_DEFAULT << 7)
#define	_DMA_ERRORC_RESETVALUE 0x00000000UL
#define	_DMA_ERRORC_MASK 0x00000001UL
#define	DMA_ERRORC_ERRORC (0x1UL << 0)
#define	_DMA_ERRORC_ERRORC_SHIFT 0
#define	_DMA_ERRORC_ERRORC_MASK 0x1UL
#define	_DMA_ERRORC_ERRORC_DEFAULT 0x00000000UL
#define	DMA_ERRORC_ERRORC_DEFAULT (_DMA_ERRORC_ERRORC_DEFAULT << 0)
#define	_DMA_CHREQSTATUS_RESETVALUE 0x00000000UL
#define	_DMA_CHREQSTATUS_MASK 0x000000FFUL
#define	DMA_CHREQSTATUS_CH0REQSTATUS (0x1UL << 0)
#define	_DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT 0
#define	_DMA_CHREQSTATUS_CH0REQSTATUS_MASK 0x1UL
#define	_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT 0x00000000UL
#define	DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0)
#define	DMA_CHREQSTATUS_CH1REQSTATUS (0x1UL << 1)
#define	_DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT 1
#define	_DMA_CHREQSTATUS_CH1REQSTATUS_MASK 0x2UL
#define	_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT 0x00000000UL
#define	DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1)
#define	DMA_CHREQSTATUS_CH2REQSTATUS (0x1UL << 2)
#define	_DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT 2
#define	_DMA_CHREQSTATUS_CH2REQSTATUS_MASK 0x4UL
#define	_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT 0x00000000UL
#define	DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2)
#define	DMA_CHREQSTATUS_CH3REQSTATUS (0x1UL << 3)
#define	_DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT 3
#define	_DMA_CHREQSTATUS_CH3REQSTATUS_MASK 0x8UL
#define	_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT 0x00000000UL
#define	DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3)
#define	DMA_CHREQSTATUS_CH4REQSTATUS (0x1UL << 4)
#define	_DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT 4
#define	_DMA_CHREQSTATUS_CH4REQSTATUS_MASK 0x10UL
#define	_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT 0x00000000UL
#define	DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4)
#define	DMA_CHREQSTATUS_CH5REQSTATUS (0x1UL << 5)
#define	_DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT 5
#define	_DMA_CHREQSTATUS_CH5REQSTATUS_MASK 0x20UL
#define	_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT 0x00000000UL
#define	DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5)
#define	DMA_CHREQSTATUS_CH6REQSTATUS (0x1UL << 6)
#define	_DMA_CHREQSTATUS_CH6REQSTATUS_SHIFT 6
#define	_DMA_CHREQSTATUS_CH6REQSTATUS_MASK 0x40UL
#define	_DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT 0x00000000UL
#define	DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT << 6)
#define	DMA_CHREQSTATUS_CH7REQSTATUS (0x1UL << 7)
#define	_DMA_CHREQSTATUS_CH7REQSTATUS_SHIFT 7
#define	_DMA_CHREQSTATUS_CH7REQSTATUS_MASK 0x80UL
#define	_DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT 0x00000000UL
#define	DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT << 7)
#define	_DMA_CHSREQSTATUS_RESETVALUE 0x00000000UL
#define	_DMA_CHSREQSTATUS_MASK 0x000000FFUL
#define	DMA_CHSREQSTATUS_CH0SREQSTATUS (0x1UL << 0)
#define	_DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT 0
#define	_DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK 0x1UL
#define	_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT 0x00000000UL
#define	DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0)
#define	DMA_CHSREQSTATUS_CH1SREQSTATUS (0x1UL << 1)
#define	_DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT 1
#define	_DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK 0x2UL
#define	_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT 0x00000000UL
#define	DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1)
#define	DMA_CHSREQSTATUS_CH2SREQSTATUS (0x1UL << 2)
#define	_DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT 2
#define	_DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK 0x4UL
#define	_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT 0x00000000UL
#define	DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2)
#define	DMA_CHSREQSTATUS_CH3SREQSTATUS (0x1UL << 3)
#define	_DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT 3
#define	_DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK 0x8UL
#define	_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT 0x00000000UL
#define	DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3)
#define	DMA_CHSREQSTATUS_CH4SREQSTATUS (0x1UL << 4)
#define	_DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT 4
#define	_DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK 0x10UL
#define	_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT 0x00000000UL
#define	DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4)
#define	DMA_CHSREQSTATUS_CH5SREQSTATUS (0x1UL << 5)
#define	_DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT 5
#define	_DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK 0x20UL
#define	_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT 0x00000000UL
#define	DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5)
#define	DMA_CHSREQSTATUS_CH6SREQSTATUS (0x1UL << 6)
#define	_DMA_CHSREQSTATUS_CH6SREQSTATUS_SHIFT 6
#define	_DMA_CHSREQSTATUS_CH6SREQSTATUS_MASK 0x40UL
#define	_DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT 0x00000000UL
#define	DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT << 6)
#define	DMA_CHSREQSTATUS_CH7SREQSTATUS (0x1UL << 7)
#define	_DMA_CHSREQSTATUS_CH7SREQSTATUS_SHIFT 7
#define	_DMA_CHSREQSTATUS_CH7SREQSTATUS_MASK 0x80UL
#define	_DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT 0x00000000UL
#define	DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT << 7)
#define	_DMA_IF_RESETVALUE 0x00000000UL
#define	_DMA_IF_MASK 0x800000FFUL
#define	DMA_IF_CH0DONE (0x1UL << 0)
#define	_DMA_IF_CH0DONE_SHIFT 0
#define	_DMA_IF_CH0DONE_MASK 0x1UL
#define	_DMA_IF_CH0DONE_DEFAULT 0x00000000UL
#define	DMA_IF_CH0DONE_DEFAULT (_DMA_IF_CH0DONE_DEFAULT << 0)
#define	DMA_IF_CH1DONE (0x1UL << 1)
#define	_DMA_IF_CH1DONE_SHIFT 1
#define	_DMA_IF_CH1DONE_MASK 0x2UL
#define	_DMA_IF_CH1DONE_DEFAULT 0x00000000UL
#define	DMA_IF_CH1DONE_DEFAULT (_DMA_IF_CH1DONE_DEFAULT << 1)
#define	DMA_IF_CH2DONE (0x1UL << 2)
#define	_DMA_IF_CH2DONE_SHIFT 2
#define	_DMA_IF_CH2DONE_MASK 0x4UL
#define	_DMA_IF_CH2DONE_DEFAULT 0x00000000UL
#define	DMA_IF_CH2DONE_DEFAULT (_DMA_IF_CH2DONE_DEFAULT << 2)
#define	DMA_IF_CH3DONE (0x1UL << 3)
#define	_DMA_IF_CH3DONE_SHIFT 3
#define	_DMA_IF_CH3DONE_MASK 0x8UL
#define	_DMA_IF_CH3DONE_DEFAULT 0x00000000UL
#define	DMA_IF_CH3DONE_DEFAULT (_DMA_IF_CH3DONE_DEFAULT << 3)
#define	DMA_IF_CH4DONE (0x1UL << 4)
#define	_DMA_IF_CH4DONE_SHIFT 4
#define	_DMA_IF_CH4DONE_MASK 0x10UL
#define	_DMA_IF_CH4DONE_DEFAULT 0x00000000UL
#define	DMA_IF_CH4DONE_DEFAULT (_DMA_IF_CH4DONE_DEFAULT << 4)
#define	DMA_IF_CH5DONE (0x1UL << 5)
#define	_DMA_IF_CH5DONE_SHIFT 5
#define	_DMA_IF_CH5DONE_MASK 0x20UL
#define	_DMA_IF_CH5DONE_DEFAULT 0x00000000UL
#define	DMA_IF_CH5DONE_DEFAULT (_DMA_IF_CH5DONE_DEFAULT << 5)
#define	DMA_IF_CH6DONE (0x1UL << 6)
#define	_DMA_IF_CH6DONE_SHIFT 6
#define	_DMA_IF_CH6DONE_MASK 0x40UL
#define	_DMA_IF_CH6DONE_DEFAULT 0x00000000UL
#define	DMA_IF_CH6DONE_DEFAULT (_DMA_IF_CH6DONE_DEFAULT << 6)
#define	DMA_IF_CH7DONE (0x1UL << 7)
#define	_DMA_IF_CH7DONE_SHIFT 7
#define	_DMA_IF_CH7DONE_MASK 0x80UL
#define	_DMA_IF_CH7DONE_DEFAULT 0x00000000UL
#define	DMA_IF_CH7DONE_DEFAULT (_DMA_IF_CH7DONE_DEFAULT << 7)
#define	DMA_IF_ERR (0x1UL << 31)
#define	_DMA_IF_ERR_SHIFT 31
#define	_DMA_IF_ERR_MASK 0x80000000UL
#define	_DMA_IF_ERR_DEFAULT 0x00000000UL
#define	DMA_IF_ERR_DEFAULT (_DMA_IF_ERR_DEFAULT << 31)
#define	_DMA_IFS_RESETVALUE 0x00000000UL
#define	_DMA_IFS_MASK 0x800000FFUL
#define	DMA_IFS_CH0DONE (0x1UL << 0)
#define	_DMA_IFS_CH0DONE_SHIFT 0
#define	_DMA_IFS_CH0DONE_MASK 0x1UL
#define	_DMA_IFS_CH0DONE_DEFAULT 0x00000000UL
#define	DMA_IFS_CH0DONE_DEFAULT (_DMA_IFS_CH0DONE_DEFAULT << 0)
#define	DMA_IFS_CH1DONE (0x1UL << 1)
#define	_DMA_IFS_CH1DONE_SHIFT 1
#define	_DMA_IFS_CH1DONE_MASK 0x2UL
#define	_DMA_IFS_CH1DONE_DEFAULT 0x00000000UL
#define	DMA_IFS_CH1DONE_DEFAULT (_DMA_IFS_CH1DONE_DEFAULT << 1)
#define	DMA_IFS_CH2DONE (0x1UL << 2)
#define	_DMA_IFS_CH2DONE_SHIFT 2
#define	_DMA_IFS_CH2DONE_MASK 0x4UL
#define	_DMA_IFS_CH2DONE_DEFAULT 0x00000000UL
#define	DMA_IFS_CH2DONE_DEFAULT (_DMA_IFS_CH2DONE_DEFAULT << 2)
#define	DMA_IFS_CH3DONE (0x1UL << 3)
#define	_DMA_IFS_CH3DONE_SHIFT 3
#define	_DMA_IFS_CH3DONE_MASK 0x8UL
#define	_DMA_IFS_CH3DONE_DEFAULT 0x00000000UL
#define	DMA_IFS_CH3DONE_DEFAULT (_DMA_IFS_CH3DONE_DEFAULT << 3)
#define	DMA_IFS_CH4DONE (0x1UL << 4)
#define	_DMA_IFS_CH4DONE_SHIFT 4
#define	_DMA_IFS_CH4DONE_MASK 0x10UL
#define	_DMA_IFS_CH4DONE_DEFAULT 0x00000000UL
#define	DMA_IFS_CH4DONE_DEFAULT (_DMA_IFS_CH4DONE_DEFAULT << 4)
#define	DMA_IFS_CH5DONE (0x1UL << 5)
#define	_DMA_IFS_CH5DONE_SHIFT 5
#define	_DMA_IFS_CH5DONE_MASK 0x20UL
#define	_DMA_IFS_CH5DONE_DEFAULT 0x00000000UL
#define	DMA_IFS_CH5DONE_DEFAULT (_DMA_IFS_CH5DONE_DEFAULT << 5)
#define	DMA_IFS_CH6DONE (0x1UL << 6)
#define	_DMA_IFS_CH6DONE_SHIFT 6
#define	_DMA_IFS_CH6DONE_MASK 0x40UL
#define	_DMA_IFS_CH6DONE_DEFAULT 0x00000000UL
#define	DMA_IFS_CH6DONE_DEFAULT (_DMA_IFS_CH6DONE_DEFAULT << 6)
#define	DMA_IFS_CH7DONE (0x1UL << 7)
#define	_DMA_IFS_CH7DONE_SHIFT 7
#define	_DMA_IFS_CH7DONE_MASK 0x80UL
#define	_DMA_IFS_CH7DONE_DEFAULT 0x00000000UL
#define	DMA_IFS_CH7DONE_DEFAULT (_DMA_IFS_CH7DONE_DEFAULT << 7)
#define	DMA_IFS_ERR (0x1UL << 31)
#define	_DMA_IFS_ERR_SHIFT 31
#define	_DMA_IFS_ERR_MASK 0x80000000UL
#define	_DMA_IFS_ERR_DEFAULT 0x00000000UL
#define	DMA_IFS_ERR_DEFAULT (_DMA_IFS_ERR_DEFAULT << 31)
#define	_DMA_IFC_RESETVALUE 0x00000000UL
#define	_DMA_IFC_MASK 0x800000FFUL
#define	DMA_IFC_CH0DONE (0x1UL << 0)
#define	_DMA_IFC_CH0DONE_SHIFT 0
#define	_DMA_IFC_CH0DONE_MASK 0x1UL
#define	_DMA_IFC_CH0DONE_DEFAULT 0x00000000UL
#define	DMA_IFC_CH0DONE_DEFAULT (_DMA_IFC_CH0DONE_DEFAULT << 0)
#define	DMA_IFC_CH1DONE (0x1UL << 1)
#define	_DMA_IFC_CH1DONE_SHIFT 1
#define	_DMA_IFC_CH1DONE_MASK 0x2UL
#define	_DMA_IFC_CH1DONE_DEFAULT 0x00000000UL
#define	DMA_IFC_CH1DONE_DEFAULT (_DMA_IFC_CH1DONE_DEFAULT << 1)
#define	DMA_IFC_CH2DONE (0x1UL << 2)
#define	_DMA_IFC_CH2DONE_SHIFT 2
#define	_DMA_IFC_CH2DONE_MASK 0x4UL
#define	_DMA_IFC_CH2DONE_DEFAULT 0x00000000UL
#define	DMA_IFC_CH2DONE_DEFAULT (_DMA_IFC_CH2DONE_DEFAULT << 2)
#define	DMA_IFC_CH3DONE (0x1UL << 3)
#define	_DMA_IFC_CH3DONE_SHIFT 3
#define	_DMA_IFC_CH3DONE_MASK 0x8UL
#define	_DMA_IFC_CH3DONE_DEFAULT 0x00000000UL
#define	DMA_IFC_CH3DONE_DEFAULT (_DMA_IFC_CH3DONE_DEFAULT << 3)
#define	DMA_IFC_CH4DONE (0x1UL << 4)
#define	_DMA_IFC_CH4DONE_SHIFT 4
#define	_DMA_IFC_CH4DONE_MASK 0x10UL
#define	_DMA_IFC_CH4DONE_DEFAULT 0x00000000UL
#define	DMA_IFC_CH4DONE_DEFAULT (_DMA_IFC_CH4DONE_DEFAULT << 4)
#define	DMA_IFC_CH5DONE (0x1UL << 5)
#define	_DMA_IFC_CH5DONE_SHIFT 5
#define	_DMA_IFC_CH5DONE_MASK 0x20UL
#define	_DMA_IFC_CH5DONE_DEFAULT 0x00000000UL
#define	DMA_IFC_CH5DONE_DEFAULT (_DMA_IFC_CH5DONE_DEFAULT << 5)
#define	DMA_IFC_CH6DONE (0x1UL << 6)
#define	_DMA_IFC_CH6DONE_SHIFT 6
#define	_DMA_IFC_CH6DONE_MASK 0x40UL
#define	_DMA_IFC_CH6DONE_DEFAULT 0x00000000UL
#define	DMA_IFC_CH6DONE_DEFAULT (_DMA_IFC_CH6DONE_DEFAULT << 6)
#define	DMA_IFC_CH7DONE (0x1UL << 7)
#define	_DMA_IFC_CH7DONE_SHIFT 7
#define	_DMA_IFC_CH7DONE_MASK 0x80UL
#define	_DMA_IFC_CH7DONE_DEFAULT 0x00000000UL
#define	DMA_IFC_CH7DONE_DEFAULT (_DMA_IFC_CH7DONE_DEFAULT << 7)
#define	DMA_IFC_ERR (0x1UL << 31)
#define	_DMA_IFC_ERR_SHIFT 31
#define	_DMA_IFC_ERR_MASK 0x80000000UL
#define	_DMA_IFC_ERR_DEFAULT 0x00000000UL
#define	DMA_IFC_ERR_DEFAULT (_DMA_IFC_ERR_DEFAULT << 31)
#define	_DMA_IEN_RESETVALUE 0x00000000UL
#define	_DMA_IEN_MASK 0x800000FFUL
#define	DMA_IEN_CH0DONE (0x1UL << 0)
#define	_DMA_IEN_CH0DONE_SHIFT 0
#define	_DMA_IEN_CH0DONE_MASK 0x1UL
#define	_DMA_IEN_CH0DONE_DEFAULT 0x00000000UL
#define	DMA_IEN_CH0DONE_DEFAULT (_DMA_IEN_CH0DONE_DEFAULT << 0)
#define	DMA_IEN_CH1DONE (0x1UL << 1)
#define	_DMA_IEN_CH1DONE_SHIFT 1
#define	_DMA_IEN_CH1DONE_MASK 0x2UL
#define	_DMA_IEN_CH1DONE_DEFAULT 0x00000000UL
#define	DMA_IEN_CH1DONE_DEFAULT (_DMA_IEN_CH1DONE_DEFAULT << 1)
#define	DMA_IEN_CH2DONE (0x1UL << 2)
#define	_DMA_IEN_CH2DONE_SHIFT 2
#define	_DMA_IEN_CH2DONE_MASK 0x4UL
#define	_DMA_IEN_CH2DONE_DEFAULT 0x00000000UL
#define	DMA_IEN_CH2DONE_DEFAULT (_DMA_IEN_CH2DONE_DEFAULT << 2)
#define	DMA_IEN_CH3DONE (0x1UL << 3)
#define	_DMA_IEN_CH3DONE_SHIFT 3
#define	_DMA_IEN_CH3DONE_MASK 0x8UL
#define	_DMA_IEN_CH3DONE_DEFAULT 0x00000000UL
#define	DMA_IEN_CH3DONE_DEFAULT (_DMA_IEN_CH3DONE_DEFAULT << 3)
#define	DMA_IEN_CH4DONE (0x1UL << 4)
#define	_DMA_IEN_CH4DONE_SHIFT 4
#define	_DMA_IEN_CH4DONE_MASK 0x10UL
#define	_DMA_IEN_CH4DONE_DEFAULT 0x00000000UL
#define	DMA_IEN_CH4DONE_DEFAULT (_DMA_IEN_CH4DONE_DEFAULT << 4)
#define	DMA_IEN_CH5DONE (0x1UL << 5)
#define	_DMA_IEN_CH5DONE_SHIFT 5
#define	_DMA_IEN_CH5DONE_MASK 0x20UL
#define	_DMA_IEN_CH5DONE_DEFAULT 0x00000000UL
#define	DMA_IEN_CH5DONE_DEFAULT (_DMA_IEN_CH5DONE_DEFAULT << 5)
#define	DMA_IEN_CH6DONE (0x1UL << 6)
#define	_DMA_IEN_CH6DONE_SHIFT 6
#define	_DMA_IEN_CH6DONE_MASK 0x40UL
#define	_DMA_IEN_CH6DONE_DEFAULT 0x00000000UL
#define	DMA_IEN_CH6DONE_DEFAULT (_DMA_IEN_CH6DONE_DEFAULT << 6)
#define	DMA_IEN_CH7DONE (0x1UL << 7)
#define	_DMA_IEN_CH7DONE_SHIFT 7
#define	_DMA_IEN_CH7DONE_MASK 0x80UL
#define	_DMA_IEN_CH7DONE_DEFAULT 0x00000000UL
#define	DMA_IEN_CH7DONE_DEFAULT (_DMA_IEN_CH7DONE_DEFAULT << 7)
#define	DMA_IEN_ERR (0x1UL << 31)
#define	_DMA_IEN_ERR_SHIFT 31
#define	_DMA_IEN_ERR_MASK 0x80000000UL
#define	_DMA_IEN_ERR_DEFAULT 0x00000000UL
#define	DMA_IEN_ERR_DEFAULT (_DMA_IEN_ERR_DEFAULT << 31)
#define	_DMA_CH_CTRL_RESETVALUE 0x00000000UL
#define	_DMA_CH_CTRL_MASK 0x003F000FUL
#define	_DMA_CH_CTRL_SIGSEL_SHIFT 0
#define	_DMA_CH_CTRL_SIGSEL_MASK 0xFUL
#define	_DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV 0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_TIMER2UFOF 0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_AESDATAWR 0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL
#define	_DMA_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL
#define	_DMA_CH_CTRL_SIGSEL_USART0TXBL 0x00000001UL
#define	_DMA_CH_CTRL_SIGSEL_USART1TXBL 0x00000001UL
#define	_DMA_CH_CTRL_SIGSEL_USART2TXBL 0x00000001UL
#define	_DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL
#define	_DMA_CH_CTRL_SIGSEL_LEUART1TXBL 0x00000001UL
#define	_DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL
#define	_DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL
#define	_DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL
#define	_DMA_CH_CTRL_SIGSEL_TIMER2CC0 0x00000001UL
#define	_DMA_CH_CTRL_SIGSEL_UART0TXBL 0x00000001UL
#define	_DMA_CH_CTRL_SIGSEL_AESXORDATAWR 0x00000001UL
#define	_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY 0x00000002UL
#define	_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 0x00000002UL
#define	_DMA_CH_CTRL_SIGSEL_USART2TXEMPTY 0x00000002UL
#define	_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL
#define	_DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY 0x00000002UL
#define	_DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL
#define	_DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL
#define	_DMA_CH_CTRL_SIGSEL_TIMER2CC1 0x00000002UL
#define	_DMA_CH_CTRL_SIGSEL_UART0TXEMPTY 0x00000002UL
#define	_DMA_CH_CTRL_SIGSEL_AESDATARD 0x00000002UL
#define	_DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL
#define	_DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL
#define	_DMA_CH_CTRL_SIGSEL_TIMER2CC2 0x00000003UL
#define	_DMA_CH_CTRL_SIGSEL_AESKEYWR 0x00000003UL
#define	DMA_CH_CTRL_SIGSEL_ADC0SINGLE (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0)
#define	DMA_CH_CTRL_SIGSEL_DAC0CH0 (_DMA_CH_CTRL_SIGSEL_DAC0CH0 << 0)
#define	DMA_CH_CTRL_SIGSEL_USART0RXDATAV (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0)
#define	DMA_CH_CTRL_SIGSEL_USART1RXDATAV (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0)
#define	DMA_CH_CTRL_SIGSEL_USART2RXDATAV (_DMA_CH_CTRL_SIGSEL_USART2RXDATAV << 0)
#define	DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0)
#define	DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV << 0)
#define	DMA_CH_CTRL_SIGSEL_I2C0RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0)
#define	DMA_CH_CTRL_SIGSEL_TIMER0UFOF (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0)
#define	DMA_CH_CTRL_SIGSEL_TIMER1UFOF (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0)
#define	DMA_CH_CTRL_SIGSEL_TIMER2UFOF (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0)
#define	DMA_CH_CTRL_SIGSEL_UART0RXDATAV (_DMA_CH_CTRL_SIGSEL_UART0RXDATAV << 0)
#define	DMA_CH_CTRL_SIGSEL_MSCWDATA (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0)
#define	DMA_CH_CTRL_SIGSEL_AESDATAWR (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0)
#define	DMA_CH_CTRL_SIGSEL_ADC0SCAN (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0)
#define	DMA_CH_CTRL_SIGSEL_DAC0CH1 (_DMA_CH_CTRL_SIGSEL_DAC0CH1 << 0)
#define	DMA_CH_CTRL_SIGSEL_USART0TXBL (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0)
#define	DMA_CH_CTRL_SIGSEL_USART1TXBL (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0)
#define	DMA_CH_CTRL_SIGSEL_USART2TXBL (_DMA_CH_CTRL_SIGSEL_USART2TXBL << 0)
#define	DMA_CH_CTRL_SIGSEL_LEUART0TXBL (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0)
#define	DMA_CH_CTRL_SIGSEL_LEUART1TXBL (_DMA_CH_CTRL_SIGSEL_LEUART1TXBL << 0)
#define	DMA_CH_CTRL_SIGSEL_I2C0TXBL (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0)
#define	DMA_CH_CTRL_SIGSEL_TIMER0CC0 (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0)
#define	DMA_CH_CTRL_SIGSEL_TIMER1CC0 (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0)
#define	DMA_CH_CTRL_SIGSEL_TIMER2CC0 (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0)
#define	DMA_CH_CTRL_SIGSEL_UART0TXBL (_DMA_CH_CTRL_SIGSEL_UART0TXBL << 0)
#define	DMA_CH_CTRL_SIGSEL_AESXORDATAWR (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0)
#define	DMA_CH_CTRL_SIGSEL_USART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0)
#define	DMA_CH_CTRL_SIGSEL_USART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0)
#define	DMA_CH_CTRL_SIGSEL_USART2TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART2TXEMPTY << 0)
#define	DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0)
#define	DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY << 0)
#define	DMA_CH_CTRL_SIGSEL_TIMER0CC1 (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0)
#define	DMA_CH_CTRL_SIGSEL_TIMER1CC1 (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0)
#define	DMA_CH_CTRL_SIGSEL_TIMER2CC1 (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0)
#define	DMA_CH_CTRL_SIGSEL_UART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_UART0TXEMPTY << 0)
#define	DMA_CH_CTRL_SIGSEL_AESDATARD (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0)
#define	DMA_CH_CTRL_SIGSEL_TIMER0CC2 (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0)
#define	DMA_CH_CTRL_SIGSEL_TIMER1CC2 (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0)
#define	DMA_CH_CTRL_SIGSEL_TIMER2CC2 (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0)
#define	DMA_CH_CTRL_SIGSEL_AESKEYWR (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0)
#define	_DMA_CH_CTRL_SOURCESEL_SHIFT 16
#define	_DMA_CH_CTRL_SOURCESEL_MASK 0x3F0000UL
#define	_DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL
#define	_DMA_CH_CTRL_SOURCESEL_ADC0 0x00000008UL
#define	_DMA_CH_CTRL_SOURCESEL_DAC0 0x0000000AUL
#define	_DMA_CH_CTRL_SOURCESEL_USART0 0x0000000CUL
#define	_DMA_CH_CTRL_SOURCESEL_USART1 0x0000000DUL
#define	_DMA_CH_CTRL_SOURCESEL_USART2 0x0000000EUL
#define	_DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL
#define	_DMA_CH_CTRL_SOURCESEL_LEUART1 0x00000011UL
#define	_DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL
#define	_DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL
#define	_DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL
#define	_DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL
#define	_DMA_CH_CTRL_SOURCESEL_UART0 0x0000002CUL
#define	_DMA_CH_CTRL_SOURCESEL_MSC 0x00000030UL
#define	_DMA_CH_CTRL_SOURCESEL_AES 0x00000031UL
#define	DMA_CH_CTRL_SOURCESEL_NONE (_DMA_CH_CTRL_SOURCESEL_NONE << 16)
#define	DMA_CH_CTRL_SOURCESEL_ADC0 (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16)
#define	DMA_CH_CTRL_SOURCESEL_DAC0 (_DMA_CH_CTRL_SOURCESEL_DAC0 << 16)
#define	DMA_CH_CTRL_SOURCESEL_USART0 (_DMA_CH_CTRL_SOURCESEL_USART0 << 16)
#define	DMA_CH_CTRL_SOURCESEL_USART1 (_DMA_CH_CTRL_SOURCESEL_USART1 << 16)
#define	DMA_CH_CTRL_SOURCESEL_USART2 (_DMA_CH_CTRL_SOURCESEL_USART2 << 16)
#define	DMA_CH_CTRL_SOURCESEL_LEUART0 (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16)
#define	DMA_CH_CTRL_SOURCESEL_LEUART1 (_DMA_CH_CTRL_SOURCESEL_LEUART1 << 16)
#define	DMA_CH_CTRL_SOURCESEL_I2C0 (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16)
#define	DMA_CH_CTRL_SOURCESEL_TIMER0 (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16)
#define	DMA_CH_CTRL_SOURCESEL_TIMER1 (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16)
#define	DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16)
#define	DMA_CH_CTRL_SOURCESEL_UART0 (_DMA_CH_CTRL_SOURCESEL_UART0 << 16)
#define	DMA_CH_CTRL_SOURCESEL_MSC (_DMA_CH_CTRL_SOURCESEL_MSC << 16)
#define	DMA_CH_CTRL_SOURCESEL_AES (_DMA_CH_CTRL_SOURCESEL_AES << 16)
#define	_VCMP_CTRL_RESETVALUE 0x47000000UL
#define	_VCMP_CTRL_MASK 0x4F030715UL
#define	VCMP_CTRL_EN (0x1UL << 0)
#define	_VCMP_CTRL_EN_SHIFT 0
#define	_VCMP_CTRL_EN_MASK 0x1UL
#define	_VCMP_CTRL_EN_DEFAULT 0x00000000UL
#define	VCMP_CTRL_EN_DEFAULT (_VCMP_CTRL_EN_DEFAULT << 0)
#define	VCMP_CTRL_INACTVAL (0x1UL << 2)
#define	_VCMP_CTRL_INACTVAL_SHIFT 2
#define	_VCMP_CTRL_INACTVAL_MASK 0x4UL
#define	_VCMP_CTRL_INACTVAL_DEFAULT 0x00000000UL
#define	VCMP_CTRL_INACTVAL_DEFAULT (_VCMP_CTRL_INACTVAL_DEFAULT << 2)
#define	VCMP_CTRL_HYSTEN (0x1UL << 4)
#define	_VCMP_CTRL_HYSTEN_SHIFT 4
#define	_VCMP_CTRL_HYSTEN_MASK 0x10UL
#define	_VCMP_CTRL_HYSTEN_DEFAULT 0x00000000UL
#define	VCMP_CTRL_HYSTEN_DEFAULT (_VCMP_CTRL_HYSTEN_DEFAULT << 4)
#define	_VCMP_CTRL_WARMTIME_SHIFT 8
#define	_VCMP_CTRL_WARMTIME_MASK 0x700UL
#define	_VCMP_CTRL_WARMTIME_DEFAULT 0x00000000UL
#define	_VCMP_CTRL_WARMTIME_4CYCLES 0x00000000UL
#define	_VCMP_CTRL_WARMTIME_8CYCLES 0x00000001UL
#define	_VCMP_CTRL_WARMTIME_16CYCLES 0x00000002UL
#define	_VCMP_CTRL_WARMTIME_32CYCLES 0x00000003UL
#define	_VCMP_CTRL_WARMTIME_64CYCLES 0x00000004UL
#define	_VCMP_CTRL_WARMTIME_128CYCLES 0x00000005UL
#define	_VCMP_CTRL_WARMTIME_256CYCLES 0x00000006UL
#define	_VCMP_CTRL_WARMTIME_512CYCLES 0x00000007UL
#define	VCMP_CTRL_WARMTIME_DEFAULT (_VCMP_CTRL_WARMTIME_DEFAULT << 8)
#define	VCMP_CTRL_WARMTIME_4CYCLES (_VCMP_CTRL_WARMTIME_4CYCLES << 8)
#define	VCMP_CTRL_WARMTIME_8CYCLES (_VCMP_CTRL_WARMTIME_8CYCLES << 8)
#define	VCMP_CTRL_WARMTIME_16CYCLES (_VCMP_CTRL_WARMTIME_16CYCLES << 8)
#define	VCMP_CTRL_WARMTIME_32CYCLES (_VCMP_CTRL_WARMTIME_32CYCLES << 8)
#define	VCMP_CTRL_WARMTIME_64CYCLES (_VCMP_CTRL_WARMTIME_64CYCLES << 8)
#define	VCMP_CTRL_WARMTIME_128CYCLES (_VCMP_CTRL_WARMTIME_128CYCLES << 8)
#define	VCMP_CTRL_WARMTIME_256CYCLES (_VCMP_CTRL_WARMTIME_256CYCLES << 8)
#define	VCMP_CTRL_WARMTIME_512CYCLES (_VCMP_CTRL_WARMTIME_512CYCLES << 8)
#define	VCMP_CTRL_IRISE (0x1UL << 16)
#define	_VCMP_CTRL_IRISE_SHIFT 16
#define	_VCMP_CTRL_IRISE_MASK 0x10000UL
#define	_VCMP_CTRL_IRISE_DEFAULT 0x00000000UL
#define	VCMP_CTRL_IRISE_DEFAULT (_VCMP_CTRL_IRISE_DEFAULT << 16)
#define	VCMP_CTRL_IFALL (0x1UL << 17)
#define	_VCMP_CTRL_IFALL_SHIFT 17
#define	_VCMP_CTRL_IFALL_MASK 0x20000UL
#define	_VCMP_CTRL_IFALL_DEFAULT 0x00000000UL
#define	VCMP_CTRL_IFALL_DEFAULT (_VCMP_CTRL_IFALL_DEFAULT << 17)
#define	_VCMP_CTRL_BIASPROG_SHIFT 24
#define	_VCMP_CTRL_BIASPROG_MASK 0xF000000UL
#define	_VCMP_CTRL_BIASPROG_DEFAULT 0x00000007UL
#define	VCMP_CTRL_BIASPROG_DEFAULT (_VCMP_CTRL_BIASPROG_DEFAULT << 24)
#define	VCMP_CTRL_HALFBIAS (0x1UL << 30)
#define	_VCMP_CTRL_HALFBIAS_SHIFT 30
#define	_VCMP_CTRL_HALFBIAS_MASK 0x40000000UL
#define	_VCMP_CTRL_HALFBIAS_DEFAULT 0x00000001UL
#define	VCMP_CTRL_HALFBIAS_DEFAULT (_VCMP_CTRL_HALFBIAS_DEFAULT << 30)
#define	_VCMP_INPUTSEL_RESETVALUE 0x00000000UL
#define	_VCMP_INPUTSEL_MASK 0x0000013FUL
#define	_VCMP_INPUTSEL_TRIGLEVEL_SHIFT 0
#define	_VCMP_INPUTSEL_TRIGLEVEL_MASK 0x3FUL
#define	_VCMP_INPUTSEL_TRIGLEVEL_DEFAULT 0x00000000UL
#define	VCMP_INPUTSEL_TRIGLEVEL_DEFAULT (_VCMP_INPUTSEL_TRIGLEVEL_DEFAULT << 0)
#define	VCMP_INPUTSEL_LPREF (0x1UL << 8)
#define	_VCMP_INPUTSEL_LPREF_SHIFT 8
#define	_VCMP_INPUTSEL_LPREF_MASK 0x100UL
#define	_VCMP_INPUTSEL_LPREF_DEFAULT 0x00000000UL
#define	VCMP_INPUTSEL_LPREF_DEFAULT (_VCMP_INPUTSEL_LPREF_DEFAULT << 8)
#define	_VCMP_STATUS_RESETVALUE 0x00000000UL
#define	_VCMP_STATUS_MASK 0x00000003UL
#define	VCMP_STATUS_VCMPACT (0x1UL << 0)
#define	_VCMP_STATUS_VCMPACT_SHIFT 0
#define	_VCMP_STATUS_VCMPACT_MASK 0x1UL
#define	_VCMP_STATUS_VCMPACT_DEFAULT 0x00000000UL
#define	VCMP_STATUS_VCMPACT_DEFAULT (_VCMP_STATUS_VCMPACT_DEFAULT << 0)
#define	VCMP_STATUS_VCMPOUT (0x1UL << 1)
#define	_VCMP_STATUS_VCMPOUT_SHIFT 1
#define	_VCMP_STATUS_VCMPOUT_MASK 0x2UL
#define	_VCMP_STATUS_VCMPOUT_DEFAULT 0x00000000UL
#define	VCMP_STATUS_VCMPOUT_DEFAULT (_VCMP_STATUS_VCMPOUT_DEFAULT << 1)
#define	_VCMP_IEN_RESETVALUE 0x00000000UL
#define	_VCMP_IEN_MASK 0x00000003UL
#define	VCMP_IEN_EDGE (0x1UL << 0)
#define	_VCMP_IEN_EDGE_SHIFT 0
#define	_VCMP_IEN_EDGE_MASK 0x1UL
#define	_VCMP_IEN_EDGE_DEFAULT 0x00000000UL
#define	VCMP_IEN_EDGE_DEFAULT (_VCMP_IEN_EDGE_DEFAULT << 0)
#define	VCMP_IEN_WARMUP (0x1UL << 1)
#define	_VCMP_IEN_WARMUP_SHIFT 1
#define	_VCMP_IEN_WARMUP_MASK 0x2UL
#define	_VCMP_IEN_WARMUP_DEFAULT 0x00000000UL
#define	VCMP_IEN_WARMUP_DEFAULT (_VCMP_IEN_WARMUP_DEFAULT << 1)
#define	_VCMP_IF_RESETVALUE 0x00000000UL
#define	_VCMP_IF_MASK 0x00000003UL
#define	VCMP_IF_EDGE (0x1UL << 0)
#define	_VCMP_IF_EDGE_SHIFT 0
#define	_VCMP_IF_EDGE_MASK 0x1UL
#define	_VCMP_IF_EDGE_DEFAULT 0x00000000UL
#define	VCMP_IF_EDGE_DEFAULT (_VCMP_IF_EDGE_DEFAULT << 0)
#define	VCMP_IF_WARMUP (0x1UL << 1)
#define	_VCMP_IF_WARMUP_SHIFT 1
#define	_VCMP_IF_WARMUP_MASK 0x2UL
#define	_VCMP_IF_WARMUP_DEFAULT 0x00000000UL
#define	VCMP_IF_WARMUP_DEFAULT (_VCMP_IF_WARMUP_DEFAULT << 1)
#define	_VCMP_IFS_RESETVALUE 0x00000000UL
#define	_VCMP_IFS_MASK 0x00000003UL
#define	VCMP_IFS_EDGE (0x1UL << 0)
#define	_VCMP_IFS_EDGE_SHIFT 0
#define	_VCMP_IFS_EDGE_MASK 0x1UL
#define	_VCMP_IFS_EDGE_DEFAULT 0x00000000UL
#define	VCMP_IFS_EDGE_DEFAULT (_VCMP_IFS_EDGE_DEFAULT << 0)
#define	VCMP_IFS_WARMUP (0x1UL << 1)
#define	_VCMP_IFS_WARMUP_SHIFT 1
#define	_VCMP_IFS_WARMUP_MASK 0x2UL
#define	_VCMP_IFS_WARMUP_DEFAULT 0x00000000UL
#define	VCMP_IFS_WARMUP_DEFAULT (_VCMP_IFS_WARMUP_DEFAULT << 1)
#define	_VCMP_IFC_RESETVALUE 0x00000000UL
#define	_VCMP_IFC_MASK 0x00000003UL
#define	VCMP_IFC_EDGE (0x1UL << 0)
#define	_VCMP_IFC_EDGE_SHIFT 0
#define	_VCMP_IFC_EDGE_MASK 0x1UL
#define	_VCMP_IFC_EDGE_DEFAULT 0x00000000UL
#define	VCMP_IFC_EDGE_DEFAULT (_VCMP_IFC_EDGE_DEFAULT << 0)
#define	VCMP_IFC_WARMUP (0x1UL << 1)
#define	_VCMP_IFC_WARMUP_SHIFT 1
#define	_VCMP_IFC_WARMUP_MASK 0x2UL
#define	_VCMP_IFC_WARMUP_DEFAULT 0x00000000UL
#define	VCMP_IFC_WARMUP_DEFAULT (_VCMP_IFC_WARMUP_DEFAULT << 1)
#define	_LCD_CTRL_RESETVALUE 0x00000000UL
#define	_LCD_CTRL_MASK 0x00000007UL
#define	LCD_CTRL_EN (0x1UL << 0)
#define	_LCD_CTRL_EN_SHIFT 0
#define	_LCD_CTRL_EN_MASK 0x1UL
#define	_LCD_CTRL_EN_DEFAULT 0x00000000UL
#define	LCD_CTRL_EN_DEFAULT (_LCD_CTRL_EN_DEFAULT << 0)
#define	_LCD_CTRL_UDCTRL_SHIFT 1
#define	_LCD_CTRL_UDCTRL_MASK 0x6UL
#define	_LCD_CTRL_UDCTRL_DEFAULT 0x00000000UL
#define	_LCD_CTRL_UDCTRL_REGULAR 0x00000000UL
#define	_LCD_CTRL_UDCTRL_FCEVENT 0x00000001UL
#define	_LCD_CTRL_UDCTRL_FRAMESTART 0x00000002UL
#define	LCD_CTRL_UDCTRL_DEFAULT (_LCD_CTRL_UDCTRL_DEFAULT << 1)
#define	LCD_CTRL_UDCTRL_REGULAR (_LCD_CTRL_UDCTRL_REGULAR << 1)
#define	LCD_CTRL_UDCTRL_FCEVENT (_LCD_CTRL_UDCTRL_FCEVENT << 1)
#define	LCD_CTRL_UDCTRL_FRAMESTART (_LCD_CTRL_UDCTRL_FRAMESTART << 1)
#define	_LCD_DISPCTRL_RESETVALUE 0x000C1F00UL
#define	_LCD_DISPCTRL_MASK 0x001D9F1FUL
#define	_LCD_DISPCTRL_MUX_SHIFT 0
#define	_LCD_DISPCTRL_MUX_MASK 0x3UL
#define	_LCD_DISPCTRL_MUX_DEFAULT 0x00000000UL
#define	_LCD_DISPCTRL_MUX_STATIC 0x00000000UL
#define	_LCD_DISPCTRL_MUX_DUPLEX 0x00000001UL
#define	_LCD_DISPCTRL_MUX_TRIPLEX 0x00000002UL
#define	_LCD_DISPCTRL_MUX_QUADRUPLEX 0x00000003UL
#define	LCD_DISPCTRL_MUX_DEFAULT (_LCD_DISPCTRL_MUX_DEFAULT << 0)
#define	LCD_DISPCTRL_MUX_STATIC (_LCD_DISPCTRL_MUX_STATIC << 0)
#define	LCD_DISPCTRL_MUX_DUPLEX (_LCD_DISPCTRL_MUX_DUPLEX << 0)
#define	LCD_DISPCTRL_MUX_TRIPLEX (_LCD_DISPCTRL_MUX_TRIPLEX << 0)
#define	LCD_DISPCTRL_MUX_QUADRUPLEX (_LCD_DISPCTRL_MUX_QUADRUPLEX << 0)
#define	_LCD_DISPCTRL_BIAS_SHIFT 2
#define	_LCD_DISPCTRL_BIAS_MASK 0xCUL
#define	_LCD_DISPCTRL_BIAS_DEFAULT 0x00000000UL
#define	_LCD_DISPCTRL_BIAS_STATIC 0x00000000UL
#define	_LCD_DISPCTRL_BIAS_ONEHALF 0x00000001UL
#define	_LCD_DISPCTRL_BIAS_ONETHIRD 0x00000002UL
#define	LCD_DISPCTRL_BIAS_DEFAULT (_LCD_DISPCTRL_BIAS_DEFAULT << 2)
#define	LCD_DISPCTRL_BIAS_STATIC (_LCD_DISPCTRL_BIAS_STATIC << 2)
#define	LCD_DISPCTRL_BIAS_ONEHALF (_LCD_DISPCTRL_BIAS_ONEHALF << 2)
#define	LCD_DISPCTRL_BIAS_ONETHIRD (_LCD_DISPCTRL_BIAS_ONETHIRD << 2)
#define	LCD_DISPCTRL_WAVE (0x1UL << 4)
#define	_LCD_DISPCTRL_WAVE_SHIFT 4
#define	_LCD_DISPCTRL_WAVE_MASK 0x10UL
#define	_LCD_DISPCTRL_WAVE_DEFAULT 0x00000000UL
#define	_LCD_DISPCTRL_WAVE_LOWPOWER 0x00000000UL
#define	_LCD_DISPCTRL_WAVE_NORMAL 0x00000001UL
#define	LCD_DISPCTRL_WAVE_DEFAULT (_LCD_DISPCTRL_WAVE_DEFAULT << 4)
#define	LCD_DISPCTRL_WAVE_LOWPOWER (_LCD_DISPCTRL_WAVE_LOWPOWER << 4)
#define	LCD_DISPCTRL_WAVE_NORMAL (_LCD_DISPCTRL_WAVE_NORMAL << 4)
#define	_LCD_DISPCTRL_CONLEV_SHIFT 8
#define	_LCD_DISPCTRL_CONLEV_MASK 0x1F00UL
#define	_LCD_DISPCTRL_CONLEV_MIN 0x00000000UL
#define	_LCD_DISPCTRL_CONLEV_DEFAULT 0x0000001FUL
#define	_LCD_DISPCTRL_CONLEV_MAX 0x0000001FUL
#define	LCD_DISPCTRL_CONLEV_MIN (_LCD_DISPCTRL_CONLEV_MIN << 8)
#define	LCD_DISPCTRL_CONLEV_DEFAULT (_LCD_DISPCTRL_CONLEV_DEFAULT << 8)
#define	LCD_DISPCTRL_CONLEV_MAX (_LCD_DISPCTRL_CONLEV_MAX << 8)
#define	LCD_DISPCTRL_CONCONF (0x1UL << 15)
#define	_LCD_DISPCTRL_CONCONF_SHIFT 15
#define	_LCD_DISPCTRL_CONCONF_MASK 0x8000UL
#define	_LCD_DISPCTRL_CONCONF_DEFAULT 0x00000000UL
#define	_LCD_DISPCTRL_CONCONF_VLCD 0x00000000UL
#define	_LCD_DISPCTRL_CONCONF_GND 0x00000001UL
#define	LCD_DISPCTRL_CONCONF_DEFAULT (_LCD_DISPCTRL_CONCONF_DEFAULT << 15)
#define	LCD_DISPCTRL_CONCONF_VLCD (_LCD_DISPCTRL_CONCONF_VLCD << 15)
#define	LCD_DISPCTRL_CONCONF_GND (_LCD_DISPCTRL_CONCONF_GND << 15)
#define	LCD_DISPCTRL_VLCDSEL (0x1UL << 16)
#define	_LCD_DISPCTRL_VLCDSEL_SHIFT 16
#define	_LCD_DISPCTRL_VLCDSEL_MASK 0x10000UL
#define	_LCD_DISPCTRL_VLCDSEL_DEFAULT 0x00000000UL
#define	_LCD_DISPCTRL_VLCDSEL_VDD 0x00000000UL
#define	_LCD_DISPCTRL_VLCDSEL_VEXTBOOST 0x00000001UL
#define	LCD_DISPCTRL_VLCDSEL_DEFAULT (_LCD_DISPCTRL_VLCDSEL_DEFAULT << 16)
#define	LCD_DISPCTRL_VLCDSEL_VDD (_LCD_DISPCTRL_VLCDSEL_VDD << 16)
#define	LCD_DISPCTRL_VLCDSEL_VEXTBOOST (_LCD_DISPCTRL_VLCDSEL_VEXTBOOST << 16)
#define	_LCD_DISPCTRL_VBLEV_SHIFT 18
#define	_LCD_DISPCTRL_VBLEV_MASK 0x1C0000UL
#define	_LCD_DISPCTRL_VBLEV_LEVEL0 0x00000000UL
#define	_LCD_DISPCTRL_VBLEV_LEVEL1 0x00000001UL
#define	_LCD_DISPCTRL_VBLEV_LEVEL2 0x00000002UL
#define	_LCD_DISPCTRL_VBLEV_DEFAULT 0x00000003UL
#define	_LCD_DISPCTRL_VBLEV_LEVEL3 0x00000003UL
#define	_LCD_DISPCTRL_VBLEV_LEVEL4 0x00000004UL
#define	_LCD_DISPCTRL_VBLEV_LEVEL5 0x00000005UL
#define	_LCD_DISPCTRL_VBLEV_LEVEL6 0x00000006UL
#define	_LCD_DISPCTRL_VBLEV_LEVEL7 0x00000007UL
#define	LCD_DISPCTRL_VBLEV_LEVEL0 (_LCD_DISPCTRL_VBLEV_LEVEL0 << 18)
#define	LCD_DISPCTRL_VBLEV_LEVEL1 (_LCD_DISPCTRL_VBLEV_LEVEL1 << 18)
#define	LCD_DISPCTRL_VBLEV_LEVEL2 (_LCD_DISPCTRL_VBLEV_LEVEL2 << 18)
#define	LCD_DISPCTRL_VBLEV_DEFAULT (_LCD_DISPCTRL_VBLEV_DEFAULT << 18)
#define	LCD_DISPCTRL_VBLEV_LEVEL3 (_LCD_DISPCTRL_VBLEV_LEVEL3 << 18)
#define	LCD_DISPCTRL_VBLEV_LEVEL4 (_LCD_DISPCTRL_VBLEV_LEVEL4 << 18)
#define	LCD_DISPCTRL_VBLEV_LEVEL5 (_LCD_DISPCTRL_VBLEV_LEVEL5 << 18)
#define	LCD_DISPCTRL_VBLEV_LEVEL6 (_LCD_DISPCTRL_VBLEV_LEVEL6 << 18)
#define	LCD_DISPCTRL_VBLEV_LEVEL7 (_LCD_DISPCTRL_VBLEV_LEVEL7 << 18)
#define	_LCD_SEGEN_RESETVALUE 0x00000000UL
#define	_LCD_SEGEN_MASK 0x000003FFUL
#define	_LCD_SEGEN_SEGEN_SHIFT 0
#define	_LCD_SEGEN_SEGEN_MASK 0x3FFUL
#define	_LCD_SEGEN_SEGEN_DEFAULT 0x00000000UL
#define	LCD_SEGEN_SEGEN_DEFAULT (_LCD_SEGEN_SEGEN_DEFAULT << 0)
#define	_LCD_BACTRL_RESETVALUE 0x00000000UL
#define	_LCD_BACTRL_MASK 0x00FF01FFUL
#define	LCD_BACTRL_BLINKEN (0x1UL << 0)
#define	_LCD_BACTRL_BLINKEN_SHIFT 0
#define	_LCD_BACTRL_BLINKEN_MASK 0x1UL
#define	_LCD_BACTRL_BLINKEN_DEFAULT 0x00000000UL
#define	LCD_BACTRL_BLINKEN_DEFAULT (_LCD_BACTRL_BLINKEN_DEFAULT << 0)
#define	LCD_BACTRL_BLANK (0x1UL << 1)
#define	_LCD_BACTRL_BLANK_SHIFT 1
#define	_LCD_BACTRL_BLANK_MASK 0x2UL
#define	_LCD_BACTRL_BLANK_DEFAULT 0x00000000UL
#define	LCD_BACTRL_BLANK_DEFAULT (_LCD_BACTRL_BLANK_DEFAULT << 1)
#define	LCD_BACTRL_AEN (0x1UL << 2)
#define	_LCD_BACTRL_AEN_SHIFT 2
#define	_LCD_BACTRL_AEN_MASK 0x4UL
#define	_LCD_BACTRL_AEN_DEFAULT 0x00000000UL
#define	LCD_BACTRL_AEN_DEFAULT (_LCD_BACTRL_AEN_DEFAULT << 2)
#define	_LCD_BACTRL_AREGASC_SHIFT 3
#define	_LCD_BACTRL_AREGASC_MASK 0x18UL
#define	_LCD_BACTRL_AREGASC_DEFAULT 0x00000000UL
#define	_LCD_BACTRL_AREGASC_NOSHIFT 0x00000000UL
#define	_LCD_BACTRL_AREGASC_SHIFTLEFT 0x00000001UL
#define	_LCD_BACTRL_AREGASC_SHIFTRIGHT 0x00000002UL
#define	LCD_BACTRL_AREGASC_DEFAULT (_LCD_BACTRL_AREGASC_DEFAULT << 3)
#define	LCD_BACTRL_AREGASC_NOSHIFT (_LCD_BACTRL_AREGASC_NOSHIFT << 3)
#define	LCD_BACTRL_AREGASC_SHIFTLEFT (_LCD_BACTRL_AREGASC_SHIFTLEFT << 3)
#define	LCD_BACTRL_AREGASC_SHIFTRIGHT (_LCD_BACTRL_AREGASC_SHIFTRIGHT << 3)
#define	_LCD_BACTRL_AREGBSC_SHIFT 5
#define	_LCD_BACTRL_AREGBSC_MASK 0x60UL
#define	_LCD_BACTRL_AREGBSC_DEFAULT 0x00000000UL
#define	_LCD_BACTRL_AREGBSC_NOSHIFT 0x00000000UL
#define	_LCD_BACTRL_AREGBSC_SHIFTLEFT 0x00000001UL
#define	_LCD_BACTRL_AREGBSC_SHIFTRIGHT 0x00000002UL
#define	LCD_BACTRL_AREGBSC_DEFAULT (_LCD_BACTRL_AREGBSC_DEFAULT << 5)
#define	LCD_BACTRL_AREGBSC_NOSHIFT (_LCD_BACTRL_AREGBSC_NOSHIFT << 5)
#define	LCD_BACTRL_AREGBSC_SHIFTLEFT (_LCD_BACTRL_AREGBSC_SHIFTLEFT << 5)
#define	LCD_BACTRL_AREGBSC_SHIFTRIGHT (_LCD_BACTRL_AREGBSC_SHIFTRIGHT << 5)
#define	LCD_BACTRL_ALOGSEL (0x1UL << 7)
#define	_LCD_BACTRL_ALOGSEL_SHIFT 7
#define	_LCD_BACTRL_ALOGSEL_MASK 0x80UL
#define	_LCD_BACTRL_ALOGSEL_DEFAULT 0x00000000UL
#define	_LCD_BACTRL_ALOGSEL_AND 0x00000000UL
#define	_LCD_BACTRL_ALOGSEL_OR 0x00000001UL
#define	LCD_BACTRL_ALOGSEL_DEFAULT (_LCD_BACTRL_ALOGSEL_DEFAULT << 7)
#define	LCD_BACTRL_ALOGSEL_AND (_LCD_BACTRL_ALOGSEL_AND << 7)
#define	LCD_BACTRL_ALOGSEL_OR (_LCD_BACTRL_ALOGSEL_OR << 7)
#define	LCD_BACTRL_FCEN (0x1UL << 8)
#define	_LCD_BACTRL_FCEN_SHIFT 8
#define	_LCD_BACTRL_FCEN_MASK 0x100UL
#define	_LCD_BACTRL_FCEN_DEFAULT 0x00000000UL
#define	LCD_BACTRL_FCEN_DEFAULT (_LCD_BACTRL_FCEN_DEFAULT << 8)
#define	_LCD_BACTRL_FCPRESC_SHIFT 16
#define	_LCD_BACTRL_FCPRESC_MASK 0x30000UL
#define	_LCD_BACTRL_FCPRESC_DEFAULT 0x00000000UL
#define	_LCD_BACTRL_FCPRESC_DIV1 0x00000000UL
#define	_LCD_BACTRL_FCPRESC_DIV2 0x00000001UL
#define	_LCD_BACTRL_FCPRESC_DIV4 0x00000002UL
#define	_LCD_BACTRL_FCPRESC_DIV8 0x00000003UL
#define	LCD_BACTRL_FCPRESC_DEFAULT (_LCD_BACTRL_FCPRESC_DEFAULT << 16)
#define	LCD_BACTRL_FCPRESC_DIV1 (_LCD_BACTRL_FCPRESC_DIV1 << 16)
#define	LCD_BACTRL_FCPRESC_DIV2 (_LCD_BACTRL_FCPRESC_DIV2 << 16)
#define	LCD_BACTRL_FCPRESC_DIV4 (_LCD_BACTRL_FCPRESC_DIV4 << 16)
#define	LCD_BACTRL_FCPRESC_DIV8 (_LCD_BACTRL_FCPRESC_DIV8 << 16)
#define	_LCD_BACTRL_FCTOP_SHIFT 18
#define	_LCD_BACTRL_FCTOP_MASK 0xFC0000UL
#define	_LCD_BACTRL_FCTOP_DEFAULT 0x00000000UL
#define	LCD_BACTRL_FCTOP_DEFAULT (_LCD_BACTRL_FCTOP_DEFAULT << 18)
#define	_LCD_STATUS_RESETVALUE 0x00000000UL
#define	_LCD_STATUS_MASK 0x0000010FUL
#define	_LCD_STATUS_ASTATE_SHIFT 0
#define	_LCD_STATUS_ASTATE_MASK 0xFUL
#define	_LCD_STATUS_ASTATE_DEFAULT 0x00000000UL
#define	LCD_STATUS_ASTATE_DEFAULT (_LCD_STATUS_ASTATE_DEFAULT << 0)
#define	LCD_STATUS_BLINK (0x1UL << 8)
#define	_LCD_STATUS_BLINK_SHIFT 8
#define	_LCD_STATUS_BLINK_MASK 0x100UL
#define	_LCD_STATUS_BLINK_DEFAULT 0x00000000UL
#define	LCD_STATUS_BLINK_DEFAULT (_LCD_STATUS_BLINK_DEFAULT << 8)
#define	_LCD_AREGA_RESETVALUE 0x00000000UL
#define	_LCD_AREGA_MASK 0x000000FFUL
#define	_LCD_AREGA_AREGA_SHIFT 0
#define	_LCD_AREGA_AREGA_MASK 0xFFUL
#define	_LCD_AREGA_AREGA_DEFAULT 0x00000000UL
#define	LCD_AREGA_AREGA_DEFAULT (_LCD_AREGA_AREGA_DEFAULT << 0)
#define	_LCD_AREGB_RESETVALUE 0x00000000UL
#define	_LCD_AREGB_MASK 0x000000FFUL
#define	_LCD_AREGB_AREGB_SHIFT 0
#define	_LCD_AREGB_AREGB_MASK 0xFFUL
#define	_LCD_AREGB_AREGB_DEFAULT 0x00000000UL
#define	LCD_AREGB_AREGB_DEFAULT (_LCD_AREGB_AREGB_DEFAULT << 0)
#define	_LCD_IF_RESETVALUE 0x00000000UL
#define	_LCD_IF_MASK 0x00000001UL
#define	LCD_IF_FC (0x1UL << 0)
#define	_LCD_IF_FC_SHIFT 0
#define	_LCD_IF_FC_MASK 0x1UL
#define	_LCD_IF_FC_DEFAULT 0x00000000UL
#define	LCD_IF_FC_DEFAULT (_LCD_IF_FC_DEFAULT << 0)
#define	_LCD_IFS_RESETVALUE 0x00000000UL
#define	_LCD_IFS_MASK 0x00000001UL
#define	LCD_IFS_FC (0x1UL << 0)
#define	_LCD_IFS_FC_SHIFT 0
#define	_LCD_IFS_FC_MASK 0x1UL
#define	_LCD_IFS_FC_DEFAULT 0x00000000UL
#define	LCD_IFS_FC_DEFAULT (_LCD_IFS_FC_DEFAULT << 0)
#define	_LCD_IFC_RESETVALUE 0x00000000UL
#define	_LCD_IFC_MASK 0x00000001UL
#define	LCD_IFC_FC (0x1UL << 0)
#define	_LCD_IFC_FC_SHIFT 0
#define	_LCD_IFC_FC_MASK 0x1UL
#define	_LCD_IFC_FC_DEFAULT 0x00000000UL
#define	LCD_IFC_FC_DEFAULT (_LCD_IFC_FC_DEFAULT << 0)
#define	_LCD_IEN_RESETVALUE 0x00000000UL
#define	_LCD_IEN_MASK 0x00000001UL
#define	LCD_IEN_FC (0x1UL << 0)
#define	_LCD_IEN_FC_SHIFT 0
#define	_LCD_IEN_FC_MASK 0x1UL
#define	_LCD_IEN_FC_DEFAULT 0x00000000UL
#define	LCD_IEN_FC_DEFAULT (_LCD_IEN_FC_DEFAULT << 0)
#define	_LCD_SEGD0L_RESETVALUE 0x00000000UL
#define	_LCD_SEGD0L_MASK 0xFFFFFFFFUL
#define	_LCD_SEGD0L_SEGD0L_SHIFT 0
#define	_LCD_SEGD0L_SEGD0L_MASK 0xFFFFFFFFUL
#define	_LCD_SEGD0L_SEGD0L_DEFAULT 0x00000000UL
#define	LCD_SEGD0L_SEGD0L_DEFAULT (_LCD_SEGD0L_SEGD0L_DEFAULT << 0)
#define	_LCD_SEGD1L_RESETVALUE 0x00000000UL
#define	_LCD_SEGD1L_MASK 0xFFFFFFFFUL
#define	_LCD_SEGD1L_SEGD1L_SHIFT 0
#define	_LCD_SEGD1L_SEGD1L_MASK 0xFFFFFFFFUL
#define	_LCD_SEGD1L_SEGD1L_DEFAULT 0x00000000UL
#define	LCD_SEGD1L_SEGD1L_DEFAULT (_LCD_SEGD1L_SEGD1L_DEFAULT << 0)
#define	_LCD_SEGD2L_RESETVALUE 0x00000000UL
#define	_LCD_SEGD2L_MASK 0xFFFFFFFFUL
#define	_LCD_SEGD2L_SEGD2L_SHIFT 0
#define	_LCD_SEGD2L_SEGD2L_MASK 0xFFFFFFFFUL
#define	_LCD_SEGD2L_SEGD2L_DEFAULT 0x00000000UL
#define	LCD_SEGD2L_SEGD2L_DEFAULT (_LCD_SEGD2L_SEGD2L_DEFAULT << 0)
#define	_LCD_SEGD3L_RESETVALUE 0x00000000UL
#define	_LCD_SEGD3L_MASK 0xFFFFFFFFUL
#define	_LCD_SEGD3L_SEGD3L_SHIFT 0
#define	_LCD_SEGD3L_SEGD3L_MASK 0xFFFFFFFFUL
#define	_LCD_SEGD3L_SEGD3L_DEFAULT 0x00000000UL
#define	LCD_SEGD3L_SEGD3L_DEFAULT (_LCD_SEGD3L_SEGD3L_DEFAULT << 0)
#define	_LCD_SEGD0H_RESETVALUE 0x00000000UL
#define	_LCD_SEGD0H_MASK 0x000000FFUL
#define	_LCD_SEGD0H_SEGD0H_SHIFT 0
#define	_LCD_SEGD0H_SEGD0H_MASK 0xFFUL
#define	_LCD_SEGD0H_SEGD0H_DEFAULT 0x00000000UL
#define	LCD_SEGD0H_SEGD0H_DEFAULT (_LCD_SEGD0H_SEGD0H_DEFAULT << 0)
#define	_LCD_SEGD1H_RESETVALUE 0x00000000UL
#define	_LCD_SEGD1H_MASK 0x000000FFUL
#define	_LCD_SEGD1H_SEGD1H_SHIFT 0
#define	_LCD_SEGD1H_SEGD1H_MASK 0xFFUL
#define	_LCD_SEGD1H_SEGD1H_DEFAULT 0x00000000UL
#define	LCD_SEGD1H_SEGD1H_DEFAULT (_LCD_SEGD1H_SEGD1H_DEFAULT << 0)
#define	_LCD_SEGD2H_RESETVALUE 0x00000000UL
#define	_LCD_SEGD2H_MASK 0x000000FFUL
#define	_LCD_SEGD2H_SEGD2H_SHIFT 0
#define	_LCD_SEGD2H_SEGD2H_MASK 0xFFUL
#define	_LCD_SEGD2H_SEGD2H_DEFAULT 0x00000000UL
#define	LCD_SEGD2H_SEGD2H_DEFAULT (_LCD_SEGD2H_SEGD2H_DEFAULT << 0)
#define	_LCD_SEGD3H_RESETVALUE 0x00000000UL
#define	_LCD_SEGD3H_MASK 0x000000FFUL
#define	_LCD_SEGD3H_SEGD3H_SHIFT 0
#define	_LCD_SEGD3H_SEGD3H_MASK 0xFFUL
#define	_LCD_SEGD3H_SEGD3H_DEFAULT 0x00000000UL
#define	LCD_SEGD3H_SEGD3H_DEFAULT (_LCD_SEGD3H_SEGD3H_DEFAULT << 0)
#define	_LCD_FREEZE_RESETVALUE 0x00000000UL
#define	_LCD_FREEZE_MASK 0x00000001UL
#define	LCD_FREEZE_REGFREEZE (0x1UL << 0)
#define	_LCD_FREEZE_REGFREEZE_SHIFT 0
#define	_LCD_FREEZE_REGFREEZE_MASK 0x1UL
#define	_LCD_FREEZE_REGFREEZE_DEFAULT 0x00000000UL
#define	_LCD_FREEZE_REGFREEZE_UPDATE 0x00000000UL
#define	_LCD_FREEZE_REGFREEZE_FREEZE 0x00000001UL
#define	LCD_FREEZE_REGFREEZE_DEFAULT (_LCD_FREEZE_REGFREEZE_DEFAULT << 0)
#define	LCD_FREEZE_REGFREEZE_UPDATE (_LCD_FREEZE_REGFREEZE_UPDATE << 0)
#define	LCD_FREEZE_REGFREEZE_FREEZE (_LCD_FREEZE_REGFREEZE_FREEZE << 0)
#define	_LCD_SYNCBUSY_RESETVALUE 0x00000000UL
#define	_LCD_SYNCBUSY_MASK 0x00000FFFUL
#define	LCD_SYNCBUSY_CTRL (0x1UL << 0)
#define	_LCD_SYNCBUSY_CTRL_SHIFT 0
#define	_LCD_SYNCBUSY_CTRL_MASK 0x1UL
#define	_LCD_SYNCBUSY_CTRL_DEFAULT 0x00000000UL
#define	LCD_SYNCBUSY_CTRL_DEFAULT (_LCD_SYNCBUSY_CTRL_DEFAULT << 0)
#define	LCD_SYNCBUSY_BACTRL (0x1UL << 1)
#define	_LCD_SYNCBUSY_BACTRL_SHIFT 1
#define	_LCD_SYNCBUSY_BACTRL_MASK 0x2UL
#define	_LCD_SYNCBUSY_BACTRL_DEFAULT 0x00000000UL
#define	LCD_SYNCBUSY_BACTRL_DEFAULT (_LCD_SYNCBUSY_BACTRL_DEFAULT << 1)
#define	LCD_SYNCBUSY_AREGA (0x1UL << 2)
#define	_LCD_SYNCBUSY_AREGA_SHIFT 2
#define	_LCD_SYNCBUSY_AREGA_MASK 0x4UL
#define	_LCD_SYNCBUSY_AREGA_DEFAULT 0x00000000UL
#define	LCD_SYNCBUSY_AREGA_DEFAULT (_LCD_SYNCBUSY_AREGA_DEFAULT << 2)
#define	LCD_SYNCBUSY_AREGB (0x1UL << 3)
#define	_LCD_SYNCBUSY_AREGB_SHIFT 3
#define	_LCD_SYNCBUSY_AREGB_MASK 0x8UL
#define	_LCD_SYNCBUSY_AREGB_DEFAULT 0x00000000UL
#define	LCD_SYNCBUSY_AREGB_DEFAULT (_LCD_SYNCBUSY_AREGB_DEFAULT << 3)
#define	LCD_SYNCBUSY_SEGD0L (0x1UL << 4)
#define	_LCD_SYNCBUSY_SEGD0L_SHIFT 4
#define	_LCD_SYNCBUSY_SEGD0L_MASK 0x10UL
#define	_LCD_SYNCBUSY_SEGD0L_DEFAULT 0x00000000UL
#define	LCD_SYNCBUSY_SEGD0L_DEFAULT (_LCD_SYNCBUSY_SEGD0L_DEFAULT << 4)
#define	LCD_SYNCBUSY_SEGD1L (0x1UL << 5)
#define	_LCD_SYNCBUSY_SEGD1L_SHIFT 5
#define	_LCD_SYNCBUSY_SEGD1L_MASK 0x20UL
#define	_LCD_SYNCBUSY_SEGD1L_DEFAULT 0x00000000UL
#define	LCD_SYNCBUSY_SEGD1L_DEFAULT (_LCD_SYNCBUSY_SEGD1L_DEFAULT << 5)
#define	LCD_SYNCBUSY_SEGD2L (0x1UL << 6)
#define	_LCD_SYNCBUSY_SEGD2L_SHIFT 6
#define	_LCD_SYNCBUSY_SEGD2L_MASK 0x40UL
#define	_LCD_SYNCBUSY_SEGD2L_DEFAULT 0x00000000UL
#define	LCD_SYNCBUSY_SEGD2L_DEFAULT (_LCD_SYNCBUSY_SEGD2L_DEFAULT << 6)
#define	LCD_SYNCBUSY_SEGD3L (0x1UL << 7)
#define	_LCD_SYNCBUSY_SEGD3L_SHIFT 7
#define	_LCD_SYNCBUSY_SEGD3L_MASK 0x80UL
#define	_LCD_SYNCBUSY_SEGD3L_DEFAULT 0x00000000UL
#define	LCD_SYNCBUSY_SEGD3L_DEFAULT (_LCD_SYNCBUSY_SEGD3L_DEFAULT << 7)
#define	LCD_SYNCBUSY_SEGD0H (0x1UL << 8)
#define	_LCD_SYNCBUSY_SEGD0H_SHIFT 8
#define	_LCD_SYNCBUSY_SEGD0H_MASK 0x100UL
#define	_LCD_SYNCBUSY_SEGD0H_DEFAULT 0x00000000UL
#define	LCD_SYNCBUSY_SEGD0H_DEFAULT (_LCD_SYNCBUSY_SEGD0H_DEFAULT << 8)
#define	LCD_SYNCBUSY_SEGD1H (0x1UL << 9)
#define	_LCD_SYNCBUSY_SEGD1H_SHIFT 9
#define	_LCD_SYNCBUSY_SEGD1H_MASK 0x200UL
#define	_LCD_SYNCBUSY_SEGD1H_DEFAULT 0x00000000UL
#define	LCD_SYNCBUSY_SEGD1H_DEFAULT (_LCD_SYNCBUSY_SEGD1H_DEFAULT << 9)
#define	LCD_SYNCBUSY_SEGD2H (0x1UL << 10)
#define	_LCD_SYNCBUSY_SEGD2H_SHIFT 10
#define	_LCD_SYNCBUSY_SEGD2H_MASK 0x400UL
#define	_LCD_SYNCBUSY_SEGD2H_DEFAULT 0x00000000UL
#define	LCD_SYNCBUSY_SEGD2H_DEFAULT (_LCD_SYNCBUSY_SEGD2H_DEFAULT << 10)
#define	LCD_SYNCBUSY_SEGD3H (0x1UL << 11)
#define	_LCD_SYNCBUSY_SEGD3H_SHIFT 11
#define	_LCD_SYNCBUSY_SEGD3H_MASK 0x800UL
#define	_LCD_SYNCBUSY_SEGD3H_DEFAULT 0x00000000UL
#define	LCD_SYNCBUSY_SEGD3H_DEFAULT (_LCD_SYNCBUSY_SEGD3H_DEFAULT << 11)
#define	_RTC_CTRL_RESETVALUE 0x00000000UL
#define	_RTC_CTRL_MASK 0x00000007UL
#define	RTC_CTRL_EN (0x1UL << 0)
#define	_RTC_CTRL_EN_SHIFT 0
#define	_RTC_CTRL_EN_MASK 0x1UL
#define	_RTC_CTRL_EN_DEFAULT 0x00000000UL
#define	RTC_CTRL_EN_DEFAULT (_RTC_CTRL_EN_DEFAULT << 0)
#define	RTC_CTRL_DEBUGRUN (0x1UL << 1)
#define	_RTC_CTRL_DEBUGRUN_SHIFT 1
#define	_RTC_CTRL_DEBUGRUN_MASK 0x2UL
#define	_RTC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL
#define	RTC_CTRL_DEBUGRUN_DEFAULT (_RTC_CTRL_DEBUGRUN_DEFAULT << 1)
#define	RTC_CTRL_COMP0TOP (0x1UL << 2)
#define	_RTC_CTRL_COMP0TOP_SHIFT 2
#define	_RTC_CTRL_COMP0TOP_MASK 0x4UL
#define	_RTC_CTRL_COMP0TOP_DEFAULT 0x00000000UL
#define	_RTC_CTRL_COMP0TOP_DISABLE 0x00000000UL
#define	_RTC_CTRL_COMP0TOP_ENABLE 0x00000001UL
#define	RTC_CTRL_COMP0TOP_DEFAULT (_RTC_CTRL_COMP0TOP_DEFAULT << 2)
#define	RTC_CTRL_COMP0TOP_DISABLE (_RTC_CTRL_COMP0TOP_DISABLE << 2)
#define	RTC_CTRL_COMP0TOP_ENABLE (_RTC_CTRL_COMP0TOP_ENABLE << 2)
#define	_RTC_CNT_RESETVALUE 0x00000000UL
#define	_RTC_CNT_MASK 0x00FFFFFFUL
#define	_RTC_CNT_CNT_SHIFT 0
#define	_RTC_CNT_CNT_MASK 0xFFFFFFUL
#define	_RTC_CNT_CNT_DEFAULT 0x00000000UL
#define	RTC_CNT_CNT_DEFAULT (_RTC_CNT_CNT_DEFAULT << 0)
#define	_RTC_COMP0_RESETVALUE 0x00000000UL
#define	_RTC_COMP0_MASK 0x00FFFFFFUL
#define	_RTC_COMP0_COMP0_SHIFT 0
#define	_RTC_COMP0_COMP0_MASK 0xFFFFFFUL
#define	_RTC_COMP0_COMP0_DEFAULT 0x00000000UL
#define	RTC_COMP0_COMP0_DEFAULT (_RTC_COMP0_COMP0_DEFAULT << 0)
#define	_RTC_COMP1_RESETVALUE 0x00000000UL
#define	_RTC_COMP1_MASK 0x00FFFFFFUL
#define	_RTC_COMP1_COMP1_SHIFT 0
#define	_RTC_COMP1_COMP1_MASK 0xFFFFFFUL
#define	_RTC_COMP1_COMP1_DEFAULT 0x00000000UL
#define	RTC_COMP1_COMP1_DEFAULT (_RTC_COMP1_COMP1_DEFAULT << 0)
#define	_RTC_IF_RESETVALUE 0x00000000UL
#define	_RTC_IF_MASK 0x00000007UL
#define	RTC_IF_OF (0x1UL << 0)
#define	_RTC_IF_OF_SHIFT 0
#define	_RTC_IF_OF_MASK 0x1UL
#define	_RTC_IF_OF_DEFAULT 0x00000000UL
#define	RTC_IF_OF_DEFAULT (_RTC_IF_OF_DEFAULT << 0)
#define	RTC_IF_COMP0 (0x1UL << 1)
#define	_RTC_IF_COMP0_SHIFT 1
#define	_RTC_IF_COMP0_MASK 0x2UL
#define	_RTC_IF_COMP0_DEFAULT 0x00000000UL
#define	RTC_IF_COMP0_DEFAULT (_RTC_IF_COMP0_DEFAULT << 1)
#define	RTC_IF_COMP1 (0x1UL << 2)
#define	_RTC_IF_COMP1_SHIFT 2
#define	_RTC_IF_COMP1_MASK 0x4UL
#define	_RTC_IF_COMP1_DEFAULT 0x00000000UL
#define	RTC_IF_COMP1_DEFAULT (_RTC_IF_COMP1_DEFAULT << 2)
#define	_RTC_IFS_RESETVALUE 0x00000000UL
#define	_RTC_IFS_MASK 0x00000007UL
#define	RTC_IFS_OF (0x1UL << 0)
#define	_RTC_IFS_OF_SHIFT 0
#define	_RTC_IFS_OF_MASK 0x1UL
#define	_RTC_IFS_OF_DEFAULT 0x00000000UL
#define	RTC_IFS_OF_DEFAULT (_RTC_IFS_OF_DEFAULT << 0)
#define	RTC_IFS_COMP0 (0x1UL << 1)
#define	_RTC_IFS_COMP0_SHIFT 1
#define	_RTC_IFS_COMP0_MASK 0x2UL
#define	_RTC_IFS_COMP0_DEFAULT 0x00000000UL
#define	RTC_IFS_COMP0_DEFAULT (_RTC_IFS_COMP0_DEFAULT << 1)
#define	RTC_IFS_COMP1 (0x1UL << 2)
#define	_RTC_IFS_COMP1_SHIFT 2
#define	_RTC_IFS_COMP1_MASK 0x4UL
#define	_RTC_IFS_COMP1_DEFAULT 0x00000000UL
#define	RTC_IFS_COMP1_DEFAULT (_RTC_IFS_COMP1_DEFAULT << 2)
#define	_RTC_IFC_RESETVALUE 0x00000000UL
#define	_RTC_IFC_MASK 0x00000007UL
#define	RTC_IFC_OF (0x1UL << 0)
#define	_RTC_IFC_OF_SHIFT 0
#define	_RTC_IFC_OF_MASK 0x1UL
#define	_RTC_IFC_OF_DEFAULT 0x00000000UL
#define	RTC_IFC_OF_DEFAULT (_RTC_IFC_OF_DEFAULT << 0)
#define	RTC_IFC_COMP0 (0x1UL << 1)
#define	_RTC_IFC_COMP0_SHIFT 1
#define	_RTC_IFC_COMP0_MASK 0x2UL
#define	_RTC_IFC_COMP0_DEFAULT 0x00000000UL
#define	RTC_IFC_COMP0_DEFAULT (_RTC_IFC_COMP0_DEFAULT << 1)
#define	RTC_IFC_COMP1 (0x1UL << 2)
#define	_RTC_IFC_COMP1_SHIFT 2
#define	_RTC_IFC_COMP1_MASK 0x4UL
#define	_RTC_IFC_COMP1_DEFAULT 0x00000000UL
#define	RTC_IFC_COMP1_DEFAULT (_RTC_IFC_COMP1_DEFAULT << 2)
#define	_RTC_IEN_RESETVALUE 0x00000000UL
#define	_RTC_IEN_MASK 0x00000007UL
#define	RTC_IEN_OF (0x1UL << 0)
#define	_RTC_IEN_OF_SHIFT 0
#define	_RTC_IEN_OF_MASK 0x1UL
#define	_RTC_IEN_OF_DEFAULT 0x00000000UL
#define	RTC_IEN_OF_DEFAULT (_RTC_IEN_OF_DEFAULT << 0)
#define	RTC_IEN_COMP0 (0x1UL << 1)
#define	_RTC_IEN_COMP0_SHIFT 1
#define	_RTC_IEN_COMP0_MASK 0x2UL
#define	_RTC_IEN_COMP0_DEFAULT 0x00000000UL
#define	RTC_IEN_COMP0_DEFAULT (_RTC_IEN_COMP0_DEFAULT << 1)
#define	RTC_IEN_COMP1 (0x1UL << 2)
#define	_RTC_IEN_COMP1_SHIFT 2
#define	_RTC_IEN_COMP1_MASK 0x4UL
#define	_RTC_IEN_COMP1_DEFAULT 0x00000000UL
#define	RTC_IEN_COMP1_DEFAULT (_RTC_IEN_COMP1_DEFAULT << 2)
#define	_RTC_FREEZE_RESETVALUE 0x00000000UL
#define	_RTC_FREEZE_MASK 0x00000001UL
#define	RTC_FREEZE_REGFREEZE (0x1UL << 0)
#define	_RTC_FREEZE_REGFREEZE_SHIFT 0
#define	_RTC_FREEZE_REGFREEZE_MASK 0x1UL
#define	_RTC_FREEZE_REGFREEZE_DEFAULT 0x00000000UL
#define	_RTC_FREEZE_REGFREEZE_UPDATE 0x00000000UL
#define	_RTC_FREEZE_REGFREEZE_FREEZE 0x00000001UL
#define	RTC_FREEZE_REGFREEZE_DEFAULT (_RTC_FREEZE_REGFREEZE_DEFAULT << 0)
#define	RTC_FREEZE_REGFREEZE_UPDATE (_RTC_FREEZE_REGFREEZE_UPDATE << 0)
#define	RTC_FREEZE_REGFREEZE_FREEZE (_RTC_FREEZE_REGFREEZE_FREEZE << 0)
#define	_RTC_SYNCBUSY_RESETVALUE 0x00000000UL
#define	_RTC_SYNCBUSY_MASK 0x00000007UL
#define	RTC_SYNCBUSY_CTRL (0x1UL << 0)
#define	_RTC_SYNCBUSY_CTRL_SHIFT 0
#define	_RTC_SYNCBUSY_CTRL_MASK 0x1UL
#define	_RTC_SYNCBUSY_CTRL_DEFAULT 0x00000000UL
#define	RTC_SYNCBUSY_CTRL_DEFAULT (_RTC_SYNCBUSY_CTRL_DEFAULT << 0)
#define	RTC_SYNCBUSY_COMP0 (0x1UL << 1)
#define	_RTC_SYNCBUSY_COMP0_SHIFT 1
#define	_RTC_SYNCBUSY_COMP0_MASK 0x2UL
#define	_RTC_SYNCBUSY_COMP0_DEFAULT 0x00000000UL
#define	RTC_SYNCBUSY_COMP0_DEFAULT (_RTC_SYNCBUSY_COMP0_DEFAULT << 1)
#define	RTC_SYNCBUSY_COMP1 (0x1UL << 2)
#define	_RTC_SYNCBUSY_COMP1_SHIFT 2
#define	_RTC_SYNCBUSY_COMP1_MASK 0x4UL
#define	_RTC_SYNCBUSY_COMP1_DEFAULT 0x00000000UL
#define	RTC_SYNCBUSY_COMP1_DEFAULT (_RTC_SYNCBUSY_COMP1_DEFAULT << 2)
#define	_WDOG_CTRL_RESETVALUE 0x00000F00UL
#define	_WDOG_CTRL_MASK 0x00003F7FUL
#define	WDOG_CTRL_EN (0x1UL << 0)
#define	_WDOG_CTRL_EN_SHIFT 0
#define	_WDOG_CTRL_EN_MASK 0x1UL
#define	_WDOG_CTRL_EN_DEFAULT 0x00000000UL
#define	WDOG_CTRL_EN_DEFAULT (_WDOG_CTRL_EN_DEFAULT << 0)
#define	WDOG_CTRL_DEBUGRUN (0x1UL << 1)
#define	_WDOG_CTRL_DEBUGRUN_SHIFT 1
#define	_WDOG_CTRL_DEBUGRUN_MASK 0x2UL
#define	_WDOG_CTRL_DEBUGRUN_DEFAULT 0x00000000UL
#define	WDOG_CTRL_DEBUGRUN_DEFAULT (_WDOG_CTRL_DEBUGRUN_DEFAULT << 1)
#define	WDOG_CTRL_EM2RUN (0x1UL << 2)
#define	_WDOG_CTRL_EM2RUN_SHIFT 2
#define	_WDOG_CTRL_EM2RUN_MASK 0x4UL
#define	_WDOG_CTRL_EM2RUN_DEFAULT 0x00000000UL
#define	WDOG_CTRL_EM2RUN_DEFAULT (_WDOG_CTRL_EM2RUN_DEFAULT << 2)
#define	WDOG_CTRL_EM3RUN (0x1UL << 3)
#define	_WDOG_CTRL_EM3RUN_SHIFT 3
#define	_WDOG_CTRL_EM3RUN_MASK 0x8UL
#define	_WDOG_CTRL_EM3RUN_DEFAULT 0x00000000UL
#define	WDOG_CTRL_EM3RUN_DEFAULT (_WDOG_CTRL_EM3RUN_DEFAULT << 3)
#define	WDOG_CTRL_LOCK (0x1UL << 4)
#define	_WDOG_CTRL_LOCK_SHIFT 4
#define	_WDOG_CTRL_LOCK_MASK 0x10UL
#define	_WDOG_CTRL_LOCK_DEFAULT 0x00000000UL
#define	WDOG_CTRL_LOCK_DEFAULT (_WDOG_CTRL_LOCK_DEFAULT << 4)
#define	WDOG_CTRL_EM4BLOCK (0x1UL << 5)
#define	_WDOG_CTRL_EM4BLOCK_SHIFT 5
#define	_WDOG_CTRL_EM4BLOCK_MASK 0x20UL
#define	_WDOG_CTRL_EM4BLOCK_DEFAULT 0x00000000UL
#define	WDOG_CTRL_EM4BLOCK_DEFAULT (_WDOG_CTRL_EM4BLOCK_DEFAULT << 5)
#define	WDOG_CTRL_SWOSCBLOCK (0x1UL << 6)
#define	_WDOG_CTRL_SWOSCBLOCK_SHIFT 6
#define	_WDOG_CTRL_SWOSCBLOCK_MASK 0x40UL
#define	_WDOG_CTRL_SWOSCBLOCK_DEFAULT 0x00000000UL
#define	WDOG_CTRL_SWOSCBLOCK_DEFAULT (_WDOG_CTRL_SWOSCBLOCK_DEFAULT << 6)
#define	_WDOG_CTRL_PERSEL_SHIFT 8
#define	_WDOG_CTRL_PERSEL_MASK 0xF00UL
#define	_WDOG_CTRL_PERSEL_DEFAULT 0x0000000FUL
#define	WDOG_CTRL_PERSEL_DEFAULT (_WDOG_CTRL_PERSEL_DEFAULT << 8)
#define	_WDOG_CTRL_CLKSEL_SHIFT 12
#define	_WDOG_CTRL_CLKSEL_MASK 0x3000UL
#define	_WDOG_CTRL_CLKSEL_DEFAULT 0x00000000UL
#define	_WDOG_CTRL_CLKSEL_ULFRCO 0x00000000UL
#define	_WDOG_CTRL_CLKSEL_LFRCO 0x00000001UL
#define	_WDOG_CTRL_CLKSEL_LFXO 0x00000002UL
#define	WDOG_CTRL_CLKSEL_DEFAULT (_WDOG_CTRL_CLKSEL_DEFAULT << 12)
#define	WDOG_CTRL_CLKSEL_ULFRCO (_WDOG_CTRL_CLKSEL_ULFRCO << 12)
#define	WDOG_CTRL_CLKSEL_LFRCO (_WDOG_CTRL_CLKSEL_LFRCO << 12)
#define	WDOG_CTRL_CLKSEL_LFXO (_WDOG_CTRL_CLKSEL_LFXO << 12)
#define	_WDOG_CMD_RESETVALUE 0x00000000UL
#define	_WDOG_CMD_MASK 0x00000001UL
#define	WDOG_CMD_CLEAR (0x1UL << 0)
#define	_WDOG_CMD_CLEAR_SHIFT 0
#define	_WDOG_CMD_CLEAR_MASK 0x1UL
#define	_WDOG_CMD_CLEAR_DEFAULT 0x00000000UL
#define	_WDOG_CMD_CLEAR_UNCHANGED 0x00000000UL
#define	_WDOG_CMD_CLEAR_CLEARED 0x00000001UL
#define	WDOG_CMD_CLEAR_DEFAULT (_WDOG_CMD_CLEAR_DEFAULT << 0)
#define	WDOG_CMD_CLEAR_UNCHANGED (_WDOG_CMD_CLEAR_UNCHANGED << 0)
#define	WDOG_CMD_CLEAR_CLEARED (_WDOG_CMD_CLEAR_CLEARED << 0)
#define	_WDOG_SYNCBUSY_RESETVALUE 0x00000000UL
#define	_WDOG_SYNCBUSY_MASK 0x00000003UL
#define	WDOG_SYNCBUSY_CTRL (0x1UL << 0)
#define	_WDOG_SYNCBUSY_CTRL_SHIFT 0
#define	_WDOG_SYNCBUSY_CTRL_MASK 0x1UL
#define	_WDOG_SYNCBUSY_CTRL_DEFAULT 0x00000000UL
#define	WDOG_SYNCBUSY_CTRL_DEFAULT (_WDOG_SYNCBUSY_CTRL_DEFAULT << 0)
#define	WDOG_SYNCBUSY_CMD (0x1UL << 1)
#define	_WDOG_SYNCBUSY_CMD_SHIFT 1
#define	_WDOG_SYNCBUSY_CMD_MASK 0x2UL
#define	_WDOG_SYNCBUSY_CMD_DEFAULT 0x00000000UL
#define	WDOG_SYNCBUSY_CMD_DEFAULT (_WDOG_SYNCBUSY_CMD_DEFAULT << 1)
#define	_DEVINFO_CAL_CRC_MASK 0x0000FFFFUL
#define	_DEVINFO_CAL_CRC_SHIFT 0
#define	_DEVINFO_CAL_TEMP_MASK 0x00FF0000UL
#define	_DEVINFO_CAL_TEMP_SHIFT 16
#define	_DEVINFO_ADC0CAL0_1V25_GAIN_MASK 0x00007F00UL
#define	_DEVINFO_ADC0CAL0_1V25_GAIN_SHIFT 8
#define	_DEVINFO_ADC0CAL0_1V25_OFFSET_MASK 0x0000007FUL
#define	_DEVINFO_ADC0CAL0_1V25_OFFSET_SHIFT 0
#define	_DEVINFO_ADC0CAL0_2V5_GAIN_MASK 0x7F000000UL
#define	_DEVINFO_ADC0CAL0_2V5_GAIN_SHIFT 24
#define	_DEVINFO_ADC0CAL0_2V5_OFFSET_MASK 0x007F0000UL
#define	_DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT 16
#define	_DEVINFO_ADC0CAL1_VDD_GAIN_MASK 0x00007F00UL
#define	_DEVINFO_ADC0CAL1_VDD_GAIN_SHIFT 8
#define	_DEVINFO_ADC0CAL1_VDD_OFFSET_MASK 0x0000007FUL
#define	_DEVINFO_ADC0CAL1_VDD_OFFSET_SHIFT 0
#define	_DEVINFO_ADC0CAL1_5VDIFF_GAIN_MASK 0x7F000000UL
#define	_DEVINFO_ADC0CAL1_5VDIFF_GAIN_SHIFT 24
#define	_DEVINFO_ADC0CAL1_5VDIFF_OFFSET_MASK 0x007F0000UL
#define	_DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT 16
#define	_DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_MASK 0x0000007FUL
#define	_DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT 0
#define	_DEVINFO_ADC0CAL2_TEMP1V25_MASK 0xFFF00000UL
#define	_DEVINFO_ADC0CAL2_TEMP1V25_SHIFT 20
#define	_DEVINFO_DAC0CAL0_1V25_GAIN_MASK 0x007F0000UL
#define	_DEVINFO_DAC0CAL0_1V25_GAIN_SHIFT 16
#define	_DEVINFO_DAC0CAL0_1V25_CH1_OFFSET_MASK 0x00003F00UL
#define	_DEVINFO_DAC0CAL0_1V25_CH1_OFFSET_SHIFT 8
#define	_DEVINFO_DAC0CAL0_1V25_CH0_OFFSET_MASK 0x0000003FUL
#define	_DEVINFO_DAC0CAL0_1V25_CH0_OFFSET_SHIFT 0
#define	_DEVINFO_DAC0CAL1_2V5_GAIN_MASK 0x007F0000UL
#define	_DEVINFO_DAC0CAL1_2V5_GAIN_SHIFT 16
#define	_DEVINFO_DAC0CAL1_2V5_CH1_OFFSET_MASK 0x00003F00UL
#define	_DEVINFO_DAC0CAL1_2V5_CH1_OFFSET_SHIFT 8
#define	_DEVINFO_DAC0CAL1_2V5_CH0_OFFSET_MASK 0x0000003FUL
#define	_DEVINFO_DAC0CAL1_2V5_CH0_OFFSET_SHIFT 0
#define	_DEVINFO_DAC0CAL2_VDD_GAIN_MASK 0x007F0000UL
#define	_DEVINFO_DAC0CAL2_VDD_GAIN_SHIFT 16
#define	_DEVINFO_DAC0CAL2_VDD_CH1_OFFSET_MASK 0x00003F00UL
#define	_DEVINFO_DAC0CAL2_VDD_CH1_OFFSET_SHIFT 8
#define	_DEVINFO_DAC0CAL2_VDD_CH0_OFFSET_MASK 0x0000003FUL
#define	_DEVINFO_DAC0CAL2_VDD_CH0_OFFSET_SHIFT 0
#define	_DEVINFO_HFRCOCAL0_BAND1_MASK 0x000000FFUL
#define	_DEVINFO_HFRCOCAL0_BAND1_SHIFT 0
#define	_DEVINFO_HFRCOCAL0_BAND7_MASK 0x0000FF00UL
#define	_DEVINFO_HFRCOCAL0_BAND7_SHIFT 8
#define	_DEVINFO_HFRCOCAL0_BAND11_MASK 0x00FF0000UL
#define	_DEVINFO_HFRCOCAL0_BAND11_SHIFT 16
#define	_DEVINFO_HFRCOCAL0_BAND14_MASK 0xFF000000UL
#define	_DEVINFO_HFRCOCAL0_BAND14_SHIFT 24
#define	_DEVINFO_HFRCOCAL1_BAND21_MASK 0x000000FFUL
#define	_DEVINFO_HFRCOCAL1_BAND21_SHIFT 0
#define	_DEVINFO_HFRCOCAL1_BAND28_MASK 0x0000FF00UL
#define	_DEVINFO_HFRCOCAL1_BAND28_SHIFT 8
#define	_DEVINFO_UNIQUEL_MASK 0xFFFFFFFFUL
#define	_DEVINFO_UNIQUEL_SHIFT 0
#define	_DEVINFO_UNIQUEH_MASK 0xFFFFFFFFUL
#define	_DEVINFO_UNIQUEH_SHIFT 0
#define	_DEVINFO_MSIZE_SRAM_MASK 0xFFFF0000UL
#define	_DEVINFO_MSIZE_SRAM_SHIFT 16
#define	_DEVINFO_MSIZE_FLASH_MASK 0x0000FFFFUL
#define	_DEVINFO_MSIZE_FLASH_SHIFT 0
#define	_DEVINFO_PART_PROD_REV_MASK 0xFF000000UL
#define	_DEVINFO_PART_PROD_REV_SHIFT 24
#define	_DEVINFO_PART_DEVICE_FAMILY_MASK 0x00FF0000UL
#define	_DEVINFO_PART_DEVICE_FAMILY_SHIFT 16
#define	_DEVINFO_PART_DEVICE_NUMBER_MASK 0x0000FFFFUL
#define	_DEVINFO_PART_DEVICE_NUMBER_SHIFT 0
#define	_ROMTABLE_PID0_FAMILYLSB_MASK 0x000000C0UL
#define	_ROMTABLE_PID0_FAMILYLSB_SHIFT 6
#define	_ROMTABLE_PID0_REVMAJOR_MASK 0x0000003FUL
#define	_ROMTABLE_PID0_REVMAJOR_SHIFT 0
#define	_ROMTABLE_PID1_FAMILYMSB_MASK 0x0000000FUL
#define	_ROMTABLE_PID1_FAMILYMSB_SHIFT 0
#define	_ROMTABLE_PID2_REVMINORMSB_MASK 0x000000F0UL
#define	_ROMTABLE_PID2_REVMINORMSB_SHIFT 4
#define	_ROMTABLE_PID3_REVMINORLSB_MASK 0x000000F0UL
#define	_ROMTABLE_PID3_REVMINORLSB_SHIFT 4
#define	MSC_UNLOCK_CODE 0x1B71
#define	EMU_UNLOCK_CODE 0xADE8
#define	CMU_UNLOCK_CODE 0x580E
#define	GPIO_UNLOCK_CODE 0xA534
#define	TIMER_UNLOCK_CODE 0xCE80
#define	AFCHAN_MAX 79
#define	AFCHANLOC_MAX 4
#define	AFACHAN_MAX 37
#define	AF_CMU_CLK0 0
#define	AF_CMU_CLK1 1
#define	AF_EBI_AD00 2
#define	AF_EBI_AD01 3
#define	AF_EBI_AD02 4
#define	AF_EBI_AD03 5
#define	AF_EBI_AD04 6
#define	AF_EBI_AD05 7
#define	AF_EBI_AD06 8
#define	AF_EBI_AD07 9
#define	AF_EBI_AD08 10
#define	AF_EBI_AD09 11
#define	AF_EBI_AD10 12
#define	AF_EBI_AD11 13
#define	AF_EBI_AD12 14
#define	AF_EBI_AD13 15
#define	AF_EBI_AD14 16
#define	AF_EBI_AD15 17
#define	AF_EBI_CS0 18
#define	AF_EBI_CS1 19
#define	AF_EBI_CS2 20
#define	AF_EBI_CS3 21
#define	AF_EBI_WEn 22
#define	AF_EBI_REn 23
#define	AF_EBI_ARDY 24
#define	AF_EBI_ALE 25
#define	AF_TIMER0_CC0 26
#define	AF_TIMER0_CC1 27
#define	AF_TIMER0_CC2 28
#define	AF_TIMER0_CDTI0 29
#define	AF_TIMER0_CDTI1 30
#define	AF_TIMER0_CDTI2 31
#define	AF_TIMER1_CC0 32
#define	AF_TIMER1_CC1 33
#define	AF_TIMER1_CC2 34
#define	AF_TIMER1_CDTI0 35
#define	AF_TIMER1_CDTI1 36
#define	AF_TIMER1_CDTI2 37
#define	AF_TIMER2_CC0 38
#define	AF_TIMER2_CC1 39
#define	AF_TIMER2_CC2 40
#define	AF_TIMER2_CDTI0 41
#define	AF_TIMER2_CDTI1 42
#define	AF_TIMER2_CDTI2 43
#define	AF_USART0_TX 44
#define	AF_USART0_RX 45
#define	AF_USART0_CLK 46
#define	AF_USART0_CS 47
#define	AF_USART1_TX 48
#define	AF_USART1_RX 49
#define	AF_USART1_CLK 50
#define	AF_USART1_CS 51
#define	AF_USART2_TX 52
#define	AF_USART2_RX 53
#define	AF_USART2_CLK 54
#define	AF_USART2_CS 55
#define	AF_UART0_TX 56
#define	AF_UART0_RX 57
#define	AF_UART0_CLK 58
#define	AF_UART0_CS 59
#define	AF_LEUART0_TX 60
#define	AF_LEUART0_RX 61
#define	AF_LEUART1_TX 62
#define	AF_LEUART1_RX 63
#define	AF_LETIMER0_OUT0 64
#define	AF_LETIMER0_OUT1 65
#define	AF_PCNT0_S0IN 66
#define	AF_PCNT0_S1IN 67
#define	AF_PCNT1_S0IN 68
#define	AF_PCNT1_S1IN 69
#define	AF_PCNT2_S0IN 70
#define	AF_PCNT2_S1IN 71
#define	AF_I2C0_SDA 72
#define	AF_I2C0_SCL 73
#define	AF_ACMP0_OUT 74
#define	AF_ACMP1_OUT 75
#define	AF_DBG_SWO 76
#define	AF_DBG_SWDIO 77
#define	AF_DBG_SWCLK 78
#define	AFA_MSC_TM0 0
#define	AFA_MSC_TM1 1
#define	AFA_MSC_TM2 2
#define	AFA_ADC0_CH0 3
#define	AFA_ADC0_CH1 4
#define	AFA_ADC0_CH2 5
#define	AFA_ADC0_CH3 6
#define	AFA_ADC0_CH4 7
#define	AFA_ADC0_CH5 8
#define	AFA_ADC0_CH6 9
#define	AFA_ADC0_CH7 10
#define	AFA_ADC0_VCM 11
#define	AFA_DAC0_OUT0 12
#define	AFA_DAC0_OUT1 13
#define	AFA_ACMP0_CH0 14
#define	AFA_ACMP0_CH1 15
#define	AFA_ACMP0_CH2 16
#define	AFA_ACMP0_CH3 17
#define	AFA_ACMP0_CH4 18
#define	AFA_ACMP0_CH5 19
#define	AFA_ACMP0_CH6 20
#define	AFA_ACMP0_CH7 21
#define	AFA_ACMP1_CH0 22
#define	AFA_ACMP1_CH1 23
#define	AFA_ACMP1_CH2 24
#define	AFA_ACMP1_CH3 25
#define	AFA_ACMP1_CH4 26
#define	AFA_ACMP1_CH5 27
#define	AFA_ACMP1_CH6 28
#define	AFA_ACMP1_CH7 29
#define	AFA_LCD_BCAP_P 30
#define	AFA_LCD_BCAP_N 31
#define	AFA_LCD_BEXT 32
#define	AFA_HFXTAL_P 33
#define	AFA_HFXTAL_N 34
#define	AFA_LFXTAL_P 35
#define	AFA_LFXTAL_N 36
#define	AF_TIMER_CC0(i) ((i) == 0 ? AF_TIMER0_CC0 : (i) == 1 ? AF_TIMER1_CC0 : (i) == 2 ? AF_TIMER2_CC0 : -1)
#define	AF_UART_CLK(i) ((i) == 0 ? AF_UART0_CLK : -1)
#define	AF_I2C_SDA(i) ((i) == 0 ? AF_I2C0_SDA : -1)
#define	AF_TIMER_CC1(i) ((i) == 0 ? AF_TIMER0_CC1 : (i) == 1 ? AF_TIMER1_CC1 : (i) == 2 ? AF_TIMER2_CC1 : -1)
#define	AF_USART_CS(i) ((i) == 0 ? AF_USART0_CS : (i) == 1 ? AF_USART1_CS : (i) == 2 ? AF_USART2_CS : -1)
#define	AF_I2C_SCL(i) ((i) == 0 ? AF_I2C0_SCL : -1)
#define	AF_TIMER_CC2(i) ((i) == 0 ? AF_TIMER0_CC2 : (i) == 1 ? AF_TIMER1_CC2 : (i) == 2 ? AF_TIMER2_CC2 : -1)
#define	AF_TIMER_CDTI1(i) ((i) == 0 ? AF_TIMER0_CDTI1 : (i) == 1 ? AF_TIMER1_CDTI1 : (i) == 2 ? AF_TIMER2_CDTI1 : -1)
#define	AF_TIMER_CDTI0(i) ((i) == 0 ? AF_TIMER0_CDTI0 : (i) == 1 ? AF_TIMER1_CDTI0 : (i) == 2 ? AF_TIMER2_CDTI0 : -1)
#define	AF_USART_CLK(i) ((i) == 0 ? AF_USART0_CLK : (i) == 1 ? AF_USART1_CLK : (i) == 2 ? AF_USART2_CLK : -1)
#define	AF_UART_RX(i) ((i) == 0 ? AF_UART0_RX : -1)
#define	AF_UART_TX(i) ((i) == 0 ? AF_UART0_TX : -1)
#define	AF_LETIMER_OUT1(i) ((i) == 0 ? AF_LETIMER0_OUT1 : -1)
#define	AF_LEUART_RX(i) ((i) == 0 ? AF_LEUART0_RX : (i) == 1 ? AF_LEUART1_RX : -1)
#define	AF_PCNT_S1IN(i) ((i) == 0 ? AF_PCNT0_S1IN : (i) == 1 ? AF_PCNT1_S1IN : (i) == 2 ? AF_PCNT2_S1IN : -1)
#define	AF_TIMER_CDTI2(i) ((i) == 0 ? AF_TIMER0_CDTI2 : (i) == 1 ? AF_TIMER1_CDTI2 : (i) == 2 ? AF_TIMER2_CDTI2 : -1)
#define	AF_LEUART_TX(i) ((i) == 0 ? AF_LEUART0_TX : (i) == 1 ? AF_LEUART1_TX : -1)
#define	AF_USART_TX(i) ((i) == 0 ? AF_USART0_TX : (i) == 1 ? AF_USART1_TX : (i) == 2 ? AF_USART2_TX : -1)
#define	AF_LETIMER_OUT0(i) ((i) == 0 ? AF_LETIMER0_OUT0 : -1)
#define	AF_ACMP_OUT(i) ((i) == 0 ? AF_ACMP0_OUT : (i) == 1 ? AF_ACMP1_OUT : -1)
#define	AF_USART_RX(i) ((i) == 0 ? AF_USART0_RX : (i) == 1 ? AF_USART1_RX : (i) == 2 ? AF_USART2_RX : -1)
#define	AF_UART_CS(i) ((i) == 0 ? AF_UART0_CS : -1)
#define	AF_PCNT_S0IN(i) ((i) == 0 ? AF_PCNT0_S0IN : (i) == 1 ? AF_PCNT1_S0IN : (i) == 2 ? AF_PCNT2_S0IN : -1)
#define	AFA_DAC_OUT1(i) ((i) == 0 ? AFA_DAC0_OUT1 : -1)
#define	AFA_DAC_OUT0(i) ((i) == 0 ? AFA_DAC0_OUT0 : -1)
#define	AFA_ADC_CH7(i) ((i) == 0 ? AFA_ADC0_CH7 : -1)
#define	AFA_ADC_VCM(i) ((i) == 0 ? AFA_ADC0_VCM : -1)
#define	AFA_ACMP_CH1(i) ((i) == 0 ? AFA_ACMP0_CH1 : (i) == 1 ? AFA_ACMP1_CH1 : -1)
#define	AFA_ADC_CH0(i) ((i) == 0 ? AFA_ADC0_CH0 : -1)
#define	AFA_ACMP_CH0(i) ((i) == 0 ? AFA_ACMP0_CH0 : (i) == 1 ? AFA_ACMP1_CH0 : -1)
#define	AFA_ACMP_CH3(i) ((i) == 0 ? AFA_ACMP0_CH3 : (i) == 1 ? AFA_ACMP1_CH3 : -1)
#define	AFA_ADC_CH1(i) ((i) == 0 ? AFA_ADC0_CH1 : -1)
#define	AFA_ACMP_CH2(i) ((i) == 0 ? AFA_ACMP0_CH2 : (i) == 1 ? AFA_ACMP1_CH2 : -1)
#define	AFA_ADC_CH2(i) ((i) == 0 ? AFA_ADC0_CH2 : -1)
#define	AFA_ADC_CH3(i) ((i) == 0 ? AFA_ADC0_CH3 : -1)
#define	AFA_ADC_CH4(i) ((i) == 0 ? AFA_ADC0_CH4 : -1)
#define	AFA_ADC_CH5(i) ((i) == 0 ? AFA_ADC0_CH5 : -1)
#define	AFA_ADC_CH6(i) ((i) == 0 ? AFA_ADC0_CH6 : -1)
#define	AFA_ACMP_CH5(i) ((i) == 0 ? AFA_ACMP0_CH5 : (i) == 1 ? AFA_ACMP1_CH5 : -1)
#define	AFA_ACMP_CH4(i) ((i) == 0 ? AFA_ACMP0_CH4 : (i) == 1 ? AFA_ACMP1_CH4 : -1)
#define	AFA_ACMP_CH7(i) ((i) == 0 ? AFA_ACMP0_CH7 : (i) == 1 ? AFA_ACMP1_CH7 : -1)
#define	AFA_ACMP_CH6(i) ((i) == 0 ? AFA_ACMP0_CH6 : (i) == 1 ? AFA_ACMP1_CH6 : -1)
#define	AF_CMU_CLK0_PORT(f) ((f) == 0 ? 0 : (f) == 1 ? 2 : -1)
#define	AF_CMU_CLK1_PORT(f) ((f) == 0 ? 0 : (f) == 1 ? 3 : -1)
#define	AF_EBI_AD00_PORT(f) ((f) == 0 ? 4 : -1)
#define	AF_EBI_AD01_PORT(f) ((f) == 0 ? 4 : -1)
#define	AF_EBI_AD02_PORT(f) ((f) == 0 ? 4 : -1)
#define	AF_EBI_AD03_PORT(f) ((f) == 0 ? 4 : -1)
#define	AF_EBI_AD04_PORT(f) ((f) == 0 ? 4 : -1)
#define	AF_EBI_AD05_PORT(f) ((f) == 0 ? 4 : -1)
#define	AF_EBI_AD06_PORT(f) ((f) == 0 ? 4 : -1)
#define	AF_EBI_AD07_PORT(f) ((f) == 0 ? 4 : -1)
#define	AF_EBI_AD08_PORT(f) ((f) == 0 ? 0 : -1)
#define	AF_EBI_AD09_PORT(f) ((f) == 0 ? 0 : -1)
#define	AF_EBI_AD10_PORT(f) ((f) == 0 ? 0 : -1)
#define	AF_EBI_AD11_PORT(f) ((f) == 0 ? 0 : -1)
#define	AF_EBI_AD12_PORT(f) ((f) == 0 ? 0 : -1)
#define	AF_EBI_AD13_PORT(f) ((f) == 0 ? 0 : -1)
#define	AF_EBI_AD14_PORT(f) ((f) == 0 ? 0 : -1)
#define	AF_EBI_AD15_PORT(f) ((f) == 0 ? 0 : -1)
#define	AF_EBI_CS0_PORT(f) ((f) == 0 ? 3 : -1)
#define	AF_EBI_CS1_PORT(f) ((f) == 0 ? 3 : -1)
#define	AF_EBI_CS2_PORT(f) ((f) == 0 ? 3 : -1)
#define	AF_EBI_CS3_PORT(f) ((f) == 0 ? 3 : -1)
#define	AF_EBI_WEn_PORT(f) ((f) == 0 ? 5 : -1)
#define	AF_EBI_REn_PORT(f) ((f) == 0 ? 5 : -1)
#define	AF_EBI_ARDY_PORT(f) ((f) == 0 ? 5 : -1)
#define	AF_EBI_ALE_PORT(f) ((f) == 0 ? 5 : -1)
#define	AF_TIMER0_CC0_PORT(f) ((f) == 0 ? 0 : (f) == 1 ? 0 : (f) == 2 ? 5 : (f) == 3 ? 3 : -1)
#define	AF_TIMER0_CC1_PORT(f) ((f) == 0 ? 0 : (f) == 1 ? 0 : (f) == 2 ? 5 : (f) == 3 ? 3 : -1)
#define	AF_TIMER0_CC2_PORT(f) ((f) == 0 ? 0 : (f) == 1 ? 0 : (f) == 2 ? 5 : (f) == 3 ? 3 : -1)
#define	AF_TIMER0_CDTI0_PORT(f) ((f) == 0 ? 0 : (f) == 1 ? 2 : (f) == 2 ? 5 : (f) == 3 ? 2 : -1)
#define	AF_TIMER0_CDTI1_PORT(f) ((f) == 0 ? 0 : (f) == 1 ? 2 : (f) == 2 ? 5 : (f) == 3 ? 2 : -1)
#define	AF_TIMER0_CDTI2_PORT(f) ((f) == 0 ? 0 : (f) == 1 ? 2 : (f) == 2 ? 5 : (f) == 3 ? 2 : -1)
#define	AF_TIMER1_CC0_PORT(f) ((f) == 0 ? 2 : (f) == 1 ? 4 : (f) == 2 ? 1 : -1)
#define	AF_TIMER1_CC1_PORT(f) ((f) == 0 ? 2 : (f) == 1 ? 4 : (f) == 2 ? 1 : -1)
#define	AF_TIMER1_CC2_PORT(f) ((f) == 0 ? 2 : (f) == 1 ? 4 : (f) == 2 ? 1 : -1)
#define	AF_TIMER1_CDTI0_PORT(f) (-1)
#define	AF_TIMER1_CDTI1_PORT(f) (-1)
#define	AF_TIMER1_CDTI2_PORT(f) (-1)
#define	AF_TIMER2_CC0_PORT(f) ((f) == 0 ? 0 : (f) == 1 ? 0 : (f) == 2 ? 2 : -1)
#define	AF_TIMER2_CC1_PORT(f) ((f) == 0 ? 0 : (f) == 1 ? 0 : (f) == 2 ? 2 : -1)
#define	AF_TIMER2_CC2_PORT(f) ((f) == 0 ? 0 : (f) == 1 ? 0 : (f) == 2 ? 2 : -1)
#define	AF_TIMER2_CDTI0_PORT(f) (-1)
#define	AF_TIMER2_CDTI1_PORT(f) (-1)
#define	AF_TIMER2_CDTI2_PORT(f) (-1)
#define	AF_USART0_TX_PORT(f) ((f) == 0 ? 4 : (f) == 1 ? 4 : (f) == 2 ? 2 : -1)
#define	AF_USART0_RX_PORT(f) ((f) == 0 ? 4 : (f) == 1 ? 4 : (f) == 2 ? 2 : -1)
#define	AF_USART0_CLK_PORT(f) ((f) == 0 ? 4 : (f) == 1 ? 4 : (f) == 2 ? 2 : -1)
#define	AF_USART0_CS_PORT(f) ((f) == 0 ? 4 : (f) == 1 ? 4 : (f) == 2 ? 2 : -1)
#define	AF_USART1_TX_PORT(f) ((f) == 0 ? 2 : (f) == 1 ? 3 : -1)
#define	AF_USART1_RX_PORT(f) ((f) == 0 ? 2 : (f) == 1 ? 3 : -1)
#define	AF_USART1_CLK_PORT(f) ((f) == 0 ? 1 : (f) == 1 ? 3 : -1)
#define	AF_USART1_CS_PORT(f) ((f) == 0 ? 1 : (f) == 1 ? 3 : -1)
#define	AF_USART2_TX_PORT(f) ((f) == 0 ? 2 : (f) == 1 ? 1 : -1)
#define	AF_USART2_RX_PORT(f) ((f) == 0 ? 2 : (f) == 1 ? 1 : -1)
#define	AF_USART2_CLK_PORT(f) ((f) == 0 ? 2 : (f) == 1 ? 1 : -1)
#define	AF_USART2_CS_PORT(f) ((f) == 0 ? 2 : (f) == 1 ? 1 : -1)
#define	AF_UART0_TX_PORT(f) ((f) == 0 ? 5 : (f) == 1 ? 4 : (f) == 2 ? 0 : (f) == 3 ? 2 : -1)
#define	AF_UART0_RX_PORT(f) ((f) == 0 ? 5 : (f) == 1 ? 4 : (f) == 2 ? 0 : (f) == 3 ? 2 : -1)
#define	AF_UART0_CLK_PORT(f) (-1)
#define	AF_UART0_CS_PORT(f) (-1)
#define	AF_LEUART0_TX_PORT(f) ((f) == 0 ? 3 : (f) == 1 ? 1 : (f) == 2 ? 4 : -1)
#define	AF_LEUART0_RX_PORT(f) ((f) == 0 ? 3 : (f) == 1 ? 1 : (f) == 2 ? 4 : -1)
#define	AF_LEUART1_TX_PORT(f) ((f) == 0 ? 2 : (f) == 1 ? 0 : -1)
#define	AF_LEUART1_RX_PORT(f) ((f) == 0 ? 2 : (f) == 1 ? 0 : -1)
#define	AF_LETIMER0_OUT0_PORT(f) ((f) == 0 ? 3 : (f) == 1 ? 1 : (f) == 2 ? 5 : (f) == 3 ? 2 : -1)
#define	AF_LETIMER0_OUT1_PORT(f) ((f) == 0 ? 3 : (f) == 1 ? 1 : (f) == 2 ? 5 : (f) == 3 ? 2 : -1)
#define	AF_PCNT0_S0IN_PORT(f) ((f) == 0 ? 2 : (f) == 1 ? 4 : (f) == 2 ? 2 : -1)
#define	AF_PCNT0_S1IN_PORT(f) ((f) == 0 ? 2 : (f) == 1 ? 4 : (f) == 2 ? 2 : -1)
#define	AF_PCNT1_S0IN_PORT(f) ((f) == 0 ? 2 : (f) == 1 ? 1 : -1)
#define	AF_PCNT1_S1IN_PORT(f) ((f) == 0 ? 2 : (f) == 1 ? 1 : -1)
#define	AF_PCNT2_S0IN_PORT(f) ((f) == 0 ? 3 : (f) == 1 ? 4 : -1)
#define	AF_PCNT2_S1IN_PORT(f) ((f) == 0 ? 3 : (f) == 1 ? 4 : -1)
#define	AF_I2C0_SDA_PORT(f) ((f) == 0 ? 0 : (f) == 1 ? 3 : (f) == 2 ? 2 : (f) == 3 ? 3 : -1)
#define	AF_I2C0_SCL_PORT(f) ((f) == 0 ? 0 : (f) == 1 ? 3 : (f) == 2 ? 2 : (f) == 3 ? 3 : -1)
#define	AF_ACMP0_OUT_PORT(f) ((f) == 0 ? 4 : (f) == 1 ? 4 : -1)
#define	AF_ACMP1_OUT_PORT(f) ((f) == 0 ? 5 : (f) == 1 ? 4 : -1)
#define	AF_DBG_SWO_PORT(f) ((f) == 0 ? 5 : (f) == 1 ? 2 : -1)
#define	AF_DBG_SWDIO_PORT(f) ((f) == 0 ? 5 : (f) == 1 ? 5 : -1)
#define	AF_DBG_SWCLK_PORT(f) ((f) == 0 ? 5 : (f) == 1 ? 5 : -1)
#define	AF_CMU_CLK0_PIN(f) ((f) == 0 ? 2 : (f) == 1 ? 12 : -1)
#define	AF_CMU_CLK1_PIN(f) ((f) == 0 ? 1 : (f) == 1 ? 8 : -1)
#define	AF_EBI_AD00_PIN(f) ((f) == 0 ? 8 : -1)
#define	AF_EBI_AD01_PIN(f) ((f) == 0 ? 9 : -1)
#define	AF_EBI_AD02_PIN(f) ((f) == 0 ? 10 : -1)
#define	AF_EBI_AD03_PIN(f) ((f) == 0 ? 11 : -1)
#define	AF_EBI_AD04_PIN(f) ((f) == 0 ? 12 : -1)
#define	AF_EBI_AD05_PIN(f) ((f) == 0 ? 13 : -1)
#define	AF_EBI_AD06_PIN(f) ((f) == 0 ? 14 : -1)
#define	AF_EBI_AD07_PIN(f) ((f) == 0 ? 15 : -1)
#define	AF_EBI_AD08_PIN(f) ((f) == 0 ? 15 : -1)
#define	AF_EBI_AD09_PIN(f) ((f) == 0 ? 0 : -1)
#define	AF_EBI_AD10_PIN(f) ((f) == 0 ? 1 : -1)
#define	AF_EBI_AD11_PIN(f) ((f) == 0 ? 2 : -1)
#define	AF_EBI_AD12_PIN(f) ((f) == 0 ? 3 : -1)
#define	AF_EBI_AD13_PIN(f) ((f) == 0 ? 4 : -1)
#define	AF_EBI_AD14_PIN(f) ((f) == 0 ? 5 : -1)
#define	AF_EBI_AD15_PIN(f) ((f) == 0 ? 6 : -1)
#define	AF_EBI_CS0_PIN(f) ((f) == 0 ? 9 : -1)
#define	AF_EBI_CS1_PIN(f) ((f) == 0 ? 10 : -1)
#define	AF_EBI_CS2_PIN(f) ((f) == 0 ? 11 : -1)
#define	AF_EBI_CS3_PIN(f) ((f) == 0 ? 12 : -1)
#define	AF_EBI_WEn_PIN(f) ((f) == 0 ? 4 : -1)
#define	AF_EBI_REn_PIN(f) ((f) == 0 ? 5 : -1)
#define	AF_EBI_ARDY_PIN(f) ((f) == 0 ? 2 : -1)
#define	AF_EBI_ALE_PIN(f) ((f) == 0 ? 3 : -1)
#define	AF_TIMER0_CC0_PIN(f) ((f) == 0 ? 0 : (f) == 1 ? 0 : (f) == 2 ? 6 : (f) == 3 ? 1 : -1)
#define	AF_TIMER0_CC1_PIN(f) ((f) == 0 ? 1 : (f) == 1 ? 1 : (f) == 2 ? 7 : (f) == 3 ? 2 : -1)
#define	AF_TIMER0_CC2_PIN(f) ((f) == 0 ? 2 : (f) == 1 ? 2 : (f) == 2 ? 8 : (f) == 3 ? 3 : -1)
#define	AF_TIMER0_CDTI0_PIN(f) ((f) == 0 ? 3 : (f) == 1 ? 13 : (f) == 2 ? 3 : (f) == 3 ? 13 : -1)
#define	AF_TIMER0_CDTI1_PIN(f) ((f) == 0 ? 4 : (f) == 1 ? 14 : (f) == 2 ? 4 : (f) == 3 ? 14 : -1)
#define	AF_TIMER0_CDTI2_PIN(f) ((f) == 0 ? 5 : (f) == 1 ? 15 : (f) == 2 ? 5 : (f) == 3 ? 15 : -1)
#define	AF_TIMER1_CC0_PIN(f) ((f) == 0 ? 13 : (f) == 1 ? 10 : (f) == 2 ? 0 : -1)
#define	AF_TIMER1_CC1_PIN(f) ((f) == 0 ? 14 : (f) == 1 ? 11 : (f) == 2 ? 1 : -1)
#define	AF_TIMER1_CC2_PIN(f) ((f) == 0 ? 15 : (f) == 1 ? 12 : (f) == 2 ? 2 : -1)
#define	AF_TIMER1_CDTI0_PIN(f) (-1)
#define	AF_TIMER1_CDTI1_PIN(f) (-1)
#define	AF_TIMER1_CDTI2_PIN(f) (-1)
#define	AF_TIMER2_CC0_PIN(f) ((f) == 0 ? 8 : (f) == 1 ? 12 : (f) == 2 ? 8 : -1)
#define	AF_TIMER2_CC1_PIN(f) ((f) == 0 ? 9 : (f) == 1 ? 13 : (f) == 2 ? 9 : -1)
#define	AF_TIMER2_CC2_PIN(f) ((f) == 0 ? 10 : (f) == 1 ? 14 : (f) == 2 ? 10 : -1)
#define	AF_TIMER2_CDTI0_PIN(f) (-1)
#define	AF_TIMER2_CDTI1_PIN(f) (-1)
#define	AF_TIMER2_CDTI2_PIN(f) (-1)
#define	AF_USART0_TX_PIN(f) ((f) == 0 ? 10 : (f) == 1 ? 7 : (f) == 2 ? 11 : -1)
#define	AF_USART0_RX_PIN(f) ((f) == 0 ? 11 : (f) == 1 ? 6 : (f) == 2 ? 10 : -1)
#define	AF_USART0_CLK_PIN(f) ((f) == 0 ? 12 : (f) == 1 ? 5 : (f) == 2 ? 9 : -1)
#define	AF_USART0_CS_PIN(f) ((f) == 0 ? 13 : (f) == 1 ? 4 : (f) == 2 ? 8 : -1)
#define	AF_USART1_TX_PIN(f) ((f) == 0 ? 0 : (f) == 1 ? 0 : -1)
#define	AF_USART1_RX_PIN(f) ((f) == 0 ? 1 : (f) == 1 ? 1 : -1)
#define	AF_USART1_CLK_PIN(f) ((f) == 0 ? 7 : (f) == 1 ? 2 : -1)
#define	AF_USART1_CS_PIN(f) ((f) == 0 ? 8 : (f) == 1 ? 3 : -1)
#define	AF_USART2_TX_PIN(f) ((f) == 0 ? 2 : (f) == 1 ? 3 : -1)
#define	AF_USART2_RX_PIN(f) ((f) == 0 ? 3 : (f) == 1 ? 4 : -1)
#define	AF_USART2_CLK_PIN(f) ((f) == 0 ? 4 : (f) == 1 ? 5 : -1)
#define	AF_USART2_CS_PIN(f) ((f) == 0 ? 5 : (f) == 1 ? 6 : -1)
#define	AF_UART0_TX_PIN(f) ((f) == 0 ? 6 : (f) == 1 ? 0 : (f) == 2 ? 3 : (f) == 3 ? 14 : -1)
#define	AF_UART0_RX_PIN(f) ((f) == 0 ? 7 : (f) == 1 ? 1 : (f) == 2 ? 4 : (f) == 3 ? 15 : -1)
#define	AF_UART0_CLK_PIN(f) (-1)
#define	AF_UART0_CS_PIN(f) (-1)
#define	AF_LEUART0_TX_PIN(f) ((f) == 0 ? 4 : (f) == 1 ? 13 : (f) == 2 ? 14 : -1)
#define	AF_LEUART0_RX_PIN(f) ((f) == 0 ? 5 : (f) == 1 ? 14 : (f) == 2 ? 15 : -1)
#define	AF_LEUART1_TX_PIN(f) ((f) == 0 ? 6 : (f) == 1 ? 5 : -1)
#define	AF_LEUART1_RX_PIN(f) ((f) == 0 ? 7 : (f) == 1 ? 6 : -1)
#define	AF_LETIMER0_OUT0_PIN(f) ((f) == 0 ? 6 : (f) == 1 ? 11 : (f) == 2 ? 0 : (f) == 3 ? 4 : -1)
#define	AF_LETIMER0_OUT1_PIN(f) ((f) == 0 ? 7 : (f) == 1 ? 12 : (f) == 2 ? 1 : (f) == 3 ? 5 : -1)
#define	AF_PCNT0_S0IN_PIN(f) ((f) == 0 ? 13 : (f) == 1 ? 0 : (f) == 2 ? 0 : -1)
#define	AF_PCNT0_S1IN_PIN(f) ((f) == 0 ? 14 : (f) == 1 ? 1 : (f) == 2 ? 1 : -1)
#define	AF_PCNT1_S0IN_PIN(f) ((f) == 0 ? 4 : (f) == 1 ? 3 : -1)
#define	AF_PCNT1_S1IN_PIN(f) ((f) == 0 ? 5 : (f) == 1 ? 4 : -1)
#define	AF_PCNT2_S0IN_PIN(f) ((f) == 0 ? 0 : (f) == 1 ? 8 : -1)
#define	AF_PCNT2_S1IN_PIN(f) ((f) == 0 ? 1 : (f) == 1 ? 9 : -1)
#define	AF_I2C0_SDA_PIN(f) ((f) == 0 ? 0 : (f) == 1 ? 6 : (f) == 2 ? 6 : (f) == 3 ? 14 : -1)
#define	AF_I2C0_SCL_PIN(f) ((f) == 0 ? 1 : (f) == 1 ? 7 : (f) == 2 ? 7 : (f) == 3 ? 15 : -1)
#define	AF_ACMP0_OUT_PIN(f) ((f) == 0 ? 13 : (f) == 1 ? 2 : -1)
#define	AF_ACMP1_OUT_PIN(f) ((f) == 0 ? 2 : (f) == 1 ? 3 : -1)
#define	AF_DBG_SWO_PIN(f) ((f) == 0 ? 2 : (f) == 1 ? 15 : -1)
#define	AF_DBG_SWDIO_PIN(f) ((f) == 0 ? 1 : (f) == 1 ? 1 : -1)
#define	AF_DBG_SWCLK_PIN(f) ((f) == 0 ? 0 : (f) == 1 ? 0 : -1)
#define	AF_PORT(c, f)
#define	AF_PIN(c, f)
#define	AF_COUNT(c)
#define	SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) REG = ((REG) &~(MASK)) \| (((VALUE) << (OFFSET)) & (MASK));
	Set the value of a bit field within a register.
Typedefs
typedef enum IRQn	IRQn_Type
Enumerations
enum	IRQn { NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, DMA_IRQn = 0, GPIO_EVEN_IRQn = 1, TIMER0_IRQn = 2, USART0_RX_IRQn = 3, USART0_TX_IRQn = 4, ACMP0_IRQn = 5, ADC0_IRQn = 6, DAC0_IRQn = 7, I2C0_IRQn = 8, GPIO_ODD_IRQn = 9, TIMER1_IRQn = 10, TIMER2_IRQn = 11, USART1_RX_IRQn = 12, USART1_TX_IRQn = 13, USART2_RX_IRQn = 14, USART2_TX_IRQn = 15, UART0_RX_IRQn = 16, UART0_TX_IRQn = 17, LEUART0_IRQn = 18, LEUART1_IRQn = 19, LETIMER0_IRQn = 20, PCNT0_IRQn = 21, PCNT1_IRQn = 22, PCNT2_IRQn = 23, RTC_IRQn = 24, CMU_IRQn = 25, VCMP_IRQn = 26, LCD_IRQn = 27, MSC_IRQn = 28, AES_IRQn = 29 }

Detailed Description

CMSIS Cortex-M3 Peripheral Access Layer for EFM EFM32G890F128.

Author:: Energy Micro AS

Version:: 1.3.0

License

This source code is the property of Energy Micro AS. The source and compiled code may only be used on Energy Micro "EFM32" microcontrollers.

This copyright notice may not be removed from the source code nor changed.

DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no obligation to support this Software. Energy Micro AS is providing the Software "AS IS", with no express or implied warranties of any kind, including, but not limited to, any implied warranties of merchantability or fitness for any particular purpose or warranties against infringement of any proprietary rights of a third party.

Energy Micro AS will not be liable for any consequential, incidental, or special damages, or any other relief, or for any claim by any third party, arising from your use of this Software.

Definition in file efm32g890f128.h.

efm32g890f128.h File Reference

Data Structures

Defines

Typedefs

Enumerations

Detailed Description

License