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Energy Micro IEC60355 Library Example Project 1.0 (internal use only!) GCC-Version
Example project demonstrating POST and BIST library functions
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Energy Micro IEC60355 Library Example Project 1.0 (internal use only!) GCC-Version
Example project demonstrating POST and BIST library functions
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00001 /**************************************************************************/ 00029 #ifndef __EFM32G890F128_H 00030 #define __EFM32G890F128_H 00031 00032 /**************************************************************************/ 00037 /**************************************************************************/ 00043 typedef enum IRQn 00044 { 00045 /****** Cortex-M3 Processor Exceptions Numbers *******************************************/ 00046 NonMaskableInt_IRQn = -14, 00047 HardFault_IRQn = -13, 00048 MemoryManagement_IRQn = -12, 00049 BusFault_IRQn = -11, 00050 UsageFault_IRQn = -10, 00051 SVCall_IRQn = -5, 00052 DebugMonitor_IRQn = -4, 00053 PendSV_IRQn = -2, 00054 SysTick_IRQn = -1, 00056 /****** EFM32G Peripheral Interrupt Numbers **********************************************/ 00057 DMA_IRQn = 0, 00058 GPIO_EVEN_IRQn = 1, 00059 TIMER0_IRQn = 2, 00060 USART0_RX_IRQn = 3, 00061 USART0_TX_IRQn = 4, 00062 ACMP0_IRQn = 5, 00063 ADC0_IRQn = 6, 00064 DAC0_IRQn = 7, 00065 I2C0_IRQn = 8, 00066 GPIO_ODD_IRQn = 9, 00067 TIMER1_IRQn = 10, 00068 TIMER2_IRQn = 11, 00069 USART1_RX_IRQn = 12, 00070 USART1_TX_IRQn = 13, 00071 USART2_RX_IRQn = 14, 00072 USART2_TX_IRQn = 15, 00073 UART0_RX_IRQn = 16, 00074 UART0_TX_IRQn = 17, 00075 LEUART0_IRQn = 18, 00076 LEUART1_IRQn = 19, 00077 LETIMER0_IRQn = 20, 00078 PCNT0_IRQn = 21, 00079 PCNT1_IRQn = 22, 00080 PCNT2_IRQn = 23, 00081 RTC_IRQn = 24, 00082 CMU_IRQn = 25, 00083 VCMP_IRQn = 26, 00084 LCD_IRQn = 27, 00085 MSC_IRQn = 28, 00086 AES_IRQn = 29, 00087 } IRQn_Type; 00088 00089 /**************************************************************************/ 00093 #define __MPU_PRESENT 1 00094 #define __NVIC_PRIO_BITS 3 00095 #define __Vendor_SysTickConfig 0 00101 /**************************************************************************/ 00106 #if !defined(EFM32G890F128) 00107 #define EFM32G890F128 00108 #endif 00109 00111 #define PART_NUMBER "EFM32G890F128" 00114 #define EBI_MEM_BASE ((uint32_t) 0x80000000UL) 00115 #define EBI_MEM_SIZE ((uint32_t) 0x10000000UL) 00116 #define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) 00117 #define EBI_MEM_BITS ((uint32_t) 0x28UL) 00118 #define AES_MEM_BASE ((uint32_t) 0x400E0000UL) 00119 #define AES_MEM_SIZE ((uint32_t) 0x400UL) 00120 #define AES_MEM_END ((uint32_t) 0x400E03FFUL) 00121 #define AES_MEM_BITS ((uint32_t) 0x10UL) 00122 #define PER_MEM_BASE ((uint32_t) 0x40000000UL) 00123 #define PER_MEM_SIZE ((uint32_t) 0xE0000UL) 00124 #define PER_MEM_END ((uint32_t) 0x400DFFFFUL) 00125 #define PER_MEM_BITS ((uint32_t) 0x20UL) 00126 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) 00127 #define RAM_MEM_SIZE ((uint32_t) 0x4000UL) 00128 #define RAM_MEM_END ((uint32_t) 0x20003FFFUL) 00129 #define RAM_MEM_BITS ((uint32_t) 0x15UL) 00130 #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) 00131 #define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) 00132 #define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) 00133 #define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) 00134 #define FLASH_MEM_BASE ((uint32_t) 0x0UL) 00135 #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) 00136 #define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) 00137 #define FLASH_MEM_BITS ((uint32_t) 0x28UL) 00140 #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) 00141 #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) 00144 #define FLASH_SIZE 0x00020000UL 00145 #define SRAM_SIZE 0x00004000UL 00146 #define __CM3_REV 0x200 00147 #define PRS_CHAN_COUNT 8 00148 #define DMA_CHAN_COUNT 8 00149 /* Part number capabilities */ 00150 00151 #define TIMER_PRESENT 00152 #define TIMER_COUNT 3 00153 #define USART_PRESENT 00154 #define USART_COUNT 3 00155 #define UART_PRESENT 00156 #define UART_COUNT 1 00157 #define LEUART_PRESENT 00158 #define LEUART_COUNT 2 00159 #define LETIMER_PRESENT 00160 #define LETIMER_COUNT 1 00161 #define PCNT_PRESENT 00162 #define PCNT_COUNT 3 00163 #define I2C_PRESENT 00164 #define I2C_COUNT 1 00165 #define ADC_PRESENT 00166 #define ADC_COUNT 1 00167 #define DAC_PRESENT 00168 #define DAC_COUNT 1 00169 #define ACMP_PRESENT 00170 #define ACMP_COUNT 2 00171 #define LE_PRESENT 00172 #define LE_COUNT 1 00173 #define MSC_PRESENT 00174 #define MSC_COUNT 1 00175 #define EMU_PRESENT 00176 #define EMU_COUNT 1 00177 #define RMU_PRESENT 00178 #define RMU_COUNT 1 00179 #define CMU_PRESENT 00180 #define CMU_COUNT 1 00181 #define AES_PRESENT 00182 #define AES_COUNT 1 00183 #define EBI_PRESENT 00184 #define EBI_COUNT 1 00185 #define GPIO_PRESENT 00186 #define GPIO_COUNT 1 00187 #define PRS_PRESENT 00188 #define PRS_COUNT 1 00189 #define DMA_PRESENT 00190 #define DMA_COUNT 1 00191 #define VCMP_PRESENT 00192 #define VCMP_COUNT 1 00193 #define LCD_PRESENT 00194 #define LCD_COUNT 1 00195 #define RTC_PRESENT 00196 #define RTC_COUNT 1 00197 #define HFXTAL_PRESENT 00198 #define HFXTAL_COUNT 1 00199 #define LFXTAL_PRESENT 00200 #define LFXTAL_COUNT 1 00201 #define WDOG_PRESENT 00202 #define WDOG_COUNT 1 00203 #define DBG_PRESENT 00204 #define DBG_COUNT 1 00205 00210 /* Include CMSIS core functionality */ 00211 #include "core_cm3.h" 00212 #include "system_efm32.h" 00213 #include <stdint.h> 00214 00215 /**************************************************************************/ 00220 /**************************************************************************/ 00225 typedef struct 00226 { 00227 __IO uint32_t CTRL; 00228 __IO uint32_t READCTRL; 00229 __IO uint32_t WRITECTRL; 00230 __IO uint32_t WRITECMD; 00231 __IO uint32_t ADDRB; 00233 uint32_t RESERVED0[1]; 00234 __IO uint32_t WDATA; 00235 __I uint32_t STATUS; 00237 uint32_t RESERVED1[3]; 00238 __I uint32_t IF; 00239 __IO uint32_t IFS; 00240 __IO uint32_t IFC; 00241 __IO uint32_t IEN; 00242 __IO uint32_t LOCK; 00243 } MSC_TypeDef; 00245 /**************************************************************************/ 00250 typedef struct 00251 { 00252 __IO uint32_t CTRL; 00253 __IO uint32_t MEMCTRL; 00254 __IO uint32_t LOCK; 00256 uint32_t RESERVED0[6]; 00257 __IO uint32_t AUXCTRL; 00258 } EMU_TypeDef; 00260 /**************************************************************************/ 00265 typedef struct 00266 { 00267 __IO uint32_t CTRL; 00268 __I uint32_t RSTCAUSE; 00269 __O uint32_t CMD; 00270 } RMU_TypeDef; 00272 /**************************************************************************/ 00277 typedef struct 00278 { 00279 __IO uint32_t CTRL; 00280 __IO uint32_t HFCORECLKDIV; 00281 __IO uint32_t HFPERCLKDIV; 00282 __IO uint32_t HFRCOCTRL; 00283 __IO uint32_t LFRCOCTRL; 00284 __IO uint32_t AUXHFRCOCTRL; 00285 __IO uint32_t CALCTRL; 00286 __IO uint32_t CALCNT; 00287 __IO uint32_t OSCENCMD; 00288 __IO uint32_t CMD; 00289 __IO uint32_t LFCLKSEL; 00290 __I uint32_t STATUS; 00291 __I uint32_t IF; 00292 __IO uint32_t IFS; 00293 __IO uint32_t IFC; 00294 __IO uint32_t IEN; 00295 __IO uint32_t HFCORECLKEN0; 00296 __IO uint32_t HFPERCLKEN0; 00297 uint32_t RESERVED0[2]; 00298 __I uint32_t SYNCBUSY; 00299 __IO uint32_t FREEZE; 00300 __IO uint32_t LFACLKEN0; 00301 uint32_t RESERVED1[1]; 00302 __IO uint32_t LFBCLKEN0; 00303 uint32_t RESERVED2[1]; 00304 __IO uint32_t LFAPRESC0; 00305 uint32_t RESERVED3[1]; 00306 __IO uint32_t LFBPRESC0; 00307 uint32_t RESERVED4[1]; 00308 __IO uint32_t PCNTCTRL; 00309 __IO uint32_t LCDCTRL; 00310 __IO uint32_t ROUTE; 00311 __IO uint32_t LOCK; 00312 } CMU_TypeDef; 00314 /**************************************************************************/ 00319 typedef struct 00320 { 00321 __IO uint32_t CTRL; 00322 __IO uint32_t CMD; 00323 __I uint32_t STATUS; 00324 __IO uint32_t IEN; 00325 __I uint32_t IF; 00326 __IO uint32_t IFS; 00327 __IO uint32_t IFC; 00328 __IO uint32_t DATA; 00329 __IO uint32_t XORDATA; 00330 uint32_t RESERVED0[3]; 00331 __IO uint32_t KEYLA; 00332 __IO uint32_t KEYLB; 00333 __IO uint32_t KEYLC; 00334 __IO uint32_t KEYLD; 00335 __IO uint32_t KEYHA; 00336 __IO uint32_t KEYHB; 00337 __IO uint32_t KEYHC; 00338 __IO uint32_t KEYHD; 00339 } AES_TypeDef; 00341 /**************************************************************************/ 00346 typedef struct 00347 { 00348 __IO uint32_t CTRL; 00349 __IO uint32_t ADDRTIMING; 00350 __IO uint32_t RDTIMING; 00351 __IO uint32_t WRTIMING; 00352 __IO uint32_t POLARITY; 00353 __IO uint32_t ROUTE; 00354 } EBI_TypeDef; 00356 /**************************************************************************/ 00359 typedef struct 00360 { 00361 __IO uint32_t CTRL; 00362 __IO uint32_t MODEL; 00363 __IO uint32_t MODEH; 00364 __IO uint32_t DOUT; 00365 __O uint32_t DOUTSET; 00366 __O uint32_t DOUTCLR; 00367 __O uint32_t DOUTTGL; 00368 __I uint32_t DIN; 00369 __IO uint32_t PINLOCKN; 00370 } GPIO_P_TypeDef; 00371 00372 /**************************************************************************/ 00377 typedef struct 00378 { 00379 GPIO_P_TypeDef P[6]; 00381 uint32_t RESERVED0[10]; 00382 __IO uint32_t EXTIPSELL; 00383 __IO uint32_t EXTIPSELH; 00384 __IO uint32_t EXTIRISE; 00385 __IO uint32_t EXTIFALL; 00386 __IO uint32_t IEN; 00387 __I uint32_t IF; 00388 __IO uint32_t IFS; 00389 __IO uint32_t IFC; 00391 __IO uint32_t ROUTE; 00392 __IO uint32_t INSENSE; 00393 __IO uint32_t LOCK; 00394 } GPIO_TypeDef; 00396 /**************************************************************************/ 00399 typedef struct 00400 { 00401 __IO uint32_t CTRL; 00402 } PRS_CH_TypeDef; 00403 00404 /**************************************************************************/ 00409 typedef struct 00410 { 00411 __IO uint32_t SWPULSE; 00412 __IO uint32_t SWLEVEL; 00414 uint32_t RESERVED0[2]; 00416 PRS_CH_TypeDef CH[8]; 00417 } PRS_TypeDef; 00419 /**************************************************************************/ 00422 typedef struct 00423 { 00424 __IO uint32_t CTRL; 00425 } DMA_CH_TypeDef; 00426 00427 /**************************************************************************/ 00432 typedef struct 00433 { 00434 __I uint32_t STATUS; 00435 __O uint32_t CONFIG; 00436 __IO uint32_t CTRLBASE; 00437 __I uint32_t ALTCTRLBASE; 00438 __I uint32_t CHWAITSTATUS; 00439 __O uint32_t CHSWREQ; 00440 __IO uint32_t CHUSEBURSTS; 00441 __O uint32_t CHUSEBURSTC; 00442 __IO uint32_t CHREQMASKS; 00443 __O uint32_t CHREQMASKC; 00444 __IO uint32_t CHENS; 00445 __O uint32_t CHENC; 00446 __IO uint32_t CHALTS; 00447 __O uint32_t CHALTC; 00448 __IO uint32_t CHPRIS; 00449 __O uint32_t CHPRIC; 00450 uint32_t RESERVED0[3]; 00451 __IO uint32_t ERRORC; 00452 uint32_t RESERVED1[880]; 00453 __I uint32_t CHREQSTATUS; 00454 uint32_t RESERVED2[1]; 00455 __I uint32_t CHSREQSTATUS; 00457 uint32_t RESERVED3[121]; 00458 __I uint32_t IF; 00459 __IO uint32_t IFS; 00460 __IO uint32_t IFC; 00461 __IO uint32_t IEN; 00463 uint32_t RESERVED4[60]; 00465 DMA_CH_TypeDef CH[8]; 00466 } DMA_TypeDef; 00468 /**************************************************************************/ 00471 typedef struct 00472 { 00473 __IO uint32_t CTRL; 00474 __IO uint32_t CCV; 00475 __I uint32_t CCVP; 00476 __IO uint32_t CCVB; 00477 } TIMER_CC_TypeDef; 00478 00479 /**************************************************************************/ 00484 typedef struct 00485 { 00486 __IO uint32_t CTRL; 00487 __IO uint32_t CMD; 00488 __I uint32_t STATUS; 00489 __IO uint32_t IEN; 00490 __I uint32_t IF; 00491 __IO uint32_t IFS; 00492 __IO uint32_t IFC; 00493 __IO uint32_t TOP; 00494 __IO uint32_t TOPB; 00495 __IO uint32_t CNT; 00496 __IO uint32_t ROUTE; 00498 uint32_t RESERVED0[1]; 00500 TIMER_CC_TypeDef CC[3]; 00502 uint32_t RESERVED1[4]; 00503 __IO uint32_t DTCTRL; 00504 __IO uint32_t DTTIME; 00505 __IO uint32_t DTFC; 00506 __IO uint32_t DTOGEN; 00507 __I uint32_t DTFAULT; 00508 __O uint32_t DTFAULTC; 00509 __IO uint32_t DTLOCK; 00510 } TIMER_TypeDef; 00512 /**************************************************************************/ 00517 typedef struct 00518 { 00519 __IO uint32_t CTRL; 00520 __IO uint32_t FRAME; 00521 __IO uint32_t TRIGCTRL; 00522 __IO uint32_t CMD; 00523 __I uint32_t STATUS; 00524 __IO uint32_t CLKDIV; 00525 __I uint32_t RXDATAX; 00526 __I uint32_t RXDATA; 00527 __I uint32_t RXDOUBLEX; 00528 __I uint32_t RXDOUBLE; 00529 __I uint32_t RXDATAXP; 00530 __I uint32_t RXDOUBLEXP; 00531 __IO uint32_t TXDATAX; 00532 __IO uint32_t TXDATA; 00533 __IO uint32_t TXDOUBLEX; 00534 __IO uint32_t TXDOUBLE; 00535 __I uint32_t IF; 00536 __IO uint32_t IFS; 00537 __IO uint32_t IFC; 00538 __IO uint32_t IEN; 00539 __IO uint32_t IRCTRL; 00540 __IO uint32_t ROUTE; 00541 } USART_TypeDef; 00543 /**************************************************************************/ 00548 typedef struct 00549 { 00550 __IO uint32_t CTRL; 00551 __IO uint32_t CMD; 00552 __I uint32_t STATUS; 00553 __IO uint32_t CLKDIV; 00554 __IO uint32_t STARTFRAME; 00555 __IO uint32_t SIGFRAME; 00556 __I uint32_t RXDATAX; 00557 __I uint32_t RXDATA; 00558 __I uint32_t RXDATAXP; 00559 __IO uint32_t TXDATAX; 00560 __IO uint32_t TXDATA; 00561 __I uint32_t IF; 00562 __IO uint32_t IFS; 00563 __IO uint32_t IFC; 00564 __IO uint32_t IEN; 00565 __IO uint32_t PULSECTRL; 00567 __IO uint32_t FREEZE; 00568 __I uint32_t SYNCBUSY; 00570 uint32_t RESERVED0[3]; 00571 __IO uint32_t ROUTE; 00572 } LEUART_TypeDef; 00574 /**************************************************************************/ 00579 typedef struct 00580 { 00581 __IO uint32_t CTRL; 00582 __IO uint32_t CMD; 00583 __I uint32_t STATUS; 00584 __I uint32_t CNT; 00585 __IO uint32_t COMP0; 00586 __IO uint32_t COMP1; 00587 __IO uint32_t REP0; 00588 __IO uint32_t REP1; 00589 __I uint32_t IF; 00590 __IO uint32_t IFS; 00591 __IO uint32_t IFC; 00592 __IO uint32_t IEN; 00594 __IO uint32_t FREEZE; 00595 __I uint32_t SYNCBUSY; 00597 uint32_t RESERVED0[2]; 00598 __IO uint32_t ROUTE; 00599 } LETIMER_TypeDef; 00601 /**************************************************************************/ 00606 typedef struct 00607 { 00608 __IO uint32_t CTRL; 00609 __IO uint32_t CMD; 00610 __I uint32_t STATUS; 00611 __I uint32_t CNT; 00612 __I uint32_t TOP; 00613 __IO uint32_t TOPB; 00614 __I uint32_t IF; 00615 __IO uint32_t IFS; 00616 __IO uint32_t IFC; 00617 __IO uint32_t IEN; 00618 __IO uint32_t ROUTE; 00620 __IO uint32_t FREEZE; 00621 __I uint32_t SYNCBUSY; 00622 } PCNT_TypeDef; 00624 /**************************************************************************/ 00629 typedef struct 00630 { 00631 __IO uint32_t CTRL; 00632 __IO uint32_t CMD; 00633 __I uint32_t STATE; 00634 __I uint32_t STATUS; 00635 __IO uint32_t CLKDIV; 00636 __IO uint32_t SADDR; 00637 __IO uint32_t SADDRMASK; 00638 __I uint32_t RXDATA; 00639 __I uint32_t RXDATAP; 00640 __IO uint32_t TXDATA; 00641 __I uint32_t IF; 00642 __IO uint32_t IFS; 00643 __IO uint32_t IFC; 00644 __IO uint32_t IEN; 00645 __IO uint32_t ROUTE; 00646 } I2C_TypeDef; 00648 /**************************************************************************/ 00653 typedef struct 00654 { 00655 __IO uint32_t CTRL; 00656 __IO uint32_t CMD; 00657 __I uint32_t STATUS; 00658 __IO uint32_t SINGLECTRL; 00659 __IO uint32_t SCANCTRL; 00660 __IO uint32_t IEN; 00661 __I uint32_t IF; 00662 __IO uint32_t IFS; 00663 __IO uint32_t IFC; 00664 __I uint32_t SINGLEDATA; 00665 __I uint32_t SCANDATA; 00666 __I uint32_t SINGLEDATAP; 00667 __I uint32_t SCANDATAP; 00668 __IO uint32_t CAL; 00670 uint32_t RESERVED0[1]; 00671 __IO uint32_t BIASPROG; 00672 } ADC_TypeDef; 00674 /**************************************************************************/ 00679 typedef struct 00680 { 00681 __IO uint32_t CTRL; 00682 __I uint32_t STATUS; 00683 __IO uint32_t CH0CTRL; 00684 __IO uint32_t CH1CTRL; 00685 __IO uint32_t IEN; 00686 __I uint32_t IF; 00687 __IO uint32_t IFS; 00688 __IO uint32_t IFC; 00689 __IO uint32_t CH0DATA; 00690 __IO uint32_t CH1DATA; 00691 __IO uint32_t COMBDATA; 00692 __IO uint32_t CAL; 00693 __IO uint32_t BIASPROG; 00694 } DAC_TypeDef; 00696 /**************************************************************************/ 00701 typedef struct 00702 { 00703 __IO uint32_t CTRL; 00704 __IO uint32_t INPUTSEL; 00705 __I uint32_t STATUS; 00706 __IO uint32_t IEN; 00707 __I uint32_t IF; 00708 __IO uint32_t IFS; 00709 __IO uint32_t IFC; 00710 __IO uint32_t ROUTE; 00711 } ACMP_TypeDef; 00713 /**************************************************************************/ 00718 typedef struct 00719 { 00720 __IO uint32_t CTRL; 00721 __IO uint32_t INPUTSEL; 00722 __I uint32_t STATUS; 00723 __IO uint32_t IEN; 00724 __I uint32_t IF; 00725 __IO uint32_t IFS; 00726 __IO uint32_t IFC; 00727 } VCMP_TypeDef; 00729 /**************************************************************************/ 00734 typedef struct 00735 { 00736 __IO uint32_t CTRL; 00737 __IO uint32_t DISPCTRL; 00738 __IO uint32_t SEGEN; 00739 __IO uint32_t BACTRL; 00740 __I uint32_t STATUS; 00741 __IO uint32_t AREGA; 00742 __IO uint32_t AREGB; 00743 __I uint32_t IF; 00744 __IO uint32_t IFS; 00745 __IO uint32_t IFC; 00746 __IO uint32_t IEN; 00748 uint32_t RESERVED0[5]; 00749 __IO uint32_t SEGD0L; 00750 __IO uint32_t SEGD1L; 00751 __IO uint32_t SEGD2L; 00752 __IO uint32_t SEGD3L; 00753 __IO uint32_t SEGD0H; 00754 __IO uint32_t SEGD1H; 00755 __IO uint32_t SEGD2H; 00756 __IO uint32_t SEGD3H; 00758 __IO uint32_t FREEZE; 00759 __I uint32_t SYNCBUSY; 00760 } LCD_TypeDef; 00762 /**************************************************************************/ 00767 typedef struct 00768 { 00769 __IO uint32_t CTRL; 00770 __I uint32_t CNT; 00771 __IO uint32_t COMP0; 00772 __IO uint32_t COMP1; 00773 __I uint32_t IF; 00774 __IO uint32_t IFS; 00775 __IO uint32_t IFC; 00776 __IO uint32_t IEN; 00778 __IO uint32_t FREEZE; 00779 __I uint32_t SYNCBUSY; 00780 } RTC_TypeDef; 00782 /**************************************************************************/ 00787 typedef struct 00788 { 00789 __IO uint32_t CTRL; 00790 __IO uint32_t CMD; 00792 __I uint32_t SYNCBUSY; 00793 } WDOG_TypeDef; 00795 /**************************************************************************/ 00800 typedef struct 00801 { 00802 __I uint32_t CAL; 00803 __I uint32_t ADC0CAL0; 00804 __I uint32_t ADC0CAL1; 00805 __I uint32_t ADC0CAL2; 00806 uint32_t RESERVED0[2]; 00807 __I uint32_t DAC0CAL0; 00808 __I uint32_t DAC0CAL1; 00809 __I uint32_t DAC0CAL2; 00810 uint32_t RESERVED1[2]; 00811 __I uint32_t HFRCOCAL0; 00812 __I uint32_t HFRCOCAL1; 00813 uint32_t RESERVED2[3]; 00814 __I uint32_t UNIQUEL; 00815 __I uint32_t UNIQUEH; 00816 __I uint32_t MSIZE; 00817 __I uint32_t PART; 00818 } DEVINFO_TypeDef; 00820 /**************************************************************************/ 00825 typedef struct 00826 { 00827 __I uint32_t PID4; 00828 __I uint32_t PID5; 00829 __I uint32_t PID6; 00830 __I uint32_t PID7; 00831 __I uint32_t PID0; 00832 __I uint32_t PID1; 00833 __I uint32_t PID2; 00834 __I uint32_t PID3; 00835 __I uint32_t CID0; 00836 } ROMTABLE_TypeDef; 00838 /**************************************************************************/ 00843 #define CALIBRATE_MAX_REGISTERS 50 00845 typedef struct 00846 { 00847 __I uint32_t ADDRESS; 00848 __I uint32_t VALUE; 00849 } CALIBRATE_TypeDef; 00851 /**************************************************************************/ 00856 #define MSC_BASE (0x400C0000UL) 00857 #define EMU_BASE (0x400C6000UL) 00858 #define RMU_BASE (0x400CA000UL) 00859 #define CMU_BASE (0x400C8000UL) 00860 #define AES_BASE (0x400E0000UL) 00861 #define EBI_BASE (0x40008000UL) 00862 #define GPIO_BASE (0x40006000UL) 00863 #define PRS_BASE (0x400CC000UL) 00864 #define DMA_BASE (0x400C2000UL) 00865 #define TIMER0_BASE (0x40010000UL) 00866 #define TIMER1_BASE (0x40010400UL) 00867 #define TIMER2_BASE (0x40010800UL) 00868 #define USART0_BASE (0x4000C000UL) 00869 #define USART1_BASE (0x4000C400UL) 00870 #define USART2_BASE (0x4000C800UL) 00871 #define UART0_BASE (0x4000E000UL) 00872 #define LEUART0_BASE (0x40084000UL) 00873 #define LEUART1_BASE (0x40084400UL) 00874 #define LETIMER0_BASE (0x40082000UL) 00875 #define PCNT0_BASE (0x40086000UL) 00876 #define PCNT1_BASE (0x40086400UL) 00877 #define PCNT2_BASE (0x40086800UL) 00878 #define I2C0_BASE (0x4000A000UL) 00879 #define ADC0_BASE (0x40002000UL) 00880 #define DAC0_BASE (0x40004000UL) 00881 #define ACMP0_BASE (0x40001000UL) 00882 #define ACMP1_BASE (0x40001400UL) 00883 #define VCMP_BASE (0x40000000UL) 00884 #define LCD_BASE (0x4008A000UL) 00885 #define RTC_BASE (0x40080000UL) 00886 #define WDOG_BASE (0x40088000UL) 00887 #define CALIBRATE_BASE (0x0FE08000UL) 00888 #define DEVINFO_BASE (0x0FE081B0UL) 00889 #define ROMTABLE_BASE (0xE00FFFD0) 00894 /**************************************************************************/ 00900 #define MSC ((MSC_TypeDef *) MSC_BASE) 00901 #define EMU ((EMU_TypeDef *) EMU_BASE) 00902 #define RMU ((RMU_TypeDef *) RMU_BASE) 00903 #define CMU ((CMU_TypeDef *) CMU_BASE) 00904 #define AES ((AES_TypeDef *) AES_BASE) 00905 #define EBI ((EBI_TypeDef *) EBI_BASE) 00906 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) 00907 #define PRS ((PRS_TypeDef *) PRS_BASE) 00908 #define DMA ((DMA_TypeDef *) DMA_BASE) 00909 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) 00910 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) 00911 #define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) 00912 #define USART0 ((USART_TypeDef *) USART0_BASE) 00913 #define USART1 ((USART_TypeDef *) USART1_BASE) 00914 #define USART2 ((USART_TypeDef *) USART2_BASE) 00915 #define UART0 ((USART_TypeDef *) UART0_BASE) 00916 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) 00917 #define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) 00918 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) 00919 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) 00920 #define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) 00921 #define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) 00922 #define I2C0 ((I2C_TypeDef *) I2C0_BASE) 00923 #define ADC0 ((ADC_TypeDef *) ADC0_BASE) 00924 #define DAC0 ((DAC_TypeDef *) DAC0_BASE) 00925 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) 00926 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) 00927 #define VCMP ((VCMP_TypeDef *) VCMP_BASE) 00928 #define LCD ((LCD_TypeDef *) LCD_BASE) 00929 #define RTC ((RTC_TypeDef *) RTC_BASE) 00930 #define WDOG ((WDOG_TypeDef *) WDOG_BASE) 00931 #define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) 00932 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) 00933 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) 00943 /**************************************************************************/ 00948 /**************************************************************************/ 00954 #define PRS_VCMP_OUT ((1 << 16) + 0) 00955 #define PRS_ACMP0_OUT ((2 << 16) + 0) 00956 #define PRS_ACMP1_OUT ((3 << 16) + 0) 00957 #define PRS_DAC0_CH0 ((6 << 16) + 0) 00958 #define PRS_DAC0_CH1 ((6 << 16) + 1) 00959 #define PRS_ADC0_SINGLE ((8 << 16) + 0) 00960 #define PRS_ADC0_SCAN ((8 << 16) + 1) 00961 #define PRS_USART0_IRTX ((16 << 16) + 0) 00962 #define PRS_USART0_TXC ((16 << 16) + 1) 00963 #define PRS_USART0_RXDATAV ((16 << 16) + 2) 00964 #define PRS_USART1_IRTX ((17 << 16) + 0) 00965 #define PRS_USART1_TXC ((17 << 16) + 1) 00966 #define PRS_USART1_RXDATAV ((17 << 16) + 2) 00967 #define PRS_USART2_IRTX ((18 << 16) + 0) 00968 #define PRS_USART2_TXC ((18 << 16) + 1) 00969 #define PRS_USART2_RXDATAV ((18 << 16) + 2) 00970 #define PRS_TIMER0_UF ((28 << 16) + 0) 00971 #define PRS_TIMER0_OF ((28 << 16) + 1) 00972 #define PRS_TIMER0_CC0 ((28 << 16) + 2) 00973 #define PRS_TIMER0_CC1 ((28 << 16) + 3) 00974 #define PRS_TIMER0_CC2 ((28 << 16) + 4) 00975 #define PRS_TIMER1_UF ((29 << 16) + 0) 00976 #define PRS_TIMER1_OF ((29 << 16) + 1) 00977 #define PRS_TIMER1_CC0 ((29 << 16) + 2) 00978 #define PRS_TIMER1_CC1 ((29 << 16) + 3) 00979 #define PRS_TIMER1_CC2 ((29 << 16) + 4) 00980 #define PRS_TIMER2_UF ((30 << 16) + 0) 00981 #define PRS_TIMER2_OF ((30 << 16) + 1) 00982 #define PRS_TIMER2_CC0 ((30 << 16) + 2) 00983 #define PRS_TIMER2_CC1 ((30 << 16) + 3) 00984 #define PRS_TIMER2_CC2 ((30 << 16) + 4) 00985 #define PRS_RTC_OF ((40 << 16) + 0) 00986 #define PRS_RTC_COMP0 ((40 << 16) + 1) 00987 #define PRS_RTC_COMP1 ((40 << 16) + 2) 00988 #define PRS_UART0_IRTX ((41 << 16) + 0) 00989 #define PRS_UART0_TXC ((41 << 16) + 1) 00990 #define PRS_UART0_RXDATAV ((41 << 16) + 2) 00991 #define PRS_GPIO_PIN0 ((48 << 16) + 0) 00992 #define PRS_GPIO_PIN1 ((48 << 16) + 1) 00993 #define PRS_GPIO_PIN2 ((48 << 16) + 2) 00994 #define PRS_GPIO_PIN3 ((48 << 16) + 3) 00995 #define PRS_GPIO_PIN4 ((48 << 16) + 4) 00996 #define PRS_GPIO_PIN5 ((48 << 16) + 5) 00997 #define PRS_GPIO_PIN6 ((48 << 16) + 6) 00998 #define PRS_GPIO_PIN7 ((48 << 16) + 7) 00999 #define PRS_GPIO_PIN8 ((49 << 16) + 0) 01000 #define PRS_GPIO_PIN9 ((49 << 16) + 1) 01001 #define PRS_GPIO_PIN10 ((49 << 16) + 2) 01002 #define PRS_GPIO_PIN11 ((49 << 16) + 3) 01003 #define PRS_GPIO_PIN12 ((49 << 16) + 4) 01004 #define PRS_GPIO_PIN13 ((49 << 16) + 5) 01005 #define PRS_GPIO_PIN14 ((49 << 16) + 6) 01006 #define PRS_GPIO_PIN15 ((49 << 16) + 7) 01012 /**************************************************************************/ 01016 #define DMAREQ_ADC0_SINGLE ((8 << 16) + 0) 01017 #define DMAREQ_ADC0_SCAN ((8 << 16) + 1) 01018 #define DMAREQ_DAC0_CH0 ((10 << 16) + 0) 01019 #define DMAREQ_DAC0_CH1 ((10 << 16) + 1) 01020 #define DMAREQ_USART0_RXDATAV ((12 << 16) + 0) 01021 #define DMAREQ_USART0_TXBL ((12 << 16) + 1) 01022 #define DMAREQ_USART0_TXEMPTY ((12 << 16) + 2) 01023 #define DMAREQ_USART1_RXDATAV ((13 << 16) + 0) 01024 #define DMAREQ_USART1_TXBL ((13 << 16) + 1) 01025 #define DMAREQ_USART1_TXEMPTY ((13 << 16) + 2) 01026 #define DMAREQ_USART2_RXDATAV ((14 << 16) + 0) 01027 #define DMAREQ_USART2_TXBL ((14 << 16) + 1) 01028 #define DMAREQ_USART2_TXEMPTY ((14 << 16) + 2) 01029 #define DMAREQ_LEUART0_RXDATAV ((16 << 16) + 0) 01030 #define DMAREQ_LEUART0_TXBL ((16 << 16) + 1) 01031 #define DMAREQ_LEUART0_TXEMPTY ((16 << 16) + 2) 01032 #define DMAREQ_LEUART1_RXDATAV ((17 << 16) + 0) 01033 #define DMAREQ_LEUART1_TXBL ((17 << 16) + 1) 01034 #define DMAREQ_LEUART1_TXEMPTY ((17 << 16) + 2) 01035 #define DMAREQ_I2C0_RXDATAV ((20 << 16) + 0) 01036 #define DMAREQ_I2C0_TXBL ((20 << 16) + 1) 01037 #define DMAREQ_TIMER0_UFOF ((24 << 16) + 0) 01038 #define DMAREQ_TIMER0_CC0 ((24 << 16) + 1) 01039 #define DMAREQ_TIMER0_CC1 ((24 << 16) + 2) 01040 #define DMAREQ_TIMER0_CC2 ((24 << 16) + 3) 01041 #define DMAREQ_TIMER1_UFOF ((25 << 16) + 0) 01042 #define DMAREQ_TIMER1_CC0 ((25 << 16) + 1) 01043 #define DMAREQ_TIMER1_CC1 ((25 << 16) + 2) 01044 #define DMAREQ_TIMER1_CC2 ((25 << 16) + 3) 01045 #define DMAREQ_TIMER2_UFOF ((26 << 16) + 0) 01046 #define DMAREQ_TIMER2_CC0 ((26 << 16) + 1) 01047 #define DMAREQ_TIMER2_CC1 ((26 << 16) + 2) 01048 #define DMAREQ_TIMER2_CC2 ((26 << 16) + 3) 01049 #define DMAREQ_UART0_RXDATAV ((44 << 16) + 0) 01050 #define DMAREQ_UART0_TXBL ((44 << 16) + 1) 01051 #define DMAREQ_UART0_TXEMPTY ((44 << 16) + 2) 01052 #define DMAREQ_MSC_WDATA ((48 << 16) + 0) 01053 #define DMAREQ_AES_DATAWR ((49 << 16) + 0) 01054 #define DMAREQ_AES_XORDATAWR ((49 << 16) + 1) 01055 #define DMAREQ_AES_DATARD ((49 << 16) + 2) 01056 #define DMAREQ_AES_KEYWR ((49 << 16) + 3) 01058 /**************************************************************************/ 01061 typedef struct 01062 { 01063 /* Note! Use of double __IO (volatile) qualifier to ensure that both */ 01064 /* pointer and referenced memory are declared volatile. */ 01065 __IO void * __IO SRCEND; 01066 __IO void * __IO DSTEND; 01067 __IO uint32_t CTRL; 01068 __IO uint32_t USER; 01069 } DMA_DESCRIPTOR_TypeDef; 01070 01071 /**************************************************************************/ 01074 #define _DMA_CTRL_DST_INC_MASK 0xC0000000UL 01075 #define _DMA_CTRL_DST_INC_SHIFT 30 01076 #define _DMA_CTRL_DST_INC_BYTE 0x00 01077 #define _DMA_CTRL_DST_INC_HALFWORD 0x01 01078 #define _DMA_CTRL_DST_INC_WORD 0x02 01079 #define _DMA_CTRL_DST_INC_NONE 0x03 01080 #define DMA_CTRL_DST_INC_BYTE 0x00000000UL 01081 #define DMA_CTRL_DST_INC_HALFWORD 0x40000000UL 01082 #define DMA_CTRL_DST_INC_WORD 0x80000000UL 01083 #define DMA_CTRL_DST_INC_NONE 0xC0000000UL 01084 #define _DMA_CTRL_DST_SIZE_MASK 0x30000000UL 01085 #define _DMA_CTRL_DST_SIZE_SHIFT 28 01086 #define _DMA_CTRL_DST_SIZE_BYTE 0x00 01087 #define _DMA_CTRL_DST_SIZE_HALFWORD 0x01 01088 #define _DMA_CTRL_DST_SIZE_WORD 0x02 01089 #define _DMA_CTRL_DST_SIZE_RSVD 0x03 01090 #define DMA_CTRL_DST_SIZE_BYTE 0x00000000UL 01091 #define DMA_CTRL_DST_SIZE_HALFWORD 0x10000000UL 01092 #define DMA_CTRL_DST_SIZE_WORD 0x20000000UL 01093 #define DMA_CTRL_DST_SIZE_RSVD 0x30000000UL 01094 #define _DMA_CTRL_SRC_INC_MASK 0x0C000000UL 01095 #define _DMA_CTRL_SRC_INC_SHIFT 26 01096 #define _DMA_CTRL_SRC_INC_BYTE 0x00 01097 #define _DMA_CTRL_SRC_INC_HALFWORD 0x01 01098 #define _DMA_CTRL_SRC_INC_WORD 0x02 01099 #define _DMA_CTRL_SRC_INC_NONE 0x03 01100 #define DMA_CTRL_SRC_INC_BYTE 0x00000000UL 01101 #define DMA_CTRL_SRC_INC_HALFWORD 0x04000000UL 01102 #define DMA_CTRL_SRC_INC_WORD 0x08000000UL 01103 #define DMA_CTRL_SRC_INC_NONE 0x0C000000UL 01104 #define _DMA_CTRL_SRC_SIZE_MASK 0x03000000UL 01105 #define _DMA_CTRL_SRC_SIZE_SHIFT 24 01106 #define _DMA_CTRL_SRC_SIZE_BYTE 0x00 01107 #define _DMA_CTRL_SRC_SIZE_HALFWORD 0x01 01108 #define _DMA_CTRL_SRC_SIZE_WORD 0x02 01109 #define _DMA_CTRL_SRC_SIZE_RSVD 0x03 01110 #define DMA_CTRL_SRC_SIZE_BYTE 0x00000000UL 01111 #define DMA_CTRL_SRC_SIZE_HALFWORD 0x01000000UL 01112 #define DMA_CTRL_SRC_SIZE_WORD 0x02000000UL 01113 #define DMA_CTRL_SRC_SIZE_RSVD 0x03000000UL 01114 #define _DMA_CTRL_DST_PROT_CTRL_MASK 0x00E00000UL 01115 #define _DMA_CTRL_DST_PROT_CTRL_SHIFT 21 01116 #define DMA_CTRL_DST_PROT_PRIVILEGED 0x00200000UL 01117 #define DMA_CTRL_DST_PROT_NON_PRIVILEGED 0x00000000UL 01118 #define _DMA_CTRL_SRC_PROT_CTRL_MASK 0x001C0000UL 01119 #define _DMA_CTRL_SRC_PROT_CTRL_SHIFT 18 01120 #define DMA_CTRL_SRC_PROT_PRIVILEGED 0x00040000UL 01121 #define DMA_CTRL_SRC_PROT_NON_PRIVILEGED 0x00000000UL 01122 #define _DMA_CTRL_PROT_NON_PRIVILEGED 0x00 01123 #define _DMA_CTRL_PROT_PRIVILEGED 0x01 01124 #define _DMA_CTRL_R_POWER_MASK 0x0003C000UL 01125 #define _DMA_CTRL_R_POWER_SHIFT 14 01126 #define _DMA_CTRL_R_POWER_1 0x00 01127 #define _DMA_CTRL_R_POWER_2 0x01 01128 #define _DMA_CTRL_R_POWER_4 0x02 01129 #define _DMA_CTRL_R_POWER_8 0x03 01130 #define _DMA_CTRL_R_POWER_16 0x04 01131 #define _DMA_CTRL_R_POWER_32 0x05 01132 #define _DMA_CTRL_R_POWER_64 0x06 01133 #define _DMA_CTRL_R_POWER_128 0x07 01134 #define _DMA_CTRL_R_POWER_256 0x08 01135 #define _DMA_CTRL_R_POWER_512 0x09 01136 #define _DMA_CTRL_R_POWER_1024 0x0a 01137 #define DMA_CTRL_R_POWER_1 0x00000000UL 01138 #define DMA_CTRL_R_POWER_2 0x00004000UL 01139 #define DMA_CTRL_R_POWER_4 0x00008000UL 01140 #define DMA_CTRL_R_POWER_8 0x0000c000UL 01141 #define DMA_CTRL_R_POWER_16 0x00010000UL 01142 #define DMA_CTRL_R_POWER_32 0x00014000UL 01143 #define DMA_CTRL_R_POWER_64 0x00018000UL 01144 #define DMA_CTRL_R_POWER_128 0x0001c000UL 01145 #define DMA_CTRL_R_POWER_256 0x00020000UL 01146 #define DMA_CTRL_R_POWER_512 0x00024000UL 01147 #define DMA_CTRL_R_POWER_1024 0x00028000UL 01148 #define _DMA_CTRL_N_MINUS_1_MASK 0x00003FF0UL 01149 #define _DMA_CTRL_N_MINUS_1_SHIFT 4 01150 #define _DMA_CTRL_NEXT_USEBURST_MASK 0x00000008UL 01151 #define _DMA_CTRL_NEXT_USEBURST_SHIFT 3 01152 #define _DMA_CTRL_CYCLE_CTRL_MASK 0x00000007UL 01153 #define _DMA_CTRL_CYCLE_CTRL_SHIFT 0 01154 #define _DMA_CTRL_CYCLE_CTRL_INVALID 0x00 01155 #define _DMA_CTRL_CYCLE_CTRL_BASIC 0x01 01156 #define _DMA_CTRL_CYCLE_CTRL_AUTO 0x02 01157 #define _DMA_CTRL_CYCLE_CTRL_PINGPONG 0x03 01158 #define _DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER 0x04 01159 #define _DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER_ALT 0x05 01160 #define _DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER 0x06 01161 #define _DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT 0x07 01162 #define DMA_CTRL_CYCLE_CTRL_INVALID 0x00000000UL 01163 #define DMA_CTRL_CYCLE_CTRL_BASIC 0x00000001UL 01164 #define DMA_CTRL_CYCLE_CTRL_AUTO 0x00000002UL 01165 #define DMA_CTRL_CYCLE_CTRL_PINGPONG 0x00000003UL 01166 #define DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER 0x000000004UL 01167 #define DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER_ALT 0x000000005UL 01168 #define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER 0x000000006UL 01169 #define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT 0x000000007UL 01175 /**************************************************************************/ 01180 /* Bit fields for TIMER CTRL */ 01181 #define _TIMER_CTRL_RESETVALUE 0x00000000UL 01182 #define _TIMER_CTRL_MASK 0x0F030FFBUL 01183 #define _TIMER_CTRL_MODE_SHIFT 0 01184 #define _TIMER_CTRL_MODE_MASK 0x3UL 01185 #define _TIMER_CTRL_MODE_DEFAULT 0x00000000UL 01186 #define _TIMER_CTRL_MODE_UP 0x00000000UL 01187 #define _TIMER_CTRL_MODE_DOWN 0x00000001UL 01188 #define _TIMER_CTRL_MODE_UPDOWN 0x00000002UL 01189 #define _TIMER_CTRL_MODE_QDEC 0x00000003UL 01190 #define TIMER_CTRL_MODE_DEFAULT (_TIMER_CTRL_MODE_DEFAULT << 0) 01191 #define TIMER_CTRL_MODE_UP (_TIMER_CTRL_MODE_UP << 0) 01192 #define TIMER_CTRL_MODE_DOWN (_TIMER_CTRL_MODE_DOWN << 0) 01193 #define TIMER_CTRL_MODE_UPDOWN (_TIMER_CTRL_MODE_UPDOWN << 0) 01194 #define TIMER_CTRL_MODE_QDEC (_TIMER_CTRL_MODE_QDEC << 0) 01195 #define TIMER_CTRL_SYNC (0x1UL << 3) 01196 #define _TIMER_CTRL_SYNC_SHIFT 3 01197 #define _TIMER_CTRL_SYNC_MASK 0x8UL 01198 #define _TIMER_CTRL_SYNC_DEFAULT 0x00000000UL 01199 #define TIMER_CTRL_SYNC_DEFAULT (_TIMER_CTRL_SYNC_DEFAULT << 3) 01200 #define TIMER_CTRL_OSMEN (0x1UL << 4) 01201 #define _TIMER_CTRL_OSMEN_SHIFT 4 01202 #define _TIMER_CTRL_OSMEN_MASK 0x10UL 01203 #define _TIMER_CTRL_OSMEN_DEFAULT 0x00000000UL 01204 #define TIMER_CTRL_OSMEN_DEFAULT (_TIMER_CTRL_OSMEN_DEFAULT << 4) 01205 #define TIMER_CTRL_QDM (0x1UL << 5) 01206 #define _TIMER_CTRL_QDM_SHIFT 5 01207 #define _TIMER_CTRL_QDM_MASK 0x20UL 01208 #define _TIMER_CTRL_QDM_DEFAULT 0x00000000UL 01209 #define _TIMER_CTRL_QDM_X2 0x00000000UL 01210 #define _TIMER_CTRL_QDM_X4 0x00000001UL 01211 #define TIMER_CTRL_QDM_DEFAULT (_TIMER_CTRL_QDM_DEFAULT << 5) 01212 #define TIMER_CTRL_QDM_X2 (_TIMER_CTRL_QDM_X2 << 5) 01213 #define TIMER_CTRL_QDM_X4 (_TIMER_CTRL_QDM_X4 << 5) 01214 #define TIMER_CTRL_DEBUGRUN (0x1UL << 6) 01215 #define _TIMER_CTRL_DEBUGRUN_SHIFT 6 01216 #define _TIMER_CTRL_DEBUGRUN_MASK 0x40UL 01217 #define _TIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL 01218 #define TIMER_CTRL_DEBUGRUN_DEFAULT (_TIMER_CTRL_DEBUGRUN_DEFAULT << 6) 01219 #define TIMER_CTRL_DMACLRACT (0x1UL << 7) 01220 #define _TIMER_CTRL_DMACLRACT_SHIFT 7 01221 #define _TIMER_CTRL_DMACLRACT_MASK 0x80UL 01222 #define _TIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL 01223 #define TIMER_CTRL_DMACLRACT_DEFAULT (_TIMER_CTRL_DMACLRACT_DEFAULT << 7) 01224 #define _TIMER_CTRL_RISEA_SHIFT 8 01225 #define _TIMER_CTRL_RISEA_MASK 0x300UL 01226 #define _TIMER_CTRL_RISEA_DEFAULT 0x00000000UL 01227 #define _TIMER_CTRL_RISEA_NONE 0x00000000UL 01228 #define _TIMER_CTRL_RISEA_START 0x00000001UL 01229 #define _TIMER_CTRL_RISEA_STOP 0x00000002UL 01230 #define _TIMER_CTRL_RISEA_RELOADSTART 0x00000003UL 01231 #define TIMER_CTRL_RISEA_DEFAULT (_TIMER_CTRL_RISEA_DEFAULT << 8) 01232 #define TIMER_CTRL_RISEA_NONE (_TIMER_CTRL_RISEA_NONE << 8) 01233 #define TIMER_CTRL_RISEA_START (_TIMER_CTRL_RISEA_START << 8) 01234 #define TIMER_CTRL_RISEA_STOP (_TIMER_CTRL_RISEA_STOP << 8) 01235 #define TIMER_CTRL_RISEA_RELOADSTART (_TIMER_CTRL_RISEA_RELOADSTART << 8) 01236 #define _TIMER_CTRL_FALLA_SHIFT 10 01237 #define _TIMER_CTRL_FALLA_MASK 0xC00UL 01238 #define _TIMER_CTRL_FALLA_DEFAULT 0x00000000UL 01239 #define _TIMER_CTRL_FALLA_NONE 0x00000000UL 01240 #define _TIMER_CTRL_FALLA_START 0x00000001UL 01241 #define _TIMER_CTRL_FALLA_STOP 0x00000002UL 01242 #define _TIMER_CTRL_FALLA_RELOADSTART 0x00000003UL 01243 #define TIMER_CTRL_FALLA_DEFAULT (_TIMER_CTRL_FALLA_DEFAULT << 10) 01244 #define TIMER_CTRL_FALLA_NONE (_TIMER_CTRL_FALLA_NONE << 10) 01245 #define TIMER_CTRL_FALLA_START (_TIMER_CTRL_FALLA_START << 10) 01246 #define TIMER_CTRL_FALLA_STOP (_TIMER_CTRL_FALLA_STOP << 10) 01247 #define TIMER_CTRL_FALLA_RELOADSTART (_TIMER_CTRL_FALLA_RELOADSTART << 10) 01248 #define _TIMER_CTRL_CLKSEL_SHIFT 16 01249 #define _TIMER_CTRL_CLKSEL_MASK 0x30000UL 01250 #define _TIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL 01251 #define _TIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL 01252 #define _TIMER_CTRL_CLKSEL_CC1 0x00000001UL 01253 #define _TIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL 01254 #define TIMER_CTRL_CLKSEL_DEFAULT (_TIMER_CTRL_CLKSEL_DEFAULT << 16) 01255 #define TIMER_CTRL_CLKSEL_PRESCHFPERCLK (_TIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) 01256 #define TIMER_CTRL_CLKSEL_CC1 (_TIMER_CTRL_CLKSEL_CC1 << 16) 01257 #define TIMER_CTRL_CLKSEL_TIMEROUF (_TIMER_CTRL_CLKSEL_TIMEROUF << 16) 01258 #define _TIMER_CTRL_PRESC_SHIFT 24 01259 #define _TIMER_CTRL_PRESC_MASK 0xF000000UL 01260 #define _TIMER_CTRL_PRESC_DEFAULT 0x00000000UL 01261 #define _TIMER_CTRL_PRESC_DIV1 0x00000000UL 01262 #define _TIMER_CTRL_PRESC_DIV2 0x00000001UL 01263 #define _TIMER_CTRL_PRESC_DIV4 0x00000002UL 01264 #define _TIMER_CTRL_PRESC_DIV8 0x00000003UL 01265 #define _TIMER_CTRL_PRESC_DIV16 0x00000004UL 01266 #define _TIMER_CTRL_PRESC_DIV32 0x00000005UL 01267 #define _TIMER_CTRL_PRESC_DIV64 0x00000006UL 01268 #define _TIMER_CTRL_PRESC_DIV128 0x00000007UL 01269 #define _TIMER_CTRL_PRESC_DIV256 0x00000008UL 01270 #define _TIMER_CTRL_PRESC_DIV512 0x00000009UL 01271 #define _TIMER_CTRL_PRESC_DIV1024 0x0000000AUL 01272 #define TIMER_CTRL_PRESC_DEFAULT (_TIMER_CTRL_PRESC_DEFAULT << 24) 01273 #define TIMER_CTRL_PRESC_DIV1 (_TIMER_CTRL_PRESC_DIV1 << 24) 01274 #define TIMER_CTRL_PRESC_DIV2 (_TIMER_CTRL_PRESC_DIV2 << 24) 01275 #define TIMER_CTRL_PRESC_DIV4 (_TIMER_CTRL_PRESC_DIV4 << 24) 01276 #define TIMER_CTRL_PRESC_DIV8 (_TIMER_CTRL_PRESC_DIV8 << 24) 01277 #define TIMER_CTRL_PRESC_DIV16 (_TIMER_CTRL_PRESC_DIV16 << 24) 01278 #define TIMER_CTRL_PRESC_DIV32 (_TIMER_CTRL_PRESC_DIV32 << 24) 01279 #define TIMER_CTRL_PRESC_DIV64 (_TIMER_CTRL_PRESC_DIV64 << 24) 01280 #define TIMER_CTRL_PRESC_DIV128 (_TIMER_CTRL_PRESC_DIV128 << 24) 01281 #define TIMER_CTRL_PRESC_DIV256 (_TIMER_CTRL_PRESC_DIV256 << 24) 01282 #define TIMER_CTRL_PRESC_DIV512 (_TIMER_CTRL_PRESC_DIV512 << 24) 01283 #define TIMER_CTRL_PRESC_DIV1024 (_TIMER_CTRL_PRESC_DIV1024 << 24) 01285 /* Bit fields for TIMER CMD */ 01286 #define _TIMER_CMD_RESETVALUE 0x00000000UL 01287 #define _TIMER_CMD_MASK 0x00000003UL 01288 #define TIMER_CMD_START (0x1UL << 0) 01289 #define _TIMER_CMD_START_SHIFT 0 01290 #define _TIMER_CMD_START_MASK 0x1UL 01291 #define _TIMER_CMD_START_DEFAULT 0x00000000UL 01292 #define TIMER_CMD_START_DEFAULT (_TIMER_CMD_START_DEFAULT << 0) 01293 #define TIMER_CMD_STOP (0x1UL << 1) 01294 #define _TIMER_CMD_STOP_SHIFT 1 01295 #define _TIMER_CMD_STOP_MASK 0x2UL 01296 #define _TIMER_CMD_STOP_DEFAULT 0x00000000UL 01297 #define TIMER_CMD_STOP_DEFAULT (_TIMER_CMD_STOP_DEFAULT << 1) 01299 /* Bit fields for TIMER STATUS */ 01300 #define _TIMER_STATUS_RESETVALUE 0x00000000UL 01301 #define _TIMER_STATUS_MASK 0x07070707UL 01302 #define TIMER_STATUS_RUNNING (0x1UL << 0) 01303 #define _TIMER_STATUS_RUNNING_SHIFT 0 01304 #define _TIMER_STATUS_RUNNING_MASK 0x1UL 01305 #define _TIMER_STATUS_RUNNING_DEFAULT 0x00000000UL 01306 #define TIMER_STATUS_RUNNING_DEFAULT (_TIMER_STATUS_RUNNING_DEFAULT << 0) 01307 #define TIMER_STATUS_DIR (0x1UL << 1) 01308 #define _TIMER_STATUS_DIR_SHIFT 1 01309 #define _TIMER_STATUS_DIR_MASK 0x2UL 01310 #define _TIMER_STATUS_DIR_DEFAULT 0x00000000UL 01311 #define _TIMER_STATUS_DIR_UP 0x00000000UL 01312 #define _TIMER_STATUS_DIR_DOWN 0x00000001UL 01313 #define TIMER_STATUS_DIR_DEFAULT (_TIMER_STATUS_DIR_DEFAULT << 1) 01314 #define TIMER_STATUS_DIR_UP (_TIMER_STATUS_DIR_UP << 1) 01315 #define TIMER_STATUS_DIR_DOWN (_TIMER_STATUS_DIR_DOWN << 1) 01316 #define TIMER_STATUS_TOPBV (0x1UL << 2) 01317 #define _TIMER_STATUS_TOPBV_SHIFT 2 01318 #define _TIMER_STATUS_TOPBV_MASK 0x4UL 01319 #define _TIMER_STATUS_TOPBV_DEFAULT 0x00000000UL 01320 #define TIMER_STATUS_TOPBV_DEFAULT (_TIMER_STATUS_TOPBV_DEFAULT << 2) 01321 #define TIMER_STATUS_CCVBV0 (0x1UL << 8) 01322 #define _TIMER_STATUS_CCVBV0_SHIFT 8 01323 #define _TIMER_STATUS_CCVBV0_MASK 0x100UL 01324 #define _TIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL 01325 #define TIMER_STATUS_CCVBV0_DEFAULT (_TIMER_STATUS_CCVBV0_DEFAULT << 8) 01326 #define TIMER_STATUS_CCVBV1 (0x1UL << 9) 01327 #define _TIMER_STATUS_CCVBV1_SHIFT 9 01328 #define _TIMER_STATUS_CCVBV1_MASK 0x200UL 01329 #define _TIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL 01330 #define TIMER_STATUS_CCVBV1_DEFAULT (_TIMER_STATUS_CCVBV1_DEFAULT << 9) 01331 #define TIMER_STATUS_CCVBV2 (0x1UL << 10) 01332 #define _TIMER_STATUS_CCVBV2_SHIFT 10 01333 #define _TIMER_STATUS_CCVBV2_MASK 0x400UL 01334 #define _TIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL 01335 #define TIMER_STATUS_CCVBV2_DEFAULT (_TIMER_STATUS_CCVBV2_DEFAULT << 10) 01336 #define TIMER_STATUS_ICV0 (0x1UL << 16) 01337 #define _TIMER_STATUS_ICV0_SHIFT 16 01338 #define _TIMER_STATUS_ICV0_MASK 0x10000UL 01339 #define _TIMER_STATUS_ICV0_DEFAULT 0x00000000UL 01340 #define TIMER_STATUS_ICV0_DEFAULT (_TIMER_STATUS_ICV0_DEFAULT << 16) 01341 #define TIMER_STATUS_ICV1 (0x1UL << 17) 01342 #define _TIMER_STATUS_ICV1_SHIFT 17 01343 #define _TIMER_STATUS_ICV1_MASK 0x20000UL 01344 #define _TIMER_STATUS_ICV1_DEFAULT 0x00000000UL 01345 #define TIMER_STATUS_ICV1_DEFAULT (_TIMER_STATUS_ICV1_DEFAULT << 17) 01346 #define TIMER_STATUS_ICV2 (0x1UL << 18) 01347 #define _TIMER_STATUS_ICV2_SHIFT 18 01348 #define _TIMER_STATUS_ICV2_MASK 0x40000UL 01349 #define _TIMER_STATUS_ICV2_DEFAULT 0x00000000UL 01350 #define TIMER_STATUS_ICV2_DEFAULT (_TIMER_STATUS_ICV2_DEFAULT << 18) 01351 #define TIMER_STATUS_CCPOL0 (0x1UL << 24) 01352 #define _TIMER_STATUS_CCPOL0_SHIFT 24 01353 #define _TIMER_STATUS_CCPOL0_MASK 0x1000000UL 01354 #define _TIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL 01355 #define _TIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL 01356 #define _TIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL 01357 #define TIMER_STATUS_CCPOL0_DEFAULT (_TIMER_STATUS_CCPOL0_DEFAULT << 24) 01358 #define TIMER_STATUS_CCPOL0_LOWRISE (_TIMER_STATUS_CCPOL0_LOWRISE << 24) 01359 #define TIMER_STATUS_CCPOL0_HIGHFALL (_TIMER_STATUS_CCPOL0_HIGHFALL << 24) 01360 #define TIMER_STATUS_CCPOL1 (0x1UL << 25) 01361 #define _TIMER_STATUS_CCPOL1_SHIFT 25 01362 #define _TIMER_STATUS_CCPOL1_MASK 0x2000000UL 01363 #define _TIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL 01364 #define _TIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL 01365 #define _TIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL 01366 #define TIMER_STATUS_CCPOL1_DEFAULT (_TIMER_STATUS_CCPOL1_DEFAULT << 25) 01367 #define TIMER_STATUS_CCPOL1_LOWRISE (_TIMER_STATUS_CCPOL1_LOWRISE << 25) 01368 #define TIMER_STATUS_CCPOL1_HIGHFALL (_TIMER_STATUS_CCPOL1_HIGHFALL << 25) 01369 #define TIMER_STATUS_CCPOL2 (0x1UL << 26) 01370 #define _TIMER_STATUS_CCPOL2_SHIFT 26 01371 #define _TIMER_STATUS_CCPOL2_MASK 0x4000000UL 01372 #define _TIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL 01373 #define _TIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL 01374 #define _TIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL 01375 #define TIMER_STATUS_CCPOL2_DEFAULT (_TIMER_STATUS_CCPOL2_DEFAULT << 26) 01376 #define TIMER_STATUS_CCPOL2_LOWRISE (_TIMER_STATUS_CCPOL2_LOWRISE << 26) 01377 #define TIMER_STATUS_CCPOL2_HIGHFALL (_TIMER_STATUS_CCPOL2_HIGHFALL << 26) 01379 /* Bit fields for TIMER IEN */ 01380 #define _TIMER_IEN_RESETVALUE 0x00000000UL 01381 #define _TIMER_IEN_MASK 0x00000773UL 01382 #define TIMER_IEN_OF (0x1UL << 0) 01383 #define _TIMER_IEN_OF_SHIFT 0 01384 #define _TIMER_IEN_OF_MASK 0x1UL 01385 #define _TIMER_IEN_OF_DEFAULT 0x00000000UL 01386 #define TIMER_IEN_OF_DEFAULT (_TIMER_IEN_OF_DEFAULT << 0) 01387 #define TIMER_IEN_UF (0x1UL << 1) 01388 #define _TIMER_IEN_UF_SHIFT 1 01389 #define _TIMER_IEN_UF_MASK 0x2UL 01390 #define _TIMER_IEN_UF_DEFAULT 0x00000000UL 01391 #define TIMER_IEN_UF_DEFAULT (_TIMER_IEN_UF_DEFAULT << 1) 01392 #define TIMER_IEN_CC0 (0x1UL << 4) 01393 #define _TIMER_IEN_CC0_SHIFT 4 01394 #define _TIMER_IEN_CC0_MASK 0x10UL 01395 #define _TIMER_IEN_CC0_DEFAULT 0x00000000UL 01396 #define TIMER_IEN_CC0_DEFAULT (_TIMER_IEN_CC0_DEFAULT << 4) 01397 #define TIMER_IEN_CC1 (0x1UL << 5) 01398 #define _TIMER_IEN_CC1_SHIFT 5 01399 #define _TIMER_IEN_CC1_MASK 0x20UL 01400 #define _TIMER_IEN_CC1_DEFAULT 0x00000000UL 01401 #define TIMER_IEN_CC1_DEFAULT (_TIMER_IEN_CC1_DEFAULT << 5) 01402 #define TIMER_IEN_CC2 (0x1UL << 6) 01403 #define _TIMER_IEN_CC2_SHIFT 6 01404 #define _TIMER_IEN_CC2_MASK 0x40UL 01405 #define _TIMER_IEN_CC2_DEFAULT 0x00000000UL 01406 #define TIMER_IEN_CC2_DEFAULT (_TIMER_IEN_CC2_DEFAULT << 6) 01407 #define TIMER_IEN_ICBOF0 (0x1UL << 8) 01408 #define _TIMER_IEN_ICBOF0_SHIFT 8 01409 #define _TIMER_IEN_ICBOF0_MASK 0x100UL 01410 #define _TIMER_IEN_ICBOF0_DEFAULT 0x00000000UL 01411 #define TIMER_IEN_ICBOF0_DEFAULT (_TIMER_IEN_ICBOF0_DEFAULT << 8) 01412 #define TIMER_IEN_ICBOF1 (0x1UL << 9) 01413 #define _TIMER_IEN_ICBOF1_SHIFT 9 01414 #define _TIMER_IEN_ICBOF1_MASK 0x200UL 01415 #define _TIMER_IEN_ICBOF1_DEFAULT 0x00000000UL 01416 #define TIMER_IEN_ICBOF1_DEFAULT (_TIMER_IEN_ICBOF1_DEFAULT << 9) 01417 #define TIMER_IEN_ICBOF2 (0x1UL << 10) 01418 #define _TIMER_IEN_ICBOF2_SHIFT 10 01419 #define _TIMER_IEN_ICBOF2_MASK 0x400UL 01420 #define _TIMER_IEN_ICBOF2_DEFAULT 0x00000000UL 01421 #define TIMER_IEN_ICBOF2_DEFAULT (_TIMER_IEN_ICBOF2_DEFAULT << 10) 01423 /* Bit fields for TIMER IF */ 01424 #define _TIMER_IF_RESETVALUE 0x00000000UL 01425 #define _TIMER_IF_MASK 0x00000773UL 01426 #define TIMER_IF_OF (0x1UL << 0) 01427 #define _TIMER_IF_OF_SHIFT 0 01428 #define _TIMER_IF_OF_MASK 0x1UL 01429 #define _TIMER_IF_OF_DEFAULT 0x00000000UL 01430 #define TIMER_IF_OF_DEFAULT (_TIMER_IF_OF_DEFAULT << 0) 01431 #define TIMER_IF_UF (0x1UL << 1) 01432 #define _TIMER_IF_UF_SHIFT 1 01433 #define _TIMER_IF_UF_MASK 0x2UL 01434 #define _TIMER_IF_UF_DEFAULT 0x00000000UL 01435 #define TIMER_IF_UF_DEFAULT (_TIMER_IF_UF_DEFAULT << 1) 01436 #define TIMER_IF_CC0 (0x1UL << 4) 01437 #define _TIMER_IF_CC0_SHIFT 4 01438 #define _TIMER_IF_CC0_MASK 0x10UL 01439 #define _TIMER_IF_CC0_DEFAULT 0x00000000UL 01440 #define TIMER_IF_CC0_DEFAULT (_TIMER_IF_CC0_DEFAULT << 4) 01441 #define TIMER_IF_CC1 (0x1UL << 5) 01442 #define _TIMER_IF_CC1_SHIFT 5 01443 #define _TIMER_IF_CC1_MASK 0x20UL 01444 #define _TIMER_IF_CC1_DEFAULT 0x00000000UL 01445 #define TIMER_IF_CC1_DEFAULT (_TIMER_IF_CC1_DEFAULT << 5) 01446 #define TIMER_IF_CC2 (0x1UL << 6) 01447 #define _TIMER_IF_CC2_SHIFT 6 01448 #define _TIMER_IF_CC2_MASK 0x40UL 01449 #define _TIMER_IF_CC2_DEFAULT 0x00000000UL 01450 #define TIMER_IF_CC2_DEFAULT (_TIMER_IF_CC2_DEFAULT << 6) 01451 #define TIMER_IF_ICBOF0 (0x1UL << 8) 01452 #define _TIMER_IF_ICBOF0_SHIFT 8 01453 #define _TIMER_IF_ICBOF0_MASK 0x100UL 01454 #define _TIMER_IF_ICBOF0_DEFAULT 0x00000000UL 01455 #define TIMER_IF_ICBOF0_DEFAULT (_TIMER_IF_ICBOF0_DEFAULT << 8) 01456 #define TIMER_IF_ICBOF1 (0x1UL << 9) 01457 #define _TIMER_IF_ICBOF1_SHIFT 9 01458 #define _TIMER_IF_ICBOF1_MASK 0x200UL 01459 #define _TIMER_IF_ICBOF1_DEFAULT 0x00000000UL 01460 #define TIMER_IF_ICBOF1_DEFAULT (_TIMER_IF_ICBOF1_DEFAULT << 9) 01461 #define TIMER_IF_ICBOF2 (0x1UL << 10) 01462 #define _TIMER_IF_ICBOF2_SHIFT 10 01463 #define _TIMER_IF_ICBOF2_MASK 0x400UL 01464 #define _TIMER_IF_ICBOF2_DEFAULT 0x00000000UL 01465 #define TIMER_IF_ICBOF2_DEFAULT (_TIMER_IF_ICBOF2_DEFAULT << 10) 01467 /* Bit fields for TIMER IFS */ 01468 #define _TIMER_IFS_RESETVALUE 0x00000000UL 01469 #define _TIMER_IFS_MASK 0x00000773UL 01470 #define TIMER_IFS_OF (0x1UL << 0) 01471 #define _TIMER_IFS_OF_SHIFT 0 01472 #define _TIMER_IFS_OF_MASK 0x1UL 01473 #define _TIMER_IFS_OF_DEFAULT 0x00000000UL 01474 #define TIMER_IFS_OF_DEFAULT (_TIMER_IFS_OF_DEFAULT << 0) 01475 #define TIMER_IFS_UF (0x1UL << 1) 01476 #define _TIMER_IFS_UF_SHIFT 1 01477 #define _TIMER_IFS_UF_MASK 0x2UL 01478 #define _TIMER_IFS_UF_DEFAULT 0x00000000UL 01479 #define TIMER_IFS_UF_DEFAULT (_TIMER_IFS_UF_DEFAULT << 1) 01480 #define TIMER_IFS_CC0 (0x1UL << 4) 01481 #define _TIMER_IFS_CC0_SHIFT 4 01482 #define _TIMER_IFS_CC0_MASK 0x10UL 01483 #define _TIMER_IFS_CC0_DEFAULT 0x00000000UL 01484 #define TIMER_IFS_CC0_DEFAULT (_TIMER_IFS_CC0_DEFAULT << 4) 01485 #define TIMER_IFS_CC1 (0x1UL << 5) 01486 #define _TIMER_IFS_CC1_SHIFT 5 01487 #define _TIMER_IFS_CC1_MASK 0x20UL 01488 #define _TIMER_IFS_CC1_DEFAULT 0x00000000UL 01489 #define TIMER_IFS_CC1_DEFAULT (_TIMER_IFS_CC1_DEFAULT << 5) 01490 #define TIMER_IFS_CC2 (0x1UL << 6) 01491 #define _TIMER_IFS_CC2_SHIFT 6 01492 #define _TIMER_IFS_CC2_MASK 0x40UL 01493 #define _TIMER_IFS_CC2_DEFAULT 0x00000000UL 01494 #define TIMER_IFS_CC2_DEFAULT (_TIMER_IFS_CC2_DEFAULT << 6) 01495 #define TIMER_IFS_ICBOF0 (0x1UL << 8) 01496 #define _TIMER_IFS_ICBOF0_SHIFT 8 01497 #define _TIMER_IFS_ICBOF0_MASK 0x100UL 01498 #define _TIMER_IFS_ICBOF0_DEFAULT 0x00000000UL 01499 #define TIMER_IFS_ICBOF0_DEFAULT (_TIMER_IFS_ICBOF0_DEFAULT << 8) 01500 #define TIMER_IFS_ICBOF1 (0x1UL << 9) 01501 #define _TIMER_IFS_ICBOF1_SHIFT 9 01502 #define _TIMER_IFS_ICBOF1_MASK 0x200UL 01503 #define _TIMER_IFS_ICBOF1_DEFAULT 0x00000000UL 01504 #define TIMER_IFS_ICBOF1_DEFAULT (_TIMER_IFS_ICBOF1_DEFAULT << 9) 01505 #define TIMER_IFS_ICBOF2 (0x1UL << 10) 01506 #define _TIMER_IFS_ICBOF2_SHIFT 10 01507 #define _TIMER_IFS_ICBOF2_MASK 0x400UL 01508 #define _TIMER_IFS_ICBOF2_DEFAULT 0x00000000UL 01509 #define TIMER_IFS_ICBOF2_DEFAULT (_TIMER_IFS_ICBOF2_DEFAULT << 10) 01511 /* Bit fields for TIMER IFC */ 01512 #define _TIMER_IFC_RESETVALUE 0x00000000UL 01513 #define _TIMER_IFC_MASK 0x00000773UL 01514 #define TIMER_IFC_OF (0x1UL << 0) 01515 #define _TIMER_IFC_OF_SHIFT 0 01516 #define _TIMER_IFC_OF_MASK 0x1UL 01517 #define _TIMER_IFC_OF_DEFAULT 0x00000000UL 01518 #define TIMER_IFC_OF_DEFAULT (_TIMER_IFC_OF_DEFAULT << 0) 01519 #define TIMER_IFC_UF (0x1UL << 1) 01520 #define _TIMER_IFC_UF_SHIFT 1 01521 #define _TIMER_IFC_UF_MASK 0x2UL 01522 #define _TIMER_IFC_UF_DEFAULT 0x00000000UL 01523 #define TIMER_IFC_UF_DEFAULT (_TIMER_IFC_UF_DEFAULT << 1) 01524 #define TIMER_IFC_CC0 (0x1UL << 4) 01525 #define _TIMER_IFC_CC0_SHIFT 4 01526 #define _TIMER_IFC_CC0_MASK 0x10UL 01527 #define _TIMER_IFC_CC0_DEFAULT 0x00000000UL 01528 #define TIMER_IFC_CC0_DEFAULT (_TIMER_IFC_CC0_DEFAULT << 4) 01529 #define TIMER_IFC_CC1 (0x1UL << 5) 01530 #define _TIMER_IFC_CC1_SHIFT 5 01531 #define _TIMER_IFC_CC1_MASK 0x20UL 01532 #define _TIMER_IFC_CC1_DEFAULT 0x00000000UL 01533 #define TIMER_IFC_CC1_DEFAULT (_TIMER_IFC_CC1_DEFAULT << 5) 01534 #define TIMER_IFC_CC2 (0x1UL << 6) 01535 #define _TIMER_IFC_CC2_SHIFT 6 01536 #define _TIMER_IFC_CC2_MASK 0x40UL 01537 #define _TIMER_IFC_CC2_DEFAULT 0x00000000UL 01538 #define TIMER_IFC_CC2_DEFAULT (_TIMER_IFC_CC2_DEFAULT << 6) 01539 #define TIMER_IFC_ICBOF0 (0x1UL << 8) 01540 #define _TIMER_IFC_ICBOF0_SHIFT 8 01541 #define _TIMER_IFC_ICBOF0_MASK 0x100UL 01542 #define _TIMER_IFC_ICBOF0_DEFAULT 0x00000000UL 01543 #define TIMER_IFC_ICBOF0_DEFAULT (_TIMER_IFC_ICBOF0_DEFAULT << 8) 01544 #define TIMER_IFC_ICBOF1 (0x1UL << 9) 01545 #define _TIMER_IFC_ICBOF1_SHIFT 9 01546 #define _TIMER_IFC_ICBOF1_MASK 0x200UL 01547 #define _TIMER_IFC_ICBOF1_DEFAULT 0x00000000UL 01548 #define TIMER_IFC_ICBOF1_DEFAULT (_TIMER_IFC_ICBOF1_DEFAULT << 9) 01549 #define TIMER_IFC_ICBOF2 (0x1UL << 10) 01550 #define _TIMER_IFC_ICBOF2_SHIFT 10 01551 #define _TIMER_IFC_ICBOF2_MASK 0x400UL 01552 #define _TIMER_IFC_ICBOF2_DEFAULT 0x00000000UL 01553 #define TIMER_IFC_ICBOF2_DEFAULT (_TIMER_IFC_ICBOF2_DEFAULT << 10) 01555 /* Bit fields for TIMER TOP */ 01556 #define _TIMER_TOP_RESETVALUE 0x0000FFFFUL 01557 #define _TIMER_TOP_MASK 0x0000FFFFUL 01558 #define _TIMER_TOP_TOP_SHIFT 0 01559 #define _TIMER_TOP_TOP_MASK 0xFFFFUL 01560 #define _TIMER_TOP_TOP_DEFAULT 0x0000FFFFUL 01561 #define TIMER_TOP_TOP_DEFAULT (_TIMER_TOP_TOP_DEFAULT << 0) 01563 /* Bit fields for TIMER TOPB */ 01564 #define _TIMER_TOPB_RESETVALUE 0x00000000UL 01565 #define _TIMER_TOPB_MASK 0x0000FFFFUL 01566 #define _TIMER_TOPB_TOPB_SHIFT 0 01567 #define _TIMER_TOPB_TOPB_MASK 0xFFFFUL 01568 #define _TIMER_TOPB_TOPB_DEFAULT 0x00000000UL 01569 #define TIMER_TOPB_TOPB_DEFAULT (_TIMER_TOPB_TOPB_DEFAULT << 0) 01571 /* Bit fields for TIMER CNT */ 01572 #define _TIMER_CNT_RESETVALUE 0x00000000UL 01573 #define _TIMER_CNT_MASK 0x0000FFFFUL 01574 #define _TIMER_CNT_CNT_SHIFT 0 01575 #define _TIMER_CNT_CNT_MASK 0xFFFFUL 01576 #define _TIMER_CNT_CNT_DEFAULT 0x00000000UL 01577 #define TIMER_CNT_CNT_DEFAULT (_TIMER_CNT_CNT_DEFAULT << 0) 01579 /* Bit fields for TIMER ROUTE */ 01580 #define _TIMER_ROUTE_RESETVALUE 0x00000000UL 01581 #define _TIMER_ROUTE_MASK 0x00030707UL 01582 #define TIMER_ROUTE_CC0PEN (0x1UL << 0) 01583 #define _TIMER_ROUTE_CC0PEN_SHIFT 0 01584 #define _TIMER_ROUTE_CC0PEN_MASK 0x1UL 01585 #define _TIMER_ROUTE_CC0PEN_DEFAULT 0x00000000UL 01586 #define TIMER_ROUTE_CC0PEN_DEFAULT (_TIMER_ROUTE_CC0PEN_DEFAULT << 0) 01587 #define TIMER_ROUTE_CC1PEN (0x1UL << 1) 01588 #define _TIMER_ROUTE_CC1PEN_SHIFT 1 01589 #define _TIMER_ROUTE_CC1PEN_MASK 0x2UL 01590 #define _TIMER_ROUTE_CC1PEN_DEFAULT 0x00000000UL 01591 #define TIMER_ROUTE_CC1PEN_DEFAULT (_TIMER_ROUTE_CC1PEN_DEFAULT << 1) 01592 #define TIMER_ROUTE_CC2PEN (0x1UL << 2) 01593 #define _TIMER_ROUTE_CC2PEN_SHIFT 2 01594 #define _TIMER_ROUTE_CC2PEN_MASK 0x4UL 01595 #define _TIMER_ROUTE_CC2PEN_DEFAULT 0x00000000UL 01596 #define TIMER_ROUTE_CC2PEN_DEFAULT (_TIMER_ROUTE_CC2PEN_DEFAULT << 2) 01597 #define TIMER_ROUTE_CDTI0PEN (0x1UL << 8) 01598 #define _TIMER_ROUTE_CDTI0PEN_SHIFT 8 01599 #define _TIMER_ROUTE_CDTI0PEN_MASK 0x100UL 01600 #define _TIMER_ROUTE_CDTI0PEN_DEFAULT 0x00000000UL 01601 #define TIMER_ROUTE_CDTI0PEN_DEFAULT (_TIMER_ROUTE_CDTI0PEN_DEFAULT << 8) 01602 #define TIMER_ROUTE_CDTI1PEN (0x1UL << 9) 01603 #define _TIMER_ROUTE_CDTI1PEN_SHIFT 9 01604 #define _TIMER_ROUTE_CDTI1PEN_MASK 0x200UL 01605 #define _TIMER_ROUTE_CDTI1PEN_DEFAULT 0x00000000UL 01606 #define TIMER_ROUTE_CDTI1PEN_DEFAULT (_TIMER_ROUTE_CDTI1PEN_DEFAULT << 9) 01607 #define TIMER_ROUTE_CDTI2PEN (0x1UL << 10) 01608 #define _TIMER_ROUTE_CDTI2PEN_SHIFT 10 01609 #define _TIMER_ROUTE_CDTI2PEN_MASK 0x400UL 01610 #define _TIMER_ROUTE_CDTI2PEN_DEFAULT 0x00000000UL 01611 #define TIMER_ROUTE_CDTI2PEN_DEFAULT (_TIMER_ROUTE_CDTI2PEN_DEFAULT << 10) 01612 #define _TIMER_ROUTE_LOCATION_SHIFT 16 01613 #define _TIMER_ROUTE_LOCATION_MASK 0x30000UL 01614 #define _TIMER_ROUTE_LOCATION_DEFAULT 0x00000000UL 01615 #define _TIMER_ROUTE_LOCATION_LOC0 0x00000000UL 01616 #define _TIMER_ROUTE_LOCATION_LOC1 0x00000001UL 01617 #define _TIMER_ROUTE_LOCATION_LOC2 0x00000002UL 01618 #define _TIMER_ROUTE_LOCATION_LOC3 0x00000003UL 01619 #define TIMER_ROUTE_LOCATION_DEFAULT (_TIMER_ROUTE_LOCATION_DEFAULT << 16) 01620 #define TIMER_ROUTE_LOCATION_LOC0 (_TIMER_ROUTE_LOCATION_LOC0 << 16) 01621 #define TIMER_ROUTE_LOCATION_LOC1 (_TIMER_ROUTE_LOCATION_LOC1 << 16) 01622 #define TIMER_ROUTE_LOCATION_LOC2 (_TIMER_ROUTE_LOCATION_LOC2 << 16) 01623 #define TIMER_ROUTE_LOCATION_LOC3 (_TIMER_ROUTE_LOCATION_LOC3 << 16) 01625 /* Bit fields for TIMER CC_CTRL */ 01626 #define _TIMER_CC_CTRL_RESETVALUE 0x00000000UL 01627 #define _TIMER_CC_CTRL_MASK 0x0F373F17UL 01628 #define _TIMER_CC_CTRL_MODE_SHIFT 0 01629 #define _TIMER_CC_CTRL_MODE_MASK 0x3UL 01630 #define _TIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL 01631 #define _TIMER_CC_CTRL_MODE_OFF 0x00000000UL 01632 #define _TIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL 01633 #define _TIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL 01634 #define _TIMER_CC_CTRL_MODE_PWM 0x00000003UL 01635 #define TIMER_CC_CTRL_MODE_DEFAULT (_TIMER_CC_CTRL_MODE_DEFAULT << 0) 01636 #define TIMER_CC_CTRL_MODE_OFF (_TIMER_CC_CTRL_MODE_OFF << 0) 01637 #define TIMER_CC_CTRL_MODE_INPUTCAPTURE (_TIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) 01638 #define TIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_TIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) 01639 #define TIMER_CC_CTRL_MODE_PWM (_TIMER_CC_CTRL_MODE_PWM << 0) 01640 #define TIMER_CC_CTRL_OUTINV (0x1UL << 2) 01641 #define _TIMER_CC_CTRL_OUTINV_SHIFT 2 01642 #define _TIMER_CC_CTRL_OUTINV_MASK 0x4UL 01643 #define _TIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL 01644 #define TIMER_CC_CTRL_OUTINV_DEFAULT (_TIMER_CC_CTRL_OUTINV_DEFAULT << 2) 01645 #define TIMER_CC_CTRL_COIST (0x1UL << 4) 01646 #define _TIMER_CC_CTRL_COIST_SHIFT 4 01647 #define _TIMER_CC_CTRL_COIST_MASK 0x10UL 01648 #define _TIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL 01649 #define TIMER_CC_CTRL_COIST_DEFAULT (_TIMER_CC_CTRL_COIST_DEFAULT << 4) 01650 #define _TIMER_CC_CTRL_CMOA_SHIFT 8 01651 #define _TIMER_CC_CTRL_CMOA_MASK 0x300UL 01652 #define _TIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL 01653 #define _TIMER_CC_CTRL_CMOA_NONE 0x00000000UL 01654 #define _TIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL 01655 #define _TIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL 01656 #define _TIMER_CC_CTRL_CMOA_SET 0x00000003UL 01657 #define TIMER_CC_CTRL_CMOA_DEFAULT (_TIMER_CC_CTRL_CMOA_DEFAULT << 8) 01658 #define TIMER_CC_CTRL_CMOA_NONE (_TIMER_CC_CTRL_CMOA_NONE << 8) 01659 #define TIMER_CC_CTRL_CMOA_TOGGLE (_TIMER_CC_CTRL_CMOA_TOGGLE << 8) 01660 #define TIMER_CC_CTRL_CMOA_CLEAR (_TIMER_CC_CTRL_CMOA_CLEAR << 8) 01661 #define TIMER_CC_CTRL_CMOA_SET (_TIMER_CC_CTRL_CMOA_SET << 8) 01662 #define _TIMER_CC_CTRL_COFOA_SHIFT 10 01663 #define _TIMER_CC_CTRL_COFOA_MASK 0xC00UL 01664 #define _TIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL 01665 #define _TIMER_CC_CTRL_COFOA_NONE 0x00000000UL 01666 #define _TIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL 01667 #define _TIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL 01668 #define _TIMER_CC_CTRL_COFOA_SET 0x00000003UL 01669 #define TIMER_CC_CTRL_COFOA_DEFAULT (_TIMER_CC_CTRL_COFOA_DEFAULT << 10) 01670 #define TIMER_CC_CTRL_COFOA_NONE (_TIMER_CC_CTRL_COFOA_NONE << 10) 01671 #define TIMER_CC_CTRL_COFOA_TOGGLE (_TIMER_CC_CTRL_COFOA_TOGGLE << 10) 01672 #define TIMER_CC_CTRL_COFOA_CLEAR (_TIMER_CC_CTRL_COFOA_CLEAR << 10) 01673 #define TIMER_CC_CTRL_COFOA_SET (_TIMER_CC_CTRL_COFOA_SET << 10) 01674 #define _TIMER_CC_CTRL_CUFOA_SHIFT 12 01675 #define _TIMER_CC_CTRL_CUFOA_MASK 0x3000UL 01676 #define _TIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL 01677 #define _TIMER_CC_CTRL_CUFOA_NONE 0x00000000UL 01678 #define _TIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL 01679 #define _TIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL 01680 #define _TIMER_CC_CTRL_CUFOA_SET 0x00000003UL 01681 #define TIMER_CC_CTRL_CUFOA_DEFAULT (_TIMER_CC_CTRL_CUFOA_DEFAULT << 12) 01682 #define TIMER_CC_CTRL_CUFOA_NONE (_TIMER_CC_CTRL_CUFOA_NONE << 12) 01683 #define TIMER_CC_CTRL_CUFOA_TOGGLE (_TIMER_CC_CTRL_CUFOA_TOGGLE << 12) 01684 #define TIMER_CC_CTRL_CUFOA_CLEAR (_TIMER_CC_CTRL_CUFOA_CLEAR << 12) 01685 #define TIMER_CC_CTRL_CUFOA_SET (_TIMER_CC_CTRL_CUFOA_SET << 12) 01686 #define _TIMER_CC_CTRL_PRSSEL_SHIFT 16 01687 #define _TIMER_CC_CTRL_PRSSEL_MASK 0x70000UL 01688 #define _TIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL 01689 #define _TIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL 01690 #define _TIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL 01691 #define _TIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL 01692 #define _TIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL 01693 #define _TIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL 01694 #define _TIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL 01695 #define _TIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL 01696 #define _TIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL 01697 #define TIMER_CC_CTRL_PRSSEL_DEFAULT (_TIMER_CC_CTRL_PRSSEL_DEFAULT << 16) 01698 #define TIMER_CC_CTRL_PRSSEL_PRSCH0 (_TIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) 01699 #define TIMER_CC_CTRL_PRSSEL_PRSCH1 (_TIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) 01700 #define TIMER_CC_CTRL_PRSSEL_PRSCH2 (_TIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) 01701 #define TIMER_CC_CTRL_PRSSEL_PRSCH3 (_TIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) 01702 #define TIMER_CC_CTRL_PRSSEL_PRSCH4 (_TIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) 01703 #define TIMER_CC_CTRL_PRSSEL_PRSCH5 (_TIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) 01704 #define TIMER_CC_CTRL_PRSSEL_PRSCH6 (_TIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) 01705 #define TIMER_CC_CTRL_PRSSEL_PRSCH7 (_TIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) 01706 #define TIMER_CC_CTRL_INSEL (0x1UL << 20) 01707 #define _TIMER_CC_CTRL_INSEL_SHIFT 20 01708 #define _TIMER_CC_CTRL_INSEL_MASK 0x100000UL 01709 #define _TIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL 01710 #define _TIMER_CC_CTRL_INSEL_PIN 0x00000000UL 01711 #define _TIMER_CC_CTRL_INSEL_PRS 0x00000001UL 01712 #define TIMER_CC_CTRL_INSEL_DEFAULT (_TIMER_CC_CTRL_INSEL_DEFAULT << 20) 01713 #define TIMER_CC_CTRL_INSEL_PIN (_TIMER_CC_CTRL_INSEL_PIN << 20) 01714 #define TIMER_CC_CTRL_INSEL_PRS (_TIMER_CC_CTRL_INSEL_PRS << 20) 01715 #define TIMER_CC_CTRL_FILT (0x1UL << 21) 01716 #define _TIMER_CC_CTRL_FILT_SHIFT 21 01717 #define _TIMER_CC_CTRL_FILT_MASK 0x200000UL 01718 #define _TIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL 01719 #define _TIMER_CC_CTRL_FILT_DISABLE 0x00000000UL 01720 #define _TIMER_CC_CTRL_FILT_ENABLE 0x00000001UL 01721 #define TIMER_CC_CTRL_FILT_DEFAULT (_TIMER_CC_CTRL_FILT_DEFAULT << 21) 01722 #define TIMER_CC_CTRL_FILT_DISABLE (_TIMER_CC_CTRL_FILT_DISABLE << 21) 01723 #define TIMER_CC_CTRL_FILT_ENABLE (_TIMER_CC_CTRL_FILT_ENABLE << 21) 01724 #define _TIMER_CC_CTRL_ICEDGE_SHIFT 24 01725 #define _TIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL 01726 #define _TIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL 01727 #define _TIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL 01728 #define _TIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL 01729 #define _TIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL 01730 #define _TIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL 01731 #define TIMER_CC_CTRL_ICEDGE_DEFAULT (_TIMER_CC_CTRL_ICEDGE_DEFAULT << 24) 01732 #define TIMER_CC_CTRL_ICEDGE_RISING (_TIMER_CC_CTRL_ICEDGE_RISING << 24) 01733 #define TIMER_CC_CTRL_ICEDGE_FALLING (_TIMER_CC_CTRL_ICEDGE_FALLING << 24) 01734 #define TIMER_CC_CTRL_ICEDGE_BOTH (_TIMER_CC_CTRL_ICEDGE_BOTH << 24) 01735 #define TIMER_CC_CTRL_ICEDGE_NONE (_TIMER_CC_CTRL_ICEDGE_NONE << 24) 01736 #define _TIMER_CC_CTRL_ICEVCTRL_SHIFT 26 01737 #define _TIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL 01738 #define _TIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL 01739 #define _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL 01740 #define _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL 01741 #define _TIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL 01742 #define _TIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL 01743 #define TIMER_CC_CTRL_ICEVCTRL_DEFAULT (_TIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) 01744 #define TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) 01745 #define TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) 01746 #define TIMER_CC_CTRL_ICEVCTRL_RISING (_TIMER_CC_CTRL_ICEVCTRL_RISING << 26) 01747 #define TIMER_CC_CTRL_ICEVCTRL_FALLING (_TIMER_CC_CTRL_ICEVCTRL_FALLING << 26) 01749 /* Bit fields for TIMER CC_CCV */ 01750 #define _TIMER_CC_CCV_RESETVALUE 0x00000000UL 01751 #define _TIMER_CC_CCV_MASK 0x0000FFFFUL 01752 #define _TIMER_CC_CCV_CCV_SHIFT 0 01753 #define _TIMER_CC_CCV_CCV_MASK 0xFFFFUL 01754 #define _TIMER_CC_CCV_CCV_DEFAULT 0x00000000UL 01755 #define TIMER_CC_CCV_CCV_DEFAULT (_TIMER_CC_CCV_CCV_DEFAULT << 0) 01757 /* Bit fields for TIMER CC_CCVP */ 01758 #define _TIMER_CC_CCVP_RESETVALUE 0x00000000UL 01759 #define _TIMER_CC_CCVP_MASK 0x0000FFFFUL 01760 #define _TIMER_CC_CCVP_CCVP_SHIFT 0 01761 #define _TIMER_CC_CCVP_CCVP_MASK 0xFFFFUL 01762 #define _TIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL 01763 #define TIMER_CC_CCVP_CCVP_DEFAULT (_TIMER_CC_CCVP_CCVP_DEFAULT << 0) 01765 /* Bit fields for TIMER CC_CCVB */ 01766 #define _TIMER_CC_CCVB_RESETVALUE 0x00000000UL 01767 #define _TIMER_CC_CCVB_MASK 0x0000FFFFUL 01768 #define _TIMER_CC_CCVB_CCVB_SHIFT 0 01769 #define _TIMER_CC_CCVB_CCVB_MASK 0xFFFFUL 01770 #define _TIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL 01771 #define TIMER_CC_CCVB_CCVB_DEFAULT (_TIMER_CC_CCVB_CCVB_DEFAULT << 0) 01773 /* Bit fields for TIMER DTCTRL */ 01774 #define _TIMER_DTCTRL_RESETVALUE 0x00000000UL 01775 #define _TIMER_DTCTRL_MASK 0x0100007FUL 01776 #define TIMER_DTCTRL_DTEN (0x1UL << 0) 01777 #define _TIMER_DTCTRL_DTEN_SHIFT 0 01778 #define _TIMER_DTCTRL_DTEN_MASK 0x1UL 01779 #define _TIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL 01780 #define TIMER_DTCTRL_DTEN_DEFAULT (_TIMER_DTCTRL_DTEN_DEFAULT << 0) 01781 #define TIMER_DTCTRL_DTDAS (0x1UL << 1) 01782 #define _TIMER_DTCTRL_DTDAS_SHIFT 1 01783 #define _TIMER_DTCTRL_DTDAS_MASK 0x2UL 01784 #define _TIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL 01785 #define _TIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL 01786 #define _TIMER_DTCTRL_DTDAS_RESTART 0x00000001UL 01787 #define TIMER_DTCTRL_DTDAS_DEFAULT (_TIMER_DTCTRL_DTDAS_DEFAULT << 1) 01788 #define TIMER_DTCTRL_DTDAS_NORESTART (_TIMER_DTCTRL_DTDAS_NORESTART << 1) 01789 #define TIMER_DTCTRL_DTDAS_RESTART (_TIMER_DTCTRL_DTDAS_RESTART << 1) 01790 #define TIMER_DTCTRL_DTIPOL (0x1UL << 2) 01791 #define _TIMER_DTCTRL_DTIPOL_SHIFT 2 01792 #define _TIMER_DTCTRL_DTIPOL_MASK 0x4UL 01793 #define _TIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL 01794 #define TIMER_DTCTRL_DTIPOL_DEFAULT (_TIMER_DTCTRL_DTIPOL_DEFAULT << 2) 01795 #define TIMER_DTCTRL_DTCINV (0x1UL << 3) 01796 #define _TIMER_DTCTRL_DTCINV_SHIFT 3 01797 #define _TIMER_DTCTRL_DTCINV_MASK 0x8UL 01798 #define _TIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL 01799 #define TIMER_DTCTRL_DTCINV_DEFAULT (_TIMER_DTCTRL_DTCINV_DEFAULT << 3) 01800 #define _TIMER_DTCTRL_DTPRSSEL_SHIFT 4 01801 #define _TIMER_DTCTRL_DTPRSSEL_MASK 0x70UL 01802 #define _TIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL 01803 #define _TIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL 01804 #define _TIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL 01805 #define _TIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL 01806 #define _TIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL 01807 #define _TIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL 01808 #define _TIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL 01809 #define _TIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL 01810 #define _TIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL 01811 #define TIMER_DTCTRL_DTPRSSEL_DEFAULT (_TIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) 01812 #define TIMER_DTCTRL_DTPRSSEL_PRSCH0 (_TIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) 01813 #define TIMER_DTCTRL_DTPRSSEL_PRSCH1 (_TIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) 01814 #define TIMER_DTCTRL_DTPRSSEL_PRSCH2 (_TIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) 01815 #define TIMER_DTCTRL_DTPRSSEL_PRSCH3 (_TIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) 01816 #define TIMER_DTCTRL_DTPRSSEL_PRSCH4 (_TIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) 01817 #define TIMER_DTCTRL_DTPRSSEL_PRSCH5 (_TIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) 01818 #define TIMER_DTCTRL_DTPRSSEL_PRSCH6 (_TIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) 01819 #define TIMER_DTCTRL_DTPRSSEL_PRSCH7 (_TIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) 01820 #define TIMER_DTCTRL_DTPRSEN (0x1UL << 24) 01821 #define _TIMER_DTCTRL_DTPRSEN_SHIFT 24 01822 #define _TIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL 01823 #define _TIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL 01824 #define TIMER_DTCTRL_DTPRSEN_DEFAULT (_TIMER_DTCTRL_DTPRSEN_DEFAULT << 24) 01826 /* Bit fields for TIMER DTTIME */ 01827 #define _TIMER_DTTIME_RESETVALUE 0x00000000UL 01828 #define _TIMER_DTTIME_MASK 0x003F3F0FUL 01829 #define _TIMER_DTTIME_DTPRESC_SHIFT 0 01830 #define _TIMER_DTTIME_DTPRESC_MASK 0xFUL 01831 #define _TIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL 01832 #define _TIMER_DTTIME_DTPRESC_DIV1 0x00000000UL 01833 #define _TIMER_DTTIME_DTPRESC_DIV2 0x00000001UL 01834 #define _TIMER_DTTIME_DTPRESC_DIV4 0x00000002UL 01835 #define _TIMER_DTTIME_DTPRESC_DIV8 0x00000003UL 01836 #define _TIMER_DTTIME_DTPRESC_DIV16 0x00000004UL 01837 #define _TIMER_DTTIME_DTPRESC_DIV32 0x00000005UL 01838 #define _TIMER_DTTIME_DTPRESC_DIV64 0x00000006UL 01839 #define _TIMER_DTTIME_DTPRESC_DIV128 0x00000007UL 01840 #define _TIMER_DTTIME_DTPRESC_DIV256 0x00000008UL 01841 #define _TIMER_DTTIME_DTPRESC_DIV512 0x00000009UL 01842 #define _TIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL 01843 #define TIMER_DTTIME_DTPRESC_DEFAULT (_TIMER_DTTIME_DTPRESC_DEFAULT << 0) 01844 #define TIMER_DTTIME_DTPRESC_DIV1 (_TIMER_DTTIME_DTPRESC_DIV1 << 0) 01845 #define TIMER_DTTIME_DTPRESC_DIV2 (_TIMER_DTTIME_DTPRESC_DIV2 << 0) 01846 #define TIMER_DTTIME_DTPRESC_DIV4 (_TIMER_DTTIME_DTPRESC_DIV4 << 0) 01847 #define TIMER_DTTIME_DTPRESC_DIV8 (_TIMER_DTTIME_DTPRESC_DIV8 << 0) 01848 #define TIMER_DTTIME_DTPRESC_DIV16 (_TIMER_DTTIME_DTPRESC_DIV16 << 0) 01849 #define TIMER_DTTIME_DTPRESC_DIV32 (_TIMER_DTTIME_DTPRESC_DIV32 << 0) 01850 #define TIMER_DTTIME_DTPRESC_DIV64 (_TIMER_DTTIME_DTPRESC_DIV64 << 0) 01851 #define TIMER_DTTIME_DTPRESC_DIV128 (_TIMER_DTTIME_DTPRESC_DIV128 << 0) 01852 #define TIMER_DTTIME_DTPRESC_DIV256 (_TIMER_DTTIME_DTPRESC_DIV256 << 0) 01853 #define TIMER_DTTIME_DTPRESC_DIV512 (_TIMER_DTTIME_DTPRESC_DIV512 << 0) 01854 #define TIMER_DTTIME_DTPRESC_DIV1024 (_TIMER_DTTIME_DTPRESC_DIV1024 << 0) 01855 #define _TIMER_DTTIME_DTRISET_SHIFT 8 01856 #define _TIMER_DTTIME_DTRISET_MASK 0x3F00UL 01857 #define _TIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL 01858 #define TIMER_DTTIME_DTRISET_DEFAULT (_TIMER_DTTIME_DTRISET_DEFAULT << 8) 01859 #define _TIMER_DTTIME_DTFALLT_SHIFT 16 01860 #define _TIMER_DTTIME_DTFALLT_MASK 0x3F0000UL 01861 #define _TIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL 01862 #define TIMER_DTTIME_DTFALLT_DEFAULT (_TIMER_DTTIME_DTFALLT_DEFAULT << 16) 01864 /* Bit fields for TIMER DTFC */ 01865 #define _TIMER_DTFC_RESETVALUE 0x00000000UL 01866 #define _TIMER_DTFC_MASK 0x0F030707UL 01867 #define _TIMER_DTFC_DTPRS0FSEL_SHIFT 0 01868 #define _TIMER_DTFC_DTPRS0FSEL_MASK 0x7UL 01869 #define _TIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL 01870 #define _TIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL 01871 #define _TIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL 01872 #define _TIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL 01873 #define _TIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL 01874 #define _TIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL 01875 #define _TIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL 01876 #define _TIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL 01877 #define _TIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL 01878 #define TIMER_DTFC_DTPRS0FSEL_DEFAULT (_TIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) 01879 #define TIMER_DTFC_DTPRS0FSEL_PRSCH0 (_TIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) 01880 #define TIMER_DTFC_DTPRS0FSEL_PRSCH1 (_TIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) 01881 #define TIMER_DTFC_DTPRS0FSEL_PRSCH2 (_TIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) 01882 #define TIMER_DTFC_DTPRS0FSEL_PRSCH3 (_TIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) 01883 #define TIMER_DTFC_DTPRS0FSEL_PRSCH4 (_TIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) 01884 #define TIMER_DTFC_DTPRS0FSEL_PRSCH5 (_TIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) 01885 #define TIMER_DTFC_DTPRS0FSEL_PRSCH6 (_TIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) 01886 #define TIMER_DTFC_DTPRS0FSEL_PRSCH7 (_TIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) 01887 #define _TIMER_DTFC_DTPRS1FSEL_SHIFT 8 01888 #define _TIMER_DTFC_DTPRS1FSEL_MASK 0x700UL 01889 #define _TIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL 01890 #define _TIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL 01891 #define _TIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL 01892 #define _TIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL 01893 #define _TIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL 01894 #define _TIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL 01895 #define _TIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL 01896 #define _TIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL 01897 #define _TIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL 01898 #define TIMER_DTFC_DTPRS1FSEL_DEFAULT (_TIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) 01899 #define TIMER_DTFC_DTPRS1FSEL_PRSCH0 (_TIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) 01900 #define TIMER_DTFC_DTPRS1FSEL_PRSCH1 (_TIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) 01901 #define TIMER_DTFC_DTPRS1FSEL_PRSCH2 (_TIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) 01902 #define TIMER_DTFC_DTPRS1FSEL_PRSCH3 (_TIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) 01903 #define TIMER_DTFC_DTPRS1FSEL_PRSCH4 (_TIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) 01904 #define TIMER_DTFC_DTPRS1FSEL_PRSCH5 (_TIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) 01905 #define TIMER_DTFC_DTPRS1FSEL_PRSCH6 (_TIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) 01906 #define TIMER_DTFC_DTPRS1FSEL_PRSCH7 (_TIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) 01907 #define _TIMER_DTFC_DTFA_SHIFT 16 01908 #define _TIMER_DTFC_DTFA_MASK 0x30000UL 01909 #define _TIMER_DTFC_DTFA_DEFAULT 0x00000000UL 01910 #define _TIMER_DTFC_DTFA_NONE 0x00000000UL 01911 #define _TIMER_DTFC_DTFA_INACTIVE 0x00000001UL 01912 #define _TIMER_DTFC_DTFA_CLEAR 0x00000002UL 01913 #define _TIMER_DTFC_DTFA_TRISTATE 0x00000003UL 01914 #define TIMER_DTFC_DTFA_DEFAULT (_TIMER_DTFC_DTFA_DEFAULT << 16) 01915 #define TIMER_DTFC_DTFA_NONE (_TIMER_DTFC_DTFA_NONE << 16) 01916 #define TIMER_DTFC_DTFA_INACTIVE (_TIMER_DTFC_DTFA_INACTIVE << 16) 01917 #define TIMER_DTFC_DTFA_CLEAR (_TIMER_DTFC_DTFA_CLEAR << 16) 01918 #define TIMER_DTFC_DTFA_TRISTATE (_TIMER_DTFC_DTFA_TRISTATE << 16) 01919 #define TIMER_DTFC_DTPRS0FEN (0x1UL << 24) 01920 #define _TIMER_DTFC_DTPRS0FEN_SHIFT 24 01921 #define _TIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL 01922 #define _TIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL 01923 #define TIMER_DTFC_DTPRS0FEN_DEFAULT (_TIMER_DTFC_DTPRS0FEN_DEFAULT << 24) 01924 #define TIMER_DTFC_DTPRS1FEN (0x1UL << 25) 01925 #define _TIMER_DTFC_DTPRS1FEN_SHIFT 25 01926 #define _TIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL 01927 #define _TIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL 01928 #define TIMER_DTFC_DTPRS1FEN_DEFAULT (_TIMER_DTFC_DTPRS1FEN_DEFAULT << 25) 01929 #define TIMER_DTFC_DTDBGFEN (0x1UL << 26) 01930 #define _TIMER_DTFC_DTDBGFEN_SHIFT 26 01931 #define _TIMER_DTFC_DTDBGFEN_MASK 0x4000000UL 01932 #define _TIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL 01933 #define TIMER_DTFC_DTDBGFEN_DEFAULT (_TIMER_DTFC_DTDBGFEN_DEFAULT << 26) 01934 #define TIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) 01935 #define _TIMER_DTFC_DTLOCKUPFEN_SHIFT 27 01936 #define _TIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL 01937 #define _TIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL 01938 #define TIMER_DTFC_DTLOCKUPFEN_DEFAULT (_TIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) 01940 /* Bit fields for TIMER DTOGEN */ 01941 #define _TIMER_DTOGEN_RESETVALUE 0x00000000UL 01942 #define _TIMER_DTOGEN_MASK 0x0000003FUL 01943 #define TIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) 01944 #define _TIMER_DTOGEN_DTOGCC0EN_SHIFT 0 01945 #define _TIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL 01946 #define _TIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL 01947 #define TIMER_DTOGEN_DTOGCC0EN_DEFAULT (_TIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) 01948 #define TIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) 01949 #define _TIMER_DTOGEN_DTOGCC1EN_SHIFT 1 01950 #define _TIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL 01951 #define _TIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL 01952 #define TIMER_DTOGEN_DTOGCC1EN_DEFAULT (_TIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) 01953 #define TIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) 01954 #define _TIMER_DTOGEN_DTOGCC2EN_SHIFT 2 01955 #define _TIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL 01956 #define _TIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL 01957 #define TIMER_DTOGEN_DTOGCC2EN_DEFAULT (_TIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) 01958 #define TIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) 01959 #define _TIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 01960 #define _TIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL 01961 #define _TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL 01962 #define TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) 01963 #define TIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) 01964 #define _TIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 01965 #define _TIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL 01966 #define _TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL 01967 #define TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) 01968 #define TIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) 01969 #define _TIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 01970 #define _TIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL 01971 #define _TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL 01972 #define TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) 01974 /* Bit fields for TIMER DTFAULT */ 01975 #define _TIMER_DTFAULT_RESETVALUE 0x00000000UL 01976 #define _TIMER_DTFAULT_MASK 0x0000000FUL 01977 #define TIMER_DTFAULT_DTPRS0F (0x1UL << 0) 01978 #define _TIMER_DTFAULT_DTPRS0F_SHIFT 0 01979 #define _TIMER_DTFAULT_DTPRS0F_MASK 0x1UL 01980 #define _TIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL 01981 #define TIMER_DTFAULT_DTPRS0F_DEFAULT (_TIMER_DTFAULT_DTPRS0F_DEFAULT << 0) 01982 #define TIMER_DTFAULT_DTPRS1F (0x1UL << 1) 01983 #define _TIMER_DTFAULT_DTPRS1F_SHIFT 1 01984 #define _TIMER_DTFAULT_DTPRS1F_MASK 0x2UL 01985 #define _TIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL 01986 #define TIMER_DTFAULT_DTPRS1F_DEFAULT (_TIMER_DTFAULT_DTPRS1F_DEFAULT << 1) 01987 #define TIMER_DTFAULT_DTDBGF (0x1UL << 2) 01988 #define _TIMER_DTFAULT_DTDBGF_SHIFT 2 01989 #define _TIMER_DTFAULT_DTDBGF_MASK 0x4UL 01990 #define _TIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL 01991 #define TIMER_DTFAULT_DTDBGF_DEFAULT (_TIMER_DTFAULT_DTDBGF_DEFAULT << 2) 01992 #define TIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) 01993 #define _TIMER_DTFAULT_DTLOCKUPF_SHIFT 3 01994 #define _TIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL 01995 #define _TIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL 01996 #define TIMER_DTFAULT_DTLOCKUPF_DEFAULT (_TIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) 01998 /* Bit fields for TIMER DTFAULTC */ 01999 #define _TIMER_DTFAULTC_RESETVALUE 0x00000000UL 02000 #define _TIMER_DTFAULTC_MASK 0x0000000FUL 02001 #define TIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) 02002 #define _TIMER_DTFAULTC_DTPRS0FC_SHIFT 0 02003 #define _TIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL 02004 #define _TIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL 02005 #define TIMER_DTFAULTC_DTPRS0FC_DEFAULT (_TIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) 02006 #define TIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) 02007 #define _TIMER_DTFAULTC_DTPRS1FC_SHIFT 1 02008 #define _TIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL 02009 #define _TIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL 02010 #define TIMER_DTFAULTC_DTPRS1FC_DEFAULT (_TIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) 02011 #define TIMER_DTFAULTC_DTDBGFC (0x1UL << 2) 02012 #define _TIMER_DTFAULTC_DTDBGFC_SHIFT 2 02013 #define _TIMER_DTFAULTC_DTDBGFC_MASK 0x4UL 02014 #define _TIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL 02015 #define TIMER_DTFAULTC_DTDBGFC_DEFAULT (_TIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) 02016 #define TIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) 02017 #define _TIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 02018 #define _TIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL 02019 #define _TIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL 02020 #define TIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_TIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) 02022 /* Bit fields for TIMER DTLOCK */ 02023 #define _TIMER_DTLOCK_RESETVALUE 0x00000000UL 02024 #define _TIMER_DTLOCK_MASK 0x0000FFFFUL 02025 #define _TIMER_DTLOCK_LOCKKEY_SHIFT 0 02026 #define _TIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL 02027 #define _TIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL 02028 #define _TIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL 02029 #define _TIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL 02030 #define _TIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL 02031 #define _TIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL 02032 #define TIMER_DTLOCK_LOCKKEY_DEFAULT (_TIMER_DTLOCK_LOCKKEY_DEFAULT << 0) 02033 #define TIMER_DTLOCK_LOCKKEY_LOCK (_TIMER_DTLOCK_LOCKKEY_LOCK << 0) 02034 #define TIMER_DTLOCK_LOCKKEY_UNLOCKED (_TIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) 02035 #define TIMER_DTLOCK_LOCKKEY_LOCKED (_TIMER_DTLOCK_LOCKKEY_LOCKED << 0) 02036 #define TIMER_DTLOCK_LOCKKEY_UNLOCK (_TIMER_DTLOCK_LOCKKEY_UNLOCK << 0) 02042 /**************************************************************************/ 02047 /* Bit fields for USART CTRL */ 02048 #define _USART_CTRL_RESETVALUE 0x00000000UL 02049 #define _USART_CTRL_MASK 0x1DFFFF7FUL 02050 #define USART_CTRL_SYNC (0x1UL << 0) 02051 #define _USART_CTRL_SYNC_SHIFT 0 02052 #define _USART_CTRL_SYNC_MASK 0x1UL 02053 #define _USART_CTRL_SYNC_DEFAULT 0x00000000UL 02054 #define USART_CTRL_SYNC_DEFAULT (_USART_CTRL_SYNC_DEFAULT << 0) 02055 #define USART_CTRL_LOOPBK (0x1UL << 1) 02056 #define _USART_CTRL_LOOPBK_SHIFT 1 02057 #define _USART_CTRL_LOOPBK_MASK 0x2UL 02058 #define _USART_CTRL_LOOPBK_DEFAULT 0x00000000UL 02059 #define USART_CTRL_LOOPBK_DEFAULT (_USART_CTRL_LOOPBK_DEFAULT << 1) 02060 #define USART_CTRL_CCEN (0x1UL << 2) 02061 #define _USART_CTRL_CCEN_SHIFT 2 02062 #define _USART_CTRL_CCEN_MASK 0x4UL 02063 #define _USART_CTRL_CCEN_DEFAULT 0x00000000UL 02064 #define USART_CTRL_CCEN_DEFAULT (_USART_CTRL_CCEN_DEFAULT << 2) 02065 #define USART_CTRL_MPM (0x1UL << 3) 02066 #define _USART_CTRL_MPM_SHIFT 3 02067 #define _USART_CTRL_MPM_MASK 0x8UL 02068 #define _USART_CTRL_MPM_DEFAULT 0x00000000UL 02069 #define USART_CTRL_MPM_DEFAULT (_USART_CTRL_MPM_DEFAULT << 3) 02070 #define USART_CTRL_MPAB (0x1UL << 4) 02071 #define _USART_CTRL_MPAB_SHIFT 4 02072 #define _USART_CTRL_MPAB_MASK 0x10UL 02073 #define _USART_CTRL_MPAB_DEFAULT 0x00000000UL 02074 #define USART_CTRL_MPAB_DEFAULT (_USART_CTRL_MPAB_DEFAULT << 4) 02075 #define _USART_CTRL_OVS_SHIFT 5 02076 #define _USART_CTRL_OVS_MASK 0x60UL 02077 #define _USART_CTRL_OVS_DEFAULT 0x00000000UL 02078 #define _USART_CTRL_OVS_X16 0x00000000UL 02079 #define _USART_CTRL_OVS_X8 0x00000001UL 02080 #define _USART_CTRL_OVS_X6 0x00000002UL 02081 #define _USART_CTRL_OVS_X4 0x00000003UL 02082 #define USART_CTRL_OVS_DEFAULT (_USART_CTRL_OVS_DEFAULT << 5) 02083 #define USART_CTRL_OVS_X16 (_USART_CTRL_OVS_X16 << 5) 02084 #define USART_CTRL_OVS_X8 (_USART_CTRL_OVS_X8 << 5) 02085 #define USART_CTRL_OVS_X6 (_USART_CTRL_OVS_X6 << 5) 02086 #define USART_CTRL_OVS_X4 (_USART_CTRL_OVS_X4 << 5) 02087 #define USART_CTRL_CLKPOL (0x1UL << 8) 02088 #define _USART_CTRL_CLKPOL_SHIFT 8 02089 #define _USART_CTRL_CLKPOL_MASK 0x100UL 02090 #define _USART_CTRL_CLKPOL_DEFAULT 0x00000000UL 02091 #define _USART_CTRL_CLKPOL_IDLELOW 0x00000000UL 02092 #define _USART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL 02093 #define USART_CTRL_CLKPOL_DEFAULT (_USART_CTRL_CLKPOL_DEFAULT << 8) 02094 #define USART_CTRL_CLKPOL_IDLELOW (_USART_CTRL_CLKPOL_IDLELOW << 8) 02095 #define USART_CTRL_CLKPOL_IDLEHIGH (_USART_CTRL_CLKPOL_IDLEHIGH << 8) 02096 #define USART_CTRL_CLKPHA (0x1UL << 9) 02097 #define _USART_CTRL_CLKPHA_SHIFT 9 02098 #define _USART_CTRL_CLKPHA_MASK 0x200UL 02099 #define _USART_CTRL_CLKPHA_DEFAULT 0x00000000UL 02100 #define _USART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL 02101 #define _USART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL 02102 #define USART_CTRL_CLKPHA_DEFAULT (_USART_CTRL_CLKPHA_DEFAULT << 9) 02103 #define USART_CTRL_CLKPHA_SAMPLELEADING (_USART_CTRL_CLKPHA_SAMPLELEADING << 9) 02104 #define USART_CTRL_CLKPHA_SAMPLETRAILING (_USART_CTRL_CLKPHA_SAMPLETRAILING << 9) 02105 #define USART_CTRL_MSBF (0x1UL << 10) 02106 #define _USART_CTRL_MSBF_SHIFT 10 02107 #define _USART_CTRL_MSBF_MASK 0x400UL 02108 #define _USART_CTRL_MSBF_DEFAULT 0x00000000UL 02109 #define USART_CTRL_MSBF_DEFAULT (_USART_CTRL_MSBF_DEFAULT << 10) 02110 #define USART_CTRL_CSMA (0x1UL << 11) 02111 #define _USART_CTRL_CSMA_SHIFT 11 02112 #define _USART_CTRL_CSMA_MASK 0x800UL 02113 #define _USART_CTRL_CSMA_DEFAULT 0x00000000UL 02114 #define _USART_CTRL_CSMA_NOACTION 0x00000000UL 02115 #define _USART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL 02116 #define USART_CTRL_CSMA_DEFAULT (_USART_CTRL_CSMA_DEFAULT << 11) 02117 #define USART_CTRL_CSMA_NOACTION (_USART_CTRL_CSMA_NOACTION << 11) 02118 #define USART_CTRL_CSMA_GOTOSLAVEMODE (_USART_CTRL_CSMA_GOTOSLAVEMODE << 11) 02119 #define USART_CTRL_TXBIL (0x1UL << 12) 02120 #define _USART_CTRL_TXBIL_SHIFT 12 02121 #define _USART_CTRL_TXBIL_MASK 0x1000UL 02122 #define _USART_CTRL_TXBIL_DEFAULT 0x00000000UL 02123 #define _USART_CTRL_TXBIL_EMPTY 0x00000000UL 02124 #define _USART_CTRL_TXBIL_HALFFULL 0x00000001UL 02125 #define USART_CTRL_TXBIL_DEFAULT (_USART_CTRL_TXBIL_DEFAULT << 12) 02126 #define USART_CTRL_TXBIL_EMPTY (_USART_CTRL_TXBIL_EMPTY << 12) 02127 #define USART_CTRL_TXBIL_HALFFULL (_USART_CTRL_TXBIL_HALFFULL << 12) 02128 #define USART_CTRL_RXINV (0x1UL << 13) 02129 #define _USART_CTRL_RXINV_SHIFT 13 02130 #define _USART_CTRL_RXINV_MASK 0x2000UL 02131 #define _USART_CTRL_RXINV_DEFAULT 0x00000000UL 02132 #define USART_CTRL_RXINV_DEFAULT (_USART_CTRL_RXINV_DEFAULT << 13) 02133 #define USART_CTRL_TXINV (0x1UL << 14) 02134 #define _USART_CTRL_TXINV_SHIFT 14 02135 #define _USART_CTRL_TXINV_MASK 0x4000UL 02136 #define _USART_CTRL_TXINV_DEFAULT 0x00000000UL 02137 #define USART_CTRL_TXINV_DEFAULT (_USART_CTRL_TXINV_DEFAULT << 14) 02138 #define USART_CTRL_CSINV (0x1UL << 15) 02139 #define _USART_CTRL_CSINV_SHIFT 15 02140 #define _USART_CTRL_CSINV_MASK 0x8000UL 02141 #define _USART_CTRL_CSINV_DEFAULT 0x00000000UL 02142 #define USART_CTRL_CSINV_DEFAULT (_USART_CTRL_CSINV_DEFAULT << 15) 02143 #define USART_CTRL_AUTOCS (0x1UL << 16) 02144 #define _USART_CTRL_AUTOCS_SHIFT 16 02145 #define _USART_CTRL_AUTOCS_MASK 0x10000UL 02146 #define _USART_CTRL_AUTOCS_DEFAULT 0x00000000UL 02147 #define USART_CTRL_AUTOCS_DEFAULT (_USART_CTRL_AUTOCS_DEFAULT << 16) 02148 #define USART_CTRL_AUTOTRI (0x1UL << 17) 02149 #define _USART_CTRL_AUTOTRI_SHIFT 17 02150 #define _USART_CTRL_AUTOTRI_MASK 0x20000UL 02151 #define _USART_CTRL_AUTOTRI_DEFAULT 0x00000000UL 02152 #define USART_CTRL_AUTOTRI_DEFAULT (_USART_CTRL_AUTOTRI_DEFAULT << 17) 02153 #define USART_CTRL_SCMODE (0x1UL << 18) 02154 #define _USART_CTRL_SCMODE_SHIFT 18 02155 #define _USART_CTRL_SCMODE_MASK 0x40000UL 02156 #define _USART_CTRL_SCMODE_DEFAULT 0x00000000UL 02157 #define USART_CTRL_SCMODE_DEFAULT (_USART_CTRL_SCMODE_DEFAULT << 18) 02158 #define USART_CTRL_SCRETRANS (0x1UL << 19) 02159 #define _USART_CTRL_SCRETRANS_SHIFT 19 02160 #define _USART_CTRL_SCRETRANS_MASK 0x80000UL 02161 #define _USART_CTRL_SCRETRANS_DEFAULT 0x00000000UL 02162 #define USART_CTRL_SCRETRANS_DEFAULT (_USART_CTRL_SCRETRANS_DEFAULT << 19) 02163 #define USART_CTRL_SKIPPERRF (0x1UL << 20) 02164 #define _USART_CTRL_SKIPPERRF_SHIFT 20 02165 #define _USART_CTRL_SKIPPERRF_MASK 0x100000UL 02166 #define _USART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL 02167 #define USART_CTRL_SKIPPERRF_DEFAULT (_USART_CTRL_SKIPPERRF_DEFAULT << 20) 02168 #define USART_CTRL_BIT8DV (0x1UL << 21) 02169 #define _USART_CTRL_BIT8DV_SHIFT 21 02170 #define _USART_CTRL_BIT8DV_MASK 0x200000UL 02171 #define _USART_CTRL_BIT8DV_DEFAULT 0x00000000UL 02172 #define USART_CTRL_BIT8DV_DEFAULT (_USART_CTRL_BIT8DV_DEFAULT << 21) 02173 #define USART_CTRL_ERRSDMA (0x1UL << 22) 02174 #define _USART_CTRL_ERRSDMA_SHIFT 22 02175 #define _USART_CTRL_ERRSDMA_MASK 0x400000UL 02176 #define _USART_CTRL_ERRSDMA_DEFAULT 0x00000000UL 02177 #define USART_CTRL_ERRSDMA_DEFAULT (_USART_CTRL_ERRSDMA_DEFAULT << 22) 02178 #define USART_CTRL_ERRSRX (0x1UL << 23) 02179 #define _USART_CTRL_ERRSRX_SHIFT 23 02180 #define _USART_CTRL_ERRSRX_MASK 0x800000UL 02181 #define _USART_CTRL_ERRSRX_DEFAULT 0x00000000UL 02182 #define USART_CTRL_ERRSRX_DEFAULT (_USART_CTRL_ERRSRX_DEFAULT << 23) 02183 #define USART_CTRL_ERRSTX (0x1UL << 24) 02184 #define _USART_CTRL_ERRSTX_SHIFT 24 02185 #define _USART_CTRL_ERRSTX_MASK 0x1000000UL 02186 #define _USART_CTRL_ERRSTX_DEFAULT 0x00000000UL 02187 #define USART_CTRL_ERRSTX_DEFAULT (_USART_CTRL_ERRSTX_DEFAULT << 24) 02188 #define _USART_CTRL_TXDELAY_SHIFT 26 02189 #define _USART_CTRL_TXDELAY_MASK 0xC000000UL 02190 #define _USART_CTRL_TXDELAY_DEFAULT 0x00000000UL 02191 #define _USART_CTRL_TXDELAY_NONE 0x00000000UL 02192 #define _USART_CTRL_TXDELAY_SINGLE 0x00000001UL 02193 #define _USART_CTRL_TXDELAY_DOUBLE 0x00000002UL 02194 #define _USART_CTRL_TXDELAY_TRIPLE 0x00000003UL 02195 #define USART_CTRL_TXDELAY_DEFAULT (_USART_CTRL_TXDELAY_DEFAULT << 26) 02196 #define USART_CTRL_TXDELAY_NONE (_USART_CTRL_TXDELAY_NONE << 26) 02197 #define USART_CTRL_TXDELAY_SINGLE (_USART_CTRL_TXDELAY_SINGLE << 26) 02198 #define USART_CTRL_TXDELAY_DOUBLE (_USART_CTRL_TXDELAY_DOUBLE << 26) 02199 #define USART_CTRL_TXDELAY_TRIPLE (_USART_CTRL_TXDELAY_TRIPLE << 26) 02200 #define USART_CTRL_BYTESWAP (0x1UL << 28) 02201 #define _USART_CTRL_BYTESWAP_SHIFT 28 02202 #define _USART_CTRL_BYTESWAP_MASK 0x10000000UL 02203 #define _USART_CTRL_BYTESWAP_DEFAULT 0x00000000UL 02204 #define USART_CTRL_BYTESWAP_DEFAULT (_USART_CTRL_BYTESWAP_DEFAULT << 28) 02206 /* Bit fields for USART FRAME */ 02207 #define _USART_FRAME_RESETVALUE 0x00001005UL 02208 #define _USART_FRAME_MASK 0x0000330FUL 02209 #define _USART_FRAME_DATABITS_SHIFT 0 02210 #define _USART_FRAME_DATABITS_MASK 0xFUL 02211 #define _USART_FRAME_DATABITS_FOUR 0x00000001UL 02212 #define _USART_FRAME_DATABITS_FIVE 0x00000002UL 02213 #define _USART_FRAME_DATABITS_SIX 0x00000003UL 02214 #define _USART_FRAME_DATABITS_SEVEN 0x00000004UL 02215 #define _USART_FRAME_DATABITS_DEFAULT 0x00000005UL 02216 #define _USART_FRAME_DATABITS_EIGHT 0x00000005UL 02217 #define _USART_FRAME_DATABITS_NINE 0x00000006UL 02218 #define _USART_FRAME_DATABITS_TEN 0x00000007UL 02219 #define _USART_FRAME_DATABITS_ELEVEN 0x00000008UL 02220 #define _USART_FRAME_DATABITS_TWELVE 0x00000009UL 02221 #define _USART_FRAME_DATABITS_THIRTEEN 0x0000000AUL 02222 #define _USART_FRAME_DATABITS_FOURTEEN 0x0000000BUL 02223 #define _USART_FRAME_DATABITS_FIFTEEN 0x0000000CUL 02224 #define _USART_FRAME_DATABITS_SIXTEEN 0x0000000DUL 02225 #define USART_FRAME_DATABITS_FOUR (_USART_FRAME_DATABITS_FOUR << 0) 02226 #define USART_FRAME_DATABITS_FIVE (_USART_FRAME_DATABITS_FIVE << 0) 02227 #define USART_FRAME_DATABITS_SIX (_USART_FRAME_DATABITS_SIX << 0) 02228 #define USART_FRAME_DATABITS_SEVEN (_USART_FRAME_DATABITS_SEVEN << 0) 02229 #define USART_FRAME_DATABITS_DEFAULT (_USART_FRAME_DATABITS_DEFAULT << 0) 02230 #define USART_FRAME_DATABITS_EIGHT (_USART_FRAME_DATABITS_EIGHT << 0) 02231 #define USART_FRAME_DATABITS_NINE (_USART_FRAME_DATABITS_NINE << 0) 02232 #define USART_FRAME_DATABITS_TEN (_USART_FRAME_DATABITS_TEN << 0) 02233 #define USART_FRAME_DATABITS_ELEVEN (_USART_FRAME_DATABITS_ELEVEN << 0) 02234 #define USART_FRAME_DATABITS_TWELVE (_USART_FRAME_DATABITS_TWELVE << 0) 02235 #define USART_FRAME_DATABITS_THIRTEEN (_USART_FRAME_DATABITS_THIRTEEN << 0) 02236 #define USART_FRAME_DATABITS_FOURTEEN (_USART_FRAME_DATABITS_FOURTEEN << 0) 02237 #define USART_FRAME_DATABITS_FIFTEEN (_USART_FRAME_DATABITS_FIFTEEN << 0) 02238 #define USART_FRAME_DATABITS_SIXTEEN (_USART_FRAME_DATABITS_SIXTEEN << 0) 02239 #define _USART_FRAME_PARITY_SHIFT 8 02240 #define _USART_FRAME_PARITY_MASK 0x300UL 02241 #define _USART_FRAME_PARITY_DEFAULT 0x00000000UL 02242 #define _USART_FRAME_PARITY_NONE 0x00000000UL 02243 #define _USART_FRAME_PARITY_EVEN 0x00000002UL 02244 #define _USART_FRAME_PARITY_ODD 0x00000003UL 02245 #define USART_FRAME_PARITY_DEFAULT (_USART_FRAME_PARITY_DEFAULT << 8) 02246 #define USART_FRAME_PARITY_NONE (_USART_FRAME_PARITY_NONE << 8) 02247 #define USART_FRAME_PARITY_EVEN (_USART_FRAME_PARITY_EVEN << 8) 02248 #define USART_FRAME_PARITY_ODD (_USART_FRAME_PARITY_ODD << 8) 02249 #define _USART_FRAME_STOPBITS_SHIFT 12 02250 #define _USART_FRAME_STOPBITS_MASK 0x3000UL 02251 #define _USART_FRAME_STOPBITS_HALF 0x00000000UL 02252 #define _USART_FRAME_STOPBITS_DEFAULT 0x00000001UL 02253 #define _USART_FRAME_STOPBITS_ONE 0x00000001UL 02254 #define _USART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL 02255 #define _USART_FRAME_STOPBITS_TWO 0x00000003UL 02256 #define USART_FRAME_STOPBITS_HALF (_USART_FRAME_STOPBITS_HALF << 12) 02257 #define USART_FRAME_STOPBITS_DEFAULT (_USART_FRAME_STOPBITS_DEFAULT << 12) 02258 #define USART_FRAME_STOPBITS_ONE (_USART_FRAME_STOPBITS_ONE << 12) 02259 #define USART_FRAME_STOPBITS_ONEANDAHALF (_USART_FRAME_STOPBITS_ONEANDAHALF << 12) 02260 #define USART_FRAME_STOPBITS_TWO (_USART_FRAME_STOPBITS_TWO << 12) 02262 /* Bit fields for USART TRIGCTRL */ 02263 #define _USART_TRIGCTRL_RESETVALUE 0x00000000UL 02264 #define _USART_TRIGCTRL_MASK 0x00000037UL 02265 #define _USART_TRIGCTRL_TSEL_SHIFT 0 02266 #define _USART_TRIGCTRL_TSEL_MASK 0x7UL 02267 #define _USART_TRIGCTRL_TSEL_DEFAULT 0x00000000UL 02268 #define _USART_TRIGCTRL_TSEL_PRSCH0 0x00000000UL 02269 #define _USART_TRIGCTRL_TSEL_PRSCH1 0x00000001UL 02270 #define _USART_TRIGCTRL_TSEL_PRSCH2 0x00000002UL 02271 #define _USART_TRIGCTRL_TSEL_PRSCH3 0x00000003UL 02272 #define _USART_TRIGCTRL_TSEL_PRSCH4 0x00000004UL 02273 #define _USART_TRIGCTRL_TSEL_PRSCH5 0x00000005UL 02274 #define _USART_TRIGCTRL_TSEL_PRSCH6 0x00000006UL 02275 #define _USART_TRIGCTRL_TSEL_PRSCH7 0x00000007UL 02276 #define USART_TRIGCTRL_TSEL_DEFAULT (_USART_TRIGCTRL_TSEL_DEFAULT << 0) 02277 #define USART_TRIGCTRL_TSEL_PRSCH0 (_USART_TRIGCTRL_TSEL_PRSCH0 << 0) 02278 #define USART_TRIGCTRL_TSEL_PRSCH1 (_USART_TRIGCTRL_TSEL_PRSCH1 << 0) 02279 #define USART_TRIGCTRL_TSEL_PRSCH2 (_USART_TRIGCTRL_TSEL_PRSCH2 << 0) 02280 #define USART_TRIGCTRL_TSEL_PRSCH3 (_USART_TRIGCTRL_TSEL_PRSCH3 << 0) 02281 #define USART_TRIGCTRL_TSEL_PRSCH4 (_USART_TRIGCTRL_TSEL_PRSCH4 << 0) 02282 #define USART_TRIGCTRL_TSEL_PRSCH5 (_USART_TRIGCTRL_TSEL_PRSCH5 << 0) 02283 #define USART_TRIGCTRL_TSEL_PRSCH6 (_USART_TRIGCTRL_TSEL_PRSCH6 << 0) 02284 #define USART_TRIGCTRL_TSEL_PRSCH7 (_USART_TRIGCTRL_TSEL_PRSCH7 << 0) 02285 #define USART_TRIGCTRL_RXTEN (0x1UL << 4) 02286 #define _USART_TRIGCTRL_RXTEN_SHIFT 4 02287 #define _USART_TRIGCTRL_RXTEN_MASK 0x10UL 02288 #define _USART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL 02289 #define USART_TRIGCTRL_RXTEN_DEFAULT (_USART_TRIGCTRL_RXTEN_DEFAULT << 4) 02290 #define USART_TRIGCTRL_TXTEN (0x1UL << 5) 02291 #define _USART_TRIGCTRL_TXTEN_SHIFT 5 02292 #define _USART_TRIGCTRL_TXTEN_MASK 0x20UL 02293 #define _USART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL 02294 #define USART_TRIGCTRL_TXTEN_DEFAULT (_USART_TRIGCTRL_TXTEN_DEFAULT << 5) 02296 /* Bit fields for USART CMD */ 02297 #define _USART_CMD_RESETVALUE 0x00000000UL 02298 #define _USART_CMD_MASK 0x00000FFFUL 02299 #define USART_CMD_RXEN (0x1UL << 0) 02300 #define _USART_CMD_RXEN_SHIFT 0 02301 #define _USART_CMD_RXEN_MASK 0x1UL 02302 #define _USART_CMD_RXEN_DEFAULT 0x00000000UL 02303 #define USART_CMD_RXEN_DEFAULT (_USART_CMD_RXEN_DEFAULT << 0) 02304 #define USART_CMD_RXDIS (0x1UL << 1) 02305 #define _USART_CMD_RXDIS_SHIFT 1 02306 #define _USART_CMD_RXDIS_MASK 0x2UL 02307 #define _USART_CMD_RXDIS_DEFAULT 0x00000000UL 02308 #define USART_CMD_RXDIS_DEFAULT (_USART_CMD_RXDIS_DEFAULT << 1) 02309 #define USART_CMD_TXEN (0x1UL << 2) 02310 #define _USART_CMD_TXEN_SHIFT 2 02311 #define _USART_CMD_TXEN_MASK 0x4UL 02312 #define _USART_CMD_TXEN_DEFAULT 0x00000000UL 02313 #define USART_CMD_TXEN_DEFAULT (_USART_CMD_TXEN_DEFAULT << 2) 02314 #define USART_CMD_TXDIS (0x1UL << 3) 02315 #define _USART_CMD_TXDIS_SHIFT 3 02316 #define _USART_CMD_TXDIS_MASK 0x8UL 02317 #define _USART_CMD_TXDIS_DEFAULT 0x00000000UL 02318 #define USART_CMD_TXDIS_DEFAULT (_USART_CMD_TXDIS_DEFAULT << 3) 02319 #define USART_CMD_MASTEREN (0x1UL << 4) 02320 #define _USART_CMD_MASTEREN_SHIFT 4 02321 #define _USART_CMD_MASTEREN_MASK 0x10UL 02322 #define _USART_CMD_MASTEREN_DEFAULT 0x00000000UL 02323 #define USART_CMD_MASTEREN_DEFAULT (_USART_CMD_MASTEREN_DEFAULT << 4) 02324 #define USART_CMD_MASTERDIS (0x1UL << 5) 02325 #define _USART_CMD_MASTERDIS_SHIFT 5 02326 #define _USART_CMD_MASTERDIS_MASK 0x20UL 02327 #define _USART_CMD_MASTERDIS_DEFAULT 0x00000000UL 02328 #define USART_CMD_MASTERDIS_DEFAULT (_USART_CMD_MASTERDIS_DEFAULT << 5) 02329 #define USART_CMD_RXBLOCKEN (0x1UL << 6) 02330 #define _USART_CMD_RXBLOCKEN_SHIFT 6 02331 #define _USART_CMD_RXBLOCKEN_MASK 0x40UL 02332 #define _USART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL 02333 #define USART_CMD_RXBLOCKEN_DEFAULT (_USART_CMD_RXBLOCKEN_DEFAULT << 6) 02334 #define USART_CMD_RXBLOCKDIS (0x1UL << 7) 02335 #define _USART_CMD_RXBLOCKDIS_SHIFT 7 02336 #define _USART_CMD_RXBLOCKDIS_MASK 0x80UL 02337 #define _USART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL 02338 #define USART_CMD_RXBLOCKDIS_DEFAULT (_USART_CMD_RXBLOCKDIS_DEFAULT << 7) 02339 #define USART_CMD_TXTRIEN (0x1UL << 8) 02340 #define _USART_CMD_TXTRIEN_SHIFT 8 02341 #define _USART_CMD_TXTRIEN_MASK 0x100UL 02342 #define _USART_CMD_TXTRIEN_DEFAULT 0x00000000UL 02343 #define USART_CMD_TXTRIEN_DEFAULT (_USART_CMD_TXTRIEN_DEFAULT << 8) 02344 #define USART_CMD_TXTRIDIS (0x1UL << 9) 02345 #define _USART_CMD_TXTRIDIS_SHIFT 9 02346 #define _USART_CMD_TXTRIDIS_MASK 0x200UL 02347 #define _USART_CMD_TXTRIDIS_DEFAULT 0x00000000UL 02348 #define USART_CMD_TXTRIDIS_DEFAULT (_USART_CMD_TXTRIDIS_DEFAULT << 9) 02349 #define USART_CMD_CLEARTX (0x1UL << 10) 02350 #define _USART_CMD_CLEARTX_SHIFT 10 02351 #define _USART_CMD_CLEARTX_MASK 0x400UL 02352 #define _USART_CMD_CLEARTX_DEFAULT 0x00000000UL 02353 #define USART_CMD_CLEARTX_DEFAULT (_USART_CMD_CLEARTX_DEFAULT << 10) 02354 #define USART_CMD_CLEARRX (0x1UL << 11) 02355 #define _USART_CMD_CLEARRX_SHIFT 11 02356 #define _USART_CMD_CLEARRX_MASK 0x800UL 02357 #define _USART_CMD_CLEARRX_DEFAULT 0x00000000UL 02358 #define USART_CMD_CLEARRX_DEFAULT (_USART_CMD_CLEARRX_DEFAULT << 11) 02360 /* Bit fields for USART STATUS */ 02361 #define _USART_STATUS_RESETVALUE 0x00000040UL 02362 #define _USART_STATUS_MASK 0x000001FFUL 02363 #define USART_STATUS_RXENS (0x1UL << 0) 02364 #define _USART_STATUS_RXENS_SHIFT 0 02365 #define _USART_STATUS_RXENS_MASK 0x1UL 02366 #define _USART_STATUS_RXENS_DEFAULT 0x00000000UL 02367 #define USART_STATUS_RXENS_DEFAULT (_USART_STATUS_RXENS_DEFAULT << 0) 02368 #define USART_STATUS_TXENS (0x1UL << 1) 02369 #define _USART_STATUS_TXENS_SHIFT 1 02370 #define _USART_STATUS_TXENS_MASK 0x2UL 02371 #define _USART_STATUS_TXENS_DEFAULT 0x00000000UL 02372 #define USART_STATUS_TXENS_DEFAULT (_USART_STATUS_TXENS_DEFAULT << 1) 02373 #define USART_STATUS_MASTER (0x1UL << 2) 02374 #define _USART_STATUS_MASTER_SHIFT 2 02375 #define _USART_STATUS_MASTER_MASK 0x4UL 02376 #define _USART_STATUS_MASTER_DEFAULT 0x00000000UL 02377 #define USART_STATUS_MASTER_DEFAULT (_USART_STATUS_MASTER_DEFAULT << 2) 02378 #define USART_STATUS_RXBLOCK (0x1UL << 3) 02379 #define _USART_STATUS_RXBLOCK_SHIFT 3 02380 #define _USART_STATUS_RXBLOCK_MASK 0x8UL 02381 #define _USART_STATUS_RXBLOCK_DEFAULT 0x00000000UL 02382 #define USART_STATUS_RXBLOCK_DEFAULT (_USART_STATUS_RXBLOCK_DEFAULT << 3) 02383 #define USART_STATUS_TXTRI (0x1UL << 4) 02384 #define _USART_STATUS_TXTRI_SHIFT 4 02385 #define _USART_STATUS_TXTRI_MASK 0x10UL 02386 #define _USART_STATUS_TXTRI_DEFAULT 0x00000000UL 02387 #define USART_STATUS_TXTRI_DEFAULT (_USART_STATUS_TXTRI_DEFAULT << 4) 02388 #define USART_STATUS_TXC (0x1UL << 5) 02389 #define _USART_STATUS_TXC_SHIFT 5 02390 #define _USART_STATUS_TXC_MASK 0x20UL 02391 #define _USART_STATUS_TXC_DEFAULT 0x00000000UL 02392 #define USART_STATUS_TXC_DEFAULT (_USART_STATUS_TXC_DEFAULT << 5) 02393 #define USART_STATUS_TXBL (0x1UL << 6) 02394 #define _USART_STATUS_TXBL_SHIFT 6 02395 #define _USART_STATUS_TXBL_MASK 0x40UL 02396 #define _USART_STATUS_TXBL_DEFAULT 0x00000001UL 02397 #define USART_STATUS_TXBL_DEFAULT (_USART_STATUS_TXBL_DEFAULT << 6) 02398 #define USART_STATUS_RXDATAV (0x1UL << 7) 02399 #define _USART_STATUS_RXDATAV_SHIFT 7 02400 #define _USART_STATUS_RXDATAV_MASK 0x80UL 02401 #define _USART_STATUS_RXDATAV_DEFAULT 0x00000000UL 02402 #define USART_STATUS_RXDATAV_DEFAULT (_USART_STATUS_RXDATAV_DEFAULT << 7) 02403 #define USART_STATUS_RXFULL (0x1UL << 8) 02404 #define _USART_STATUS_RXFULL_SHIFT 8 02405 #define _USART_STATUS_RXFULL_MASK 0x100UL 02406 #define _USART_STATUS_RXFULL_DEFAULT 0x00000000UL 02407 #define USART_STATUS_RXFULL_DEFAULT (_USART_STATUS_RXFULL_DEFAULT << 8) 02409 /* Bit fields for USART CLKDIV */ 02410 #define _USART_CLKDIV_RESETVALUE 0x00000000UL 02411 #define _USART_CLKDIV_MASK 0x001FFFC0UL 02412 #define _USART_CLKDIV_DIV_SHIFT 6 02413 #define _USART_CLKDIV_DIV_MASK 0x1FFFC0UL 02414 #define _USART_CLKDIV_DIV_DEFAULT 0x00000000UL 02415 #define USART_CLKDIV_DIV_DEFAULT (_USART_CLKDIV_DIV_DEFAULT << 6) 02417 /* Bit fields for USART RXDATAX */ 02418 #define _USART_RXDATAX_RESETVALUE 0x00000000UL 02419 #define _USART_RXDATAX_MASK 0x0000C1FFUL 02420 #define _USART_RXDATAX_RXDATA_SHIFT 0 02421 #define _USART_RXDATAX_RXDATA_MASK 0x1FFUL 02422 #define _USART_RXDATAX_RXDATA_DEFAULT 0x00000000UL 02423 #define USART_RXDATAX_RXDATA_DEFAULT (_USART_RXDATAX_RXDATA_DEFAULT << 0) 02424 #define USART_RXDATAX_PERR (0x1UL << 14) 02425 #define _USART_RXDATAX_PERR_SHIFT 14 02426 #define _USART_RXDATAX_PERR_MASK 0x4000UL 02427 #define _USART_RXDATAX_PERR_DEFAULT 0x00000000UL 02428 #define USART_RXDATAX_PERR_DEFAULT (_USART_RXDATAX_PERR_DEFAULT << 14) 02429 #define USART_RXDATAX_FERR (0x1UL << 15) 02430 #define _USART_RXDATAX_FERR_SHIFT 15 02431 #define _USART_RXDATAX_FERR_MASK 0x8000UL 02432 #define _USART_RXDATAX_FERR_DEFAULT 0x00000000UL 02433 #define USART_RXDATAX_FERR_DEFAULT (_USART_RXDATAX_FERR_DEFAULT << 15) 02435 /* Bit fields for USART RXDATA */ 02436 #define _USART_RXDATA_RESETVALUE 0x00000000UL 02437 #define _USART_RXDATA_MASK 0x000000FFUL 02438 #define _USART_RXDATA_RXDATA_SHIFT 0 02439 #define _USART_RXDATA_RXDATA_MASK 0xFFUL 02440 #define _USART_RXDATA_RXDATA_DEFAULT 0x00000000UL 02441 #define USART_RXDATA_RXDATA_DEFAULT (_USART_RXDATA_RXDATA_DEFAULT << 0) 02443 /* Bit fields for USART RXDOUBLEX */ 02444 #define _USART_RXDOUBLEX_RESETVALUE 0x00000000UL 02445 #define _USART_RXDOUBLEX_MASK 0xC1FFC1FFUL 02446 #define _USART_RXDOUBLEX_RXDATA0_SHIFT 0 02447 #define _USART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL 02448 #define _USART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL 02449 #define USART_RXDOUBLEX_RXDATA0_DEFAULT (_USART_RXDOUBLEX_RXDATA0_DEFAULT << 0) 02450 #define USART_RXDOUBLEX_PERR0 (0x1UL << 14) 02451 #define _USART_RXDOUBLEX_PERR0_SHIFT 14 02452 #define _USART_RXDOUBLEX_PERR0_MASK 0x4000UL 02453 #define _USART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL 02454 #define USART_RXDOUBLEX_PERR0_DEFAULT (_USART_RXDOUBLEX_PERR0_DEFAULT << 14) 02455 #define USART_RXDOUBLEX_FERR0 (0x1UL << 15) 02456 #define _USART_RXDOUBLEX_FERR0_SHIFT 15 02457 #define _USART_RXDOUBLEX_FERR0_MASK 0x8000UL 02458 #define _USART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL 02459 #define USART_RXDOUBLEX_FERR0_DEFAULT (_USART_RXDOUBLEX_FERR0_DEFAULT << 15) 02460 #define _USART_RXDOUBLEX_RXDATA1_SHIFT 16 02461 #define _USART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL 02462 #define _USART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL 02463 #define USART_RXDOUBLEX_RXDATA1_DEFAULT (_USART_RXDOUBLEX_RXDATA1_DEFAULT << 16) 02464 #define USART_RXDOUBLEX_PERR1 (0x1UL << 30) 02465 #define _USART_RXDOUBLEX_PERR1_SHIFT 30 02466 #define _USART_RXDOUBLEX_PERR1_MASK 0x40000000UL 02467 #define _USART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL 02468 #define USART_RXDOUBLEX_PERR1_DEFAULT (_USART_RXDOUBLEX_PERR1_DEFAULT << 30) 02469 #define USART_RXDOUBLEX_FERR1 (0x1UL << 31) 02470 #define _USART_RXDOUBLEX_FERR1_SHIFT 31 02471 #define _USART_RXDOUBLEX_FERR1_MASK 0x80000000UL 02472 #define _USART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL 02473 #define USART_RXDOUBLEX_FERR1_DEFAULT (_USART_RXDOUBLEX_FERR1_DEFAULT << 31) 02475 /* Bit fields for USART RXDOUBLE */ 02476 #define _USART_RXDOUBLE_RESETVALUE 0x00000000UL 02477 #define _USART_RXDOUBLE_MASK 0x0000FFFFUL 02478 #define _USART_RXDOUBLE_RXDATA0_SHIFT 0 02479 #define _USART_RXDOUBLE_RXDATA0_MASK 0xFFUL 02480 #define _USART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL 02481 #define USART_RXDOUBLE_RXDATA0_DEFAULT (_USART_RXDOUBLE_RXDATA0_DEFAULT << 0) 02482 #define _USART_RXDOUBLE_RXDATA1_SHIFT 8 02483 #define _USART_RXDOUBLE_RXDATA1_MASK 0xFF00UL 02484 #define _USART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL 02485 #define USART_RXDOUBLE_RXDATA1_DEFAULT (_USART_RXDOUBLE_RXDATA1_DEFAULT << 8) 02487 /* Bit fields for USART RXDATAXP */ 02488 #define _USART_RXDATAXP_RESETVALUE 0x00000000UL 02489 #define _USART_RXDATAXP_MASK 0x0000C1FFUL 02490 #define _USART_RXDATAXP_RXDATAP_SHIFT 0 02491 #define _USART_RXDATAXP_RXDATAP_MASK 0x1FFUL 02492 #define _USART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL 02493 #define USART_RXDATAXP_RXDATAP_DEFAULT (_USART_RXDATAXP_RXDATAP_DEFAULT << 0) 02494 #define USART_RXDATAXP_PERRP (0x1UL << 14) 02495 #define _USART_RXDATAXP_PERRP_SHIFT 14 02496 #define _USART_RXDATAXP_PERRP_MASK 0x4000UL 02497 #define _USART_RXDATAXP_PERRP_DEFAULT 0x00000000UL 02498 #define USART_RXDATAXP_PERRP_DEFAULT (_USART_RXDATAXP_PERRP_DEFAULT << 14) 02499 #define USART_RXDATAXP_FERRP (0x1UL << 15) 02500 #define _USART_RXDATAXP_FERRP_SHIFT 15 02501 #define _USART_RXDATAXP_FERRP_MASK 0x8000UL 02502 #define _USART_RXDATAXP_FERRP_DEFAULT 0x00000000UL 02503 #define USART_RXDATAXP_FERRP_DEFAULT (_USART_RXDATAXP_FERRP_DEFAULT << 15) 02505 /* Bit fields for USART RXDOUBLEXP */ 02506 #define _USART_RXDOUBLEXP_RESETVALUE 0x00000000UL 02507 #define _USART_RXDOUBLEXP_MASK 0xC1FFC1FFUL 02508 #define _USART_RXDOUBLEXP_RXDATAP0_SHIFT 0 02509 #define _USART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL 02510 #define _USART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL 02511 #define USART_RXDOUBLEXP_RXDATAP0_DEFAULT (_USART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0) 02512 #define USART_RXDOUBLEXP_PERRP0 (0x1UL << 14) 02513 #define _USART_RXDOUBLEXP_PERRP0_SHIFT 14 02514 #define _USART_RXDOUBLEXP_PERRP0_MASK 0x4000UL 02515 #define _USART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL 02516 #define USART_RXDOUBLEXP_PERRP0_DEFAULT (_USART_RXDOUBLEXP_PERRP0_DEFAULT << 14) 02517 #define USART_RXDOUBLEXP_FERRP0 (0x1UL << 15) 02518 #define _USART_RXDOUBLEXP_FERRP0_SHIFT 15 02519 #define _USART_RXDOUBLEXP_FERRP0_MASK 0x8000UL 02520 #define _USART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL 02521 #define USART_RXDOUBLEXP_FERRP0_DEFAULT (_USART_RXDOUBLEXP_FERRP0_DEFAULT << 15) 02522 #define _USART_RXDOUBLEXP_RXDATAP1_SHIFT 16 02523 #define _USART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL 02524 #define _USART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL 02525 #define USART_RXDOUBLEXP_RXDATAP1_DEFAULT (_USART_RXDOUBLEXP_RXDATAP1_DEFAULT << 16) 02526 #define USART_RXDOUBLEXP_PERRP1 (0x1UL << 30) 02527 #define _USART_RXDOUBLEXP_PERRP1_SHIFT 30 02528 #define _USART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL 02529 #define _USART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL 02530 #define USART_RXDOUBLEXP_PERRP1_DEFAULT (_USART_RXDOUBLEXP_PERRP1_DEFAULT << 30) 02531 #define USART_RXDOUBLEXP_FERRP1 (0x1UL << 31) 02532 #define _USART_RXDOUBLEXP_FERRP1_SHIFT 31 02533 #define _USART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL 02534 #define _USART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL 02535 #define USART_RXDOUBLEXP_FERRP1_DEFAULT (_USART_RXDOUBLEXP_FERRP1_DEFAULT << 31) 02537 /* Bit fields for USART TXDATAX */ 02538 #define _USART_TXDATAX_RESETVALUE 0x00000000UL 02539 #define _USART_TXDATAX_MASK 0x0000F9FFUL 02540 #define _USART_TXDATAX_TXDATAX_SHIFT 0 02541 #define _USART_TXDATAX_TXDATAX_MASK 0x1FFUL 02542 #define _USART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL 02543 #define USART_TXDATAX_TXDATAX_DEFAULT (_USART_TXDATAX_TXDATAX_DEFAULT << 0) 02544 #define USART_TXDATAX_UBRXAT (0x1UL << 11) 02545 #define _USART_TXDATAX_UBRXAT_SHIFT 11 02546 #define _USART_TXDATAX_UBRXAT_MASK 0x800UL 02547 #define _USART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL 02548 #define USART_TXDATAX_UBRXAT_DEFAULT (_USART_TXDATAX_UBRXAT_DEFAULT << 11) 02549 #define USART_TXDATAX_TXTRIAT (0x1UL << 12) 02550 #define _USART_TXDATAX_TXTRIAT_SHIFT 12 02551 #define _USART_TXDATAX_TXTRIAT_MASK 0x1000UL 02552 #define _USART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL 02553 #define USART_TXDATAX_TXTRIAT_DEFAULT (_USART_TXDATAX_TXTRIAT_DEFAULT << 12) 02554 #define USART_TXDATAX_TXBREAK (0x1UL << 13) 02555 #define _USART_TXDATAX_TXBREAK_SHIFT 13 02556 #define _USART_TXDATAX_TXBREAK_MASK 0x2000UL 02557 #define _USART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL 02558 #define USART_TXDATAX_TXBREAK_DEFAULT (_USART_TXDATAX_TXBREAK_DEFAULT << 13) 02559 #define USART_TXDATAX_TXDISAT (0x1UL << 14) 02560 #define _USART_TXDATAX_TXDISAT_SHIFT 14 02561 #define _USART_TXDATAX_TXDISAT_MASK 0x4000UL 02562 #define _USART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL 02563 #define USART_TXDATAX_TXDISAT_DEFAULT (_USART_TXDATAX_TXDISAT_DEFAULT << 14) 02564 #define USART_TXDATAX_RXENAT (0x1UL << 15) 02565 #define _USART_TXDATAX_RXENAT_SHIFT 15 02566 #define _USART_TXDATAX_RXENAT_MASK 0x8000UL 02567 #define _USART_TXDATAX_RXENAT_DEFAULT 0x00000000UL 02568 #define USART_TXDATAX_RXENAT_DEFAULT (_USART_TXDATAX_RXENAT_DEFAULT << 15) 02570 /* Bit fields for USART TXDATA */ 02571 #define _USART_TXDATA_RESETVALUE 0x00000000UL 02572 #define _USART_TXDATA_MASK 0x000000FFUL 02573 #define _USART_TXDATA_TXDATA_SHIFT 0 02574 #define _USART_TXDATA_TXDATA_MASK 0xFFUL 02575 #define _USART_TXDATA_TXDATA_DEFAULT 0x00000000UL 02576 #define USART_TXDATA_TXDATA_DEFAULT (_USART_TXDATA_TXDATA_DEFAULT << 0) 02578 /* Bit fields for USART TXDOUBLEX */ 02579 #define _USART_TXDOUBLEX_RESETVALUE 0x00000000UL 02580 #define _USART_TXDOUBLEX_MASK 0xF9FFF9FFUL 02581 #define _USART_TXDOUBLEX_TXDATA0_SHIFT 0 02582 #define _USART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL 02583 #define _USART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL 02584 #define USART_TXDOUBLEX_TXDATA0_DEFAULT (_USART_TXDOUBLEX_TXDATA0_DEFAULT << 0) 02585 #define USART_TXDOUBLEX_UBRXAT0 (0x1UL << 11) 02586 #define _USART_TXDOUBLEX_UBRXAT0_SHIFT 11 02587 #define _USART_TXDOUBLEX_UBRXAT0_MASK 0x800UL 02588 #define _USART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL 02589 #define USART_TXDOUBLEX_UBRXAT0_DEFAULT (_USART_TXDOUBLEX_UBRXAT0_DEFAULT << 11) 02590 #define USART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12) 02591 #define _USART_TXDOUBLEX_TXTRIAT0_SHIFT 12 02592 #define _USART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL 02593 #define _USART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL 02594 #define USART_TXDOUBLEX_TXTRIAT0_DEFAULT (_USART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12) 02595 #define USART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) 02596 #define _USART_TXDOUBLEX_TXBREAK0_SHIFT 13 02597 #define _USART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL 02598 #define _USART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL 02599 #define USART_TXDOUBLEX_TXBREAK0_DEFAULT (_USART_TXDOUBLEX_TXBREAK0_DEFAULT << 13) 02600 #define USART_TXDOUBLEX_TXDISAT0 (0x1UL << 14) 02601 #define _USART_TXDOUBLEX_TXDISAT0_SHIFT 14 02602 #define _USART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL 02603 #define _USART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL 02604 #define USART_TXDOUBLEX_TXDISAT0_DEFAULT (_USART_TXDOUBLEX_TXDISAT0_DEFAULT << 14) 02605 #define USART_TXDOUBLEX_RXENAT0 (0x1UL << 15) 02606 #define _USART_TXDOUBLEX_RXENAT0_SHIFT 15 02607 #define _USART_TXDOUBLEX_RXENAT0_MASK 0x8000UL 02608 #define _USART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL 02609 #define USART_TXDOUBLEX_RXENAT0_DEFAULT (_USART_TXDOUBLEX_RXENAT0_DEFAULT << 15) 02610 #define _USART_TXDOUBLEX_TXDATA1_SHIFT 16 02611 #define _USART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL 02612 #define _USART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL 02613 #define USART_TXDOUBLEX_TXDATA1_DEFAULT (_USART_TXDOUBLEX_TXDATA1_DEFAULT << 16) 02614 #define USART_TXDOUBLEX_UBRXAT1 (0x1UL << 27) 02615 #define _USART_TXDOUBLEX_UBRXAT1_SHIFT 27 02616 #define _USART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL 02617 #define _USART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL 02618 #define USART_TXDOUBLEX_UBRXAT1_DEFAULT (_USART_TXDOUBLEX_UBRXAT1_DEFAULT << 27) 02619 #define USART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28) 02620 #define _USART_TXDOUBLEX_TXTRIAT1_SHIFT 28 02621 #define _USART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL 02622 #define _USART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL 02623 #define USART_TXDOUBLEX_TXTRIAT1_DEFAULT (_USART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28) 02624 #define USART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) 02625 #define _USART_TXDOUBLEX_TXBREAK1_SHIFT 29 02626 #define _USART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL 02627 #define _USART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL 02628 #define USART_TXDOUBLEX_TXBREAK1_DEFAULT (_USART_TXDOUBLEX_TXBREAK1_DEFAULT << 29) 02629 #define USART_TXDOUBLEX_TXDISAT1 (0x1UL << 30) 02630 #define _USART_TXDOUBLEX_TXDISAT1_SHIFT 30 02631 #define _USART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL 02632 #define _USART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL 02633 #define USART_TXDOUBLEX_TXDISAT1_DEFAULT (_USART_TXDOUBLEX_TXDISAT1_DEFAULT << 30) 02634 #define USART_TXDOUBLEX_RXENAT1 (0x1UL << 31) 02635 #define _USART_TXDOUBLEX_RXENAT1_SHIFT 31 02636 #define _USART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL 02637 #define _USART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL 02638 #define USART_TXDOUBLEX_RXENAT1_DEFAULT (_USART_TXDOUBLEX_RXENAT1_DEFAULT << 31) 02640 /* Bit fields for USART TXDOUBLE */ 02641 #define _USART_TXDOUBLE_RESETVALUE 0x00000000UL 02642 #define _USART_TXDOUBLE_MASK 0x0000FFFFUL 02643 #define _USART_TXDOUBLE_TXDATA0_SHIFT 0 02644 #define _USART_TXDOUBLE_TXDATA0_MASK 0xFFUL 02645 #define _USART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL 02646 #define USART_TXDOUBLE_TXDATA0_DEFAULT (_USART_TXDOUBLE_TXDATA0_DEFAULT << 0) 02647 #define _USART_TXDOUBLE_TXDATA1_SHIFT 8 02648 #define _USART_TXDOUBLE_TXDATA1_MASK 0xFF00UL 02649 #define _USART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL 02650 #define USART_TXDOUBLE_TXDATA1_DEFAULT (_USART_TXDOUBLE_TXDATA1_DEFAULT << 8) 02652 /* Bit fields for USART IF */ 02653 #define _USART_IF_RESETVALUE 0x00000002UL 02654 #define _USART_IF_MASK 0x00001FFFUL 02655 #define USART_IF_TXC (0x1UL << 0) 02656 #define _USART_IF_TXC_SHIFT 0 02657 #define _USART_IF_TXC_MASK 0x1UL 02658 #define _USART_IF_TXC_DEFAULT 0x00000000UL 02659 #define USART_IF_TXC_DEFAULT (_USART_IF_TXC_DEFAULT << 0) 02660 #define USART_IF_TXBL (0x1UL << 1) 02661 #define _USART_IF_TXBL_SHIFT 1 02662 #define _USART_IF_TXBL_MASK 0x2UL 02663 #define _USART_IF_TXBL_DEFAULT 0x00000001UL 02664 #define USART_IF_TXBL_DEFAULT (_USART_IF_TXBL_DEFAULT << 1) 02665 #define USART_IF_RXDATAV (0x1UL << 2) 02666 #define _USART_IF_RXDATAV_SHIFT 2 02667 #define _USART_IF_RXDATAV_MASK 0x4UL 02668 #define _USART_IF_RXDATAV_DEFAULT 0x00000000UL 02669 #define USART_IF_RXDATAV_DEFAULT (_USART_IF_RXDATAV_DEFAULT << 2) 02670 #define USART_IF_RXFULL (0x1UL << 3) 02671 #define _USART_IF_RXFULL_SHIFT 3 02672 #define _USART_IF_RXFULL_MASK 0x8UL 02673 #define _USART_IF_RXFULL_DEFAULT 0x00000000UL 02674 #define USART_IF_RXFULL_DEFAULT (_USART_IF_RXFULL_DEFAULT << 3) 02675 #define USART_IF_RXOF (0x1UL << 4) 02676 #define _USART_IF_RXOF_SHIFT 4 02677 #define _USART_IF_RXOF_MASK 0x10UL 02678 #define _USART_IF_RXOF_DEFAULT 0x00000000UL 02679 #define USART_IF_RXOF_DEFAULT (_USART_IF_RXOF_DEFAULT << 4) 02680 #define USART_IF_RXUF (0x1UL << 5) 02681 #define _USART_IF_RXUF_SHIFT 5 02682 #define _USART_IF_RXUF_MASK 0x20UL 02683 #define _USART_IF_RXUF_DEFAULT 0x00000000UL 02684 #define USART_IF_RXUF_DEFAULT (_USART_IF_RXUF_DEFAULT << 5) 02685 #define USART_IF_TXOF (0x1UL << 6) 02686 #define _USART_IF_TXOF_SHIFT 6 02687 #define _USART_IF_TXOF_MASK 0x40UL 02688 #define _USART_IF_TXOF_DEFAULT 0x00000000UL 02689 #define USART_IF_TXOF_DEFAULT (_USART_IF_TXOF_DEFAULT << 6) 02690 #define USART_IF_TXUF (0x1UL << 7) 02691 #define _USART_IF_TXUF_SHIFT 7 02692 #define _USART_IF_TXUF_MASK 0x80UL 02693 #define _USART_IF_TXUF_DEFAULT 0x00000000UL 02694 #define USART_IF_TXUF_DEFAULT (_USART_IF_TXUF_DEFAULT << 7) 02695 #define USART_IF_PERR (0x1UL << 8) 02696 #define _USART_IF_PERR_SHIFT 8 02697 #define _USART_IF_PERR_MASK 0x100UL 02698 #define _USART_IF_PERR_DEFAULT 0x00000000UL 02699 #define USART_IF_PERR_DEFAULT (_USART_IF_PERR_DEFAULT << 8) 02700 #define USART_IF_FERR (0x1UL << 9) 02701 #define _USART_IF_FERR_SHIFT 9 02702 #define _USART_IF_FERR_MASK 0x200UL 02703 #define _USART_IF_FERR_DEFAULT 0x00000000UL 02704 #define USART_IF_FERR_DEFAULT (_USART_IF_FERR_DEFAULT << 9) 02705 #define USART_IF_MPAF (0x1UL << 10) 02706 #define _USART_IF_MPAF_SHIFT 10 02707 #define _USART_IF_MPAF_MASK 0x400UL 02708 #define _USART_IF_MPAF_DEFAULT 0x00000000UL 02709 #define USART_IF_MPAF_DEFAULT (_USART_IF_MPAF_DEFAULT << 10) 02710 #define USART_IF_SSM (0x1UL << 11) 02711 #define _USART_IF_SSM_SHIFT 11 02712 #define _USART_IF_SSM_MASK 0x800UL 02713 #define _USART_IF_SSM_DEFAULT 0x00000000UL 02714 #define USART_IF_SSM_DEFAULT (_USART_IF_SSM_DEFAULT << 11) 02715 #define USART_IF_CCF (0x1UL << 12) 02716 #define _USART_IF_CCF_SHIFT 12 02717 #define _USART_IF_CCF_MASK 0x1000UL 02718 #define _USART_IF_CCF_DEFAULT 0x00000000UL 02719 #define USART_IF_CCF_DEFAULT (_USART_IF_CCF_DEFAULT << 12) 02721 /* Bit fields for USART IFS */ 02722 #define _USART_IFS_RESETVALUE 0x00000000UL 02723 #define _USART_IFS_MASK 0x00001FF9UL 02724 #define USART_IFS_TXC (0x1UL << 0) 02725 #define _USART_IFS_TXC_SHIFT 0 02726 #define _USART_IFS_TXC_MASK 0x1UL 02727 #define _USART_IFS_TXC_DEFAULT 0x00000000UL 02728 #define USART_IFS_TXC_DEFAULT (_USART_IFS_TXC_DEFAULT << 0) 02729 #define USART_IFS_RXFULL (0x1UL << 3) 02730 #define _USART_IFS_RXFULL_SHIFT 3 02731 #define _USART_IFS_RXFULL_MASK 0x8UL 02732 #define _USART_IFS_RXFULL_DEFAULT 0x00000000UL 02733 #define USART_IFS_RXFULL_DEFAULT (_USART_IFS_RXFULL_DEFAULT << 3) 02734 #define USART_IFS_RXOF (0x1UL << 4) 02735 #define _USART_IFS_RXOF_SHIFT 4 02736 #define _USART_IFS_RXOF_MASK 0x10UL 02737 #define _USART_IFS_RXOF_DEFAULT 0x00000000UL 02738 #define USART_IFS_RXOF_DEFAULT (_USART_IFS_RXOF_DEFAULT << 4) 02739 #define USART_IFS_RXUF (0x1UL << 5) 02740 #define _USART_IFS_RXUF_SHIFT 5 02741 #define _USART_IFS_RXUF_MASK 0x20UL 02742 #define _USART_IFS_RXUF_DEFAULT 0x00000000UL 02743 #define USART_IFS_RXUF_DEFAULT (_USART_IFS_RXUF_DEFAULT << 5) 02744 #define USART_IFS_TXOF (0x1UL << 6) 02745 #define _USART_IFS_TXOF_SHIFT 6 02746 #define _USART_IFS_TXOF_MASK 0x40UL 02747 #define _USART_IFS_TXOF_DEFAULT 0x00000000UL 02748 #define USART_IFS_TXOF_DEFAULT (_USART_IFS_TXOF_DEFAULT << 6) 02749 #define USART_IFS_TXUF (0x1UL << 7) 02750 #define _USART_IFS_TXUF_SHIFT 7 02751 #define _USART_IFS_TXUF_MASK 0x80UL 02752 #define _USART_IFS_TXUF_DEFAULT 0x00000000UL 02753 #define USART_IFS_TXUF_DEFAULT (_USART_IFS_TXUF_DEFAULT << 7) 02754 #define USART_IFS_PERR (0x1UL << 8) 02755 #define _USART_IFS_PERR_SHIFT 8 02756 #define _USART_IFS_PERR_MASK 0x100UL 02757 #define _USART_IFS_PERR_DEFAULT 0x00000000UL 02758 #define USART_IFS_PERR_DEFAULT (_USART_IFS_PERR_DEFAULT << 8) 02759 #define USART_IFS_FERR (0x1UL << 9) 02760 #define _USART_IFS_FERR_SHIFT 9 02761 #define _USART_IFS_FERR_MASK 0x200UL 02762 #define _USART_IFS_FERR_DEFAULT 0x00000000UL 02763 #define USART_IFS_FERR_DEFAULT (_USART_IFS_FERR_DEFAULT << 9) 02764 #define USART_IFS_MPAF (0x1UL << 10) 02765 #define _USART_IFS_MPAF_SHIFT 10 02766 #define _USART_IFS_MPAF_MASK 0x400UL 02767 #define _USART_IFS_MPAF_DEFAULT 0x00000000UL 02768 #define USART_IFS_MPAF_DEFAULT (_USART_IFS_MPAF_DEFAULT << 10) 02769 #define USART_IFS_SSM (0x1UL << 11) 02770 #define _USART_IFS_SSM_SHIFT 11 02771 #define _USART_IFS_SSM_MASK 0x800UL 02772 #define _USART_IFS_SSM_DEFAULT 0x00000000UL 02773 #define USART_IFS_SSM_DEFAULT (_USART_IFS_SSM_DEFAULT << 11) 02774 #define USART_IFS_CCF (0x1UL << 12) 02775 #define _USART_IFS_CCF_SHIFT 12 02776 #define _USART_IFS_CCF_MASK 0x1000UL 02777 #define _USART_IFS_CCF_DEFAULT 0x00000000UL 02778 #define USART_IFS_CCF_DEFAULT (_USART_IFS_CCF_DEFAULT << 12) 02780 /* Bit fields for USART IFC */ 02781 #define _USART_IFC_RESETVALUE 0x00000000UL 02782 #define _USART_IFC_MASK 0x00001FF9UL 02783 #define USART_IFC_TXC (0x1UL << 0) 02784 #define _USART_IFC_TXC_SHIFT 0 02785 #define _USART_IFC_TXC_MASK 0x1UL 02786 #define _USART_IFC_TXC_DEFAULT 0x00000000UL 02787 #define USART_IFC_TXC_DEFAULT (_USART_IFC_TXC_DEFAULT << 0) 02788 #define USART_IFC_RXFULL (0x1UL << 3) 02789 #define _USART_IFC_RXFULL_SHIFT 3 02790 #define _USART_IFC_RXFULL_MASK 0x8UL 02791 #define _USART_IFC_RXFULL_DEFAULT 0x00000000UL 02792 #define USART_IFC_RXFULL_DEFAULT (_USART_IFC_RXFULL_DEFAULT << 3) 02793 #define USART_IFC_RXOF (0x1UL << 4) 02794 #define _USART_IFC_RXOF_SHIFT 4 02795 #define _USART_IFC_RXOF_MASK 0x10UL 02796 #define _USART_IFC_RXOF_DEFAULT 0x00000000UL 02797 #define USART_IFC_RXOF_DEFAULT (_USART_IFC_RXOF_DEFAULT << 4) 02798 #define USART_IFC_RXUF (0x1UL << 5) 02799 #define _USART_IFC_RXUF_SHIFT 5 02800 #define _USART_IFC_RXUF_MASK 0x20UL 02801 #define _USART_IFC_RXUF_DEFAULT 0x00000000UL 02802 #define USART_IFC_RXUF_DEFAULT (_USART_IFC_RXUF_DEFAULT << 5) 02803 #define USART_IFC_TXOF (0x1UL << 6) 02804 #define _USART_IFC_TXOF_SHIFT 6 02805 #define _USART_IFC_TXOF_MASK 0x40UL 02806 #define _USART_IFC_TXOF_DEFAULT 0x00000000UL 02807 #define USART_IFC_TXOF_DEFAULT (_USART_IFC_TXOF_DEFAULT << 6) 02808 #define USART_IFC_TXUF (0x1UL << 7) 02809 #define _USART_IFC_TXUF_SHIFT 7 02810 #define _USART_IFC_TXUF_MASK 0x80UL 02811 #define _USART_IFC_TXUF_DEFAULT 0x00000000UL 02812 #define USART_IFC_TXUF_DEFAULT (_USART_IFC_TXUF_DEFAULT << 7) 02813 #define USART_IFC_PERR (0x1UL << 8) 02814 #define _USART_IFC_PERR_SHIFT 8 02815 #define _USART_IFC_PERR_MASK 0x100UL 02816 #define _USART_IFC_PERR_DEFAULT 0x00000000UL 02817 #define USART_IFC_PERR_DEFAULT (_USART_IFC_PERR_DEFAULT << 8) 02818 #define USART_IFC_FERR (0x1UL << 9) 02819 #define _USART_IFC_FERR_SHIFT 9 02820 #define _USART_IFC_FERR_MASK 0x200UL 02821 #define _USART_IFC_FERR_DEFAULT 0x00000000UL 02822 #define USART_IFC_FERR_DEFAULT (_USART_IFC_FERR_DEFAULT << 9) 02823 #define USART_IFC_MPAF (0x1UL << 10) 02824 #define _USART_IFC_MPAF_SHIFT 10 02825 #define _USART_IFC_MPAF_MASK 0x400UL 02826 #define _USART_IFC_MPAF_DEFAULT 0x00000000UL 02827 #define USART_IFC_MPAF_DEFAULT (_USART_IFC_MPAF_DEFAULT << 10) 02828 #define USART_IFC_SSM (0x1UL << 11) 02829 #define _USART_IFC_SSM_SHIFT 11 02830 #define _USART_IFC_SSM_MASK 0x800UL 02831 #define _USART_IFC_SSM_DEFAULT 0x00000000UL 02832 #define USART_IFC_SSM_DEFAULT (_USART_IFC_SSM_DEFAULT << 11) 02833 #define USART_IFC_CCF (0x1UL << 12) 02834 #define _USART_IFC_CCF_SHIFT 12 02835 #define _USART_IFC_CCF_MASK 0x1000UL 02836 #define _USART_IFC_CCF_DEFAULT 0x00000000UL 02837 #define USART_IFC_CCF_DEFAULT (_USART_IFC_CCF_DEFAULT << 12) 02839 /* Bit fields for USART IEN */ 02840 #define _USART_IEN_RESETVALUE 0x00000000UL 02841 #define _USART_IEN_MASK 0x00001FFFUL 02842 #define USART_IEN_TXC (0x1UL << 0) 02843 #define _USART_IEN_TXC_SHIFT 0 02844 #define _USART_IEN_TXC_MASK 0x1UL 02845 #define _USART_IEN_TXC_DEFAULT 0x00000000UL 02846 #define USART_IEN_TXC_DEFAULT (_USART_IEN_TXC_DEFAULT << 0) 02847 #define USART_IEN_TXBL (0x1UL << 1) 02848 #define _USART_IEN_TXBL_SHIFT 1 02849 #define _USART_IEN_TXBL_MASK 0x2UL 02850 #define _USART_IEN_TXBL_DEFAULT 0x00000000UL 02851 #define USART_IEN_TXBL_DEFAULT (_USART_IEN_TXBL_DEFAULT << 1) 02852 #define USART_IEN_RXDATAV (0x1UL << 2) 02853 #define _USART_IEN_RXDATAV_SHIFT 2 02854 #define _USART_IEN_RXDATAV_MASK 0x4UL 02855 #define _USART_IEN_RXDATAV_DEFAULT 0x00000000UL 02856 #define USART_IEN_RXDATAV_DEFAULT (_USART_IEN_RXDATAV_DEFAULT << 2) 02857 #define USART_IEN_RXFULL (0x1UL << 3) 02858 #define _USART_IEN_RXFULL_SHIFT 3 02859 #define _USART_IEN_RXFULL_MASK 0x8UL 02860 #define _USART_IEN_RXFULL_DEFAULT 0x00000000UL 02861 #define USART_IEN_RXFULL_DEFAULT (_USART_IEN_RXFULL_DEFAULT << 3) 02862 #define USART_IEN_RXOF (0x1UL << 4) 02863 #define _USART_IEN_RXOF_SHIFT 4 02864 #define _USART_IEN_RXOF_MASK 0x10UL 02865 #define _USART_IEN_RXOF_DEFAULT 0x00000000UL 02866 #define USART_IEN_RXOF_DEFAULT (_USART_IEN_RXOF_DEFAULT << 4) 02867 #define USART_IEN_RXUF (0x1UL << 5) 02868 #define _USART_IEN_RXUF_SHIFT 5 02869 #define _USART_IEN_RXUF_MASK 0x20UL 02870 #define _USART_IEN_RXUF_DEFAULT 0x00000000UL 02871 #define USART_IEN_RXUF_DEFAULT (_USART_IEN_RXUF_DEFAULT << 5) 02872 #define USART_IEN_TXOF (0x1UL << 6) 02873 #define _USART_IEN_TXOF_SHIFT 6 02874 #define _USART_IEN_TXOF_MASK 0x40UL 02875 #define _USART_IEN_TXOF_DEFAULT 0x00000000UL 02876 #define USART_IEN_TXOF_DEFAULT (_USART_IEN_TXOF_DEFAULT << 6) 02877 #define USART_IEN_TXUF (0x1UL << 7) 02878 #define _USART_IEN_TXUF_SHIFT 7 02879 #define _USART_IEN_TXUF_MASK 0x80UL 02880 #define _USART_IEN_TXUF_DEFAULT 0x00000000UL 02881 #define USART_IEN_TXUF_DEFAULT (_USART_IEN_TXUF_DEFAULT << 7) 02882 #define USART_IEN_PERR (0x1UL << 8) 02883 #define _USART_IEN_PERR_SHIFT 8 02884 #define _USART_IEN_PERR_MASK 0x100UL 02885 #define _USART_IEN_PERR_DEFAULT 0x00000000UL 02886 #define USART_IEN_PERR_DEFAULT (_USART_IEN_PERR_DEFAULT << 8) 02887 #define USART_IEN_FERR (0x1UL << 9) 02888 #define _USART_IEN_FERR_SHIFT 9 02889 #define _USART_IEN_FERR_MASK 0x200UL 02890 #define _USART_IEN_FERR_DEFAULT 0x00000000UL 02891 #define USART_IEN_FERR_DEFAULT (_USART_IEN_FERR_DEFAULT << 9) 02892 #define USART_IEN_MPAF (0x1UL << 10) 02893 #define _USART_IEN_MPAF_SHIFT 10 02894 #define _USART_IEN_MPAF_MASK 0x400UL 02895 #define _USART_IEN_MPAF_DEFAULT 0x00000000UL 02896 #define USART_IEN_MPAF_DEFAULT (_USART_IEN_MPAF_DEFAULT << 10) 02897 #define USART_IEN_SSM (0x1UL << 11) 02898 #define _USART_IEN_SSM_SHIFT 11 02899 #define _USART_IEN_SSM_MASK 0x800UL 02900 #define _USART_IEN_SSM_DEFAULT 0x00000000UL 02901 #define USART_IEN_SSM_DEFAULT (_USART_IEN_SSM_DEFAULT << 11) 02902 #define USART_IEN_CCF (0x1UL << 12) 02903 #define _USART_IEN_CCF_SHIFT 12 02904 #define _USART_IEN_CCF_MASK 0x1000UL 02905 #define _USART_IEN_CCF_DEFAULT 0x00000000UL 02906 #define USART_IEN_CCF_DEFAULT (_USART_IEN_CCF_DEFAULT << 12) 02908 /* Bit fields for USART IRCTRL */ 02909 #define _USART_IRCTRL_RESETVALUE 0x00000000UL 02910 #define _USART_IRCTRL_MASK 0x000000FFUL 02911 #define USART_IRCTRL_IREN (0x1UL << 0) 02912 #define _USART_IRCTRL_IREN_SHIFT 0 02913 #define _USART_IRCTRL_IREN_MASK 0x1UL 02914 #define _USART_IRCTRL_IREN_DEFAULT 0x00000000UL 02915 #define USART_IRCTRL_IREN_DEFAULT (_USART_IRCTRL_IREN_DEFAULT << 0) 02916 #define _USART_IRCTRL_IRPW_SHIFT 1 02917 #define _USART_IRCTRL_IRPW_MASK 0x6UL 02918 #define _USART_IRCTRL_IRPW_DEFAULT 0x00000000UL 02919 #define _USART_IRCTRL_IRPW_ONE 0x00000000UL 02920 #define _USART_IRCTRL_IRPW_TWO 0x00000001UL 02921 #define _USART_IRCTRL_IRPW_THREE 0x00000002UL 02922 #define _USART_IRCTRL_IRPW_FOUR 0x00000003UL 02923 #define USART_IRCTRL_IRPW_DEFAULT (_USART_IRCTRL_IRPW_DEFAULT << 1) 02924 #define USART_IRCTRL_IRPW_ONE (_USART_IRCTRL_IRPW_ONE << 1) 02925 #define USART_IRCTRL_IRPW_TWO (_USART_IRCTRL_IRPW_TWO << 1) 02926 #define USART_IRCTRL_IRPW_THREE (_USART_IRCTRL_IRPW_THREE << 1) 02927 #define USART_IRCTRL_IRPW_FOUR (_USART_IRCTRL_IRPW_FOUR << 1) 02928 #define USART_IRCTRL_IRFILT (0x1UL << 3) 02929 #define _USART_IRCTRL_IRFILT_SHIFT 3 02930 #define _USART_IRCTRL_IRFILT_MASK 0x8UL 02931 #define _USART_IRCTRL_IRFILT_DEFAULT 0x00000000UL 02932 #define USART_IRCTRL_IRFILT_DEFAULT (_USART_IRCTRL_IRFILT_DEFAULT << 3) 02933 #define _USART_IRCTRL_IRPRSSEL_SHIFT 4 02934 #define _USART_IRCTRL_IRPRSSEL_MASK 0x70UL 02935 #define _USART_IRCTRL_IRPRSSEL_DEFAULT 0x00000000UL 02936 #define _USART_IRCTRL_IRPRSSEL_PRSCH0 0x00000000UL 02937 #define _USART_IRCTRL_IRPRSSEL_PRSCH1 0x00000001UL 02938 #define _USART_IRCTRL_IRPRSSEL_PRSCH2 0x00000002UL 02939 #define _USART_IRCTRL_IRPRSSEL_PRSCH3 0x00000003UL 02940 #define _USART_IRCTRL_IRPRSSEL_PRSCH4 0x00000004UL 02941 #define _USART_IRCTRL_IRPRSSEL_PRSCH5 0x00000005UL 02942 #define _USART_IRCTRL_IRPRSSEL_PRSCH6 0x00000006UL 02943 #define _USART_IRCTRL_IRPRSSEL_PRSCH7 0x00000007UL 02944 #define USART_IRCTRL_IRPRSSEL_DEFAULT (_USART_IRCTRL_IRPRSSEL_DEFAULT << 4) 02945 #define USART_IRCTRL_IRPRSSEL_PRSCH0 (_USART_IRCTRL_IRPRSSEL_PRSCH0 << 4) 02946 #define USART_IRCTRL_IRPRSSEL_PRSCH1 (_USART_IRCTRL_IRPRSSEL_PRSCH1 << 4) 02947 #define USART_IRCTRL_IRPRSSEL_PRSCH2 (_USART_IRCTRL_IRPRSSEL_PRSCH2 << 4) 02948 #define USART_IRCTRL_IRPRSSEL_PRSCH3 (_USART_IRCTRL_IRPRSSEL_PRSCH3 << 4) 02949 #define USART_IRCTRL_IRPRSSEL_PRSCH4 (_USART_IRCTRL_IRPRSSEL_PRSCH4 << 4) 02950 #define USART_IRCTRL_IRPRSSEL_PRSCH5 (_USART_IRCTRL_IRPRSSEL_PRSCH5 << 4) 02951 #define USART_IRCTRL_IRPRSSEL_PRSCH6 (_USART_IRCTRL_IRPRSSEL_PRSCH6 << 4) 02952 #define USART_IRCTRL_IRPRSSEL_PRSCH7 (_USART_IRCTRL_IRPRSSEL_PRSCH7 << 4) 02953 #define USART_IRCTRL_IRPRSEN (0x1UL << 7) 02954 #define _USART_IRCTRL_IRPRSEN_SHIFT 7 02955 #define _USART_IRCTRL_IRPRSEN_MASK 0x80UL 02956 #define _USART_IRCTRL_IRPRSEN_DEFAULT 0x00000000UL 02957 #define USART_IRCTRL_IRPRSEN_DEFAULT (_USART_IRCTRL_IRPRSEN_DEFAULT << 7) 02959 /* Bit fields for USART ROUTE */ 02960 #define _USART_ROUTE_RESETVALUE 0x00000000UL 02961 #define _USART_ROUTE_MASK 0x0000030FUL 02962 #define USART_ROUTE_RXPEN (0x1UL << 0) 02963 #define _USART_ROUTE_RXPEN_SHIFT 0 02964 #define _USART_ROUTE_RXPEN_MASK 0x1UL 02965 #define _USART_ROUTE_RXPEN_DEFAULT 0x00000000UL 02966 #define USART_ROUTE_RXPEN_DEFAULT (_USART_ROUTE_RXPEN_DEFAULT << 0) 02967 #define USART_ROUTE_TXPEN (0x1UL << 1) 02968 #define _USART_ROUTE_TXPEN_SHIFT 1 02969 #define _USART_ROUTE_TXPEN_MASK 0x2UL 02970 #define _USART_ROUTE_TXPEN_DEFAULT 0x00000000UL 02971 #define USART_ROUTE_TXPEN_DEFAULT (_USART_ROUTE_TXPEN_DEFAULT << 1) 02972 #define USART_ROUTE_CSPEN (0x1UL << 2) 02973 #define _USART_ROUTE_CSPEN_SHIFT 2 02974 #define _USART_ROUTE_CSPEN_MASK 0x4UL 02975 #define _USART_ROUTE_CSPEN_DEFAULT 0x00000000UL 02976 #define USART_ROUTE_CSPEN_DEFAULT (_USART_ROUTE_CSPEN_DEFAULT << 2) 02977 #define USART_ROUTE_CLKPEN (0x1UL << 3) 02978 #define _USART_ROUTE_CLKPEN_SHIFT 3 02979 #define _USART_ROUTE_CLKPEN_MASK 0x8UL 02980 #define _USART_ROUTE_CLKPEN_DEFAULT 0x00000000UL 02981 #define USART_ROUTE_CLKPEN_DEFAULT (_USART_ROUTE_CLKPEN_DEFAULT << 3) 02982 #define _USART_ROUTE_LOCATION_SHIFT 8 02983 #define _USART_ROUTE_LOCATION_MASK 0x300UL 02984 #define _USART_ROUTE_LOCATION_DEFAULT 0x00000000UL 02985 #define _USART_ROUTE_LOCATION_LOC0 0x00000000UL 02986 #define _USART_ROUTE_LOCATION_LOC1 0x00000001UL 02987 #define _USART_ROUTE_LOCATION_LOC2 0x00000002UL 02988 #define _USART_ROUTE_LOCATION_LOC3 0x00000003UL 02989 #define USART_ROUTE_LOCATION_DEFAULT (_USART_ROUTE_LOCATION_DEFAULT << 8) 02990 #define USART_ROUTE_LOCATION_LOC0 (_USART_ROUTE_LOCATION_LOC0 << 8) 02991 #define USART_ROUTE_LOCATION_LOC1 (_USART_ROUTE_LOCATION_LOC1 << 8) 02992 #define USART_ROUTE_LOCATION_LOC2 (_USART_ROUTE_LOCATION_LOC2 << 8) 02993 #define USART_ROUTE_LOCATION_LOC3 (_USART_ROUTE_LOCATION_LOC3 << 8) 02999 /**************************************************************************/ 03004 /* Bit fields for UART CTRL */ 03005 #define _UART_CTRL_RESETVALUE 0x00000000UL 03006 #define _UART_CTRL_MASK 0x1DFFFF7FUL 03007 #define UART_CTRL_SYNC (0x1UL << 0) 03008 #define _UART_CTRL_SYNC_SHIFT 0 03009 #define _UART_CTRL_SYNC_MASK 0x1UL 03010 #define _UART_CTRL_SYNC_DEFAULT 0x00000000UL 03011 #define UART_CTRL_SYNC_DEFAULT (_UART_CTRL_SYNC_DEFAULT << 0) 03012 #define UART_CTRL_LOOPBK (0x1UL << 1) 03013 #define _UART_CTRL_LOOPBK_SHIFT 1 03014 #define _UART_CTRL_LOOPBK_MASK 0x2UL 03015 #define _UART_CTRL_LOOPBK_DEFAULT 0x00000000UL 03016 #define UART_CTRL_LOOPBK_DEFAULT (_UART_CTRL_LOOPBK_DEFAULT << 1) 03017 #define UART_CTRL_CCEN (0x1UL << 2) 03018 #define _UART_CTRL_CCEN_SHIFT 2 03019 #define _UART_CTRL_CCEN_MASK 0x4UL 03020 #define _UART_CTRL_CCEN_DEFAULT 0x00000000UL 03021 #define UART_CTRL_CCEN_DEFAULT (_UART_CTRL_CCEN_DEFAULT << 2) 03022 #define UART_CTRL_MPM (0x1UL << 3) 03023 #define _UART_CTRL_MPM_SHIFT 3 03024 #define _UART_CTRL_MPM_MASK 0x8UL 03025 #define _UART_CTRL_MPM_DEFAULT 0x00000000UL 03026 #define UART_CTRL_MPM_DEFAULT (_UART_CTRL_MPM_DEFAULT << 3) 03027 #define UART_CTRL_MPAB (0x1UL << 4) 03028 #define _UART_CTRL_MPAB_SHIFT 4 03029 #define _UART_CTRL_MPAB_MASK 0x10UL 03030 #define _UART_CTRL_MPAB_DEFAULT 0x00000000UL 03031 #define UART_CTRL_MPAB_DEFAULT (_UART_CTRL_MPAB_DEFAULT << 4) 03032 #define _UART_CTRL_OVS_SHIFT 5 03033 #define _UART_CTRL_OVS_MASK 0x60UL 03034 #define _UART_CTRL_OVS_DEFAULT 0x00000000UL 03035 #define _UART_CTRL_OVS_X16 0x00000000UL 03036 #define _UART_CTRL_OVS_X8 0x00000001UL 03037 #define _UART_CTRL_OVS_X6 0x00000002UL 03038 #define _UART_CTRL_OVS_X4 0x00000003UL 03039 #define UART_CTRL_OVS_DEFAULT (_UART_CTRL_OVS_DEFAULT << 5) 03040 #define UART_CTRL_OVS_X16 (_UART_CTRL_OVS_X16 << 5) 03041 #define UART_CTRL_OVS_X8 (_UART_CTRL_OVS_X8 << 5) 03042 #define UART_CTRL_OVS_X6 (_UART_CTRL_OVS_X6 << 5) 03043 #define UART_CTRL_OVS_X4 (_UART_CTRL_OVS_X4 << 5) 03044 #define UART_CTRL_CLKPOL (0x1UL << 8) 03045 #define _UART_CTRL_CLKPOL_SHIFT 8 03046 #define _UART_CTRL_CLKPOL_MASK 0x100UL 03047 #define _UART_CTRL_CLKPOL_DEFAULT 0x00000000UL 03048 #define _UART_CTRL_CLKPOL_IDLELOW 0x00000000UL 03049 #define _UART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL 03050 #define UART_CTRL_CLKPOL_DEFAULT (_UART_CTRL_CLKPOL_DEFAULT << 8) 03051 #define UART_CTRL_CLKPOL_IDLELOW (_UART_CTRL_CLKPOL_IDLELOW << 8) 03052 #define UART_CTRL_CLKPOL_IDLEHIGH (_UART_CTRL_CLKPOL_IDLEHIGH << 8) 03053 #define UART_CTRL_CLKPHA (0x1UL << 9) 03054 #define _UART_CTRL_CLKPHA_SHIFT 9 03055 #define _UART_CTRL_CLKPHA_MASK 0x200UL 03056 #define _UART_CTRL_CLKPHA_DEFAULT 0x00000000UL 03057 #define _UART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL 03058 #define _UART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL 03059 #define UART_CTRL_CLKPHA_DEFAULT (_UART_CTRL_CLKPHA_DEFAULT << 9) 03060 #define UART_CTRL_CLKPHA_SAMPLELEADING (_UART_CTRL_CLKPHA_SAMPLELEADING << 9) 03061 #define UART_CTRL_CLKPHA_SAMPLETRAILING (_UART_CTRL_CLKPHA_SAMPLETRAILING << 9) 03062 #define UART_CTRL_MSBF (0x1UL << 10) 03063 #define _UART_CTRL_MSBF_SHIFT 10 03064 #define _UART_CTRL_MSBF_MASK 0x400UL 03065 #define _UART_CTRL_MSBF_DEFAULT 0x00000000UL 03066 #define UART_CTRL_MSBF_DEFAULT (_UART_CTRL_MSBF_DEFAULT << 10) 03067 #define UART_CTRL_CSMA (0x1UL << 11) 03068 #define _UART_CTRL_CSMA_SHIFT 11 03069 #define _UART_CTRL_CSMA_MASK 0x800UL 03070 #define _UART_CTRL_CSMA_DEFAULT 0x00000000UL 03071 #define _UART_CTRL_CSMA_NOACTION 0x00000000UL 03072 #define _UART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL 03073 #define UART_CTRL_CSMA_DEFAULT (_UART_CTRL_CSMA_DEFAULT << 11) 03074 #define UART_CTRL_CSMA_NOACTION (_UART_CTRL_CSMA_NOACTION << 11) 03075 #define UART_CTRL_CSMA_GOTOSLAVEMODE (_UART_CTRL_CSMA_GOTOSLAVEMODE << 11) 03076 #define UART_CTRL_TXBIL (0x1UL << 12) 03077 #define _UART_CTRL_TXBIL_SHIFT 12 03078 #define _UART_CTRL_TXBIL_MASK 0x1000UL 03079 #define _UART_CTRL_TXBIL_DEFAULT 0x00000000UL 03080 #define _UART_CTRL_TXBIL_EMPTY 0x00000000UL 03081 #define _UART_CTRL_TXBIL_HALFFULL 0x00000001UL 03082 #define UART_CTRL_TXBIL_DEFAULT (_UART_CTRL_TXBIL_DEFAULT << 12) 03083 #define UART_CTRL_TXBIL_EMPTY (_UART_CTRL_TXBIL_EMPTY << 12) 03084 #define UART_CTRL_TXBIL_HALFFULL (_UART_CTRL_TXBIL_HALFFULL << 12) 03085 #define UART_CTRL_RXINV (0x1UL << 13) 03086 #define _UART_CTRL_RXINV_SHIFT 13 03087 #define _UART_CTRL_RXINV_MASK 0x2000UL 03088 #define _UART_CTRL_RXINV_DEFAULT 0x00000000UL 03089 #define UART_CTRL_RXINV_DEFAULT (_UART_CTRL_RXINV_DEFAULT << 13) 03090 #define UART_CTRL_TXINV (0x1UL << 14) 03091 #define _UART_CTRL_TXINV_SHIFT 14 03092 #define _UART_CTRL_TXINV_MASK 0x4000UL 03093 #define _UART_CTRL_TXINV_DEFAULT 0x00000000UL 03094 #define UART_CTRL_TXINV_DEFAULT (_UART_CTRL_TXINV_DEFAULT << 14) 03095 #define UART_CTRL_CSINV (0x1UL << 15) 03096 #define _UART_CTRL_CSINV_SHIFT 15 03097 #define _UART_CTRL_CSINV_MASK 0x8000UL 03098 #define _UART_CTRL_CSINV_DEFAULT 0x00000000UL 03099 #define UART_CTRL_CSINV_DEFAULT (_UART_CTRL_CSINV_DEFAULT << 15) 03100 #define UART_CTRL_AUTOCS (0x1UL << 16) 03101 #define _UART_CTRL_AUTOCS_SHIFT 16 03102 #define _UART_CTRL_AUTOCS_MASK 0x10000UL 03103 #define _UART_CTRL_AUTOCS_DEFAULT 0x00000000UL 03104 #define UART_CTRL_AUTOCS_DEFAULT (_UART_CTRL_AUTOCS_DEFAULT << 16) 03105 #define UART_CTRL_AUTOTRI (0x1UL << 17) 03106 #define _UART_CTRL_AUTOTRI_SHIFT 17 03107 #define _UART_CTRL_AUTOTRI_MASK 0x20000UL 03108 #define _UART_CTRL_AUTOTRI_DEFAULT 0x00000000UL 03109 #define UART_CTRL_AUTOTRI_DEFAULT (_UART_CTRL_AUTOTRI_DEFAULT << 17) 03110 #define UART_CTRL_SCMODE (0x1UL << 18) 03111 #define _UART_CTRL_SCMODE_SHIFT 18 03112 #define _UART_CTRL_SCMODE_MASK 0x40000UL 03113 #define _UART_CTRL_SCMODE_DEFAULT 0x00000000UL 03114 #define UART_CTRL_SCMODE_DEFAULT (_UART_CTRL_SCMODE_DEFAULT << 18) 03115 #define UART_CTRL_SCRETRANS (0x1UL << 19) 03116 #define _UART_CTRL_SCRETRANS_SHIFT 19 03117 #define _UART_CTRL_SCRETRANS_MASK 0x80000UL 03118 #define _UART_CTRL_SCRETRANS_DEFAULT 0x00000000UL 03119 #define UART_CTRL_SCRETRANS_DEFAULT (_UART_CTRL_SCRETRANS_DEFAULT << 19) 03120 #define UART_CTRL_SKIPPERRF (0x1UL << 20) 03121 #define _UART_CTRL_SKIPPERRF_SHIFT 20 03122 #define _UART_CTRL_SKIPPERRF_MASK 0x100000UL 03123 #define _UART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL 03124 #define UART_CTRL_SKIPPERRF_DEFAULT (_UART_CTRL_SKIPPERRF_DEFAULT << 20) 03125 #define UART_CTRL_BIT8DV (0x1UL << 21) 03126 #define _UART_CTRL_BIT8DV_SHIFT 21 03127 #define _UART_CTRL_BIT8DV_MASK 0x200000UL 03128 #define _UART_CTRL_BIT8DV_DEFAULT 0x00000000UL 03129 #define UART_CTRL_BIT8DV_DEFAULT (_UART_CTRL_BIT8DV_DEFAULT << 21) 03130 #define UART_CTRL_ERRSDMA (0x1UL << 22) 03131 #define _UART_CTRL_ERRSDMA_SHIFT 22 03132 #define _UART_CTRL_ERRSDMA_MASK 0x400000UL 03133 #define _UART_CTRL_ERRSDMA_DEFAULT 0x00000000UL 03134 #define UART_CTRL_ERRSDMA_DEFAULT (_UART_CTRL_ERRSDMA_DEFAULT << 22) 03135 #define UART_CTRL_ERRSRX (0x1UL << 23) 03136 #define _UART_CTRL_ERRSRX_SHIFT 23 03137 #define _UART_CTRL_ERRSRX_MASK 0x800000UL 03138 #define _UART_CTRL_ERRSRX_DEFAULT 0x00000000UL 03139 #define UART_CTRL_ERRSRX_DEFAULT (_UART_CTRL_ERRSRX_DEFAULT << 23) 03140 #define UART_CTRL_ERRSTX (0x1UL << 24) 03141 #define _UART_CTRL_ERRSTX_SHIFT 24 03142 #define _UART_CTRL_ERRSTX_MASK 0x1000000UL 03143 #define _UART_CTRL_ERRSTX_DEFAULT 0x00000000UL 03144 #define UART_CTRL_ERRSTX_DEFAULT (_UART_CTRL_ERRSTX_DEFAULT << 24) 03145 #define _UART_CTRL_TXDELAY_SHIFT 26 03146 #define _UART_CTRL_TXDELAY_MASK 0xC000000UL 03147 #define _UART_CTRL_TXDELAY_DEFAULT 0x00000000UL 03148 #define _UART_CTRL_TXDELAY_NONE 0x00000000UL 03149 #define _UART_CTRL_TXDELAY_SINGLE 0x00000001UL 03150 #define _UART_CTRL_TXDELAY_DOUBLE 0x00000002UL 03151 #define _UART_CTRL_TXDELAY_TRIPLE 0x00000003UL 03152 #define UART_CTRL_TXDELAY_DEFAULT (_UART_CTRL_TXDELAY_DEFAULT << 26) 03153 #define UART_CTRL_TXDELAY_NONE (_UART_CTRL_TXDELAY_NONE << 26) 03154 #define UART_CTRL_TXDELAY_SINGLE (_UART_CTRL_TXDELAY_SINGLE << 26) 03155 #define UART_CTRL_TXDELAY_DOUBLE (_UART_CTRL_TXDELAY_DOUBLE << 26) 03156 #define UART_CTRL_TXDELAY_TRIPLE (_UART_CTRL_TXDELAY_TRIPLE << 26) 03157 #define UART_CTRL_BYTESWAP (0x1UL << 28) 03158 #define _UART_CTRL_BYTESWAP_SHIFT 28 03159 #define _UART_CTRL_BYTESWAP_MASK 0x10000000UL 03160 #define _UART_CTRL_BYTESWAP_DEFAULT 0x00000000UL 03161 #define UART_CTRL_BYTESWAP_DEFAULT (_UART_CTRL_BYTESWAP_DEFAULT << 28) 03163 /* Bit fields for UART FRAME */ 03164 #define _UART_FRAME_RESETVALUE 0x00001005UL 03165 #define _UART_FRAME_MASK 0x0000330FUL 03166 #define _UART_FRAME_DATABITS_SHIFT 0 03167 #define _UART_FRAME_DATABITS_MASK 0xFUL 03168 #define _UART_FRAME_DATABITS_FOUR 0x00000001UL 03169 #define _UART_FRAME_DATABITS_FIVE 0x00000002UL 03170 #define _UART_FRAME_DATABITS_SIX 0x00000003UL 03171 #define _UART_FRAME_DATABITS_SEVEN 0x00000004UL 03172 #define _UART_FRAME_DATABITS_DEFAULT 0x00000005UL 03173 #define _UART_FRAME_DATABITS_EIGHT 0x00000005UL 03174 #define _UART_FRAME_DATABITS_NINE 0x00000006UL 03175 #define _UART_FRAME_DATABITS_TEN 0x00000007UL 03176 #define _UART_FRAME_DATABITS_ELEVEN 0x00000008UL 03177 #define _UART_FRAME_DATABITS_TWELVE 0x00000009UL 03178 #define _UART_FRAME_DATABITS_THIRTEEN 0x0000000AUL 03179 #define _UART_FRAME_DATABITS_FOURTEEN 0x0000000BUL 03180 #define _UART_FRAME_DATABITS_FIFTEEN 0x0000000CUL 03181 #define _UART_FRAME_DATABITS_SIXTEEN 0x0000000DUL 03182 #define UART_FRAME_DATABITS_FOUR (_UART_FRAME_DATABITS_FOUR << 0) 03183 #define UART_FRAME_DATABITS_FIVE (_UART_FRAME_DATABITS_FIVE << 0) 03184 #define UART_FRAME_DATABITS_SIX (_UART_FRAME_DATABITS_SIX << 0) 03185 #define UART_FRAME_DATABITS_SEVEN (_UART_FRAME_DATABITS_SEVEN << 0) 03186 #define UART_FRAME_DATABITS_DEFAULT (_UART_FRAME_DATABITS_DEFAULT << 0) 03187 #define UART_FRAME_DATABITS_EIGHT (_UART_FRAME_DATABITS_EIGHT << 0) 03188 #define UART_FRAME_DATABITS_NINE (_UART_FRAME_DATABITS_NINE << 0) 03189 #define UART_FRAME_DATABITS_TEN (_UART_FRAME_DATABITS_TEN << 0) 03190 #define UART_FRAME_DATABITS_ELEVEN (_UART_FRAME_DATABITS_ELEVEN << 0) 03191 #define UART_FRAME_DATABITS_TWELVE (_UART_FRAME_DATABITS_TWELVE << 0) 03192 #define UART_FRAME_DATABITS_THIRTEEN (_UART_FRAME_DATABITS_THIRTEEN << 0) 03193 #define UART_FRAME_DATABITS_FOURTEEN (_UART_FRAME_DATABITS_FOURTEEN << 0) 03194 #define UART_FRAME_DATABITS_FIFTEEN (_UART_FRAME_DATABITS_FIFTEEN << 0) 03195 #define UART_FRAME_DATABITS_SIXTEEN (_UART_FRAME_DATABITS_SIXTEEN << 0) 03196 #define _UART_FRAME_PARITY_SHIFT 8 03197 #define _UART_FRAME_PARITY_MASK 0x300UL 03198 #define _UART_FRAME_PARITY_DEFAULT 0x00000000UL 03199 #define _UART_FRAME_PARITY_NONE 0x00000000UL 03200 #define _UART_FRAME_PARITY_EVEN 0x00000002UL 03201 #define _UART_FRAME_PARITY_ODD 0x00000003UL 03202 #define UART_FRAME_PARITY_DEFAULT (_UART_FRAME_PARITY_DEFAULT << 8) 03203 #define UART_FRAME_PARITY_NONE (_UART_FRAME_PARITY_NONE << 8) 03204 #define UART_FRAME_PARITY_EVEN (_UART_FRAME_PARITY_EVEN << 8) 03205 #define UART_FRAME_PARITY_ODD (_UART_FRAME_PARITY_ODD << 8) 03206 #define _UART_FRAME_STOPBITS_SHIFT 12 03207 #define _UART_FRAME_STOPBITS_MASK 0x3000UL 03208 #define _UART_FRAME_STOPBITS_HALF 0x00000000UL 03209 #define _UART_FRAME_STOPBITS_DEFAULT 0x00000001UL 03210 #define _UART_FRAME_STOPBITS_ONE 0x00000001UL 03211 #define _UART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL 03212 #define _UART_FRAME_STOPBITS_TWO 0x00000003UL 03213 #define UART_FRAME_STOPBITS_HALF (_UART_FRAME_STOPBITS_HALF << 12) 03214 #define UART_FRAME_STOPBITS_DEFAULT (_UART_FRAME_STOPBITS_DEFAULT << 12) 03215 #define UART_FRAME_STOPBITS_ONE (_UART_FRAME_STOPBITS_ONE << 12) 03216 #define UART_FRAME_STOPBITS_ONEANDAHALF (_UART_FRAME_STOPBITS_ONEANDAHALF << 12) 03217 #define UART_FRAME_STOPBITS_TWO (_UART_FRAME_STOPBITS_TWO << 12) 03219 /* Bit fields for UART TRIGCTRL */ 03220 #define _UART_TRIGCTRL_RESETVALUE 0x00000000UL 03221 #define _UART_TRIGCTRL_MASK 0x00000037UL 03222 #define _UART_TRIGCTRL_TSEL_SHIFT 0 03223 #define _UART_TRIGCTRL_TSEL_MASK 0x7UL 03224 #define _UART_TRIGCTRL_TSEL_DEFAULT 0x00000000UL 03225 #define _UART_TRIGCTRL_TSEL_PRSCH0 0x00000000UL 03226 #define _UART_TRIGCTRL_TSEL_PRSCH1 0x00000001UL 03227 #define _UART_TRIGCTRL_TSEL_PRSCH2 0x00000002UL 03228 #define _UART_TRIGCTRL_TSEL_PRSCH3 0x00000003UL 03229 #define _UART_TRIGCTRL_TSEL_PRSCH4 0x00000004UL 03230 #define _UART_TRIGCTRL_TSEL_PRSCH5 0x00000005UL 03231 #define _UART_TRIGCTRL_TSEL_PRSCH6 0x00000006UL 03232 #define _UART_TRIGCTRL_TSEL_PRSCH7 0x00000007UL 03233 #define UART_TRIGCTRL_TSEL_DEFAULT (_UART_TRIGCTRL_TSEL_DEFAULT << 0) 03234 #define UART_TRIGCTRL_TSEL_PRSCH0 (_UART_TRIGCTRL_TSEL_PRSCH0 << 0) 03235 #define UART_TRIGCTRL_TSEL_PRSCH1 (_UART_TRIGCTRL_TSEL_PRSCH1 << 0) 03236 #define UART_TRIGCTRL_TSEL_PRSCH2 (_UART_TRIGCTRL_TSEL_PRSCH2 << 0) 03237 #define UART_TRIGCTRL_TSEL_PRSCH3 (_UART_TRIGCTRL_TSEL_PRSCH3 << 0) 03238 #define UART_TRIGCTRL_TSEL_PRSCH4 (_UART_TRIGCTRL_TSEL_PRSCH4 << 0) 03239 #define UART_TRIGCTRL_TSEL_PRSCH5 (_UART_TRIGCTRL_TSEL_PRSCH5 << 0) 03240 #define UART_TRIGCTRL_TSEL_PRSCH6 (_UART_TRIGCTRL_TSEL_PRSCH6 << 0) 03241 #define UART_TRIGCTRL_TSEL_PRSCH7 (_UART_TRIGCTRL_TSEL_PRSCH7 << 0) 03242 #define UART_TRIGCTRL_RXTEN (0x1UL << 4) 03243 #define _UART_TRIGCTRL_RXTEN_SHIFT 4 03244 #define _UART_TRIGCTRL_RXTEN_MASK 0x10UL 03245 #define _UART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL 03246 #define UART_TRIGCTRL_RXTEN_DEFAULT (_UART_TRIGCTRL_RXTEN_DEFAULT << 4) 03247 #define UART_TRIGCTRL_TXTEN (0x1UL << 5) 03248 #define _UART_TRIGCTRL_TXTEN_SHIFT 5 03249 #define _UART_TRIGCTRL_TXTEN_MASK 0x20UL 03250 #define _UART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL 03251 #define UART_TRIGCTRL_TXTEN_DEFAULT (_UART_TRIGCTRL_TXTEN_DEFAULT << 5) 03253 /* Bit fields for UART CMD */ 03254 #define _UART_CMD_RESETVALUE 0x00000000UL 03255 #define _UART_CMD_MASK 0x00000FFFUL 03256 #define UART_CMD_RXEN (0x1UL << 0) 03257 #define _UART_CMD_RXEN_SHIFT 0 03258 #define _UART_CMD_RXEN_MASK 0x1UL 03259 #define _UART_CMD_RXEN_DEFAULT 0x00000000UL 03260 #define UART_CMD_RXEN_DEFAULT (_UART_CMD_RXEN_DEFAULT << 0) 03261 #define UART_CMD_RXDIS (0x1UL << 1) 03262 #define _UART_CMD_RXDIS_SHIFT 1 03263 #define _UART_CMD_RXDIS_MASK 0x2UL 03264 #define _UART_CMD_RXDIS_DEFAULT 0x00000000UL 03265 #define UART_CMD_RXDIS_DEFAULT (_UART_CMD_RXDIS_DEFAULT << 1) 03266 #define UART_CMD_TXEN (0x1UL << 2) 03267 #define _UART_CMD_TXEN_SHIFT 2 03268 #define _UART_CMD_TXEN_MASK 0x4UL 03269 #define _UART_CMD_TXEN_DEFAULT 0x00000000UL 03270 #define UART_CMD_TXEN_DEFAULT (_UART_CMD_TXEN_DEFAULT << 2) 03271 #define UART_CMD_TXDIS (0x1UL << 3) 03272 #define _UART_CMD_TXDIS_SHIFT 3 03273 #define _UART_CMD_TXDIS_MASK 0x8UL 03274 #define _UART_CMD_TXDIS_DEFAULT 0x00000000UL 03275 #define UART_CMD_TXDIS_DEFAULT (_UART_CMD_TXDIS_DEFAULT << 3) 03276 #define UART_CMD_MASTEREN (0x1UL << 4) 03277 #define _UART_CMD_MASTEREN_SHIFT 4 03278 #define _UART_CMD_MASTEREN_MASK 0x10UL 03279 #define _UART_CMD_MASTEREN_DEFAULT 0x00000000UL 03280 #define UART_CMD_MASTEREN_DEFAULT (_UART_CMD_MASTEREN_DEFAULT << 4) 03281 #define UART_CMD_MASTERDIS (0x1UL << 5) 03282 #define _UART_CMD_MASTERDIS_SHIFT 5 03283 #define _UART_CMD_MASTERDIS_MASK 0x20UL 03284 #define _UART_CMD_MASTERDIS_DEFAULT 0x00000000UL 03285 #define UART_CMD_MASTERDIS_DEFAULT (_UART_CMD_MASTERDIS_DEFAULT << 5) 03286 #define UART_CMD_RXBLOCKEN (0x1UL << 6) 03287 #define _UART_CMD_RXBLOCKEN_SHIFT 6 03288 #define _UART_CMD_RXBLOCKEN_MASK 0x40UL 03289 #define _UART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL 03290 #define UART_CMD_RXBLOCKEN_DEFAULT (_UART_CMD_RXBLOCKEN_DEFAULT << 6) 03291 #define UART_CMD_RXBLOCKDIS (0x1UL << 7) 03292 #define _UART_CMD_RXBLOCKDIS_SHIFT 7 03293 #define _UART_CMD_RXBLOCKDIS_MASK 0x80UL 03294 #define _UART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL 03295 #define UART_CMD_RXBLOCKDIS_DEFAULT (_UART_CMD_RXBLOCKDIS_DEFAULT << 7) 03296 #define UART_CMD_TXTRIEN (0x1UL << 8) 03297 #define _UART_CMD_TXTRIEN_SHIFT 8 03298 #define _UART_CMD_TXTRIEN_MASK 0x100UL 03299 #define _UART_CMD_TXTRIEN_DEFAULT 0x00000000UL 03300 #define UART_CMD_TXTRIEN_DEFAULT (_UART_CMD_TXTRIEN_DEFAULT << 8) 03301 #define UART_CMD_TXTRIDIS (0x1UL << 9) 03302 #define _UART_CMD_TXTRIDIS_SHIFT 9 03303 #define _UART_CMD_TXTRIDIS_MASK 0x200UL 03304 #define _UART_CMD_TXTRIDIS_DEFAULT 0x00000000UL 03305 #define UART_CMD_TXTRIDIS_DEFAULT (_UART_CMD_TXTRIDIS_DEFAULT << 9) 03306 #define UART_CMD_CLEARTX (0x1UL << 10) 03307 #define _UART_CMD_CLEARTX_SHIFT 10 03308 #define _UART_CMD_CLEARTX_MASK 0x400UL 03309 #define _UART_CMD_CLEARTX_DEFAULT 0x00000000UL 03310 #define UART_CMD_CLEARTX_DEFAULT (_UART_CMD_CLEARTX_DEFAULT << 10) 03311 #define UART_CMD_CLEARRX (0x1UL << 11) 03312 #define _UART_CMD_CLEARRX_SHIFT 11 03313 #define _UART_CMD_CLEARRX_MASK 0x800UL 03314 #define _UART_CMD_CLEARRX_DEFAULT 0x00000000UL 03315 #define UART_CMD_CLEARRX_DEFAULT (_UART_CMD_CLEARRX_DEFAULT << 11) 03317 /* Bit fields for UART STATUS */ 03318 #define _UART_STATUS_RESETVALUE 0x00000040UL 03319 #define _UART_STATUS_MASK 0x000001FFUL 03320 #define UART_STATUS_RXENS (0x1UL << 0) 03321 #define _UART_STATUS_RXENS_SHIFT 0 03322 #define _UART_STATUS_RXENS_MASK 0x1UL 03323 #define _UART_STATUS_RXENS_DEFAULT 0x00000000UL 03324 #define UART_STATUS_RXENS_DEFAULT (_UART_STATUS_RXENS_DEFAULT << 0) 03325 #define UART_STATUS_TXENS (0x1UL << 1) 03326 #define _UART_STATUS_TXENS_SHIFT 1 03327 #define _UART_STATUS_TXENS_MASK 0x2UL 03328 #define _UART_STATUS_TXENS_DEFAULT 0x00000000UL 03329 #define UART_STATUS_TXENS_DEFAULT (_UART_STATUS_TXENS_DEFAULT << 1) 03330 #define UART_STATUS_MASTER (0x1UL << 2) 03331 #define _UART_STATUS_MASTER_SHIFT 2 03332 #define _UART_STATUS_MASTER_MASK 0x4UL 03333 #define _UART_STATUS_MASTER_DEFAULT 0x00000000UL 03334 #define UART_STATUS_MASTER_DEFAULT (_UART_STATUS_MASTER_DEFAULT << 2) 03335 #define UART_STATUS_RXBLOCK (0x1UL << 3) 03336 #define _UART_STATUS_RXBLOCK_SHIFT 3 03337 #define _UART_STATUS_RXBLOCK_MASK 0x8UL 03338 #define _UART_STATUS_RXBLOCK_DEFAULT 0x00000000UL 03339 #define UART_STATUS_RXBLOCK_DEFAULT (_UART_STATUS_RXBLOCK_DEFAULT << 3) 03340 #define UART_STATUS_TXTRI (0x1UL << 4) 03341 #define _UART_STATUS_TXTRI_SHIFT 4 03342 #define _UART_STATUS_TXTRI_MASK 0x10UL 03343 #define _UART_STATUS_TXTRI_DEFAULT 0x00000000UL 03344 #define UART_STATUS_TXTRI_DEFAULT (_UART_STATUS_TXTRI_DEFAULT << 4) 03345 #define UART_STATUS_TXC (0x1UL << 5) 03346 #define _UART_STATUS_TXC_SHIFT 5 03347 #define _UART_STATUS_TXC_MASK 0x20UL 03348 #define _UART_STATUS_TXC_DEFAULT 0x00000000UL 03349 #define UART_STATUS_TXC_DEFAULT (_UART_STATUS_TXC_DEFAULT << 5) 03350 #define UART_STATUS_TXBL (0x1UL << 6) 03351 #define _UART_STATUS_TXBL_SHIFT 6 03352 #define _UART_STATUS_TXBL_MASK 0x40UL 03353 #define _UART_STATUS_TXBL_DEFAULT 0x00000001UL 03354 #define UART_STATUS_TXBL_DEFAULT (_UART_STATUS_TXBL_DEFAULT << 6) 03355 #define UART_STATUS_RXDATAV (0x1UL << 7) 03356 #define _UART_STATUS_RXDATAV_SHIFT 7 03357 #define _UART_STATUS_RXDATAV_MASK 0x80UL 03358 #define _UART_STATUS_RXDATAV_DEFAULT 0x00000000UL 03359 #define UART_STATUS_RXDATAV_DEFAULT (_UART_STATUS_RXDATAV_DEFAULT << 7) 03360 #define UART_STATUS_RXFULL (0x1UL << 8) 03361 #define _UART_STATUS_RXFULL_SHIFT 8 03362 #define _UART_STATUS_RXFULL_MASK 0x100UL 03363 #define _UART_STATUS_RXFULL_DEFAULT 0x00000000UL 03364 #define UART_STATUS_RXFULL_DEFAULT (_UART_STATUS_RXFULL_DEFAULT << 8) 03366 /* Bit fields for UART CLKDIV */ 03367 #define _UART_CLKDIV_RESETVALUE 0x00000000UL 03368 #define _UART_CLKDIV_MASK 0x001FFFC0UL 03369 #define _UART_CLKDIV_DIV_SHIFT 6 03370 #define _UART_CLKDIV_DIV_MASK 0x1FFFC0UL 03371 #define _UART_CLKDIV_DIV_DEFAULT 0x00000000UL 03372 #define UART_CLKDIV_DIV_DEFAULT (_UART_CLKDIV_DIV_DEFAULT << 6) 03374 /* Bit fields for UART RXDATAX */ 03375 #define _UART_RXDATAX_RESETVALUE 0x00000000UL 03376 #define _UART_RXDATAX_MASK 0x0000C1FFUL 03377 #define _UART_RXDATAX_RXDATA_SHIFT 0 03378 #define _UART_RXDATAX_RXDATA_MASK 0x1FFUL 03379 #define _UART_RXDATAX_RXDATA_DEFAULT 0x00000000UL 03380 #define UART_RXDATAX_RXDATA_DEFAULT (_UART_RXDATAX_RXDATA_DEFAULT << 0) 03381 #define UART_RXDATAX_PERR (0x1UL << 14) 03382 #define _UART_RXDATAX_PERR_SHIFT 14 03383 #define _UART_RXDATAX_PERR_MASK 0x4000UL 03384 #define _UART_RXDATAX_PERR_DEFAULT 0x00000000UL 03385 #define UART_RXDATAX_PERR_DEFAULT (_UART_RXDATAX_PERR_DEFAULT << 14) 03386 #define UART_RXDATAX_FERR (0x1UL << 15) 03387 #define _UART_RXDATAX_FERR_SHIFT 15 03388 #define _UART_RXDATAX_FERR_MASK 0x8000UL 03389 #define _UART_RXDATAX_FERR_DEFAULT 0x00000000UL 03390 #define UART_RXDATAX_FERR_DEFAULT (_UART_RXDATAX_FERR_DEFAULT << 15) 03392 /* Bit fields for UART RXDATA */ 03393 #define _UART_RXDATA_RESETVALUE 0x00000000UL 03394 #define _UART_RXDATA_MASK 0x000000FFUL 03395 #define _UART_RXDATA_RXDATA_SHIFT 0 03396 #define _UART_RXDATA_RXDATA_MASK 0xFFUL 03397 #define _UART_RXDATA_RXDATA_DEFAULT 0x00000000UL 03398 #define UART_RXDATA_RXDATA_DEFAULT (_UART_RXDATA_RXDATA_DEFAULT << 0) 03400 /* Bit fields for UART RXDOUBLEX */ 03401 #define _UART_RXDOUBLEX_RESETVALUE 0x00000000UL 03402 #define _UART_RXDOUBLEX_MASK 0xC1FFC1FFUL 03403 #define _UART_RXDOUBLEX_RXDATA0_SHIFT 0 03404 #define _UART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL 03405 #define _UART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL 03406 #define UART_RXDOUBLEX_RXDATA0_DEFAULT (_UART_RXDOUBLEX_RXDATA0_DEFAULT << 0) 03407 #define UART_RXDOUBLEX_PERR0 (0x1UL << 14) 03408 #define _UART_RXDOUBLEX_PERR0_SHIFT 14 03409 #define _UART_RXDOUBLEX_PERR0_MASK 0x4000UL 03410 #define _UART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL 03411 #define UART_RXDOUBLEX_PERR0_DEFAULT (_UART_RXDOUBLEX_PERR0_DEFAULT << 14) 03412 #define UART_RXDOUBLEX_FERR0 (0x1UL << 15) 03413 #define _UART_RXDOUBLEX_FERR0_SHIFT 15 03414 #define _UART_RXDOUBLEX_FERR0_MASK 0x8000UL 03415 #define _UART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL 03416 #define UART_RXDOUBLEX_FERR0_DEFAULT (_UART_RXDOUBLEX_FERR0_DEFAULT << 15) 03417 #define _UART_RXDOUBLEX_RXDATA1_SHIFT 16 03418 #define _UART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL 03419 #define _UART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL 03420 #define UART_RXDOUBLEX_RXDATA1_DEFAULT (_UART_RXDOUBLEX_RXDATA1_DEFAULT << 16) 03421 #define UART_RXDOUBLEX_PERR1 (0x1UL << 30) 03422 #define _UART_RXDOUBLEX_PERR1_SHIFT 30 03423 #define _UART_RXDOUBLEX_PERR1_MASK 0x40000000UL 03424 #define _UART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL 03425 #define UART_RXDOUBLEX_PERR1_DEFAULT (_UART_RXDOUBLEX_PERR1_DEFAULT << 30) 03426 #define UART_RXDOUBLEX_FERR1 (0x1UL << 31) 03427 #define _UART_RXDOUBLEX_FERR1_SHIFT 31 03428 #define _UART_RXDOUBLEX_FERR1_MASK 0x80000000UL 03429 #define _UART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL 03430 #define UART_RXDOUBLEX_FERR1_DEFAULT (_UART_RXDOUBLEX_FERR1_DEFAULT << 31) 03432 /* Bit fields for UART RXDOUBLE */ 03433 #define _UART_RXDOUBLE_RESETVALUE 0x00000000UL 03434 #define _UART_RXDOUBLE_MASK 0x0000FFFFUL 03435 #define _UART_RXDOUBLE_RXDATA0_SHIFT 0 03436 #define _UART_RXDOUBLE_RXDATA0_MASK 0xFFUL 03437 #define _UART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL 03438 #define UART_RXDOUBLE_RXDATA0_DEFAULT (_UART_RXDOUBLE_RXDATA0_DEFAULT << 0) 03439 #define _UART_RXDOUBLE_RXDATA1_SHIFT 8 03440 #define _UART_RXDOUBLE_RXDATA1_MASK 0xFF00UL 03441 #define _UART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL 03442 #define UART_RXDOUBLE_RXDATA1_DEFAULT (_UART_RXDOUBLE_RXDATA1_DEFAULT << 8) 03444 /* Bit fields for UART RXDATAXP */ 03445 #define _UART_RXDATAXP_RESETVALUE 0x00000000UL 03446 #define _UART_RXDATAXP_MASK 0x0000C1FFUL 03447 #define _UART_RXDATAXP_RXDATAP_SHIFT 0 03448 #define _UART_RXDATAXP_RXDATAP_MASK 0x1FFUL 03449 #define _UART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL 03450 #define UART_RXDATAXP_RXDATAP_DEFAULT (_UART_RXDATAXP_RXDATAP_DEFAULT << 0) 03451 #define UART_RXDATAXP_PERRP (0x1UL << 14) 03452 #define _UART_RXDATAXP_PERRP_SHIFT 14 03453 #define _UART_RXDATAXP_PERRP_MASK 0x4000UL 03454 #define _UART_RXDATAXP_PERRP_DEFAULT 0x00000000UL 03455 #define UART_RXDATAXP_PERRP_DEFAULT (_UART_RXDATAXP_PERRP_DEFAULT << 14) 03456 #define UART_RXDATAXP_FERRP (0x1UL << 15) 03457 #define _UART_RXDATAXP_FERRP_SHIFT 15 03458 #define _UART_RXDATAXP_FERRP_MASK 0x8000UL 03459 #define _UART_RXDATAXP_FERRP_DEFAULT 0x00000000UL 03460 #define UART_RXDATAXP_FERRP_DEFAULT (_UART_RXDATAXP_FERRP_DEFAULT << 15) 03462 /* Bit fields for UART RXDOUBLEXP */ 03463 #define _UART_RXDOUBLEXP_RESETVALUE 0x00000000UL 03464 #define _UART_RXDOUBLEXP_MASK 0xC1FFC1FFUL 03465 #define _UART_RXDOUBLEXP_RXDATAP0_SHIFT 0 03466 #define _UART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL 03467 #define _UART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL 03468 #define UART_RXDOUBLEXP_RXDATAP0_DEFAULT (_UART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0) 03469 #define UART_RXDOUBLEXP_PERRP0 (0x1UL << 14) 03470 #define _UART_RXDOUBLEXP_PERRP0_SHIFT 14 03471 #define _UART_RXDOUBLEXP_PERRP0_MASK 0x4000UL 03472 #define _UART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL 03473 #define UART_RXDOUBLEXP_PERRP0_DEFAULT (_UART_RXDOUBLEXP_PERRP0_DEFAULT << 14) 03474 #define UART_RXDOUBLEXP_FERRP0 (0x1UL << 15) 03475 #define _UART_RXDOUBLEXP_FERRP0_SHIFT 15 03476 #define _UART_RXDOUBLEXP_FERRP0_MASK 0x8000UL 03477 #define _UART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL 03478 #define UART_RXDOUBLEXP_FERRP0_DEFAULT (_UART_RXDOUBLEXP_FERRP0_DEFAULT << 15) 03479 #define _UART_RXDOUBLEXP_RXDATAP1_SHIFT 16 03480 #define _UART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL 03481 #define _UART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL 03482 #define UART_RXDOUBLEXP_RXDATAP1_DEFAULT (_UART_RXDOUBLEXP_RXDATAP1_DEFAULT << 16) 03483 #define UART_RXDOUBLEXP_PERRP1 (0x1UL << 30) 03484 #define _UART_RXDOUBLEXP_PERRP1_SHIFT 30 03485 #define _UART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL 03486 #define _UART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL 03487 #define UART_RXDOUBLEXP_PERRP1_DEFAULT (_UART_RXDOUBLEXP_PERRP1_DEFAULT << 30) 03488 #define UART_RXDOUBLEXP_FERRP1 (0x1UL << 31) 03489 #define _UART_RXDOUBLEXP_FERRP1_SHIFT 31 03490 #define _UART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL 03491 #define _UART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL 03492 #define UART_RXDOUBLEXP_FERRP1_DEFAULT (_UART_RXDOUBLEXP_FERRP1_DEFAULT << 31) 03494 /* Bit fields for UART TXDATAX */ 03495 #define _UART_TXDATAX_RESETVALUE 0x00000000UL 03496 #define _UART_TXDATAX_MASK 0x0000F9FFUL 03497 #define _UART_TXDATAX_TXDATAX_SHIFT 0 03498 #define _UART_TXDATAX_TXDATAX_MASK 0x1FFUL 03499 #define _UART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL 03500 #define UART_TXDATAX_TXDATAX_DEFAULT (_UART_TXDATAX_TXDATAX_DEFAULT << 0) 03501 #define UART_TXDATAX_UBRXAT (0x1UL << 11) 03502 #define _UART_TXDATAX_UBRXAT_SHIFT 11 03503 #define _UART_TXDATAX_UBRXAT_MASK 0x800UL 03504 #define _UART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL 03505 #define UART_TXDATAX_UBRXAT_DEFAULT (_UART_TXDATAX_UBRXAT_DEFAULT << 11) 03506 #define UART_TXDATAX_TXTRIAT (0x1UL << 12) 03507 #define _UART_TXDATAX_TXTRIAT_SHIFT 12 03508 #define _UART_TXDATAX_TXTRIAT_MASK 0x1000UL 03509 #define _UART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL 03510 #define UART_TXDATAX_TXTRIAT_DEFAULT (_UART_TXDATAX_TXTRIAT_DEFAULT << 12) 03511 #define UART_TXDATAX_TXBREAK (0x1UL << 13) 03512 #define _UART_TXDATAX_TXBREAK_SHIFT 13 03513 #define _UART_TXDATAX_TXBREAK_MASK 0x2000UL 03514 #define _UART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL 03515 #define UART_TXDATAX_TXBREAK_DEFAULT (_UART_TXDATAX_TXBREAK_DEFAULT << 13) 03516 #define UART_TXDATAX_TXDISAT (0x1UL << 14) 03517 #define _UART_TXDATAX_TXDISAT_SHIFT 14 03518 #define _UART_TXDATAX_TXDISAT_MASK 0x4000UL 03519 #define _UART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL 03520 #define UART_TXDATAX_TXDISAT_DEFAULT (_UART_TXDATAX_TXDISAT_DEFAULT << 14) 03521 #define UART_TXDATAX_RXENAT (0x1UL << 15) 03522 #define _UART_TXDATAX_RXENAT_SHIFT 15 03523 #define _UART_TXDATAX_RXENAT_MASK 0x8000UL 03524 #define _UART_TXDATAX_RXENAT_DEFAULT 0x00000000UL 03525 #define UART_TXDATAX_RXENAT_DEFAULT (_UART_TXDATAX_RXENAT_DEFAULT << 15) 03527 /* Bit fields for UART TXDATA */ 03528 #define _UART_TXDATA_RESETVALUE 0x00000000UL 03529 #define _UART_TXDATA_MASK 0x000000FFUL 03530 #define _UART_TXDATA_TXDATA_SHIFT 0 03531 #define _UART_TXDATA_TXDATA_MASK 0xFFUL 03532 #define _UART_TXDATA_TXDATA_DEFAULT 0x00000000UL 03533 #define UART_TXDATA_TXDATA_DEFAULT (_UART_TXDATA_TXDATA_DEFAULT << 0) 03535 /* Bit fields for UART TXDOUBLEX */ 03536 #define _UART_TXDOUBLEX_RESETVALUE 0x00000000UL 03537 #define _UART_TXDOUBLEX_MASK 0xF9FFF9FFUL 03538 #define _UART_TXDOUBLEX_TXDATA0_SHIFT 0 03539 #define _UART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL 03540 #define _UART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL 03541 #define UART_TXDOUBLEX_TXDATA0_DEFAULT (_UART_TXDOUBLEX_TXDATA0_DEFAULT << 0) 03542 #define UART_TXDOUBLEX_UBRXAT0 (0x1UL << 11) 03543 #define _UART_TXDOUBLEX_UBRXAT0_SHIFT 11 03544 #define _UART_TXDOUBLEX_UBRXAT0_MASK 0x800UL 03545 #define _UART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL 03546 #define UART_TXDOUBLEX_UBRXAT0_DEFAULT (_UART_TXDOUBLEX_UBRXAT0_DEFAULT << 11) 03547 #define UART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12) 03548 #define _UART_TXDOUBLEX_TXTRIAT0_SHIFT 12 03549 #define _UART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL 03550 #define _UART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL 03551 #define UART_TXDOUBLEX_TXTRIAT0_DEFAULT (_UART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12) 03552 #define UART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) 03553 #define _UART_TXDOUBLEX_TXBREAK0_SHIFT 13 03554 #define _UART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL 03555 #define _UART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL 03556 #define UART_TXDOUBLEX_TXBREAK0_DEFAULT (_UART_TXDOUBLEX_TXBREAK0_DEFAULT << 13) 03557 #define UART_TXDOUBLEX_TXDISAT0 (0x1UL << 14) 03558 #define _UART_TXDOUBLEX_TXDISAT0_SHIFT 14 03559 #define _UART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL 03560 #define _UART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL 03561 #define UART_TXDOUBLEX_TXDISAT0_DEFAULT (_UART_TXDOUBLEX_TXDISAT0_DEFAULT << 14) 03562 #define UART_TXDOUBLEX_RXENAT0 (0x1UL << 15) 03563 #define _UART_TXDOUBLEX_RXENAT0_SHIFT 15 03564 #define _UART_TXDOUBLEX_RXENAT0_MASK 0x8000UL 03565 #define _UART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL 03566 #define UART_TXDOUBLEX_RXENAT0_DEFAULT (_UART_TXDOUBLEX_RXENAT0_DEFAULT << 15) 03567 #define _UART_TXDOUBLEX_TXDATA1_SHIFT 16 03568 #define _UART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL 03569 #define _UART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL 03570 #define UART_TXDOUBLEX_TXDATA1_DEFAULT (_UART_TXDOUBLEX_TXDATA1_DEFAULT << 16) 03571 #define UART_TXDOUBLEX_UBRXAT1 (0x1UL << 27) 03572 #define _UART_TXDOUBLEX_UBRXAT1_SHIFT 27 03573 #define _UART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL 03574 #define _UART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL 03575 #define UART_TXDOUBLEX_UBRXAT1_DEFAULT (_UART_TXDOUBLEX_UBRXAT1_DEFAULT << 27) 03576 #define UART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28) 03577 #define _UART_TXDOUBLEX_TXTRIAT1_SHIFT 28 03578 #define _UART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL 03579 #define _UART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL 03580 #define UART_TXDOUBLEX_TXTRIAT1_DEFAULT (_UART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28) 03581 #define UART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) 03582 #define _UART_TXDOUBLEX_TXBREAK1_SHIFT 29 03583 #define _UART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL 03584 #define _UART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL 03585 #define UART_TXDOUBLEX_TXBREAK1_DEFAULT (_UART_TXDOUBLEX_TXBREAK1_DEFAULT << 29) 03586 #define UART_TXDOUBLEX_TXDISAT1 (0x1UL << 30) 03587 #define _UART_TXDOUBLEX_TXDISAT1_SHIFT 30 03588 #define _UART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL 03589 #define _UART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL 03590 #define UART_TXDOUBLEX_TXDISAT1_DEFAULT (_UART_TXDOUBLEX_TXDISAT1_DEFAULT << 30) 03591 #define UART_TXDOUBLEX_RXENAT1 (0x1UL << 31) 03592 #define _UART_TXDOUBLEX_RXENAT1_SHIFT 31 03593 #define _UART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL 03594 #define _UART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL 03595 #define UART_TXDOUBLEX_RXENAT1_DEFAULT (_UART_TXDOUBLEX_RXENAT1_DEFAULT << 31) 03597 /* Bit fields for UART TXDOUBLE */ 03598 #define _UART_TXDOUBLE_RESETVALUE 0x00000000UL 03599 #define _UART_TXDOUBLE_MASK 0x0000FFFFUL 03600 #define _UART_TXDOUBLE_TXDATA0_SHIFT 0 03601 #define _UART_TXDOUBLE_TXDATA0_MASK 0xFFUL 03602 #define _UART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL 03603 #define UART_TXDOUBLE_TXDATA0_DEFAULT (_UART_TXDOUBLE_TXDATA0_DEFAULT << 0) 03604 #define _UART_TXDOUBLE_TXDATA1_SHIFT 8 03605 #define _UART_TXDOUBLE_TXDATA1_MASK 0xFF00UL 03606 #define _UART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL 03607 #define UART_TXDOUBLE_TXDATA1_DEFAULT (_UART_TXDOUBLE_TXDATA1_DEFAULT << 8) 03609 /* Bit fields for UART IF */ 03610 #define _UART_IF_RESETVALUE 0x00000002UL 03611 #define _UART_IF_MASK 0x00001FFFUL 03612 #define UART_IF_TXC (0x1UL << 0) 03613 #define _UART_IF_TXC_SHIFT 0 03614 #define _UART_IF_TXC_MASK 0x1UL 03615 #define _UART_IF_TXC_DEFAULT 0x00000000UL 03616 #define UART_IF_TXC_DEFAULT (_UART_IF_TXC_DEFAULT << 0) 03617 #define UART_IF_TXBL (0x1UL << 1) 03618 #define _UART_IF_TXBL_SHIFT 1 03619 #define _UART_IF_TXBL_MASK 0x2UL 03620 #define _UART_IF_TXBL_DEFAULT 0x00000001UL 03621 #define UART_IF_TXBL_DEFAULT (_UART_IF_TXBL_DEFAULT << 1) 03622 #define UART_IF_RXDATAV (0x1UL << 2) 03623 #define _UART_IF_RXDATAV_SHIFT 2 03624 #define _UART_IF_RXDATAV_MASK 0x4UL 03625 #define _UART_IF_RXDATAV_DEFAULT 0x00000000UL 03626 #define UART_IF_RXDATAV_DEFAULT (_UART_IF_RXDATAV_DEFAULT << 2) 03627 #define UART_IF_RXFULL (0x1UL << 3) 03628 #define _UART_IF_RXFULL_SHIFT 3 03629 #define _UART_IF_RXFULL_MASK 0x8UL 03630 #define _UART_IF_RXFULL_DEFAULT 0x00000000UL 03631 #define UART_IF_RXFULL_DEFAULT (_UART_IF_RXFULL_DEFAULT << 3) 03632 #define UART_IF_RXOF (0x1UL << 4) 03633 #define _UART_IF_RXOF_SHIFT 4 03634 #define _UART_IF_RXOF_MASK 0x10UL 03635 #define _UART_IF_RXOF_DEFAULT 0x00000000UL 03636 #define UART_IF_RXOF_DEFAULT (_UART_IF_RXOF_DEFAULT << 4) 03637 #define UART_IF_RXUF (0x1UL << 5) 03638 #define _UART_IF_RXUF_SHIFT 5 03639 #define _UART_IF_RXUF_MASK 0x20UL 03640 #define _UART_IF_RXUF_DEFAULT 0x00000000UL 03641 #define UART_IF_RXUF_DEFAULT (_UART_IF_RXUF_DEFAULT << 5) 03642 #define UART_IF_TXOF (0x1UL << 6) 03643 #define _UART_IF_TXOF_SHIFT 6 03644 #define _UART_IF_TXOF_MASK 0x40UL 03645 #define _UART_IF_TXOF_DEFAULT 0x00000000UL 03646 #define UART_IF_TXOF_DEFAULT (_UART_IF_TXOF_DEFAULT << 6) 03647 #define UART_IF_TXUF (0x1UL << 7) 03648 #define _UART_IF_TXUF_SHIFT 7 03649 #define _UART_IF_TXUF_MASK 0x80UL 03650 #define _UART_IF_TXUF_DEFAULT 0x00000000UL 03651 #define UART_IF_TXUF_DEFAULT (_UART_IF_TXUF_DEFAULT << 7) 03652 #define UART_IF_PERR (0x1UL << 8) 03653 #define _UART_IF_PERR_SHIFT 8 03654 #define _UART_IF_PERR_MASK 0x100UL 03655 #define _UART_IF_PERR_DEFAULT 0x00000000UL 03656 #define UART_IF_PERR_DEFAULT (_UART_IF_PERR_DEFAULT << 8) 03657 #define UART_IF_FERR (0x1UL << 9) 03658 #define _UART_IF_FERR_SHIFT 9 03659 #define _UART_IF_FERR_MASK 0x200UL 03660 #define _UART_IF_FERR_DEFAULT 0x00000000UL 03661 #define UART_IF_FERR_DEFAULT (_UART_IF_FERR_DEFAULT << 9) 03662 #define UART_IF_MPAF (0x1UL << 10) 03663 #define _UART_IF_MPAF_SHIFT 10 03664 #define _UART_IF_MPAF_MASK 0x400UL 03665 #define _UART_IF_MPAF_DEFAULT 0x00000000UL 03666 #define UART_IF_MPAF_DEFAULT (_UART_IF_MPAF_DEFAULT << 10) 03667 #define UART_IF_SSM (0x1UL << 11) 03668 #define _UART_IF_SSM_SHIFT 11 03669 #define _UART_IF_SSM_MASK 0x800UL 03670 #define _UART_IF_SSM_DEFAULT 0x00000000UL 03671 #define UART_IF_SSM_DEFAULT (_UART_IF_SSM_DEFAULT << 11) 03672 #define UART_IF_CCF (0x1UL << 12) 03673 #define _UART_IF_CCF_SHIFT 12 03674 #define _UART_IF_CCF_MASK 0x1000UL 03675 #define _UART_IF_CCF_DEFAULT 0x00000000UL 03676 #define UART_IF_CCF_DEFAULT (_UART_IF_CCF_DEFAULT << 12) 03678 /* Bit fields for UART IFS */ 03679 #define _UART_IFS_RESETVALUE 0x00000000UL 03680 #define _UART_IFS_MASK 0x00001FF9UL 03681 #define UART_IFS_TXC (0x1UL << 0) 03682 #define _UART_IFS_TXC_SHIFT 0 03683 #define _UART_IFS_TXC_MASK 0x1UL 03684 #define _UART_IFS_TXC_DEFAULT 0x00000000UL 03685 #define UART_IFS_TXC_DEFAULT (_UART_IFS_TXC_DEFAULT << 0) 03686 #define UART_IFS_RXFULL (0x1UL << 3) 03687 #define _UART_IFS_RXFULL_SHIFT 3 03688 #define _UART_IFS_RXFULL_MASK 0x8UL 03689 #define _UART_IFS_RXFULL_DEFAULT 0x00000000UL 03690 #define UART_IFS_RXFULL_DEFAULT (_UART_IFS_RXFULL_DEFAULT << 3) 03691 #define UART_IFS_RXOF (0x1UL << 4) 03692 #define _UART_IFS_RXOF_SHIFT 4 03693 #define _UART_IFS_RXOF_MASK 0x10UL 03694 #define _UART_IFS_RXOF_DEFAULT 0x00000000UL 03695 #define UART_IFS_RXOF_DEFAULT (_UART_IFS_RXOF_DEFAULT << 4) 03696 #define UART_IFS_RXUF (0x1UL << 5) 03697 #define _UART_IFS_RXUF_SHIFT 5 03698 #define _UART_IFS_RXUF_MASK 0x20UL 03699 #define _UART_IFS_RXUF_DEFAULT 0x00000000UL 03700 #define UART_IFS_RXUF_DEFAULT (_UART_IFS_RXUF_DEFAULT << 5) 03701 #define UART_IFS_TXOF (0x1UL << 6) 03702 #define _UART_IFS_TXOF_SHIFT 6 03703 #define _UART_IFS_TXOF_MASK 0x40UL 03704 #define _UART_IFS_TXOF_DEFAULT 0x00000000UL 03705 #define UART_IFS_TXOF_DEFAULT (_UART_IFS_TXOF_DEFAULT << 6) 03706 #define UART_IFS_TXUF (0x1UL << 7) 03707 #define _UART_IFS_TXUF_SHIFT 7 03708 #define _UART_IFS_TXUF_MASK 0x80UL 03709 #define _UART_IFS_TXUF_DEFAULT 0x00000000UL 03710 #define UART_IFS_TXUF_DEFAULT (_UART_IFS_TXUF_DEFAULT << 7) 03711 #define UART_IFS_PERR (0x1UL << 8) 03712 #define _UART_IFS_PERR_SHIFT 8 03713 #define _UART_IFS_PERR_MASK 0x100UL 03714 #define _UART_IFS_PERR_DEFAULT 0x00000000UL 03715 #define UART_IFS_PERR_DEFAULT (_UART_IFS_PERR_DEFAULT << 8) 03716 #define UART_IFS_FERR (0x1UL << 9) 03717 #define _UART_IFS_FERR_SHIFT 9 03718 #define _UART_IFS_FERR_MASK 0x200UL 03719 #define _UART_IFS_FERR_DEFAULT 0x00000000UL 03720 #define UART_IFS_FERR_DEFAULT (_UART_IFS_FERR_DEFAULT << 9) 03721 #define UART_IFS_MPAF (0x1UL << 10) 03722 #define _UART_IFS_MPAF_SHIFT 10 03723 #define _UART_IFS_MPAF_MASK 0x400UL 03724 #define _UART_IFS_MPAF_DEFAULT 0x00000000UL 03725 #define UART_IFS_MPAF_DEFAULT (_UART_IFS_MPAF_DEFAULT << 10) 03726 #define UART_IFS_SSM (0x1UL << 11) 03727 #define _UART_IFS_SSM_SHIFT 11 03728 #define _UART_IFS_SSM_MASK 0x800UL 03729 #define _UART_IFS_SSM_DEFAULT 0x00000000UL 03730 #define UART_IFS_SSM_DEFAULT (_UART_IFS_SSM_DEFAULT << 11) 03731 #define UART_IFS_CCF (0x1UL << 12) 03732 #define _UART_IFS_CCF_SHIFT 12 03733 #define _UART_IFS_CCF_MASK 0x1000UL 03734 #define _UART_IFS_CCF_DEFAULT 0x00000000UL 03735 #define UART_IFS_CCF_DEFAULT (_UART_IFS_CCF_DEFAULT << 12) 03737 /* Bit fields for UART IFC */ 03738 #define _UART_IFC_RESETVALUE 0x00000000UL 03739 #define _UART_IFC_MASK 0x00001FF9UL 03740 #define UART_IFC_TXC (0x1UL << 0) 03741 #define _UART_IFC_TXC_SHIFT 0 03742 #define _UART_IFC_TXC_MASK 0x1UL 03743 #define _UART_IFC_TXC_DEFAULT 0x00000000UL 03744 #define UART_IFC_TXC_DEFAULT (_UART_IFC_TXC_DEFAULT << 0) 03745 #define UART_IFC_RXFULL (0x1UL << 3) 03746 #define _UART_IFC_RXFULL_SHIFT 3 03747 #define _UART_IFC_RXFULL_MASK 0x8UL 03748 #define _UART_IFC_RXFULL_DEFAULT 0x00000000UL 03749 #define UART_IFC_RXFULL_DEFAULT (_UART_IFC_RXFULL_DEFAULT << 3) 03750 #define UART_IFC_RXOF (0x1UL << 4) 03751 #define _UART_IFC_RXOF_SHIFT 4 03752 #define _UART_IFC_RXOF_MASK 0x10UL 03753 #define _UART_IFC_RXOF_DEFAULT 0x00000000UL 03754 #define UART_IFC_RXOF_DEFAULT (_UART_IFC_RXOF_DEFAULT << 4) 03755 #define UART_IFC_RXUF (0x1UL << 5) 03756 #define _UART_IFC_RXUF_SHIFT 5 03757 #define _UART_IFC_RXUF_MASK 0x20UL 03758 #define _UART_IFC_RXUF_DEFAULT 0x00000000UL 03759 #define UART_IFC_RXUF_DEFAULT (_UART_IFC_RXUF_DEFAULT << 5) 03760 #define UART_IFC_TXOF (0x1UL << 6) 03761 #define _UART_IFC_TXOF_SHIFT 6 03762 #define _UART_IFC_TXOF_MASK 0x40UL 03763 #define _UART_IFC_TXOF_DEFAULT 0x00000000UL 03764 #define UART_IFC_TXOF_DEFAULT (_UART_IFC_TXOF_DEFAULT << 6) 03765 #define UART_IFC_TXUF (0x1UL << 7) 03766 #define _UART_IFC_TXUF_SHIFT 7 03767 #define _UART_IFC_TXUF_MASK 0x80UL 03768 #define _UART_IFC_TXUF_DEFAULT 0x00000000UL 03769 #define UART_IFC_TXUF_DEFAULT (_UART_IFC_TXUF_DEFAULT << 7) 03770 #define UART_IFC_PERR (0x1UL << 8) 03771 #define _UART_IFC_PERR_SHIFT 8 03772 #define _UART_IFC_PERR_MASK 0x100UL 03773 #define _UART_IFC_PERR_DEFAULT 0x00000000UL 03774 #define UART_IFC_PERR_DEFAULT (_UART_IFC_PERR_DEFAULT << 8) 03775 #define UART_IFC_FERR (0x1UL << 9) 03776 #define _UART_IFC_FERR_SHIFT 9 03777 #define _UART_IFC_FERR_MASK 0x200UL 03778 #define _UART_IFC_FERR_DEFAULT 0x00000000UL 03779 #define UART_IFC_FERR_DEFAULT (_UART_IFC_FERR_DEFAULT << 9) 03780 #define UART_IFC_MPAF (0x1UL << 10) 03781 #define _UART_IFC_MPAF_SHIFT 10 03782 #define _UART_IFC_MPAF_MASK 0x400UL 03783 #define _UART_IFC_MPAF_DEFAULT 0x00000000UL 03784 #define UART_IFC_MPAF_DEFAULT (_UART_IFC_MPAF_DEFAULT << 10) 03785 #define UART_IFC_SSM (0x1UL << 11) 03786 #define _UART_IFC_SSM_SHIFT 11 03787 #define _UART_IFC_SSM_MASK 0x800UL 03788 #define _UART_IFC_SSM_DEFAULT 0x00000000UL 03789 #define UART_IFC_SSM_DEFAULT (_UART_IFC_SSM_DEFAULT << 11) 03790 #define UART_IFC_CCF (0x1UL << 12) 03791 #define _UART_IFC_CCF_SHIFT 12 03792 #define _UART_IFC_CCF_MASK 0x1000UL 03793 #define _UART_IFC_CCF_DEFAULT 0x00000000UL 03794 #define UART_IFC_CCF_DEFAULT (_UART_IFC_CCF_DEFAULT << 12) 03796 /* Bit fields for UART IEN */ 03797 #define _UART_IEN_RESETVALUE 0x00000000UL 03798 #define _UART_IEN_MASK 0x00001FFFUL 03799 #define UART_IEN_TXC (0x1UL << 0) 03800 #define _UART_IEN_TXC_SHIFT 0 03801 #define _UART_IEN_TXC_MASK 0x1UL 03802 #define _UART_IEN_TXC_DEFAULT 0x00000000UL 03803 #define UART_IEN_TXC_DEFAULT (_UART_IEN_TXC_DEFAULT << 0) 03804 #define UART_IEN_TXBL (0x1UL << 1) 03805 #define _UART_IEN_TXBL_SHIFT 1 03806 #define _UART_IEN_TXBL_MASK 0x2UL 03807 #define _UART_IEN_TXBL_DEFAULT 0x00000000UL 03808 #define UART_IEN_TXBL_DEFAULT (_UART_IEN_TXBL_DEFAULT << 1) 03809 #define UART_IEN_RXDATAV (0x1UL << 2) 03810 #define _UART_IEN_RXDATAV_SHIFT 2 03811 #define _UART_IEN_RXDATAV_MASK 0x4UL 03812 #define _UART_IEN_RXDATAV_DEFAULT 0x00000000UL 03813 #define UART_IEN_RXDATAV_DEFAULT (_UART_IEN_RXDATAV_DEFAULT << 2) 03814 #define UART_IEN_RXFULL (0x1UL << 3) 03815 #define _UART_IEN_RXFULL_SHIFT 3 03816 #define _UART_IEN_RXFULL_MASK 0x8UL 03817 #define _UART_IEN_RXFULL_DEFAULT 0x00000000UL 03818 #define UART_IEN_RXFULL_DEFAULT (_UART_IEN_RXFULL_DEFAULT << 3) 03819 #define UART_IEN_RXOF (0x1UL << 4) 03820 #define _UART_IEN_RXOF_SHIFT 4 03821 #define _UART_IEN_RXOF_MASK 0x10UL 03822 #define _UART_IEN_RXOF_DEFAULT 0x00000000UL 03823 #define UART_IEN_RXOF_DEFAULT (_UART_IEN_RXOF_DEFAULT << 4) 03824 #define UART_IEN_RXUF (0x1UL << 5) 03825 #define _UART_IEN_RXUF_SHIFT 5 03826 #define _UART_IEN_RXUF_MASK 0x20UL 03827 #define _UART_IEN_RXUF_DEFAULT 0x00000000UL 03828 #define UART_IEN_RXUF_DEFAULT (_UART_IEN_RXUF_DEFAULT << 5) 03829 #define UART_IEN_TXOF (0x1UL << 6) 03830 #define _UART_IEN_TXOF_SHIFT 6 03831 #define _UART_IEN_TXOF_MASK 0x40UL 03832 #define _UART_IEN_TXOF_DEFAULT 0x00000000UL 03833 #define UART_IEN_TXOF_DEFAULT (_UART_IEN_TXOF_DEFAULT << 6) 03834 #define UART_IEN_TXUF (0x1UL << 7) 03835 #define _UART_IEN_TXUF_SHIFT 7 03836 #define _UART_IEN_TXUF_MASK 0x80UL 03837 #define _UART_IEN_TXUF_DEFAULT 0x00000000UL 03838 #define UART_IEN_TXUF_DEFAULT (_UART_IEN_TXUF_DEFAULT << 7) 03839 #define UART_IEN_PERR (0x1UL << 8) 03840 #define _UART_IEN_PERR_SHIFT 8 03841 #define _UART_IEN_PERR_MASK 0x100UL 03842 #define _UART_IEN_PERR_DEFAULT 0x00000000UL 03843 #define UART_IEN_PERR_DEFAULT (_UART_IEN_PERR_DEFAULT << 8) 03844 #define UART_IEN_FERR (0x1UL << 9) 03845 #define _UART_IEN_FERR_SHIFT 9 03846 #define _UART_IEN_FERR_MASK 0x200UL 03847 #define _UART_IEN_FERR_DEFAULT 0x00000000UL 03848 #define UART_IEN_FERR_DEFAULT (_UART_IEN_FERR_DEFAULT << 9) 03849 #define UART_IEN_MPAF (0x1UL << 10) 03850 #define _UART_IEN_MPAF_SHIFT 10 03851 #define _UART_IEN_MPAF_MASK 0x400UL 03852 #define _UART_IEN_MPAF_DEFAULT 0x00000000UL 03853 #define UART_IEN_MPAF_DEFAULT (_UART_IEN_MPAF_DEFAULT << 10) 03854 #define UART_IEN_SSM (0x1UL << 11) 03855 #define _UART_IEN_SSM_SHIFT 11 03856 #define _UART_IEN_SSM_MASK 0x800UL 03857 #define _UART_IEN_SSM_DEFAULT 0x00000000UL 03858 #define UART_IEN_SSM_DEFAULT (_UART_IEN_SSM_DEFAULT << 11) 03859 #define UART_IEN_CCF (0x1UL << 12) 03860 #define _UART_IEN_CCF_SHIFT 12 03861 #define _UART_IEN_CCF_MASK 0x1000UL 03862 #define _UART_IEN_CCF_DEFAULT 0x00000000UL 03863 #define UART_IEN_CCF_DEFAULT (_UART_IEN_CCF_DEFAULT << 12) 03865 /* Bit fields for UART IRCTRL */ 03866 #define _UART_IRCTRL_RESETVALUE 0x00000000UL 03867 #define _UART_IRCTRL_MASK 0x000000FFUL 03868 #define UART_IRCTRL_IREN (0x1UL << 0) 03869 #define _UART_IRCTRL_IREN_SHIFT 0 03870 #define _UART_IRCTRL_IREN_MASK 0x1UL 03871 #define _UART_IRCTRL_IREN_DEFAULT 0x00000000UL 03872 #define UART_IRCTRL_IREN_DEFAULT (_UART_IRCTRL_IREN_DEFAULT << 0) 03873 #define _UART_IRCTRL_IRPW_SHIFT 1 03874 #define _UART_IRCTRL_IRPW_MASK 0x6UL 03875 #define _UART_IRCTRL_IRPW_DEFAULT 0x00000000UL 03876 #define _UART_IRCTRL_IRPW_ONE 0x00000000UL 03877 #define _UART_IRCTRL_IRPW_TWO 0x00000001UL 03878 #define _UART_IRCTRL_IRPW_THREE 0x00000002UL 03879 #define _UART_IRCTRL_IRPW_FOUR 0x00000003UL 03880 #define UART_IRCTRL_IRPW_DEFAULT (_UART_IRCTRL_IRPW_DEFAULT << 1) 03881 #define UART_IRCTRL_IRPW_ONE (_UART_IRCTRL_IRPW_ONE << 1) 03882 #define UART_IRCTRL_IRPW_TWO (_UART_IRCTRL_IRPW_TWO << 1) 03883 #define UART_IRCTRL_IRPW_THREE (_UART_IRCTRL_IRPW_THREE << 1) 03884 #define UART_IRCTRL_IRPW_FOUR (_UART_IRCTRL_IRPW_FOUR << 1) 03885 #define UART_IRCTRL_IRFILT (0x1UL << 3) 03886 #define _UART_IRCTRL_IRFILT_SHIFT 3 03887 #define _UART_IRCTRL_IRFILT_MASK 0x8UL 03888 #define _UART_IRCTRL_IRFILT_DEFAULT 0x00000000UL 03889 #define UART_IRCTRL_IRFILT_DEFAULT (_UART_IRCTRL_IRFILT_DEFAULT << 3) 03890 #define _UART_IRCTRL_IRPRSSEL_SHIFT 4 03891 #define _UART_IRCTRL_IRPRSSEL_MASK 0x70UL 03892 #define _UART_IRCTRL_IRPRSSEL_DEFAULT 0x00000000UL 03893 #define _UART_IRCTRL_IRPRSSEL_PRSCH0 0x00000000UL 03894 #define _UART_IRCTRL_IRPRSSEL_PRSCH1 0x00000001UL 03895 #define _UART_IRCTRL_IRPRSSEL_PRSCH2 0x00000002UL 03896 #define _UART_IRCTRL_IRPRSSEL_PRSCH3 0x00000003UL 03897 #define _UART_IRCTRL_IRPRSSEL_PRSCH4 0x00000004UL 03898 #define _UART_IRCTRL_IRPRSSEL_PRSCH5 0x00000005UL 03899 #define _UART_IRCTRL_IRPRSSEL_PRSCH6 0x00000006UL 03900 #define _UART_IRCTRL_IRPRSSEL_PRSCH7 0x00000007UL 03901 #define UART_IRCTRL_IRPRSSEL_DEFAULT (_UART_IRCTRL_IRPRSSEL_DEFAULT << 4) 03902 #define UART_IRCTRL_IRPRSSEL_PRSCH0 (_UART_IRCTRL_IRPRSSEL_PRSCH0 << 4) 03903 #define UART_IRCTRL_IRPRSSEL_PRSCH1 (_UART_IRCTRL_IRPRSSEL_PRSCH1 << 4) 03904 #define UART_IRCTRL_IRPRSSEL_PRSCH2 (_UART_IRCTRL_IRPRSSEL_PRSCH2 << 4) 03905 #define UART_IRCTRL_IRPRSSEL_PRSCH3 (_UART_IRCTRL_IRPRSSEL_PRSCH3 << 4) 03906 #define UART_IRCTRL_IRPRSSEL_PRSCH4 (_UART_IRCTRL_IRPRSSEL_PRSCH4 << 4) 03907 #define UART_IRCTRL_IRPRSSEL_PRSCH5 (_UART_IRCTRL_IRPRSSEL_PRSCH5 << 4) 03908 #define UART_IRCTRL_IRPRSSEL_PRSCH6 (_UART_IRCTRL_IRPRSSEL_PRSCH6 << 4) 03909 #define UART_IRCTRL_IRPRSSEL_PRSCH7 (_UART_IRCTRL_IRPRSSEL_PRSCH7 << 4) 03910 #define UART_IRCTRL_IRPRSEN (0x1UL << 7) 03911 #define _UART_IRCTRL_IRPRSEN_SHIFT 7 03912 #define _UART_IRCTRL_IRPRSEN_MASK 0x80UL 03913 #define _UART_IRCTRL_IRPRSEN_DEFAULT 0x00000000UL 03914 #define UART_IRCTRL_IRPRSEN_DEFAULT (_UART_IRCTRL_IRPRSEN_DEFAULT << 7) 03916 /* Bit fields for UART ROUTE */ 03917 #define _UART_ROUTE_RESETVALUE 0x00000000UL 03918 #define _UART_ROUTE_MASK 0x0000030FUL 03919 #define UART_ROUTE_RXPEN (0x1UL << 0) 03920 #define _UART_ROUTE_RXPEN_SHIFT 0 03921 #define _UART_ROUTE_RXPEN_MASK 0x1UL 03922 #define _UART_ROUTE_RXPEN_DEFAULT 0x00000000UL 03923 #define UART_ROUTE_RXPEN_DEFAULT (_UART_ROUTE_RXPEN_DEFAULT << 0) 03924 #define UART_ROUTE_TXPEN (0x1UL << 1) 03925 #define _UART_ROUTE_TXPEN_SHIFT 1 03926 #define _UART_ROUTE_TXPEN_MASK 0x2UL 03927 #define _UART_ROUTE_TXPEN_DEFAULT 0x00000000UL 03928 #define UART_ROUTE_TXPEN_DEFAULT (_UART_ROUTE_TXPEN_DEFAULT << 1) 03929 #define UART_ROUTE_CSPEN (0x1UL << 2) 03930 #define _UART_ROUTE_CSPEN_SHIFT 2 03931 #define _UART_ROUTE_CSPEN_MASK 0x4UL 03932 #define _UART_ROUTE_CSPEN_DEFAULT 0x00000000UL 03933 #define UART_ROUTE_CSPEN_DEFAULT (_UART_ROUTE_CSPEN_DEFAULT << 2) 03934 #define UART_ROUTE_CLKPEN (0x1UL << 3) 03935 #define _UART_ROUTE_CLKPEN_SHIFT 3 03936 #define _UART_ROUTE_CLKPEN_MASK 0x8UL 03937 #define _UART_ROUTE_CLKPEN_DEFAULT 0x00000000UL 03938 #define UART_ROUTE_CLKPEN_DEFAULT (_UART_ROUTE_CLKPEN_DEFAULT << 3) 03939 #define _UART_ROUTE_LOCATION_SHIFT 8 03940 #define _UART_ROUTE_LOCATION_MASK 0x300UL 03941 #define _UART_ROUTE_LOCATION_DEFAULT 0x00000000UL 03942 #define _UART_ROUTE_LOCATION_LOC0 0x00000000UL 03943 #define _UART_ROUTE_LOCATION_LOC1 0x00000001UL 03944 #define _UART_ROUTE_LOCATION_LOC2 0x00000002UL 03945 #define _UART_ROUTE_LOCATION_LOC3 0x00000003UL 03946 #define UART_ROUTE_LOCATION_DEFAULT (_UART_ROUTE_LOCATION_DEFAULT << 8) 03947 #define UART_ROUTE_LOCATION_LOC0 (_UART_ROUTE_LOCATION_LOC0 << 8) 03948 #define UART_ROUTE_LOCATION_LOC1 (_UART_ROUTE_LOCATION_LOC1 << 8) 03949 #define UART_ROUTE_LOCATION_LOC2 (_UART_ROUTE_LOCATION_LOC2 << 8) 03950 #define UART_ROUTE_LOCATION_LOC3 (_UART_ROUTE_LOCATION_LOC3 << 8) 03956 /**************************************************************************/ 03961 /* Bit fields for LEUART CTRL */ 03962 #define _LEUART_CTRL_RESETVALUE 0x00000000UL 03963 #define _LEUART_CTRL_MASK 0x0000FFFFUL 03964 #define LEUART_CTRL_AUTOTRI (0x1UL << 0) 03965 #define _LEUART_CTRL_AUTOTRI_SHIFT 0 03966 #define _LEUART_CTRL_AUTOTRI_MASK 0x1UL 03967 #define _LEUART_CTRL_AUTOTRI_DEFAULT 0x00000000UL 03968 #define LEUART_CTRL_AUTOTRI_DEFAULT (_LEUART_CTRL_AUTOTRI_DEFAULT << 0) 03969 #define LEUART_CTRL_DATABITS (0x1UL << 1) 03970 #define _LEUART_CTRL_DATABITS_SHIFT 1 03971 #define _LEUART_CTRL_DATABITS_MASK 0x2UL 03972 #define _LEUART_CTRL_DATABITS_DEFAULT 0x00000000UL 03973 #define _LEUART_CTRL_DATABITS_EIGHT 0x00000000UL 03974 #define _LEUART_CTRL_DATABITS_NINE 0x00000001UL 03975 #define LEUART_CTRL_DATABITS_DEFAULT (_LEUART_CTRL_DATABITS_DEFAULT << 1) 03976 #define LEUART_CTRL_DATABITS_EIGHT (_LEUART_CTRL_DATABITS_EIGHT << 1) 03977 #define LEUART_CTRL_DATABITS_NINE (_LEUART_CTRL_DATABITS_NINE << 1) 03978 #define _LEUART_CTRL_PARITY_SHIFT 2 03979 #define _LEUART_CTRL_PARITY_MASK 0xCUL 03980 #define _LEUART_CTRL_PARITY_DEFAULT 0x00000000UL 03981 #define _LEUART_CTRL_PARITY_NONE 0x00000000UL 03982 #define _LEUART_CTRL_PARITY_EVEN 0x00000002UL 03983 #define _LEUART_CTRL_PARITY_ODD 0x00000003UL 03984 #define LEUART_CTRL_PARITY_DEFAULT (_LEUART_CTRL_PARITY_DEFAULT << 2) 03985 #define LEUART_CTRL_PARITY_NONE (_LEUART_CTRL_PARITY_NONE << 2) 03986 #define LEUART_CTRL_PARITY_EVEN (_LEUART_CTRL_PARITY_EVEN << 2) 03987 #define LEUART_CTRL_PARITY_ODD (_LEUART_CTRL_PARITY_ODD << 2) 03988 #define LEUART_CTRL_STOPBITS (0x1UL << 4) 03989 #define _LEUART_CTRL_STOPBITS_SHIFT 4 03990 #define _LEUART_CTRL_STOPBITS_MASK 0x10UL 03991 #define _LEUART_CTRL_STOPBITS_DEFAULT 0x00000000UL 03992 #define _LEUART_CTRL_STOPBITS_ONE 0x00000000UL 03993 #define _LEUART_CTRL_STOPBITS_TWO 0x00000001UL 03994 #define LEUART_CTRL_STOPBITS_DEFAULT (_LEUART_CTRL_STOPBITS_DEFAULT << 4) 03995 #define LEUART_CTRL_STOPBITS_ONE (_LEUART_CTRL_STOPBITS_ONE << 4) 03996 #define LEUART_CTRL_STOPBITS_TWO (_LEUART_CTRL_STOPBITS_TWO << 4) 03997 #define LEUART_CTRL_INV (0x1UL << 5) 03998 #define _LEUART_CTRL_INV_SHIFT 5 03999 #define _LEUART_CTRL_INV_MASK 0x20UL 04000 #define _LEUART_CTRL_INV_DEFAULT 0x00000000UL 04001 #define LEUART_CTRL_INV_DEFAULT (_LEUART_CTRL_INV_DEFAULT << 5) 04002 #define LEUART_CTRL_ERRSDMA (0x1UL << 6) 04003 #define _LEUART_CTRL_ERRSDMA_SHIFT 6 04004 #define _LEUART_CTRL_ERRSDMA_MASK 0x40UL 04005 #define _LEUART_CTRL_ERRSDMA_DEFAULT 0x00000000UL 04006 #define LEUART_CTRL_ERRSDMA_DEFAULT (_LEUART_CTRL_ERRSDMA_DEFAULT << 6) 04007 #define LEUART_CTRL_LOOPBK (0x1UL << 7) 04008 #define _LEUART_CTRL_LOOPBK_SHIFT 7 04009 #define _LEUART_CTRL_LOOPBK_MASK 0x80UL 04010 #define _LEUART_CTRL_LOOPBK_DEFAULT 0x00000000UL 04011 #define LEUART_CTRL_LOOPBK_DEFAULT (_LEUART_CTRL_LOOPBK_DEFAULT << 7) 04012 #define LEUART_CTRL_SFUBRX (0x1UL << 8) 04013 #define _LEUART_CTRL_SFUBRX_SHIFT 8 04014 #define _LEUART_CTRL_SFUBRX_MASK 0x100UL 04015 #define _LEUART_CTRL_SFUBRX_DEFAULT 0x00000000UL 04016 #define LEUART_CTRL_SFUBRX_DEFAULT (_LEUART_CTRL_SFUBRX_DEFAULT << 8) 04017 #define LEUART_CTRL_MPM (0x1UL << 9) 04018 #define _LEUART_CTRL_MPM_SHIFT 9 04019 #define _LEUART_CTRL_MPM_MASK 0x200UL 04020 #define _LEUART_CTRL_MPM_DEFAULT 0x00000000UL 04021 #define LEUART_CTRL_MPM_DEFAULT (_LEUART_CTRL_MPM_DEFAULT << 9) 04022 #define LEUART_CTRL_MPAB (0x1UL << 10) 04023 #define _LEUART_CTRL_MPAB_SHIFT 10 04024 #define _LEUART_CTRL_MPAB_MASK 0x400UL 04025 #define _LEUART_CTRL_MPAB_DEFAULT 0x00000000UL 04026 #define LEUART_CTRL_MPAB_DEFAULT (_LEUART_CTRL_MPAB_DEFAULT << 10) 04027 #define LEUART_CTRL_BIT8DV (0x1UL << 11) 04028 #define _LEUART_CTRL_BIT8DV_SHIFT 11 04029 #define _LEUART_CTRL_BIT8DV_MASK 0x800UL 04030 #define _LEUART_CTRL_BIT8DV_DEFAULT 0x00000000UL 04031 #define LEUART_CTRL_BIT8DV_DEFAULT (_LEUART_CTRL_BIT8DV_DEFAULT << 11) 04032 #define LEUART_CTRL_RXDMAWU (0x1UL << 12) 04033 #define _LEUART_CTRL_RXDMAWU_SHIFT 12 04034 #define _LEUART_CTRL_RXDMAWU_MASK 0x1000UL 04035 #define _LEUART_CTRL_RXDMAWU_DEFAULT 0x00000000UL 04036 #define LEUART_CTRL_RXDMAWU_DEFAULT (_LEUART_CTRL_RXDMAWU_DEFAULT << 12) 04037 #define LEUART_CTRL_TXDMAWU (0x1UL << 13) 04038 #define _LEUART_CTRL_TXDMAWU_SHIFT 13 04039 #define _LEUART_CTRL_TXDMAWU_MASK 0x2000UL 04040 #define _LEUART_CTRL_TXDMAWU_DEFAULT 0x00000000UL 04041 #define LEUART_CTRL_TXDMAWU_DEFAULT (_LEUART_CTRL_TXDMAWU_DEFAULT << 13) 04042 #define _LEUART_CTRL_TXDELAY_SHIFT 14 04043 #define _LEUART_CTRL_TXDELAY_MASK 0xC000UL 04044 #define _LEUART_CTRL_TXDELAY_DEFAULT 0x00000000UL 04045 #define _LEUART_CTRL_TXDELAY_NONE 0x00000000UL 04046 #define _LEUART_CTRL_TXDELAY_SINGLE 0x00000001UL 04047 #define _LEUART_CTRL_TXDELAY_DOUBLE 0x00000002UL 04048 #define _LEUART_CTRL_TXDELAY_TRIPLE 0x00000003UL 04049 #define LEUART_CTRL_TXDELAY_DEFAULT (_LEUART_CTRL_TXDELAY_DEFAULT << 14) 04050 #define LEUART_CTRL_TXDELAY_NONE (_LEUART_CTRL_TXDELAY_NONE << 14) 04051 #define LEUART_CTRL_TXDELAY_SINGLE (_LEUART_CTRL_TXDELAY_SINGLE << 14) 04052 #define LEUART_CTRL_TXDELAY_DOUBLE (_LEUART_CTRL_TXDELAY_DOUBLE << 14) 04053 #define LEUART_CTRL_TXDELAY_TRIPLE (_LEUART_CTRL_TXDELAY_TRIPLE << 14) 04055 /* Bit fields for LEUART CMD */ 04056 #define _LEUART_CMD_RESETVALUE 0x00000000UL 04057 #define _LEUART_CMD_MASK 0x000000FFUL 04058 #define LEUART_CMD_RXEN (0x1UL << 0) 04059 #define _LEUART_CMD_RXEN_SHIFT 0 04060 #define _LEUART_CMD_RXEN_MASK 0x1UL 04061 #define _LEUART_CMD_RXEN_DEFAULT 0x00000000UL 04062 #define LEUART_CMD_RXEN_DEFAULT (_LEUART_CMD_RXEN_DEFAULT << 0) 04063 #define LEUART_CMD_RXDIS (0x1UL << 1) 04064 #define _LEUART_CMD_RXDIS_SHIFT 1 04065 #define _LEUART_CMD_RXDIS_MASK 0x2UL 04066 #define _LEUART_CMD_RXDIS_DEFAULT 0x00000000UL 04067 #define LEUART_CMD_RXDIS_DEFAULT (_LEUART_CMD_RXDIS_DEFAULT << 1) 04068 #define LEUART_CMD_TXEN (0x1UL << 2) 04069 #define _LEUART_CMD_TXEN_SHIFT 2 04070 #define _LEUART_CMD_TXEN_MASK 0x4UL 04071 #define _LEUART_CMD_TXEN_DEFAULT 0x00000000UL 04072 #define LEUART_CMD_TXEN_DEFAULT (_LEUART_CMD_TXEN_DEFAULT << 2) 04073 #define LEUART_CMD_TXDIS (0x1UL << 3) 04074 #define _LEUART_CMD_TXDIS_SHIFT 3 04075 #define _LEUART_CMD_TXDIS_MASK 0x8UL 04076 #define _LEUART_CMD_TXDIS_DEFAULT 0x00000000UL 04077 #define LEUART_CMD_TXDIS_DEFAULT (_LEUART_CMD_TXDIS_DEFAULT << 3) 04078 #define LEUART_CMD_RXBLOCKEN (0x1UL << 4) 04079 #define _LEUART_CMD_RXBLOCKEN_SHIFT 4 04080 #define _LEUART_CMD_RXBLOCKEN_MASK 0x10UL 04081 #define _LEUART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL 04082 #define LEUART_CMD_RXBLOCKEN_DEFAULT (_LEUART_CMD_RXBLOCKEN_DEFAULT << 4) 04083 #define LEUART_CMD_RXBLOCKDIS (0x1UL << 5) 04084 #define _LEUART_CMD_RXBLOCKDIS_SHIFT 5 04085 #define _LEUART_CMD_RXBLOCKDIS_MASK 0x20UL 04086 #define _LEUART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL 04087 #define LEUART_CMD_RXBLOCKDIS_DEFAULT (_LEUART_CMD_RXBLOCKDIS_DEFAULT << 5) 04088 #define LEUART_CMD_CLEARTX (0x1UL << 6) 04089 #define _LEUART_CMD_CLEARTX_SHIFT 6 04090 #define _LEUART_CMD_CLEARTX_MASK 0x40UL 04091 #define _LEUART_CMD_CLEARTX_DEFAULT 0x00000000UL 04092 #define LEUART_CMD_CLEARTX_DEFAULT (_LEUART_CMD_CLEARTX_DEFAULT << 6) 04093 #define LEUART_CMD_CLEARRX (0x1UL << 7) 04094 #define _LEUART_CMD_CLEARRX_SHIFT 7 04095 #define _LEUART_CMD_CLEARRX_MASK 0x80UL 04096 #define _LEUART_CMD_CLEARRX_DEFAULT 0x00000000UL 04097 #define LEUART_CMD_CLEARRX_DEFAULT (_LEUART_CMD_CLEARRX_DEFAULT << 7) 04099 /* Bit fields for LEUART STATUS */ 04100 #define _LEUART_STATUS_RESETVALUE 0x00000010UL 04101 #define _LEUART_STATUS_MASK 0x0000003FUL 04102 #define LEUART_STATUS_RXENS (0x1UL << 0) 04103 #define _LEUART_STATUS_RXENS_SHIFT 0 04104 #define _LEUART_STATUS_RXENS_MASK 0x1UL 04105 #define _LEUART_STATUS_RXENS_DEFAULT 0x00000000UL 04106 #define LEUART_STATUS_RXENS_DEFAULT (_LEUART_STATUS_RXENS_DEFAULT << 0) 04107 #define LEUART_STATUS_TXENS (0x1UL << 1) 04108 #define _LEUART_STATUS_TXENS_SHIFT 1 04109 #define _LEUART_STATUS_TXENS_MASK 0x2UL 04110 #define _LEUART_STATUS_TXENS_DEFAULT 0x00000000UL 04111 #define LEUART_STATUS_TXENS_DEFAULT (_LEUART_STATUS_TXENS_DEFAULT << 1) 04112 #define LEUART_STATUS_RXBLOCK (0x1UL << 2) 04113 #define _LEUART_STATUS_RXBLOCK_SHIFT 2 04114 #define _LEUART_STATUS_RXBLOCK_MASK 0x4UL 04115 #define _LEUART_STATUS_RXBLOCK_DEFAULT 0x00000000UL 04116 #define LEUART_STATUS_RXBLOCK_DEFAULT (_LEUART_STATUS_RXBLOCK_DEFAULT << 2) 04117 #define LEUART_STATUS_TXC (0x1UL << 3) 04118 #define _LEUART_STATUS_TXC_SHIFT 3 04119 #define _LEUART_STATUS_TXC_MASK 0x8UL 04120 #define _LEUART_STATUS_TXC_DEFAULT 0x00000000UL 04121 #define LEUART_STATUS_TXC_DEFAULT (_LEUART_STATUS_TXC_DEFAULT << 3) 04122 #define LEUART_STATUS_TXBL (0x1UL << 4) 04123 #define _LEUART_STATUS_TXBL_SHIFT 4 04124 #define _LEUART_STATUS_TXBL_MASK 0x10UL 04125 #define _LEUART_STATUS_TXBL_DEFAULT 0x00000001UL 04126 #define LEUART_STATUS_TXBL_DEFAULT (_LEUART_STATUS_TXBL_DEFAULT << 4) 04127 #define LEUART_STATUS_RXDATAV (0x1UL << 5) 04128 #define _LEUART_STATUS_RXDATAV_SHIFT 5 04129 #define _LEUART_STATUS_RXDATAV_MASK 0x20UL 04130 #define _LEUART_STATUS_RXDATAV_DEFAULT 0x00000000UL 04131 #define LEUART_STATUS_RXDATAV_DEFAULT (_LEUART_STATUS_RXDATAV_DEFAULT << 5) 04133 /* Bit fields for LEUART CLKDIV */ 04134 #define _LEUART_CLKDIV_RESETVALUE 0x00000000UL 04135 #define _LEUART_CLKDIV_MASK 0x00007FF8UL 04136 #define _LEUART_CLKDIV_DIV_SHIFT 3 04137 #define _LEUART_CLKDIV_DIV_MASK 0x7FF8UL 04138 #define _LEUART_CLKDIV_DIV_DEFAULT 0x00000000UL 04139 #define LEUART_CLKDIV_DIV_DEFAULT (_LEUART_CLKDIV_DIV_DEFAULT << 3) 04141 /* Bit fields for LEUART STARTFRAME */ 04142 #define _LEUART_STARTFRAME_RESETVALUE 0x00000000UL 04143 #define _LEUART_STARTFRAME_MASK 0x000001FFUL 04144 #define _LEUART_STARTFRAME_STARTFRAME_SHIFT 0 04145 #define _LEUART_STARTFRAME_STARTFRAME_MASK 0x1FFUL 04146 #define _LEUART_STARTFRAME_STARTFRAME_DEFAULT 0x00000000UL 04147 #define LEUART_STARTFRAME_STARTFRAME_DEFAULT (_LEUART_STARTFRAME_STARTFRAME_DEFAULT << 0) 04149 /* Bit fields for LEUART SIGFRAME */ 04150 #define _LEUART_SIGFRAME_RESETVALUE 0x00000000UL 04151 #define _LEUART_SIGFRAME_MASK 0x000001FFUL 04152 #define _LEUART_SIGFRAME_SIGFRAME_SHIFT 0 04153 #define _LEUART_SIGFRAME_SIGFRAME_MASK 0x1FFUL 04154 #define _LEUART_SIGFRAME_SIGFRAME_DEFAULT 0x00000000UL 04155 #define LEUART_SIGFRAME_SIGFRAME_DEFAULT (_LEUART_SIGFRAME_SIGFRAME_DEFAULT << 0) 04157 /* Bit fields for LEUART RXDATAX */ 04158 #define _LEUART_RXDATAX_RESETVALUE 0x00000000UL 04159 #define _LEUART_RXDATAX_MASK 0x0000C1FFUL 04160 #define _LEUART_RXDATAX_RXDATA_SHIFT 0 04161 #define _LEUART_RXDATAX_RXDATA_MASK 0x1FFUL 04162 #define _LEUART_RXDATAX_RXDATA_DEFAULT 0x00000000UL 04163 #define LEUART_RXDATAX_RXDATA_DEFAULT (_LEUART_RXDATAX_RXDATA_DEFAULT << 0) 04164 #define LEUART_RXDATAX_PERR (0x1UL << 14) 04165 #define _LEUART_RXDATAX_PERR_SHIFT 14 04166 #define _LEUART_RXDATAX_PERR_MASK 0x4000UL 04167 #define _LEUART_RXDATAX_PERR_DEFAULT 0x00000000UL 04168 #define LEUART_RXDATAX_PERR_DEFAULT (_LEUART_RXDATAX_PERR_DEFAULT << 14) 04169 #define LEUART_RXDATAX_FERR (0x1UL << 15) 04170 #define _LEUART_RXDATAX_FERR_SHIFT 15 04171 #define _LEUART_RXDATAX_FERR_MASK 0x8000UL 04172 #define _LEUART_RXDATAX_FERR_DEFAULT 0x00000000UL 04173 #define LEUART_RXDATAX_FERR_DEFAULT (_LEUART_RXDATAX_FERR_DEFAULT << 15) 04175 /* Bit fields for LEUART RXDATA */ 04176 #define _LEUART_RXDATA_RESETVALUE 0x00000000UL 04177 #define _LEUART_RXDATA_MASK 0x000000FFUL 04178 #define _LEUART_RXDATA_RXDATA_SHIFT 0 04179 #define _LEUART_RXDATA_RXDATA_MASK 0xFFUL 04180 #define _LEUART_RXDATA_RXDATA_DEFAULT 0x00000000UL 04181 #define LEUART_RXDATA_RXDATA_DEFAULT (_LEUART_RXDATA_RXDATA_DEFAULT << 0) 04183 /* Bit fields for LEUART RXDATAXP */ 04184 #define _LEUART_RXDATAXP_RESETVALUE 0x00000000UL 04185 #define _LEUART_RXDATAXP_MASK 0x0000C1FFUL 04186 #define _LEUART_RXDATAXP_RXDATAP_SHIFT 0 04187 #define _LEUART_RXDATAXP_RXDATAP_MASK 0x1FFUL 04188 #define _LEUART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL 04189 #define LEUART_RXDATAXP_RXDATAP_DEFAULT (_LEUART_RXDATAXP_RXDATAP_DEFAULT << 0) 04190 #define LEUART_RXDATAXP_PERRP (0x1UL << 14) 04191 #define _LEUART_RXDATAXP_PERRP_SHIFT 14 04192 #define _LEUART_RXDATAXP_PERRP_MASK 0x4000UL 04193 #define _LEUART_RXDATAXP_PERRP_DEFAULT 0x00000000UL 04194 #define LEUART_RXDATAXP_PERRP_DEFAULT (_LEUART_RXDATAXP_PERRP_DEFAULT << 14) 04195 #define LEUART_RXDATAXP_FERRP (0x1UL << 15) 04196 #define _LEUART_RXDATAXP_FERRP_SHIFT 15 04197 #define _LEUART_RXDATAXP_FERRP_MASK 0x8000UL 04198 #define _LEUART_RXDATAXP_FERRP_DEFAULT 0x00000000UL 04199 #define LEUART_RXDATAXP_FERRP_DEFAULT (_LEUART_RXDATAXP_FERRP_DEFAULT << 15) 04201 /* Bit fields for LEUART TXDATAX */ 04202 #define _LEUART_TXDATAX_RESETVALUE 0x00000000UL 04203 #define _LEUART_TXDATAX_MASK 0x0000E1FFUL 04204 #define _LEUART_TXDATAX_TXDATA_SHIFT 0 04205 #define _LEUART_TXDATAX_TXDATA_MASK 0x1FFUL 04206 #define _LEUART_TXDATAX_TXDATA_DEFAULT 0x00000000UL 04207 #define LEUART_TXDATAX_TXDATA_DEFAULT (_LEUART_TXDATAX_TXDATA_DEFAULT << 0) 04208 #define LEUART_TXDATAX_TXBREAK (0x1UL << 13) 04209 #define _LEUART_TXDATAX_TXBREAK_SHIFT 13 04210 #define _LEUART_TXDATAX_TXBREAK_MASK 0x2000UL 04211 #define _LEUART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL 04212 #define LEUART_TXDATAX_TXBREAK_DEFAULT (_LEUART_TXDATAX_TXBREAK_DEFAULT << 13) 04213 #define LEUART_TXDATAX_TXDISAT (0x1UL << 14) 04214 #define _LEUART_TXDATAX_TXDISAT_SHIFT 14 04215 #define _LEUART_TXDATAX_TXDISAT_MASK 0x4000UL 04216 #define _LEUART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL 04217 #define LEUART_TXDATAX_TXDISAT_DEFAULT (_LEUART_TXDATAX_TXDISAT_DEFAULT << 14) 04218 #define LEUART_TXDATAX_RXENAT (0x1UL << 15) 04219 #define _LEUART_TXDATAX_RXENAT_SHIFT 15 04220 #define _LEUART_TXDATAX_RXENAT_MASK 0x8000UL 04221 #define _LEUART_TXDATAX_RXENAT_DEFAULT 0x00000000UL 04222 #define LEUART_TXDATAX_RXENAT_DEFAULT (_LEUART_TXDATAX_RXENAT_DEFAULT << 15) 04224 /* Bit fields for LEUART TXDATA */ 04225 #define _LEUART_TXDATA_RESETVALUE 0x00000000UL 04226 #define _LEUART_TXDATA_MASK 0x000000FFUL 04227 #define _LEUART_TXDATA_TXDATA_SHIFT 0 04228 #define _LEUART_TXDATA_TXDATA_MASK 0xFFUL 04229 #define _LEUART_TXDATA_TXDATA_DEFAULT 0x00000000UL 04230 #define LEUART_TXDATA_TXDATA_DEFAULT (_LEUART_TXDATA_TXDATA_DEFAULT << 0) 04232 /* Bit fields for LEUART IF */ 04233 #define _LEUART_IF_RESETVALUE 0x00000002UL 04234 #define _LEUART_IF_MASK 0x000007FFUL 04235 #define LEUART_IF_TXC (0x1UL << 0) 04236 #define _LEUART_IF_TXC_SHIFT 0 04237 #define _LEUART_IF_TXC_MASK 0x1UL 04238 #define _LEUART_IF_TXC_DEFAULT 0x00000000UL 04239 #define LEUART_IF_TXC_DEFAULT (_LEUART_IF_TXC_DEFAULT << 0) 04240 #define LEUART_IF_TXBL (0x1UL << 1) 04241 #define _LEUART_IF_TXBL_SHIFT 1 04242 #define _LEUART_IF_TXBL_MASK 0x2UL 04243 #define _LEUART_IF_TXBL_DEFAULT 0x00000001UL 04244 #define LEUART_IF_TXBL_DEFAULT (_LEUART_IF_TXBL_DEFAULT << 1) 04245 #define LEUART_IF_RXDATAV (0x1UL << 2) 04246 #define _LEUART_IF_RXDATAV_SHIFT 2 04247 #define _LEUART_IF_RXDATAV_MASK 0x4UL 04248 #define _LEUART_IF_RXDATAV_DEFAULT 0x00000000UL 04249 #define LEUART_IF_RXDATAV_DEFAULT (_LEUART_IF_RXDATAV_DEFAULT << 2) 04250 #define LEUART_IF_RXOF (0x1UL << 3) 04251 #define _LEUART_IF_RXOF_SHIFT 3 04252 #define _LEUART_IF_RXOF_MASK 0x8UL 04253 #define _LEUART_IF_RXOF_DEFAULT 0x00000000UL 04254 #define LEUART_IF_RXOF_DEFAULT (_LEUART_IF_RXOF_DEFAULT << 3) 04255 #define LEUART_IF_RXUF (0x1UL << 4) 04256 #define _LEUART_IF_RXUF_SHIFT 4 04257 #define _LEUART_IF_RXUF_MASK 0x10UL 04258 #define _LEUART_IF_RXUF_DEFAULT 0x00000000UL 04259 #define LEUART_IF_RXUF_DEFAULT (_LEUART_IF_RXUF_DEFAULT << 4) 04260 #define LEUART_IF_TXOF (0x1UL << 5) 04261 #define _LEUART_IF_TXOF_SHIFT 5 04262 #define _LEUART_IF_TXOF_MASK 0x20UL 04263 #define _LEUART_IF_TXOF_DEFAULT 0x00000000UL 04264 #define LEUART_IF_TXOF_DEFAULT (_LEUART_IF_TXOF_DEFAULT << 5) 04265 #define LEUART_IF_PERR (0x1UL << 6) 04266 #define _LEUART_IF_PERR_SHIFT 6 04267 #define _LEUART_IF_PERR_MASK 0x40UL 04268 #define _LEUART_IF_PERR_DEFAULT 0x00000000UL 04269 #define LEUART_IF_PERR_DEFAULT (_LEUART_IF_PERR_DEFAULT << 6) 04270 #define LEUART_IF_FERR (0x1UL << 7) 04271 #define _LEUART_IF_FERR_SHIFT 7 04272 #define _LEUART_IF_FERR_MASK 0x80UL 04273 #define _LEUART_IF_FERR_DEFAULT 0x00000000UL 04274 #define LEUART_IF_FERR_DEFAULT (_LEUART_IF_FERR_DEFAULT << 7) 04275 #define LEUART_IF_MPAF (0x1UL << 8) 04276 #define _LEUART_IF_MPAF_SHIFT 8 04277 #define _LEUART_IF_MPAF_MASK 0x100UL 04278 #define _LEUART_IF_MPAF_DEFAULT 0x00000000UL 04279 #define LEUART_IF_MPAF_DEFAULT (_LEUART_IF_MPAF_DEFAULT << 8) 04280 #define LEUART_IF_STARTF (0x1UL << 9) 04281 #define _LEUART_IF_STARTF_SHIFT 9 04282 #define _LEUART_IF_STARTF_MASK 0x200UL 04283 #define _LEUART_IF_STARTF_DEFAULT 0x00000000UL 04284 #define LEUART_IF_STARTF_DEFAULT (_LEUART_IF_STARTF_DEFAULT << 9) 04285 #define LEUART_IF_SIGF (0x1UL << 10) 04286 #define _LEUART_IF_SIGF_SHIFT 10 04287 #define _LEUART_IF_SIGF_MASK 0x400UL 04288 #define _LEUART_IF_SIGF_DEFAULT 0x00000000UL 04289 #define LEUART_IF_SIGF_DEFAULT (_LEUART_IF_SIGF_DEFAULT << 10) 04291 /* Bit fields for LEUART IFS */ 04292 #define _LEUART_IFS_RESETVALUE 0x00000000UL 04293 #define _LEUART_IFS_MASK 0x000007F9UL 04294 #define LEUART_IFS_TXC (0x1UL << 0) 04295 #define _LEUART_IFS_TXC_SHIFT 0 04296 #define _LEUART_IFS_TXC_MASK 0x1UL 04297 #define _LEUART_IFS_TXC_DEFAULT 0x00000000UL 04298 #define LEUART_IFS_TXC_DEFAULT (_LEUART_IFS_TXC_DEFAULT << 0) 04299 #define LEUART_IFS_RXOF (0x1UL << 3) 04300 #define _LEUART_IFS_RXOF_SHIFT 3 04301 #define _LEUART_IFS_RXOF_MASK 0x8UL 04302 #define _LEUART_IFS_RXOF_DEFAULT 0x00000000UL 04303 #define LEUART_IFS_RXOF_DEFAULT (_LEUART_IFS_RXOF_DEFAULT << 3) 04304 #define LEUART_IFS_RXUF (0x1UL << 4) 04305 #define _LEUART_IFS_RXUF_SHIFT 4 04306 #define _LEUART_IFS_RXUF_MASK 0x10UL 04307 #define _LEUART_IFS_RXUF_DEFAULT 0x00000000UL 04308 #define LEUART_IFS_RXUF_DEFAULT (_LEUART_IFS_RXUF_DEFAULT << 4) 04309 #define LEUART_IFS_TXOF (0x1UL << 5) 04310 #define _LEUART_IFS_TXOF_SHIFT 5 04311 #define _LEUART_IFS_TXOF_MASK 0x20UL 04312 #define _LEUART_IFS_TXOF_DEFAULT 0x00000000UL 04313 #define LEUART_IFS_TXOF_DEFAULT (_LEUART_IFS_TXOF_DEFAULT << 5) 04314 #define LEUART_IFS_PERR (0x1UL << 6) 04315 #define _LEUART_IFS_PERR_SHIFT 6 04316 #define _LEUART_IFS_PERR_MASK 0x40UL 04317 #define _LEUART_IFS_PERR_DEFAULT 0x00000000UL 04318 #define LEUART_IFS_PERR_DEFAULT (_LEUART_IFS_PERR_DEFAULT << 6) 04319 #define LEUART_IFS_FERR (0x1UL << 7) 04320 #define _LEUART_IFS_FERR_SHIFT 7 04321 #define _LEUART_IFS_FERR_MASK 0x80UL 04322 #define _LEUART_IFS_FERR_DEFAULT 0x00000000UL 04323 #define LEUART_IFS_FERR_DEFAULT (_LEUART_IFS_FERR_DEFAULT << 7) 04324 #define LEUART_IFS_MPAF (0x1UL << 8) 04325 #define _LEUART_IFS_MPAF_SHIFT 8 04326 #define _LEUART_IFS_MPAF_MASK 0x100UL 04327 #define _LEUART_IFS_MPAF_DEFAULT 0x00000000UL 04328 #define LEUART_IFS_MPAF_DEFAULT (_LEUART_IFS_MPAF_DEFAULT << 8) 04329 #define LEUART_IFS_STARTF (0x1UL << 9) 04330 #define _LEUART_IFS_STARTF_SHIFT 9 04331 #define _LEUART_IFS_STARTF_MASK 0x200UL 04332 #define _LEUART_IFS_STARTF_DEFAULT 0x00000000UL 04333 #define LEUART_IFS_STARTF_DEFAULT (_LEUART_IFS_STARTF_DEFAULT << 9) 04334 #define LEUART_IFS_SIGF (0x1UL << 10) 04335 #define _LEUART_IFS_SIGF_SHIFT 10 04336 #define _LEUART_IFS_SIGF_MASK 0x400UL 04337 #define _LEUART_IFS_SIGF_DEFAULT 0x00000000UL 04338 #define LEUART_IFS_SIGF_DEFAULT (_LEUART_IFS_SIGF_DEFAULT << 10) 04340 /* Bit fields for LEUART IFC */ 04341 #define _LEUART_IFC_RESETVALUE 0x00000000UL 04342 #define _LEUART_IFC_MASK 0x000007F9UL 04343 #define LEUART_IFC_TXC (0x1UL << 0) 04344 #define _LEUART_IFC_TXC_SHIFT 0 04345 #define _LEUART_IFC_TXC_MASK 0x1UL 04346 #define _LEUART_IFC_TXC_DEFAULT 0x00000000UL 04347 #define LEUART_IFC_TXC_DEFAULT (_LEUART_IFC_TXC_DEFAULT << 0) 04348 #define LEUART_IFC_RXOF (0x1UL << 3) 04349 #define _LEUART_IFC_RXOF_SHIFT 3 04350 #define _LEUART_IFC_RXOF_MASK 0x8UL 04351 #define _LEUART_IFC_RXOF_DEFAULT 0x00000000UL 04352 #define LEUART_IFC_RXOF_DEFAULT (_LEUART_IFC_RXOF_DEFAULT << 3) 04353 #define LEUART_IFC_RXUF (0x1UL << 4) 04354 #define _LEUART_IFC_RXUF_SHIFT 4 04355 #define _LEUART_IFC_RXUF_MASK 0x10UL 04356 #define _LEUART_IFC_RXUF_DEFAULT 0x00000000UL 04357 #define LEUART_IFC_RXUF_DEFAULT (_LEUART_IFC_RXUF_DEFAULT << 4) 04358 #define LEUART_IFC_TXOF (0x1UL << 5) 04359 #define _LEUART_IFC_TXOF_SHIFT 5 04360 #define _LEUART_IFC_TXOF_MASK 0x20UL 04361 #define _LEUART_IFC_TXOF_DEFAULT 0x00000000UL 04362 #define LEUART_IFC_TXOF_DEFAULT (_LEUART_IFC_TXOF_DEFAULT << 5) 04363 #define LEUART_IFC_PERR (0x1UL << 6) 04364 #define _LEUART_IFC_PERR_SHIFT 6 04365 #define _LEUART_IFC_PERR_MASK 0x40UL 04366 #define _LEUART_IFC_PERR_DEFAULT 0x00000000UL 04367 #define LEUART_IFC_PERR_DEFAULT (_LEUART_IFC_PERR_DEFAULT << 6) 04368 #define LEUART_IFC_FERR (0x1UL << 7) 04369 #define _LEUART_IFC_FERR_SHIFT 7 04370 #define _LEUART_IFC_FERR_MASK 0x80UL 04371 #define _LEUART_IFC_FERR_DEFAULT 0x00000000UL 04372 #define LEUART_IFC_FERR_DEFAULT (_LEUART_IFC_FERR_DEFAULT << 7) 04373 #define LEUART_IFC_MPAF (0x1UL << 8) 04374 #define _LEUART_IFC_MPAF_SHIFT 8 04375 #define _LEUART_IFC_MPAF_MASK 0x100UL 04376 #define _LEUART_IFC_MPAF_DEFAULT 0x00000000UL 04377 #define LEUART_IFC_MPAF_DEFAULT (_LEUART_IFC_MPAF_DEFAULT << 8) 04378 #define LEUART_IFC_STARTF (0x1UL << 9) 04379 #define _LEUART_IFC_STARTF_SHIFT 9 04380 #define _LEUART_IFC_STARTF_MASK 0x200UL 04381 #define _LEUART_IFC_STARTF_DEFAULT 0x00000000UL 04382 #define LEUART_IFC_STARTF_DEFAULT (_LEUART_IFC_STARTF_DEFAULT << 9) 04383 #define LEUART_IFC_SIGF (0x1UL << 10) 04384 #define _LEUART_IFC_SIGF_SHIFT 10 04385 #define _LEUART_IFC_SIGF_MASK 0x400UL 04386 #define _LEUART_IFC_SIGF_DEFAULT 0x00000000UL 04387 #define LEUART_IFC_SIGF_DEFAULT (_LEUART_IFC_SIGF_DEFAULT << 10) 04389 /* Bit fields for LEUART IEN */ 04390 #define _LEUART_IEN_RESETVALUE 0x00000000UL 04391 #define _LEUART_IEN_MASK 0x000007FFUL 04392 #define LEUART_IEN_TXC (0x1UL << 0) 04393 #define _LEUART_IEN_TXC_SHIFT 0 04394 #define _LEUART_IEN_TXC_MASK 0x1UL 04395 #define _LEUART_IEN_TXC_DEFAULT 0x00000000UL 04396 #define LEUART_IEN_TXC_DEFAULT (_LEUART_IEN_TXC_DEFAULT << 0) 04397 #define LEUART_IEN_TXBL (0x1UL << 1) 04398 #define _LEUART_IEN_TXBL_SHIFT 1 04399 #define _LEUART_IEN_TXBL_MASK 0x2UL 04400 #define _LEUART_IEN_TXBL_DEFAULT 0x00000000UL 04401 #define LEUART_IEN_TXBL_DEFAULT (_LEUART_IEN_TXBL_DEFAULT << 1) 04402 #define LEUART_IEN_RXDATAV (0x1UL << 2) 04403 #define _LEUART_IEN_RXDATAV_SHIFT 2 04404 #define _LEUART_IEN_RXDATAV_MASK 0x4UL 04405 #define _LEUART_IEN_RXDATAV_DEFAULT 0x00000000UL 04406 #define LEUART_IEN_RXDATAV_DEFAULT (_LEUART_IEN_RXDATAV_DEFAULT << 2) 04407 #define LEUART_IEN_RXOF (0x1UL << 3) 04408 #define _LEUART_IEN_RXOF_SHIFT 3 04409 #define _LEUART_IEN_RXOF_MASK 0x8UL 04410 #define _LEUART_IEN_RXOF_DEFAULT 0x00000000UL 04411 #define LEUART_IEN_RXOF_DEFAULT (_LEUART_IEN_RXOF_DEFAULT << 3) 04412 #define LEUART_IEN_RXUF (0x1UL << 4) 04413 #define _LEUART_IEN_RXUF_SHIFT 4 04414 #define _LEUART_IEN_RXUF_MASK 0x10UL 04415 #define _LEUART_IEN_RXUF_DEFAULT 0x00000000UL 04416 #define LEUART_IEN_RXUF_DEFAULT (_LEUART_IEN_RXUF_DEFAULT << 4) 04417 #define LEUART_IEN_TXOF (0x1UL << 5) 04418 #define _LEUART_IEN_TXOF_SHIFT 5 04419 #define _LEUART_IEN_TXOF_MASK 0x20UL 04420 #define _LEUART_IEN_TXOF_DEFAULT 0x00000000UL 04421 #define LEUART_IEN_TXOF_DEFAULT (_LEUART_IEN_TXOF_DEFAULT << 5) 04422 #define LEUART_IEN_PERR (0x1UL << 6) 04423 #define _LEUART_IEN_PERR_SHIFT 6 04424 #define _LEUART_IEN_PERR_MASK 0x40UL 04425 #define _LEUART_IEN_PERR_DEFAULT 0x00000000UL 04426 #define LEUART_IEN_PERR_DEFAULT (_LEUART_IEN_PERR_DEFAULT << 6) 04427 #define LEUART_IEN_FERR (0x1UL << 7) 04428 #define _LEUART_IEN_FERR_SHIFT 7 04429 #define _LEUART_IEN_FERR_MASK 0x80UL 04430 #define _LEUART_IEN_FERR_DEFAULT 0x00000000UL 04431 #define LEUART_IEN_FERR_DEFAULT (_LEUART_IEN_FERR_DEFAULT << 7) 04432 #define LEUART_IEN_MPAF (0x1UL << 8) 04433 #define _LEUART_IEN_MPAF_SHIFT 8 04434 #define _LEUART_IEN_MPAF_MASK 0x100UL 04435 #define _LEUART_IEN_MPAF_DEFAULT 0x00000000UL 04436 #define LEUART_IEN_MPAF_DEFAULT (_LEUART_IEN_MPAF_DEFAULT << 8) 04437 #define LEUART_IEN_STARTF (0x1UL << 9) 04438 #define _LEUART_IEN_STARTF_SHIFT 9 04439 #define _LEUART_IEN_STARTF_MASK 0x200UL 04440 #define _LEUART_IEN_STARTF_DEFAULT 0x00000000UL 04441 #define LEUART_IEN_STARTF_DEFAULT (_LEUART_IEN_STARTF_DEFAULT << 9) 04442 #define LEUART_IEN_SIGF (0x1UL << 10) 04443 #define _LEUART_IEN_SIGF_SHIFT 10 04444 #define _LEUART_IEN_SIGF_MASK 0x400UL 04445 #define _LEUART_IEN_SIGF_DEFAULT 0x00000000UL 04446 #define LEUART_IEN_SIGF_DEFAULT (_LEUART_IEN_SIGF_DEFAULT << 10) 04448 /* Bit fields for LEUART PULSECTRL */ 04449 #define _LEUART_PULSECTRL_RESETVALUE 0x00000000UL 04450 #define _LEUART_PULSECTRL_MASK 0x0000003FUL 04451 #define _LEUART_PULSECTRL_PULSEW_SHIFT 0 04452 #define _LEUART_PULSECTRL_PULSEW_MASK 0xFUL 04453 #define _LEUART_PULSECTRL_PULSEW_DEFAULT 0x00000000UL 04454 #define LEUART_PULSECTRL_PULSEW_DEFAULT (_LEUART_PULSECTRL_PULSEW_DEFAULT << 0) 04455 #define LEUART_PULSECTRL_PULSEEN (0x1UL << 4) 04456 #define _LEUART_PULSECTRL_PULSEEN_SHIFT 4 04457 #define _LEUART_PULSECTRL_PULSEEN_MASK 0x10UL 04458 #define _LEUART_PULSECTRL_PULSEEN_DEFAULT 0x00000000UL 04459 #define LEUART_PULSECTRL_PULSEEN_DEFAULT (_LEUART_PULSECTRL_PULSEEN_DEFAULT << 4) 04460 #define LEUART_PULSECTRL_PULSEFILT (0x1UL << 5) 04461 #define _LEUART_PULSECTRL_PULSEFILT_SHIFT 5 04462 #define _LEUART_PULSECTRL_PULSEFILT_MASK 0x20UL 04463 #define _LEUART_PULSECTRL_PULSEFILT_DEFAULT 0x00000000UL 04464 #define LEUART_PULSECTRL_PULSEFILT_DEFAULT (_LEUART_PULSECTRL_PULSEFILT_DEFAULT << 5) 04466 /* Bit fields for LEUART FREEZE */ 04467 #define _LEUART_FREEZE_RESETVALUE 0x00000000UL 04468 #define _LEUART_FREEZE_MASK 0x00000001UL 04469 #define LEUART_FREEZE_REGFREEZE (0x1UL << 0) 04470 #define _LEUART_FREEZE_REGFREEZE_SHIFT 0 04471 #define _LEUART_FREEZE_REGFREEZE_MASK 0x1UL 04472 #define _LEUART_FREEZE_REGFREEZE_DEFAULT 0x00000000UL 04473 #define _LEUART_FREEZE_REGFREEZE_UPDATE 0x00000000UL 04474 #define _LEUART_FREEZE_REGFREEZE_FREEZE 0x00000001UL 04475 #define LEUART_FREEZE_REGFREEZE_DEFAULT (_LEUART_FREEZE_REGFREEZE_DEFAULT << 0) 04476 #define LEUART_FREEZE_REGFREEZE_UPDATE (_LEUART_FREEZE_REGFREEZE_UPDATE << 0) 04477 #define LEUART_FREEZE_REGFREEZE_FREEZE (_LEUART_FREEZE_REGFREEZE_FREEZE << 0) 04479 /* Bit fields for LEUART SYNCBUSY */ 04480 #define _LEUART_SYNCBUSY_RESETVALUE 0x00000000UL 04481 #define _LEUART_SYNCBUSY_MASK 0x000000FFUL 04482 #define LEUART_SYNCBUSY_CTRL (0x1UL << 0) 04483 #define _LEUART_SYNCBUSY_CTRL_SHIFT 0 04484 #define _LEUART_SYNCBUSY_CTRL_MASK 0x1UL 04485 #define _LEUART_SYNCBUSY_CTRL_DEFAULT 0x00000000UL 04486 #define LEUART_SYNCBUSY_CTRL_DEFAULT (_LEUART_SYNCBUSY_CTRL_DEFAULT << 0) 04487 #define LEUART_SYNCBUSY_CMD (0x1UL << 1) 04488 #define _LEUART_SYNCBUSY_CMD_SHIFT 1 04489 #define _LEUART_SYNCBUSY_CMD_MASK 0x2UL 04490 #define _LEUART_SYNCBUSY_CMD_DEFAULT 0x00000000UL 04491 #define LEUART_SYNCBUSY_CMD_DEFAULT (_LEUART_SYNCBUSY_CMD_DEFAULT << 1) 04492 #define LEUART_SYNCBUSY_CLKDIV (0x1UL << 2) 04493 #define _LEUART_SYNCBUSY_CLKDIV_SHIFT 2 04494 #define _LEUART_SYNCBUSY_CLKDIV_MASK 0x4UL 04495 #define _LEUART_SYNCBUSY_CLKDIV_DEFAULT 0x00000000UL 04496 #define LEUART_SYNCBUSY_CLKDIV_DEFAULT (_LEUART_SYNCBUSY_CLKDIV_DEFAULT << 2) 04497 #define LEUART_SYNCBUSY_STARTFRAME (0x1UL << 3) 04498 #define _LEUART_SYNCBUSY_STARTFRAME_SHIFT 3 04499 #define _LEUART_SYNCBUSY_STARTFRAME_MASK 0x8UL 04500 #define _LEUART_SYNCBUSY_STARTFRAME_DEFAULT 0x00000000UL 04501 #define LEUART_SYNCBUSY_STARTFRAME_DEFAULT (_LEUART_SYNCBUSY_STARTFRAME_DEFAULT << 3) 04502 #define LEUART_SYNCBUSY_SIGFRAME (0x1UL << 4) 04503 #define _LEUART_SYNCBUSY_SIGFRAME_SHIFT 4 04504 #define _LEUART_SYNCBUSY_SIGFRAME_MASK 0x10UL 04505 #define _LEUART_SYNCBUSY_SIGFRAME_DEFAULT 0x00000000UL 04506 #define LEUART_SYNCBUSY_SIGFRAME_DEFAULT (_LEUART_SYNCBUSY_SIGFRAME_DEFAULT << 4) 04507 #define LEUART_SYNCBUSY_TXDATAX (0x1UL << 5) 04508 #define _LEUART_SYNCBUSY_TXDATAX_SHIFT 5 04509 #define _LEUART_SYNCBUSY_TXDATAX_MASK 0x20UL 04510 #define _LEUART_SYNCBUSY_TXDATAX_DEFAULT 0x00000000UL 04511 #define LEUART_SYNCBUSY_TXDATAX_DEFAULT (_LEUART_SYNCBUSY_TXDATAX_DEFAULT << 5) 04512 #define LEUART_SYNCBUSY_TXDATA (0x1UL << 6) 04513 #define _LEUART_SYNCBUSY_TXDATA_SHIFT 6 04514 #define _LEUART_SYNCBUSY_TXDATA_MASK 0x40UL 04515 #define _LEUART_SYNCBUSY_TXDATA_DEFAULT 0x00000000UL 04516 #define LEUART_SYNCBUSY_TXDATA_DEFAULT (_LEUART_SYNCBUSY_TXDATA_DEFAULT << 6) 04517 #define LEUART_SYNCBUSY_PULSECTRL (0x1UL << 7) 04518 #define _LEUART_SYNCBUSY_PULSECTRL_SHIFT 7 04519 #define _LEUART_SYNCBUSY_PULSECTRL_MASK 0x80UL 04520 #define _LEUART_SYNCBUSY_PULSECTRL_DEFAULT 0x00000000UL 04521 #define LEUART_SYNCBUSY_PULSECTRL_DEFAULT (_LEUART_SYNCBUSY_PULSECTRL_DEFAULT << 7) 04523 /* Bit fields for LEUART ROUTE */ 04524 #define _LEUART_ROUTE_RESETVALUE 0x00000000UL 04525 #define _LEUART_ROUTE_MASK 0x00000303UL 04526 #define LEUART_ROUTE_RXPEN (0x1UL << 0) 04527 #define _LEUART_ROUTE_RXPEN_SHIFT 0 04528 #define _LEUART_ROUTE_RXPEN_MASK 0x1UL 04529 #define _LEUART_ROUTE_RXPEN_DEFAULT 0x00000000UL 04530 #define LEUART_ROUTE_RXPEN_DEFAULT (_LEUART_ROUTE_RXPEN_DEFAULT << 0) 04531 #define LEUART_ROUTE_TXPEN (0x1UL << 1) 04532 #define _LEUART_ROUTE_TXPEN_SHIFT 1 04533 #define _LEUART_ROUTE_TXPEN_MASK 0x2UL 04534 #define _LEUART_ROUTE_TXPEN_DEFAULT 0x00000000UL 04535 #define LEUART_ROUTE_TXPEN_DEFAULT (_LEUART_ROUTE_TXPEN_DEFAULT << 1) 04536 #define _LEUART_ROUTE_LOCATION_SHIFT 8 04537 #define _LEUART_ROUTE_LOCATION_MASK 0x300UL 04538 #define _LEUART_ROUTE_LOCATION_DEFAULT 0x00000000UL 04539 #define _LEUART_ROUTE_LOCATION_LOC0 0x00000000UL 04540 #define _LEUART_ROUTE_LOCATION_LOC1 0x00000001UL 04541 #define _LEUART_ROUTE_LOCATION_LOC2 0x00000002UL 04542 #define _LEUART_ROUTE_LOCATION_LOC3 0x00000003UL 04543 #define LEUART_ROUTE_LOCATION_DEFAULT (_LEUART_ROUTE_LOCATION_DEFAULT << 8) 04544 #define LEUART_ROUTE_LOCATION_LOC0 (_LEUART_ROUTE_LOCATION_LOC0 << 8) 04545 #define LEUART_ROUTE_LOCATION_LOC1 (_LEUART_ROUTE_LOCATION_LOC1 << 8) 04546 #define LEUART_ROUTE_LOCATION_LOC2 (_LEUART_ROUTE_LOCATION_LOC2 << 8) 04547 #define LEUART_ROUTE_LOCATION_LOC3 (_LEUART_ROUTE_LOCATION_LOC3 << 8) 04553 /**************************************************************************/ 04558 /* Bit fields for LETIMER CTRL */ 04559 #define _LETIMER_CTRL_RESETVALUE 0x00000000UL 04560 #define _LETIMER_CTRL_MASK 0x00001FFFUL 04561 #define _LETIMER_CTRL_REPMODE_SHIFT 0 04562 #define _LETIMER_CTRL_REPMODE_MASK 0x3UL 04563 #define _LETIMER_CTRL_REPMODE_DEFAULT 0x00000000UL 04564 #define _LETIMER_CTRL_REPMODE_FREE 0x00000000UL 04565 #define _LETIMER_CTRL_REPMODE_ONESHOT 0x00000001UL 04566 #define _LETIMER_CTRL_REPMODE_BUFFERED 0x00000002UL 04567 #define _LETIMER_CTRL_REPMODE_DOUBLE 0x00000003UL 04568 #define LETIMER_CTRL_REPMODE_DEFAULT (_LETIMER_CTRL_REPMODE_DEFAULT << 0) 04569 #define LETIMER_CTRL_REPMODE_FREE (_LETIMER_CTRL_REPMODE_FREE << 0) 04570 #define LETIMER_CTRL_REPMODE_ONESHOT (_LETIMER_CTRL_REPMODE_ONESHOT << 0) 04571 #define LETIMER_CTRL_REPMODE_BUFFERED (_LETIMER_CTRL_REPMODE_BUFFERED << 0) 04572 #define LETIMER_CTRL_REPMODE_DOUBLE (_LETIMER_CTRL_REPMODE_DOUBLE << 0) 04573 #define _LETIMER_CTRL_UFOA0_SHIFT 2 04574 #define _LETIMER_CTRL_UFOA0_MASK 0xCUL 04575 #define _LETIMER_CTRL_UFOA0_DEFAULT 0x00000000UL 04576 #define _LETIMER_CTRL_UFOA0_NONE 0x00000000UL 04577 #define _LETIMER_CTRL_UFOA0_TOGGLE 0x00000001UL 04578 #define _LETIMER_CTRL_UFOA0_PULSE 0x00000002UL 04579 #define _LETIMER_CTRL_UFOA0_PWM 0x00000003UL 04580 #define LETIMER_CTRL_UFOA0_DEFAULT (_LETIMER_CTRL_UFOA0_DEFAULT << 2) 04581 #define LETIMER_CTRL_UFOA0_NONE (_LETIMER_CTRL_UFOA0_NONE << 2) 04582 #define LETIMER_CTRL_UFOA0_TOGGLE (_LETIMER_CTRL_UFOA0_TOGGLE << 2) 04583 #define LETIMER_CTRL_UFOA0_PULSE (_LETIMER_CTRL_UFOA0_PULSE << 2) 04584 #define LETIMER_CTRL_UFOA0_PWM (_LETIMER_CTRL_UFOA0_PWM << 2) 04585 #define _LETIMER_CTRL_UFOA1_SHIFT 4 04586 #define _LETIMER_CTRL_UFOA1_MASK 0x30UL 04587 #define _LETIMER_CTRL_UFOA1_DEFAULT 0x00000000UL 04588 #define _LETIMER_CTRL_UFOA1_NONE 0x00000000UL 04589 #define _LETIMER_CTRL_UFOA1_TOGGLE 0x00000001UL 04590 #define _LETIMER_CTRL_UFOA1_PULSE 0x00000002UL 04591 #define _LETIMER_CTRL_UFOA1_PWM 0x00000003UL 04592 #define LETIMER_CTRL_UFOA1_DEFAULT (_LETIMER_CTRL_UFOA1_DEFAULT << 4) 04593 #define LETIMER_CTRL_UFOA1_NONE (_LETIMER_CTRL_UFOA1_NONE << 4) 04594 #define LETIMER_CTRL_UFOA1_TOGGLE (_LETIMER_CTRL_UFOA1_TOGGLE << 4) 04595 #define LETIMER_CTRL_UFOA1_PULSE (_LETIMER_CTRL_UFOA1_PULSE << 4) 04596 #define LETIMER_CTRL_UFOA1_PWM (_LETIMER_CTRL_UFOA1_PWM << 4) 04597 #define LETIMER_CTRL_OPOL0 (0x1UL << 6) 04598 #define _LETIMER_CTRL_OPOL0_SHIFT 6 04599 #define _LETIMER_CTRL_OPOL0_MASK 0x40UL 04600 #define _LETIMER_CTRL_OPOL0_DEFAULT 0x00000000UL 04601 #define LETIMER_CTRL_OPOL0_DEFAULT (_LETIMER_CTRL_OPOL0_DEFAULT << 6) 04602 #define LETIMER_CTRL_OPOL1 (0x1UL << 7) 04603 #define _LETIMER_CTRL_OPOL1_SHIFT 7 04604 #define _LETIMER_CTRL_OPOL1_MASK 0x80UL 04605 #define _LETIMER_CTRL_OPOL1_DEFAULT 0x00000000UL 04606 #define LETIMER_CTRL_OPOL1_DEFAULT (_LETIMER_CTRL_OPOL1_DEFAULT << 7) 04607 #define LETIMER_CTRL_BUFTOP (0x1UL << 8) 04608 #define _LETIMER_CTRL_BUFTOP_SHIFT 8 04609 #define _LETIMER_CTRL_BUFTOP_MASK 0x100UL 04610 #define _LETIMER_CTRL_BUFTOP_DEFAULT 0x00000000UL 04611 #define LETIMER_CTRL_BUFTOP_DEFAULT (_LETIMER_CTRL_BUFTOP_DEFAULT << 8) 04612 #define LETIMER_CTRL_COMP0TOP (0x1UL << 9) 04613 #define _LETIMER_CTRL_COMP0TOP_SHIFT 9 04614 #define _LETIMER_CTRL_COMP0TOP_MASK 0x200UL 04615 #define _LETIMER_CTRL_COMP0TOP_DEFAULT 0x00000000UL 04616 #define LETIMER_CTRL_COMP0TOP_DEFAULT (_LETIMER_CTRL_COMP0TOP_DEFAULT << 9) 04617 #define LETIMER_CTRL_RTCC0TEN (0x1UL << 10) 04618 #define _LETIMER_CTRL_RTCC0TEN_SHIFT 10 04619 #define _LETIMER_CTRL_RTCC0TEN_MASK 0x400UL 04620 #define _LETIMER_CTRL_RTCC0TEN_DEFAULT 0x00000000UL 04621 #define LETIMER_CTRL_RTCC0TEN_DEFAULT (_LETIMER_CTRL_RTCC0TEN_DEFAULT << 10) 04622 #define LETIMER_CTRL_RTCC1TEN (0x1UL << 11) 04623 #define _LETIMER_CTRL_RTCC1TEN_SHIFT 11 04624 #define _LETIMER_CTRL_RTCC1TEN_MASK 0x800UL 04625 #define _LETIMER_CTRL_RTCC1TEN_DEFAULT 0x00000000UL 04626 #define LETIMER_CTRL_RTCC1TEN_DEFAULT (_LETIMER_CTRL_RTCC1TEN_DEFAULT << 11) 04627 #define LETIMER_CTRL_DEBUGRUN (0x1UL << 12) 04628 #define _LETIMER_CTRL_DEBUGRUN_SHIFT 12 04629 #define _LETIMER_CTRL_DEBUGRUN_MASK 0x1000UL 04630 #define _LETIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL 04631 #define LETIMER_CTRL_DEBUGRUN_DEFAULT (_LETIMER_CTRL_DEBUGRUN_DEFAULT << 12) 04633 /* Bit fields for LETIMER CMD */ 04634 #define _LETIMER_CMD_RESETVALUE 0x00000000UL 04635 #define _LETIMER_CMD_MASK 0x0000001FUL 04636 #define LETIMER_CMD_START (0x1UL << 0) 04637 #define _LETIMER_CMD_START_SHIFT 0 04638 #define _LETIMER_CMD_START_MASK 0x1UL 04639 #define _LETIMER_CMD_START_DEFAULT 0x00000000UL 04640 #define LETIMER_CMD_START_DEFAULT (_LETIMER_CMD_START_DEFAULT << 0) 04641 #define LETIMER_CMD_STOP (0x1UL << 1) 04642 #define _LETIMER_CMD_STOP_SHIFT 1 04643 #define _LETIMER_CMD_STOP_MASK 0x2UL 04644 #define _LETIMER_CMD_STOP_DEFAULT 0x00000000UL 04645 #define LETIMER_CMD_STOP_DEFAULT (_LETIMER_CMD_STOP_DEFAULT << 1) 04646 #define LETIMER_CMD_CLEAR (0x1UL << 2) 04647 #define _LETIMER_CMD_CLEAR_SHIFT 2 04648 #define _LETIMER_CMD_CLEAR_MASK 0x4UL 04649 #define _LETIMER_CMD_CLEAR_DEFAULT 0x00000000UL 04650 #define LETIMER_CMD_CLEAR_DEFAULT (_LETIMER_CMD_CLEAR_DEFAULT << 2) 04651 #define LETIMER_CMD_CTO0 (0x1UL << 3) 04652 #define _LETIMER_CMD_CTO0_SHIFT 3 04653 #define _LETIMER_CMD_CTO0_MASK 0x8UL 04654 #define _LETIMER_CMD_CTO0_DEFAULT 0x00000000UL 04655 #define LETIMER_CMD_CTO0_DEFAULT (_LETIMER_CMD_CTO0_DEFAULT << 3) 04656 #define LETIMER_CMD_CTO1 (0x1UL << 4) 04657 #define _LETIMER_CMD_CTO1_SHIFT 4 04658 #define _LETIMER_CMD_CTO1_MASK 0x10UL 04659 #define _LETIMER_CMD_CTO1_DEFAULT 0x00000000UL 04660 #define LETIMER_CMD_CTO1_DEFAULT (_LETIMER_CMD_CTO1_DEFAULT << 4) 04662 /* Bit fields for LETIMER STATUS */ 04663 #define _LETIMER_STATUS_RESETVALUE 0x00000000UL 04664 #define _LETIMER_STATUS_MASK 0x00000001UL 04665 #define LETIMER_STATUS_RUNNING (0x1UL << 0) 04666 #define _LETIMER_STATUS_RUNNING_SHIFT 0 04667 #define _LETIMER_STATUS_RUNNING_MASK 0x1UL 04668 #define _LETIMER_STATUS_RUNNING_DEFAULT 0x00000000UL 04669 #define LETIMER_STATUS_RUNNING_DEFAULT (_LETIMER_STATUS_RUNNING_DEFAULT << 0) 04671 /* Bit fields for LETIMER CNT */ 04672 #define _LETIMER_CNT_RESETVALUE 0x00000000UL 04673 #define _LETIMER_CNT_MASK 0x0000FFFFUL 04674 #define _LETIMER_CNT_CNT_SHIFT 0 04675 #define _LETIMER_CNT_CNT_MASK 0xFFFFUL 04676 #define _LETIMER_CNT_CNT_DEFAULT 0x00000000UL 04677 #define LETIMER_CNT_CNT_DEFAULT (_LETIMER_CNT_CNT_DEFAULT << 0) 04679 /* Bit fields for LETIMER COMP0 */ 04680 #define _LETIMER_COMP0_RESETVALUE 0x00000000UL 04681 #define _LETIMER_COMP0_MASK 0x0000FFFFUL 04682 #define _LETIMER_COMP0_COMP0_SHIFT 0 04683 #define _LETIMER_COMP0_COMP0_MASK 0xFFFFUL 04684 #define _LETIMER_COMP0_COMP0_DEFAULT 0x00000000UL 04685 #define LETIMER_COMP0_COMP0_DEFAULT (_LETIMER_COMP0_COMP0_DEFAULT << 0) 04687 /* Bit fields for LETIMER COMP1 */ 04688 #define _LETIMER_COMP1_RESETVALUE 0x00000000UL 04689 #define _LETIMER_COMP1_MASK 0x0000FFFFUL 04690 #define _LETIMER_COMP1_COMP1_SHIFT 0 04691 #define _LETIMER_COMP1_COMP1_MASK 0xFFFFUL 04692 #define _LETIMER_COMP1_COMP1_DEFAULT 0x00000000UL 04693 #define LETIMER_COMP1_COMP1_DEFAULT (_LETIMER_COMP1_COMP1_DEFAULT << 0) 04695 /* Bit fields for LETIMER REP0 */ 04696 #define _LETIMER_REP0_RESETVALUE 0x00000000UL 04697 #define _LETIMER_REP0_MASK 0x000000FFUL 04698 #define _LETIMER_REP0_REP0_SHIFT 0 04699 #define _LETIMER_REP0_REP0_MASK 0xFFUL 04700 #define _LETIMER_REP0_REP0_DEFAULT 0x00000000UL 04701 #define LETIMER_REP0_REP0_DEFAULT (_LETIMER_REP0_REP0_DEFAULT << 0) 04703 /* Bit fields for LETIMER REP1 */ 04704 #define _LETIMER_REP1_RESETVALUE 0x00000000UL 04705 #define _LETIMER_REP1_MASK 0x000000FFUL 04706 #define _LETIMER_REP1_REP1_SHIFT 0 04707 #define _LETIMER_REP1_REP1_MASK 0xFFUL 04708 #define _LETIMER_REP1_REP1_DEFAULT 0x00000000UL 04709 #define LETIMER_REP1_REP1_DEFAULT (_LETIMER_REP1_REP1_DEFAULT << 0) 04711 /* Bit fields for LETIMER IF */ 04712 #define _LETIMER_IF_RESETVALUE 0x00000000UL 04713 #define _LETIMER_IF_MASK 0x0000001FUL 04714 #define LETIMER_IF_COMP0 (0x1UL << 0) 04715 #define _LETIMER_IF_COMP0_SHIFT 0 04716 #define _LETIMER_IF_COMP0_MASK 0x1UL 04717 #define _LETIMER_IF_COMP0_DEFAULT 0x00000000UL 04718 #define LETIMER_IF_COMP0_DEFAULT (_LETIMER_IF_COMP0_DEFAULT << 0) 04719 #define LETIMER_IF_COMP1 (0x1UL << 1) 04720 #define _LETIMER_IF_COMP1_SHIFT 1 04721 #define _LETIMER_IF_COMP1_MASK 0x2UL 04722 #define _LETIMER_IF_COMP1_DEFAULT 0x00000000UL 04723 #define LETIMER_IF_COMP1_DEFAULT (_LETIMER_IF_COMP1_DEFAULT << 1) 04724 #define LETIMER_IF_UF (0x1UL << 2) 04725 #define _LETIMER_IF_UF_SHIFT 2 04726 #define _LETIMER_IF_UF_MASK 0x4UL 04727 #define _LETIMER_IF_UF_DEFAULT 0x00000000UL 04728 #define LETIMER_IF_UF_DEFAULT (_LETIMER_IF_UF_DEFAULT << 2) 04729 #define LETIMER_IF_REP0 (0x1UL << 3) 04730 #define _LETIMER_IF_REP0_SHIFT 3 04731 #define _LETIMER_IF_REP0_MASK 0x8UL 04732 #define _LETIMER_IF_REP0_DEFAULT 0x00000000UL 04733 #define LETIMER_IF_REP0_DEFAULT (_LETIMER_IF_REP0_DEFAULT << 3) 04734 #define LETIMER_IF_REP1 (0x1UL << 4) 04735 #define _LETIMER_IF_REP1_SHIFT 4 04736 #define _LETIMER_IF_REP1_MASK 0x10UL 04737 #define _LETIMER_IF_REP1_DEFAULT 0x00000000UL 04738 #define LETIMER_IF_REP1_DEFAULT (_LETIMER_IF_REP1_DEFAULT << 4) 04740 /* Bit fields for LETIMER IFS */ 04741 #define _LETIMER_IFS_RESETVALUE 0x00000000UL 04742 #define _LETIMER_IFS_MASK 0x0000001FUL 04743 #define LETIMER_IFS_COMP0 (0x1UL << 0) 04744 #define _LETIMER_IFS_COMP0_SHIFT 0 04745 #define _LETIMER_IFS_COMP0_MASK 0x1UL 04746 #define _LETIMER_IFS_COMP0_DEFAULT 0x00000000UL 04747 #define LETIMER_IFS_COMP0_DEFAULT (_LETIMER_IFS_COMP0_DEFAULT << 0) 04748 #define LETIMER_IFS_COMP1 (0x1UL << 1) 04749 #define _LETIMER_IFS_COMP1_SHIFT 1 04750 #define _LETIMER_IFS_COMP1_MASK 0x2UL 04751 #define _LETIMER_IFS_COMP1_DEFAULT 0x00000000UL 04752 #define LETIMER_IFS_COMP1_DEFAULT (_LETIMER_IFS_COMP1_DEFAULT << 1) 04753 #define LETIMER_IFS_UF (0x1UL << 2) 04754 #define _LETIMER_IFS_UF_SHIFT 2 04755 #define _LETIMER_IFS_UF_MASK 0x4UL 04756 #define _LETIMER_IFS_UF_DEFAULT 0x00000000UL 04757 #define LETIMER_IFS_UF_DEFAULT (_LETIMER_IFS_UF_DEFAULT << 2) 04758 #define LETIMER_IFS_REP0 (0x1UL << 3) 04759 #define _LETIMER_IFS_REP0_SHIFT 3 04760 #define _LETIMER_IFS_REP0_MASK 0x8UL 04761 #define _LETIMER_IFS_REP0_DEFAULT 0x00000000UL 04762 #define LETIMER_IFS_REP0_DEFAULT (_LETIMER_IFS_REP0_DEFAULT << 3) 04763 #define LETIMER_IFS_REP1 (0x1UL << 4) 04764 #define _LETIMER_IFS_REP1_SHIFT 4 04765 #define _LETIMER_IFS_REP1_MASK 0x10UL 04766 #define _LETIMER_IFS_REP1_DEFAULT 0x00000000UL 04767 #define LETIMER_IFS_REP1_DEFAULT (_LETIMER_IFS_REP1_DEFAULT << 4) 04769 /* Bit fields for LETIMER IFC */ 04770 #define _LETIMER_IFC_RESETVALUE 0x00000000UL 04771 #define _LETIMER_IFC_MASK 0x0000001FUL 04772 #define LETIMER_IFC_COMP0 (0x1UL << 0) 04773 #define _LETIMER_IFC_COMP0_SHIFT 0 04774 #define _LETIMER_IFC_COMP0_MASK 0x1UL 04775 #define _LETIMER_IFC_COMP0_DEFAULT 0x00000000UL 04776 #define LETIMER_IFC_COMP0_DEFAULT (_LETIMER_IFC_COMP0_DEFAULT << 0) 04777 #define LETIMER_IFC_COMP1 (0x1UL << 1) 04778 #define _LETIMER_IFC_COMP1_SHIFT 1 04779 #define _LETIMER_IFC_COMP1_MASK 0x2UL 04780 #define _LETIMER_IFC_COMP1_DEFAULT 0x00000000UL 04781 #define LETIMER_IFC_COMP1_DEFAULT (_LETIMER_IFC_COMP1_DEFAULT << 1) 04782 #define LETIMER_IFC_UF (0x1UL << 2) 04783 #define _LETIMER_IFC_UF_SHIFT 2 04784 #define _LETIMER_IFC_UF_MASK 0x4UL 04785 #define _LETIMER_IFC_UF_DEFAULT 0x00000000UL 04786 #define LETIMER_IFC_UF_DEFAULT (_LETIMER_IFC_UF_DEFAULT << 2) 04787 #define LETIMER_IFC_REP0 (0x1UL << 3) 04788 #define _LETIMER_IFC_REP0_SHIFT 3 04789 #define _LETIMER_IFC_REP0_MASK 0x8UL 04790 #define _LETIMER_IFC_REP0_DEFAULT 0x00000000UL 04791 #define LETIMER_IFC_REP0_DEFAULT (_LETIMER_IFC_REP0_DEFAULT << 3) 04792 #define LETIMER_IFC_REP1 (0x1UL << 4) 04793 #define _LETIMER_IFC_REP1_SHIFT 4 04794 #define _LETIMER_IFC_REP1_MASK 0x10UL 04795 #define _LETIMER_IFC_REP1_DEFAULT 0x00000000UL 04796 #define LETIMER_IFC_REP1_DEFAULT (_LETIMER_IFC_REP1_DEFAULT << 4) 04798 /* Bit fields for LETIMER IEN */ 04799 #define _LETIMER_IEN_RESETVALUE 0x00000000UL 04800 #define _LETIMER_IEN_MASK 0x0000001FUL 04801 #define LETIMER_IEN_COMP0 (0x1UL << 0) 04802 #define _LETIMER_IEN_COMP0_SHIFT 0 04803 #define _LETIMER_IEN_COMP0_MASK 0x1UL 04804 #define _LETIMER_IEN_COMP0_DEFAULT 0x00000000UL 04805 #define LETIMER_IEN_COMP0_DEFAULT (_LETIMER_IEN_COMP0_DEFAULT << 0) 04806 #define LETIMER_IEN_COMP1 (0x1UL << 1) 04807 #define _LETIMER_IEN_COMP1_SHIFT 1 04808 #define _LETIMER_IEN_COMP1_MASK 0x2UL 04809 #define _LETIMER_IEN_COMP1_DEFAULT 0x00000000UL 04810 #define LETIMER_IEN_COMP1_DEFAULT (_LETIMER_IEN_COMP1_DEFAULT << 1) 04811 #define LETIMER_IEN_UF (0x1UL << 2) 04812 #define _LETIMER_IEN_UF_SHIFT 2 04813 #define _LETIMER_IEN_UF_MASK 0x4UL 04814 #define _LETIMER_IEN_UF_DEFAULT 0x00000000UL 04815 #define LETIMER_IEN_UF_DEFAULT (_LETIMER_IEN_UF_DEFAULT << 2) 04816 #define LETIMER_IEN_REP0 (0x1UL << 3) 04817 #define _LETIMER_IEN_REP0_SHIFT 3 04818 #define _LETIMER_IEN_REP0_MASK 0x8UL 04819 #define _LETIMER_IEN_REP0_DEFAULT 0x00000000UL 04820 #define LETIMER_IEN_REP0_DEFAULT (_LETIMER_IEN_REP0_DEFAULT << 3) 04821 #define LETIMER_IEN_REP1 (0x1UL << 4) 04822 #define _LETIMER_IEN_REP1_SHIFT 4 04823 #define _LETIMER_IEN_REP1_MASK 0x10UL 04824 #define _LETIMER_IEN_REP1_DEFAULT 0x00000000UL 04825 #define LETIMER_IEN_REP1_DEFAULT (_LETIMER_IEN_REP1_DEFAULT << 4) 04827 /* Bit fields for LETIMER FREEZE */ 04828 #define _LETIMER_FREEZE_RESETVALUE 0x00000000UL 04829 #define _LETIMER_FREEZE_MASK 0x00000001UL 04830 #define LETIMER_FREEZE_REGFREEZE (0x1UL << 0) 04831 #define _LETIMER_FREEZE_REGFREEZE_SHIFT 0 04832 #define _LETIMER_FREEZE_REGFREEZE_MASK 0x1UL 04833 #define _LETIMER_FREEZE_REGFREEZE_DEFAULT 0x00000000UL 04834 #define _LETIMER_FREEZE_REGFREEZE_UPDATE 0x00000000UL 04835 #define _LETIMER_FREEZE_REGFREEZE_FREEZE 0x00000001UL 04836 #define LETIMER_FREEZE_REGFREEZE_DEFAULT (_LETIMER_FREEZE_REGFREEZE_DEFAULT << 0) 04837 #define LETIMER_FREEZE_REGFREEZE_UPDATE (_LETIMER_FREEZE_REGFREEZE_UPDATE << 0) 04838 #define LETIMER_FREEZE_REGFREEZE_FREEZE (_LETIMER_FREEZE_REGFREEZE_FREEZE << 0) 04840 /* Bit fields for LETIMER SYNCBUSY */ 04841 #define _LETIMER_SYNCBUSY_RESETVALUE 0x00000000UL 04842 #define _LETIMER_SYNCBUSY_MASK 0x0000003FUL 04843 #define LETIMER_SYNCBUSY_CTRL (0x1UL << 0) 04844 #define _LETIMER_SYNCBUSY_CTRL_SHIFT 0 04845 #define _LETIMER_SYNCBUSY_CTRL_MASK 0x1UL 04846 #define _LETIMER_SYNCBUSY_CTRL_DEFAULT 0x00000000UL 04847 #define LETIMER_SYNCBUSY_CTRL_DEFAULT (_LETIMER_SYNCBUSY_CTRL_DEFAULT << 0) 04848 #define LETIMER_SYNCBUSY_CMD (0x1UL << 1) 04849 #define _LETIMER_SYNCBUSY_CMD_SHIFT 1 04850 #define _LETIMER_SYNCBUSY_CMD_MASK 0x2UL 04851 #define _LETIMER_SYNCBUSY_CMD_DEFAULT 0x00000000UL 04852 #define LETIMER_SYNCBUSY_CMD_DEFAULT (_LETIMER_SYNCBUSY_CMD_DEFAULT << 1) 04853 #define LETIMER_SYNCBUSY_COMP0 (0x1UL << 2) 04854 #define _LETIMER_SYNCBUSY_COMP0_SHIFT 2 04855 #define _LETIMER_SYNCBUSY_COMP0_MASK 0x4UL 04856 #define _LETIMER_SYNCBUSY_COMP0_DEFAULT 0x00000000UL 04857 #define LETIMER_SYNCBUSY_COMP0_DEFAULT (_LETIMER_SYNCBUSY_COMP0_DEFAULT << 2) 04858 #define LETIMER_SYNCBUSY_COMP1 (0x1UL << 3) 04859 #define _LETIMER_SYNCBUSY_COMP1_SHIFT 3 04860 #define _LETIMER_SYNCBUSY_COMP1_MASK 0x8UL 04861 #define _LETIMER_SYNCBUSY_COMP1_DEFAULT 0x00000000UL 04862 #define LETIMER_SYNCBUSY_COMP1_DEFAULT (_LETIMER_SYNCBUSY_COMP1_DEFAULT << 3) 04863 #define LETIMER_SYNCBUSY_REP0 (0x1UL << 4) 04864 #define _LETIMER_SYNCBUSY_REP0_SHIFT 4 04865 #define _LETIMER_SYNCBUSY_REP0_MASK 0x10UL 04866 #define _LETIMER_SYNCBUSY_REP0_DEFAULT 0x00000000UL 04867 #define LETIMER_SYNCBUSY_REP0_DEFAULT (_LETIMER_SYNCBUSY_REP0_DEFAULT << 4) 04868 #define LETIMER_SYNCBUSY_REP1 (0x1UL << 5) 04869 #define _LETIMER_SYNCBUSY_REP1_SHIFT 5 04870 #define _LETIMER_SYNCBUSY_REP1_MASK 0x20UL 04871 #define _LETIMER_SYNCBUSY_REP1_DEFAULT 0x00000000UL 04872 #define LETIMER_SYNCBUSY_REP1_DEFAULT (_LETIMER_SYNCBUSY_REP1_DEFAULT << 5) 04874 /* Bit fields for LETIMER ROUTE */ 04875 #define _LETIMER_ROUTE_RESETVALUE 0x00000000UL 04876 #define _LETIMER_ROUTE_MASK 0x00000303UL 04877 #define LETIMER_ROUTE_OUT0PEN (0x1UL << 0) 04878 #define _LETIMER_ROUTE_OUT0PEN_SHIFT 0 04879 #define _LETIMER_ROUTE_OUT0PEN_MASK 0x1UL 04880 #define _LETIMER_ROUTE_OUT0PEN_DEFAULT 0x00000000UL 04881 #define LETIMER_ROUTE_OUT0PEN_DEFAULT (_LETIMER_ROUTE_OUT0PEN_DEFAULT << 0) 04882 #define LETIMER_ROUTE_OUT1PEN (0x1UL << 1) 04883 #define _LETIMER_ROUTE_OUT1PEN_SHIFT 1 04884 #define _LETIMER_ROUTE_OUT1PEN_MASK 0x2UL 04885 #define _LETIMER_ROUTE_OUT1PEN_DEFAULT 0x00000000UL 04886 #define LETIMER_ROUTE_OUT1PEN_DEFAULT (_LETIMER_ROUTE_OUT1PEN_DEFAULT << 1) 04887 #define _LETIMER_ROUTE_LOCATION_SHIFT 8 04888 #define _LETIMER_ROUTE_LOCATION_MASK 0x300UL 04889 #define _LETIMER_ROUTE_LOCATION_DEFAULT 0x00000000UL 04890 #define _LETIMER_ROUTE_LOCATION_LOC0 0x00000000UL 04891 #define _LETIMER_ROUTE_LOCATION_LOC1 0x00000001UL 04892 #define _LETIMER_ROUTE_LOCATION_LOC2 0x00000002UL 04893 #define _LETIMER_ROUTE_LOCATION_LOC3 0x00000003UL 04894 #define LETIMER_ROUTE_LOCATION_DEFAULT (_LETIMER_ROUTE_LOCATION_DEFAULT << 8) 04895 #define LETIMER_ROUTE_LOCATION_LOC0 (_LETIMER_ROUTE_LOCATION_LOC0 << 8) 04896 #define LETIMER_ROUTE_LOCATION_LOC1 (_LETIMER_ROUTE_LOCATION_LOC1 << 8) 04897 #define LETIMER_ROUTE_LOCATION_LOC2 (_LETIMER_ROUTE_LOCATION_LOC2 << 8) 04898 #define LETIMER_ROUTE_LOCATION_LOC3 (_LETIMER_ROUTE_LOCATION_LOC3 << 8) 04904 /**************************************************************************/ 04909 /* Bit fields for PCNT CTRL */ 04910 #define _PCNT_CTRL_RESETVALUE 0x00000000UL 04911 #define _PCNT_CTRL_MASK 0x0000003FUL 04912 #define _PCNT_CTRL_MODE_SHIFT 0 04913 #define _PCNT_CTRL_MODE_MASK 0x3UL 04914 #define _PCNT_CTRL_MODE_DEFAULT 0x00000000UL 04915 #define _PCNT_CTRL_MODE_DISABLE 0x00000000UL 04916 #define _PCNT_CTRL_MODE_OVSSINGLE 0x00000001UL 04917 #define _PCNT_CTRL_MODE_EXTCLKSINGLE 0x00000002UL 04918 #define _PCNT_CTRL_MODE_EXTCLKQUAD 0x00000003UL 04919 #define PCNT_CTRL_MODE_DEFAULT (_PCNT_CTRL_MODE_DEFAULT << 0) 04920 #define PCNT_CTRL_MODE_DISABLE (_PCNT_CTRL_MODE_DISABLE << 0) 04921 #define PCNT_CTRL_MODE_OVSSINGLE (_PCNT_CTRL_MODE_OVSSINGLE << 0) 04922 #define PCNT_CTRL_MODE_EXTCLKSINGLE (_PCNT_CTRL_MODE_EXTCLKSINGLE << 0) 04923 #define PCNT_CTRL_MODE_EXTCLKQUAD (_PCNT_CTRL_MODE_EXTCLKQUAD << 0) 04924 #define PCNT_CTRL_CNTDIR (0x1UL << 2) 04925 #define _PCNT_CTRL_CNTDIR_SHIFT 2 04926 #define _PCNT_CTRL_CNTDIR_MASK 0x4UL 04927 #define _PCNT_CTRL_CNTDIR_DEFAULT 0x00000000UL 04928 #define _PCNT_CTRL_CNTDIR_UP 0x00000000UL 04929 #define _PCNT_CTRL_CNTDIR_DOWN 0x00000001UL 04930 #define PCNT_CTRL_CNTDIR_DEFAULT (_PCNT_CTRL_CNTDIR_DEFAULT << 2) 04931 #define PCNT_CTRL_CNTDIR_UP (_PCNT_CTRL_CNTDIR_UP << 2) 04932 #define PCNT_CTRL_CNTDIR_DOWN (_PCNT_CTRL_CNTDIR_DOWN << 2) 04933 #define PCNT_CTRL_EDGE (0x1UL << 3) 04934 #define _PCNT_CTRL_EDGE_SHIFT 3 04935 #define _PCNT_CTRL_EDGE_MASK 0x8UL 04936 #define _PCNT_CTRL_EDGE_DEFAULT 0x00000000UL 04937 #define _PCNT_CTRL_EDGE_POS 0x00000000UL 04938 #define _PCNT_CTRL_EDGE_NEG 0x00000001UL 04939 #define PCNT_CTRL_EDGE_DEFAULT (_PCNT_CTRL_EDGE_DEFAULT << 3) 04940 #define PCNT_CTRL_EDGE_POS (_PCNT_CTRL_EDGE_POS << 3) 04941 #define PCNT_CTRL_EDGE_NEG (_PCNT_CTRL_EDGE_NEG << 3) 04942 #define PCNT_CTRL_FILT (0x1UL << 4) 04943 #define _PCNT_CTRL_FILT_SHIFT 4 04944 #define _PCNT_CTRL_FILT_MASK 0x10UL 04945 #define _PCNT_CTRL_FILT_DEFAULT 0x00000000UL 04946 #define PCNT_CTRL_FILT_DEFAULT (_PCNT_CTRL_FILT_DEFAULT << 4) 04947 #define PCNT_CTRL_RSTEN (0x1UL << 5) 04948 #define _PCNT_CTRL_RSTEN_SHIFT 5 04949 #define _PCNT_CTRL_RSTEN_MASK 0x20UL 04950 #define _PCNT_CTRL_RSTEN_DEFAULT 0x00000000UL 04951 #define PCNT_CTRL_RSTEN_DEFAULT (_PCNT_CTRL_RSTEN_DEFAULT << 5) 04953 /* Bit fields for PCNT CMD */ 04954 #define _PCNT_CMD_RESETVALUE 0x00000000UL 04955 #define _PCNT_CMD_MASK 0x00000003UL 04956 #define PCNT_CMD_LCNTIM (0x1UL << 0) 04957 #define _PCNT_CMD_LCNTIM_SHIFT 0 04958 #define _PCNT_CMD_LCNTIM_MASK 0x1UL 04959 #define _PCNT_CMD_LCNTIM_DEFAULT 0x00000000UL 04960 #define PCNT_CMD_LCNTIM_DEFAULT (_PCNT_CMD_LCNTIM_DEFAULT << 0) 04961 #define PCNT_CMD_LTOPBIM (0x1UL << 1) 04962 #define _PCNT_CMD_LTOPBIM_SHIFT 1 04963 #define _PCNT_CMD_LTOPBIM_MASK 0x2UL 04964 #define _PCNT_CMD_LTOPBIM_DEFAULT 0x00000000UL 04965 #define PCNT_CMD_LTOPBIM_DEFAULT (_PCNT_CMD_LTOPBIM_DEFAULT << 1) 04967 /* Bit fields for PCNT STATUS */ 04968 #define _PCNT_STATUS_RESETVALUE 0x00000000UL 04969 #define _PCNT_STATUS_MASK 0x00000001UL 04970 #define PCNT_STATUS_DIR (0x1UL << 0) 04971 #define _PCNT_STATUS_DIR_SHIFT 0 04972 #define _PCNT_STATUS_DIR_MASK 0x1UL 04973 #define _PCNT_STATUS_DIR_DEFAULT 0x00000000UL 04974 #define _PCNT_STATUS_DIR_UP 0x00000000UL 04975 #define _PCNT_STATUS_DIR_DOWN 0x00000001UL 04976 #define PCNT_STATUS_DIR_DEFAULT (_PCNT_STATUS_DIR_DEFAULT << 0) 04977 #define PCNT_STATUS_DIR_UP (_PCNT_STATUS_DIR_UP << 0) 04978 #define PCNT_STATUS_DIR_DOWN (_PCNT_STATUS_DIR_DOWN << 0) 04980 /* Bit fields for PCNT CNT */ 04981 #define _PCNT_CNT_RESETVALUE 0x00000000UL 04982 #define _PCNT_CNT_MASK 0x0000FFFFUL 04983 #define _PCNT_CNT_CNT_SHIFT 0 04984 #define _PCNT_CNT_CNT_MASK 0xFFFFUL 04985 #define _PCNT_CNT_CNT_DEFAULT 0x00000000UL 04986 #define PCNT_CNT_CNT_DEFAULT (_PCNT_CNT_CNT_DEFAULT << 0) 04988 /* Bit fields for PCNT TOP */ 04989 #define _PCNT_TOP_RESETVALUE 0x000000FFUL 04990 #define _PCNT_TOP_MASK 0x0000FFFFUL 04991 #define _PCNT_TOP_TOP_SHIFT 0 04992 #define _PCNT_TOP_TOP_MASK 0xFFFFUL 04993 #define _PCNT_TOP_TOP_DEFAULT 0x000000FFUL 04994 #define PCNT_TOP_TOP_DEFAULT (_PCNT_TOP_TOP_DEFAULT << 0) 04996 /* Bit fields for PCNT TOPB */ 04997 #define _PCNT_TOPB_RESETVALUE 0x000000FFUL 04998 #define _PCNT_TOPB_MASK 0x0000FFFFUL 04999 #define _PCNT_TOPB_TOPB_SHIFT 0 05000 #define _PCNT_TOPB_TOPB_MASK 0xFFFFUL 05001 #define _PCNT_TOPB_TOPB_DEFAULT 0x000000FFUL 05002 #define PCNT_TOPB_TOPB_DEFAULT (_PCNT_TOPB_TOPB_DEFAULT << 0) 05004 /* Bit fields for PCNT IF */ 05005 #define _PCNT_IF_RESETVALUE 0x00000000UL 05006 #define _PCNT_IF_MASK 0x00000007UL 05007 #define PCNT_IF_UF (0x1UL << 0) 05008 #define _PCNT_IF_UF_SHIFT 0 05009 #define _PCNT_IF_UF_MASK 0x1UL 05010 #define _PCNT_IF_UF_DEFAULT 0x00000000UL 05011 #define PCNT_IF_UF_DEFAULT (_PCNT_IF_UF_DEFAULT << 0) 05012 #define PCNT_IF_OF (0x1UL << 1) 05013 #define _PCNT_IF_OF_SHIFT 1 05014 #define _PCNT_IF_OF_MASK 0x2UL 05015 #define _PCNT_IF_OF_DEFAULT 0x00000000UL 05016 #define PCNT_IF_OF_DEFAULT (_PCNT_IF_OF_DEFAULT << 1) 05017 #define PCNT_IF_DIRCNG (0x1UL << 2) 05018 #define _PCNT_IF_DIRCNG_SHIFT 2 05019 #define _PCNT_IF_DIRCNG_MASK 0x4UL 05020 #define _PCNT_IF_DIRCNG_DEFAULT 0x00000000UL 05021 #define PCNT_IF_DIRCNG_DEFAULT (_PCNT_IF_DIRCNG_DEFAULT << 2) 05023 /* Bit fields for PCNT IFS */ 05024 #define _PCNT_IFS_RESETVALUE 0x00000000UL 05025 #define _PCNT_IFS_MASK 0x00000007UL 05026 #define PCNT_IFS_UF (0x1UL << 0) 05027 #define _PCNT_IFS_UF_SHIFT 0 05028 #define _PCNT_IFS_UF_MASK 0x1UL 05029 #define _PCNT_IFS_UF_DEFAULT 0x00000000UL 05030 #define PCNT_IFS_UF_DEFAULT (_PCNT_IFS_UF_DEFAULT << 0) 05031 #define PCNT_IFS_OF (0x1UL << 1) 05032 #define _PCNT_IFS_OF_SHIFT 1 05033 #define _PCNT_IFS_OF_MASK 0x2UL 05034 #define _PCNT_IFS_OF_DEFAULT 0x00000000UL 05035 #define PCNT_IFS_OF_DEFAULT (_PCNT_IFS_OF_DEFAULT << 1) 05036 #define PCNT_IFS_DIRCNG (0x1UL << 2) 05037 #define _PCNT_IFS_DIRCNG_SHIFT 2 05038 #define _PCNT_IFS_DIRCNG_MASK 0x4UL 05039 #define _PCNT_IFS_DIRCNG_DEFAULT 0x00000000UL 05040 #define PCNT_IFS_DIRCNG_DEFAULT (_PCNT_IFS_DIRCNG_DEFAULT << 2) 05042 /* Bit fields for PCNT IFC */ 05043 #define _PCNT_IFC_RESETVALUE 0x00000000UL 05044 #define _PCNT_IFC_MASK 0x00000007UL 05045 #define PCNT_IFC_UF (0x1UL << 0) 05046 #define _PCNT_IFC_UF_SHIFT 0 05047 #define _PCNT_IFC_UF_MASK 0x1UL 05048 #define _PCNT_IFC_UF_DEFAULT 0x00000000UL 05049 #define PCNT_IFC_UF_DEFAULT (_PCNT_IFC_UF_DEFAULT << 0) 05050 #define PCNT_IFC_OF (0x1UL << 1) 05051 #define _PCNT_IFC_OF_SHIFT 1 05052 #define _PCNT_IFC_OF_MASK 0x2UL 05053 #define _PCNT_IFC_OF_DEFAULT 0x00000000UL 05054 #define PCNT_IFC_OF_DEFAULT (_PCNT_IFC_OF_DEFAULT << 1) 05055 #define PCNT_IFC_DIRCNG (0x1UL << 2) 05056 #define _PCNT_IFC_DIRCNG_SHIFT 2 05057 #define _PCNT_IFC_DIRCNG_MASK 0x4UL 05058 #define _PCNT_IFC_DIRCNG_DEFAULT 0x00000000UL 05059 #define PCNT_IFC_DIRCNG_DEFAULT (_PCNT_IFC_DIRCNG_DEFAULT << 2) 05061 /* Bit fields for PCNT IEN */ 05062 #define _PCNT_IEN_RESETVALUE 0x00000000UL 05063 #define _PCNT_IEN_MASK 0x00000007UL 05064 #define PCNT_IEN_UF (0x1UL << 0) 05065 #define _PCNT_IEN_UF_SHIFT 0 05066 #define _PCNT_IEN_UF_MASK 0x1UL 05067 #define _PCNT_IEN_UF_DEFAULT 0x00000000UL 05068 #define PCNT_IEN_UF_DEFAULT (_PCNT_IEN_UF_DEFAULT << 0) 05069 #define PCNT_IEN_OF (0x1UL << 1) 05070 #define _PCNT_IEN_OF_SHIFT 1 05071 #define _PCNT_IEN_OF_MASK 0x2UL 05072 #define _PCNT_IEN_OF_DEFAULT 0x00000000UL 05073 #define PCNT_IEN_OF_DEFAULT (_PCNT_IEN_OF_DEFAULT << 1) 05074 #define PCNT_IEN_DIRCNG (0x1UL << 2) 05075 #define _PCNT_IEN_DIRCNG_SHIFT 2 05076 #define _PCNT_IEN_DIRCNG_MASK 0x4UL 05077 #define _PCNT_IEN_DIRCNG_DEFAULT 0x00000000UL 05078 #define PCNT_IEN_DIRCNG_DEFAULT (_PCNT_IEN_DIRCNG_DEFAULT << 2) 05080 /* Bit fields for PCNT ROUTE */ 05081 #define _PCNT_ROUTE_RESETVALUE 0x00000000UL 05082 #define _PCNT_ROUTE_MASK 0x00000300UL 05083 #define _PCNT_ROUTE_LOCATION_SHIFT 8 05084 #define _PCNT_ROUTE_LOCATION_MASK 0x300UL 05085 #define _PCNT_ROUTE_LOCATION_DEFAULT 0x00000000UL 05086 #define _PCNT_ROUTE_LOCATION_LOC0 0x00000000UL 05087 #define _PCNT_ROUTE_LOCATION_LOC1 0x00000001UL 05088 #define _PCNT_ROUTE_LOCATION_LOC2 0x00000002UL 05089 #define PCNT_ROUTE_LOCATION_DEFAULT (_PCNT_ROUTE_LOCATION_DEFAULT << 8) 05090 #define PCNT_ROUTE_LOCATION_LOC0 (_PCNT_ROUTE_LOCATION_LOC0 << 8) 05091 #define PCNT_ROUTE_LOCATION_LOC1 (_PCNT_ROUTE_LOCATION_LOC1 << 8) 05092 #define PCNT_ROUTE_LOCATION_LOC2 (_PCNT_ROUTE_LOCATION_LOC2 << 8) 05094 /* Bit fields for PCNT FREEZE */ 05095 #define _PCNT_FREEZE_RESETVALUE 0x00000000UL 05096 #define _PCNT_FREEZE_MASK 0x00000001UL 05097 #define PCNT_FREEZE_REGFREEZE (0x1UL << 0) 05098 #define _PCNT_FREEZE_REGFREEZE_SHIFT 0 05099 #define _PCNT_FREEZE_REGFREEZE_MASK 0x1UL 05100 #define _PCNT_FREEZE_REGFREEZE_DEFAULT 0x00000000UL 05101 #define _PCNT_FREEZE_REGFREEZE_UPDATE 0x00000000UL 05102 #define _PCNT_FREEZE_REGFREEZE_FREEZE 0x00000001UL 05103 #define PCNT_FREEZE_REGFREEZE_DEFAULT (_PCNT_FREEZE_REGFREEZE_DEFAULT << 0) 05104 #define PCNT_FREEZE_REGFREEZE_UPDATE (_PCNT_FREEZE_REGFREEZE_UPDATE << 0) 05105 #define PCNT_FREEZE_REGFREEZE_FREEZE (_PCNT_FREEZE_REGFREEZE_FREEZE << 0) 05107 /* Bit fields for PCNT SYNCBUSY */ 05108 #define _PCNT_SYNCBUSY_RESETVALUE 0x00000000UL 05109 #define _PCNT_SYNCBUSY_MASK 0x00000007UL 05110 #define PCNT_SYNCBUSY_CTRL (0x1UL << 0) 05111 #define _PCNT_SYNCBUSY_CTRL_SHIFT 0 05112 #define _PCNT_SYNCBUSY_CTRL_MASK 0x1UL 05113 #define _PCNT_SYNCBUSY_CTRL_DEFAULT 0x00000000UL 05114 #define PCNT_SYNCBUSY_CTRL_DEFAULT (_PCNT_SYNCBUSY_CTRL_DEFAULT << 0) 05115 #define PCNT_SYNCBUSY_CMD (0x1UL << 1) 05116 #define _PCNT_SYNCBUSY_CMD_SHIFT 1 05117 #define _PCNT_SYNCBUSY_CMD_MASK 0x2UL 05118 #define _PCNT_SYNCBUSY_CMD_DEFAULT 0x00000000UL 05119 #define PCNT_SYNCBUSY_CMD_DEFAULT (_PCNT_SYNCBUSY_CMD_DEFAULT << 1) 05120 #define PCNT_SYNCBUSY_TOPB (0x1UL << 2) 05121 #define _PCNT_SYNCBUSY_TOPB_SHIFT 2 05122 #define _PCNT_SYNCBUSY_TOPB_MASK 0x4UL 05123 #define _PCNT_SYNCBUSY_TOPB_DEFAULT 0x00000000UL 05124 #define PCNT_SYNCBUSY_TOPB_DEFAULT (_PCNT_SYNCBUSY_TOPB_DEFAULT << 2) 05130 /**************************************************************************/ 05135 /* Bit fields for I2C CTRL */ 05136 #define _I2C_CTRL_RESETVALUE 0x00000000UL 05137 #define _I2C_CTRL_MASK 0x0007B37FUL 05138 #define I2C_CTRL_EN (0x1UL << 0) 05139 #define _I2C_CTRL_EN_SHIFT 0 05140 #define _I2C_CTRL_EN_MASK 0x1UL 05141 #define _I2C_CTRL_EN_DEFAULT 0x00000000UL 05142 #define I2C_CTRL_EN_DEFAULT (_I2C_CTRL_EN_DEFAULT << 0) 05143 #define I2C_CTRL_SLAVE (0x1UL << 1) 05144 #define _I2C_CTRL_SLAVE_SHIFT 1 05145 #define _I2C_CTRL_SLAVE_MASK 0x2UL 05146 #define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL 05147 #define I2C_CTRL_SLAVE_DEFAULT (_I2C_CTRL_SLAVE_DEFAULT << 1) 05148 #define I2C_CTRL_AUTOACK (0x1UL << 2) 05149 #define _I2C_CTRL_AUTOACK_SHIFT 2 05150 #define _I2C_CTRL_AUTOACK_MASK 0x4UL 05151 #define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL 05152 #define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) 05153 #define I2C_CTRL_AUTOSE (0x1UL << 3) 05154 #define _I2C_CTRL_AUTOSE_SHIFT 3 05155 #define _I2C_CTRL_AUTOSE_MASK 0x8UL 05156 #define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL 05157 #define I2C_CTRL_AUTOSE_DEFAULT (_I2C_CTRL_AUTOSE_DEFAULT << 3) 05158 #define I2C_CTRL_AUTOSN (0x1UL << 4) 05159 #define _I2C_CTRL_AUTOSN_SHIFT 4 05160 #define _I2C_CTRL_AUTOSN_MASK 0x10UL 05161 #define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL 05162 #define I2C_CTRL_AUTOSN_DEFAULT (_I2C_CTRL_AUTOSN_DEFAULT << 4) 05163 #define I2C_CTRL_ARBDIS (0x1UL << 5) 05164 #define _I2C_CTRL_ARBDIS_SHIFT 5 05165 #define _I2C_CTRL_ARBDIS_MASK 0x20UL 05166 #define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL 05167 #define I2C_CTRL_ARBDIS_DEFAULT (_I2C_CTRL_ARBDIS_DEFAULT << 5) 05168 #define I2C_CTRL_GCAMEN (0x1UL << 6) 05169 #define _I2C_CTRL_GCAMEN_SHIFT 6 05170 #define _I2C_CTRL_GCAMEN_MASK 0x40UL 05171 #define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL 05172 #define I2C_CTRL_GCAMEN_DEFAULT (_I2C_CTRL_GCAMEN_DEFAULT << 6) 05173 #define _I2C_CTRL_CLHR_SHIFT 8 05174 #define _I2C_CTRL_CLHR_MASK 0x300UL 05175 #define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL 05176 #define _I2C_CTRL_CLHR_STANDARD 0x00000000UL 05177 #define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL 05178 #define _I2C_CTRL_CLHR_FAST 0x00000002UL 05179 #define I2C_CTRL_CLHR_DEFAULT (_I2C_CTRL_CLHR_DEFAULT << 8) 05180 #define I2C_CTRL_CLHR_STANDARD (_I2C_CTRL_CLHR_STANDARD << 8) 05181 #define I2C_CTRL_CLHR_ASYMMETRIC (_I2C_CTRL_CLHR_ASYMMETRIC << 8) 05182 #define I2C_CTRL_CLHR_FAST (_I2C_CTRL_CLHR_FAST << 8) 05183 #define _I2C_CTRL_BITO_SHIFT 12 05184 #define _I2C_CTRL_BITO_MASK 0x3000UL 05185 #define _I2C_CTRL_BITO_DEFAULT 0x00000000UL 05186 #define _I2C_CTRL_BITO_OFF 0x00000000UL 05187 #define _I2C_CTRL_BITO_40PCC 0x00000001UL 05188 #define _I2C_CTRL_BITO_80PCC 0x00000002UL 05189 #define _I2C_CTRL_BITO_160PCC 0x00000003UL 05190 #define I2C_CTRL_BITO_DEFAULT (_I2C_CTRL_BITO_DEFAULT << 12) 05191 #define I2C_CTRL_BITO_OFF (_I2C_CTRL_BITO_OFF << 12) 05192 #define I2C_CTRL_BITO_40PCC (_I2C_CTRL_BITO_40PCC << 12) 05193 #define I2C_CTRL_BITO_80PCC (_I2C_CTRL_BITO_80PCC << 12) 05194 #define I2C_CTRL_BITO_160PCC (_I2C_CTRL_BITO_160PCC << 12) 05195 #define I2C_CTRL_GIBITO (0x1UL << 15) 05196 #define _I2C_CTRL_GIBITO_SHIFT 15 05197 #define _I2C_CTRL_GIBITO_MASK 0x8000UL 05198 #define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL 05199 #define I2C_CTRL_GIBITO_DEFAULT (_I2C_CTRL_GIBITO_DEFAULT << 15) 05200 #define _I2C_CTRL_CLTO_SHIFT 16 05201 #define _I2C_CTRL_CLTO_MASK 0x70000UL 05202 #define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL 05203 #define _I2C_CTRL_CLTO_OFF 0x00000000UL 05204 #define _I2C_CTRL_CLTO_40PCC 0x00000001UL 05205 #define _I2C_CTRL_CLTO_80PCC 0x00000002UL 05206 #define _I2C_CTRL_CLTO_160PCC 0x00000003UL 05207 #define _I2C_CTRL_CLTO_320PPC 0x00000004UL 05208 #define _I2C_CTRL_CLTO_1024PPC 0x00000005UL 05209 #define I2C_CTRL_CLTO_DEFAULT (_I2C_CTRL_CLTO_DEFAULT << 16) 05210 #define I2C_CTRL_CLTO_OFF (_I2C_CTRL_CLTO_OFF << 16) 05211 #define I2C_CTRL_CLTO_40PCC (_I2C_CTRL_CLTO_40PCC << 16) 05212 #define I2C_CTRL_CLTO_80PCC (_I2C_CTRL_CLTO_80PCC << 16) 05213 #define I2C_CTRL_CLTO_160PCC (_I2C_CTRL_CLTO_160PCC << 16) 05214 #define I2C_CTRL_CLTO_320PPC (_I2C_CTRL_CLTO_320PPC << 16) 05215 #define I2C_CTRL_CLTO_1024PPC (_I2C_CTRL_CLTO_1024PPC << 16) 05217 /* Bit fields for I2C CMD */ 05218 #define _I2C_CMD_RESETVALUE 0x00000000UL 05219 #define _I2C_CMD_MASK 0x000000FFUL 05220 #define I2C_CMD_START (0x1UL << 0) 05221 #define _I2C_CMD_START_SHIFT 0 05222 #define _I2C_CMD_START_MASK 0x1UL 05223 #define _I2C_CMD_START_DEFAULT 0x00000000UL 05224 #define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) 05225 #define I2C_CMD_STOP (0x1UL << 1) 05226 #define _I2C_CMD_STOP_SHIFT 1 05227 #define _I2C_CMD_STOP_MASK 0x2UL 05228 #define _I2C_CMD_STOP_DEFAULT 0x00000000UL 05229 #define I2C_CMD_STOP_DEFAULT (_I2C_CMD_STOP_DEFAULT << 1) 05230 #define I2C_CMD_ACK (0x1UL << 2) 05231 #define _I2C_CMD_ACK_SHIFT 2 05232 #define _I2C_CMD_ACK_MASK 0x4UL 05233 #define _I2C_CMD_ACK_DEFAULT 0x00000000UL 05234 #define I2C_CMD_ACK_DEFAULT (_I2C_CMD_ACK_DEFAULT << 2) 05235 #define I2C_CMD_NACK (0x1UL << 3) 05236 #define _I2C_CMD_NACK_SHIFT 3 05237 #define _I2C_CMD_NACK_MASK 0x8UL 05238 #define _I2C_CMD_NACK_DEFAULT 0x00000000UL 05239 #define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) 05240 #define I2C_CMD_CONT (0x1UL << 4) 05241 #define _I2C_CMD_CONT_SHIFT 4 05242 #define _I2C_CMD_CONT_MASK 0x10UL 05243 #define _I2C_CMD_CONT_DEFAULT 0x00000000UL 05244 #define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) 05245 #define I2C_CMD_ABORT (0x1UL << 5) 05246 #define _I2C_CMD_ABORT_SHIFT 5 05247 #define _I2C_CMD_ABORT_MASK 0x20UL 05248 #define _I2C_CMD_ABORT_DEFAULT 0x00000000UL 05249 #define I2C_CMD_ABORT_DEFAULT (_I2C_CMD_ABORT_DEFAULT << 5) 05250 #define I2C_CMD_CLEARTX (0x1UL << 6) 05251 #define _I2C_CMD_CLEARTX_SHIFT 6 05252 #define _I2C_CMD_CLEARTX_MASK 0x40UL 05253 #define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL 05254 #define I2C_CMD_CLEARTX_DEFAULT (_I2C_CMD_CLEARTX_DEFAULT << 6) 05255 #define I2C_CMD_CLEARPC (0x1UL << 7) 05256 #define _I2C_CMD_CLEARPC_SHIFT 7 05257 #define _I2C_CMD_CLEARPC_MASK 0x80UL 05258 #define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL 05259 #define I2C_CMD_CLEARPC_DEFAULT (_I2C_CMD_CLEARPC_DEFAULT << 7) 05261 /* Bit fields for I2C STATE */ 05262 #define _I2C_STATE_RESETVALUE 0x00000001UL 05263 #define _I2C_STATE_MASK 0x000000FFUL 05264 #define I2C_STATE_BUSY (0x1UL << 0) 05265 #define _I2C_STATE_BUSY_SHIFT 0 05266 #define _I2C_STATE_BUSY_MASK 0x1UL 05267 #define _I2C_STATE_BUSY_DEFAULT 0x00000001UL 05268 #define I2C_STATE_BUSY_DEFAULT (_I2C_STATE_BUSY_DEFAULT << 0) 05269 #define I2C_STATE_MASTER (0x1UL << 1) 05270 #define _I2C_STATE_MASTER_SHIFT 1 05271 #define _I2C_STATE_MASTER_MASK 0x2UL 05272 #define _I2C_STATE_MASTER_DEFAULT 0x00000000UL 05273 #define I2C_STATE_MASTER_DEFAULT (_I2C_STATE_MASTER_DEFAULT << 1) 05274 #define I2C_STATE_TRANSMITTER (0x1UL << 2) 05275 #define _I2C_STATE_TRANSMITTER_SHIFT 2 05276 #define _I2C_STATE_TRANSMITTER_MASK 0x4UL 05277 #define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL 05278 #define I2C_STATE_TRANSMITTER_DEFAULT (_I2C_STATE_TRANSMITTER_DEFAULT << 2) 05279 #define I2C_STATE_NACKED (0x1UL << 3) 05280 #define _I2C_STATE_NACKED_SHIFT 3 05281 #define _I2C_STATE_NACKED_MASK 0x8UL 05282 #define _I2C_STATE_NACKED_DEFAULT 0x00000000UL 05283 #define I2C_STATE_NACKED_DEFAULT (_I2C_STATE_NACKED_DEFAULT << 3) 05284 #define I2C_STATE_BUSHOLD (0x1UL << 4) 05285 #define _I2C_STATE_BUSHOLD_SHIFT 4 05286 #define _I2C_STATE_BUSHOLD_MASK 0x10UL 05287 #define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL 05288 #define I2C_STATE_BUSHOLD_DEFAULT (_I2C_STATE_BUSHOLD_DEFAULT << 4) 05289 #define _I2C_STATE_STATE_SHIFT 5 05290 #define _I2C_STATE_STATE_MASK 0xE0UL 05291 #define _I2C_STATE_STATE_DEFAULT 0x00000000UL 05292 #define _I2C_STATE_STATE_IDLE 0x00000000UL 05293 #define _I2C_STATE_STATE_WAIT 0x00000001UL 05294 #define _I2C_STATE_STATE_START 0x00000002UL 05295 #define _I2C_STATE_STATE_ADDR 0x00000003UL 05296 #define _I2C_STATE_STATE_ADDRACK 0x00000004UL 05297 #define _I2C_STATE_STATE_DATA 0x00000005UL 05298 #define _I2C_STATE_STATE_DATAACK 0x00000006UL 05299 #define I2C_STATE_STATE_DEFAULT (_I2C_STATE_STATE_DEFAULT << 5) 05300 #define I2C_STATE_STATE_IDLE (_I2C_STATE_STATE_IDLE << 5) 05301 #define I2C_STATE_STATE_WAIT (_I2C_STATE_STATE_WAIT << 5) 05302 #define I2C_STATE_STATE_START (_I2C_STATE_STATE_START << 5) 05303 #define I2C_STATE_STATE_ADDR (_I2C_STATE_STATE_ADDR << 5) 05304 #define I2C_STATE_STATE_ADDRACK (_I2C_STATE_STATE_ADDRACK << 5) 05305 #define I2C_STATE_STATE_DATA (_I2C_STATE_STATE_DATA << 5) 05306 #define I2C_STATE_STATE_DATAACK (_I2C_STATE_STATE_DATAACK << 5) 05308 /* Bit fields for I2C STATUS */ 05309 #define _I2C_STATUS_RESETVALUE 0x00000080UL 05310 #define _I2C_STATUS_MASK 0x000001FFUL 05311 #define I2C_STATUS_PSTART (0x1UL << 0) 05312 #define _I2C_STATUS_PSTART_SHIFT 0 05313 #define _I2C_STATUS_PSTART_MASK 0x1UL 05314 #define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL 05315 #define I2C_STATUS_PSTART_DEFAULT (_I2C_STATUS_PSTART_DEFAULT << 0) 05316 #define I2C_STATUS_PSTOP (0x1UL << 1) 05317 #define _I2C_STATUS_PSTOP_SHIFT 1 05318 #define _I2C_STATUS_PSTOP_MASK 0x2UL 05319 #define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL 05320 #define I2C_STATUS_PSTOP_DEFAULT (_I2C_STATUS_PSTOP_DEFAULT << 1) 05321 #define I2C_STATUS_PACK (0x1UL << 2) 05322 #define _I2C_STATUS_PACK_SHIFT 2 05323 #define _I2C_STATUS_PACK_MASK 0x4UL 05324 #define _I2C_STATUS_PACK_DEFAULT 0x00000000UL 05325 #define I2C_STATUS_PACK_DEFAULT (_I2C_STATUS_PACK_DEFAULT << 2) 05326 #define I2C_STATUS_PNACK (0x1UL << 3) 05327 #define _I2C_STATUS_PNACK_SHIFT 3 05328 #define _I2C_STATUS_PNACK_MASK 0x8UL 05329 #define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL 05330 #define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) 05331 #define I2C_STATUS_PCONT (0x1UL << 4) 05332 #define _I2C_STATUS_PCONT_SHIFT 4 05333 #define _I2C_STATUS_PCONT_MASK 0x10UL 05334 #define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL 05335 #define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) 05336 #define I2C_STATUS_PABORT (0x1UL << 5) 05337 #define _I2C_STATUS_PABORT_SHIFT 5 05338 #define _I2C_STATUS_PABORT_MASK 0x20UL 05339 #define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL 05340 #define I2C_STATUS_PABORT_DEFAULT (_I2C_STATUS_PABORT_DEFAULT << 5) 05341 #define I2C_STATUS_TXC (0x1UL << 6) 05342 #define _I2C_STATUS_TXC_SHIFT 6 05343 #define _I2C_STATUS_TXC_MASK 0x40UL 05344 #define _I2C_STATUS_TXC_DEFAULT 0x00000000UL 05345 #define I2C_STATUS_TXC_DEFAULT (_I2C_STATUS_TXC_DEFAULT << 6) 05346 #define I2C_STATUS_TXBL (0x1UL << 7) 05347 #define _I2C_STATUS_TXBL_SHIFT 7 05348 #define _I2C_STATUS_TXBL_MASK 0x80UL 05349 #define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL 05350 #define I2C_STATUS_TXBL_DEFAULT (_I2C_STATUS_TXBL_DEFAULT << 7) 05351 #define I2C_STATUS_RXDATAV (0x1UL << 8) 05352 #define _I2C_STATUS_RXDATAV_SHIFT 8 05353 #define _I2C_STATUS_RXDATAV_MASK 0x100UL 05354 #define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL 05355 #define I2C_STATUS_RXDATAV_DEFAULT (_I2C_STATUS_RXDATAV_DEFAULT << 8) 05357 /* Bit fields for I2C CLKDIV */ 05358 #define _I2C_CLKDIV_RESETVALUE 0x00000000UL 05359 #define _I2C_CLKDIV_MASK 0x000001FFUL 05360 #define _I2C_CLKDIV_DIV_SHIFT 0 05361 #define _I2C_CLKDIV_DIV_MASK 0x1FFUL 05362 #define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL 05363 #define I2C_CLKDIV_DIV_DEFAULT (_I2C_CLKDIV_DIV_DEFAULT << 0) 05365 /* Bit fields for I2C SADDR */ 05366 #define _I2C_SADDR_RESETVALUE 0x00000000UL 05367 #define _I2C_SADDR_MASK 0x000000FEUL 05368 #define _I2C_SADDR_ADDR_SHIFT 1 05369 #define _I2C_SADDR_ADDR_MASK 0xFEUL 05370 #define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL 05371 #define I2C_SADDR_ADDR_DEFAULT (_I2C_SADDR_ADDR_DEFAULT << 1) 05373 /* Bit fields for I2C SADDRMASK */ 05374 #define _I2C_SADDRMASK_RESETVALUE 0x00000000UL 05375 #define _I2C_SADDRMASK_MASK 0x000000FEUL 05376 #define _I2C_SADDRMASK_MASK_SHIFT 1 05377 #define _I2C_SADDRMASK_MASK_MASK 0xFEUL 05378 #define _I2C_SADDRMASK_MASK_DEFAULT 0x00000000UL 05379 #define I2C_SADDRMASK_MASK_DEFAULT (_I2C_SADDRMASK_MASK_DEFAULT << 1) 05381 /* Bit fields for I2C RXDATA */ 05382 #define _I2C_RXDATA_RESETVALUE 0x00000000UL 05383 #define _I2C_RXDATA_MASK 0x000000FFUL 05384 #define _I2C_RXDATA_RXDATA_SHIFT 0 05385 #define _I2C_RXDATA_RXDATA_MASK 0xFFUL 05386 #define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL 05387 #define I2C_RXDATA_RXDATA_DEFAULT (_I2C_RXDATA_RXDATA_DEFAULT << 0) 05389 /* Bit fields for I2C RXDATAP */ 05390 #define _I2C_RXDATAP_RESETVALUE 0x00000000UL 05391 #define _I2C_RXDATAP_MASK 0x000000FFUL 05392 #define _I2C_RXDATAP_RXDATAP_SHIFT 0 05393 #define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL 05394 #define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL 05395 #define I2C_RXDATAP_RXDATAP_DEFAULT (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) 05397 /* Bit fields for I2C TXDATA */ 05398 #define _I2C_TXDATA_RESETVALUE 0x00000000UL 05399 #define _I2C_TXDATA_MASK 0x000000FFUL 05400 #define _I2C_TXDATA_TXDATA_SHIFT 0 05401 #define _I2C_TXDATA_TXDATA_MASK 0xFFUL 05402 #define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL 05403 #define I2C_TXDATA_TXDATA_DEFAULT (_I2C_TXDATA_TXDATA_DEFAULT << 0) 05405 /* Bit fields for I2C IF */ 05406 #define _I2C_IF_RESETVALUE 0x00000010UL 05407 #define _I2C_IF_MASK 0x0001FFFFUL 05408 #define I2C_IF_START (0x1UL << 0) 05409 #define _I2C_IF_START_SHIFT 0 05410 #define _I2C_IF_START_MASK 0x1UL 05411 #define _I2C_IF_START_DEFAULT 0x00000000UL 05412 #define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) 05413 #define I2C_IF_RSTART (0x1UL << 1) 05414 #define _I2C_IF_RSTART_SHIFT 1 05415 #define _I2C_IF_RSTART_MASK 0x2UL 05416 #define _I2C_IF_RSTART_DEFAULT 0x00000000UL 05417 #define I2C_IF_RSTART_DEFAULT (_I2C_IF_RSTART_DEFAULT << 1) 05418 #define I2C_IF_ADDR (0x1UL << 2) 05419 #define _I2C_IF_ADDR_SHIFT 2 05420 #define _I2C_IF_ADDR_MASK 0x4UL 05421 #define _I2C_IF_ADDR_DEFAULT 0x00000000UL 05422 #define I2C_IF_ADDR_DEFAULT (_I2C_IF_ADDR_DEFAULT << 2) 05423 #define I2C_IF_TXC (0x1UL << 3) 05424 #define _I2C_IF_TXC_SHIFT 3 05425 #define _I2C_IF_TXC_MASK 0x8UL 05426 #define _I2C_IF_TXC_DEFAULT 0x00000000UL 05427 #define I2C_IF_TXC_DEFAULT (_I2C_IF_TXC_DEFAULT << 3) 05428 #define I2C_IF_TXBL (0x1UL << 4) 05429 #define _I2C_IF_TXBL_SHIFT 4 05430 #define _I2C_IF_TXBL_MASK 0x10UL 05431 #define _I2C_IF_TXBL_DEFAULT 0x00000000UL 05432 #define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) 05433 #define I2C_IF_RXDATAV (0x1UL << 5) 05434 #define _I2C_IF_RXDATAV_SHIFT 5 05435 #define _I2C_IF_RXDATAV_MASK 0x20UL 05436 #define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL 05437 #define I2C_IF_RXDATAV_DEFAULT (_I2C_IF_RXDATAV_DEFAULT << 5) 05438 #define I2C_IF_ACK (0x1UL << 6) 05439 #define _I2C_IF_ACK_SHIFT 6 05440 #define _I2C_IF_ACK_MASK 0x40UL 05441 #define _I2C_IF_ACK_DEFAULT 0x00000000UL 05442 #define I2C_IF_ACK_DEFAULT (_I2C_IF_ACK_DEFAULT << 6) 05443 #define I2C_IF_NACK (0x1UL << 7) 05444 #define _I2C_IF_NACK_SHIFT 7 05445 #define _I2C_IF_NACK_MASK 0x80UL 05446 #define _I2C_IF_NACK_DEFAULT 0x00000000UL 05447 #define I2C_IF_NACK_DEFAULT (_I2C_IF_NACK_DEFAULT << 7) 05448 #define I2C_IF_MSTOP (0x1UL << 8) 05449 #define _I2C_IF_MSTOP_SHIFT 8 05450 #define _I2C_IF_MSTOP_MASK 0x100UL 05451 #define _I2C_IF_MSTOP_DEFAULT 0x00000000UL 05452 #define I2C_IF_MSTOP_DEFAULT (_I2C_IF_MSTOP_DEFAULT << 8) 05453 #define I2C_IF_ARBLOST (0x1UL << 9) 05454 #define _I2C_IF_ARBLOST_SHIFT 9 05455 #define _I2C_IF_ARBLOST_MASK 0x200UL 05456 #define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL 05457 #define I2C_IF_ARBLOST_DEFAULT (_I2C_IF_ARBLOST_DEFAULT << 9) 05458 #define I2C_IF_BUSERR (0x1UL << 10) 05459 #define _I2C_IF_BUSERR_SHIFT 10 05460 #define _I2C_IF_BUSERR_MASK 0x400UL 05461 #define _I2C_IF_BUSERR_DEFAULT 0x00000000UL 05462 #define I2C_IF_BUSERR_DEFAULT (_I2C_IF_BUSERR_DEFAULT << 10) 05463 #define I2C_IF_BUSHOLD (0x1UL << 11) 05464 #define _I2C_IF_BUSHOLD_SHIFT 11 05465 #define _I2C_IF_BUSHOLD_MASK 0x800UL 05466 #define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL 05467 #define I2C_IF_BUSHOLD_DEFAULT (_I2C_IF_BUSHOLD_DEFAULT << 11) 05468 #define I2C_IF_TXOF (0x1UL << 12) 05469 #define _I2C_IF_TXOF_SHIFT 12 05470 #define _I2C_IF_TXOF_MASK 0x1000UL 05471 #define _I2C_IF_TXOF_DEFAULT 0x00000000UL 05472 #define I2C_IF_TXOF_DEFAULT (_I2C_IF_TXOF_DEFAULT << 12) 05473 #define I2C_IF_RXUF (0x1UL << 13) 05474 #define _I2C_IF_RXUF_SHIFT 13 05475 #define _I2C_IF_RXUF_MASK 0x2000UL 05476 #define _I2C_IF_RXUF_DEFAULT 0x00000000UL 05477 #define I2C_IF_RXUF_DEFAULT (_I2C_IF_RXUF_DEFAULT << 13) 05478 #define I2C_IF_BITO (0x1UL << 14) 05479 #define _I2C_IF_BITO_SHIFT 14 05480 #define _I2C_IF_BITO_MASK 0x4000UL 05481 #define _I2C_IF_BITO_DEFAULT 0x00000000UL 05482 #define I2C_IF_BITO_DEFAULT (_I2C_IF_BITO_DEFAULT << 14) 05483 #define I2C_IF_CLTO (0x1UL << 15) 05484 #define _I2C_IF_CLTO_SHIFT 15 05485 #define _I2C_IF_CLTO_MASK 0x8000UL 05486 #define _I2C_IF_CLTO_DEFAULT 0x00000000UL 05487 #define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) 05488 #define I2C_IF_SSTOP (0x1UL << 16) 05489 #define _I2C_IF_SSTOP_SHIFT 16 05490 #define _I2C_IF_SSTOP_MASK 0x10000UL 05491 #define _I2C_IF_SSTOP_DEFAULT 0x00000000UL 05492 #define I2C_IF_SSTOP_DEFAULT (_I2C_IF_SSTOP_DEFAULT << 16) 05494 /* Bit fields for I2C IFS */ 05495 #define _I2C_IFS_RESETVALUE 0x00000000UL 05496 #define _I2C_IFS_MASK 0x0001FFFFUL 05497 #define I2C_IFS_START (0x1UL << 0) 05498 #define _I2C_IFS_START_SHIFT 0 05499 #define _I2C_IFS_START_MASK 0x1UL 05500 #define _I2C_IFS_START_DEFAULT 0x00000000UL 05501 #define I2C_IFS_START_DEFAULT (_I2C_IFS_START_DEFAULT << 0) 05502 #define I2C_IFS_RSTART (0x1UL << 1) 05503 #define _I2C_IFS_RSTART_SHIFT 1 05504 #define _I2C_IFS_RSTART_MASK 0x2UL 05505 #define _I2C_IFS_RSTART_DEFAULT 0x00000000UL 05506 #define I2C_IFS_RSTART_DEFAULT (_I2C_IFS_RSTART_DEFAULT << 1) 05507 #define I2C_IFS_ADDR (0x1UL << 2) 05508 #define _I2C_IFS_ADDR_SHIFT 2 05509 #define _I2C_IFS_ADDR_MASK 0x4UL 05510 #define _I2C_IFS_ADDR_DEFAULT 0x00000000UL 05511 #define I2C_IFS_ADDR_DEFAULT (_I2C_IFS_ADDR_DEFAULT << 2) 05512 #define I2C_IFS_TXC (0x1UL << 3) 05513 #define _I2C_IFS_TXC_SHIFT 3 05514 #define _I2C_IFS_TXC_MASK 0x8UL 05515 #define _I2C_IFS_TXC_DEFAULT 0x00000000UL 05516 #define I2C_IFS_TXC_DEFAULT (_I2C_IFS_TXC_DEFAULT << 3) 05517 #define I2C_IFS_ACK (0x1UL << 6) 05518 #define _I2C_IFS_ACK_SHIFT 6 05519 #define _I2C_IFS_ACK_MASK 0x40UL 05520 #define _I2C_IFS_ACK_DEFAULT 0x00000000UL 05521 #define I2C_IFS_ACK_DEFAULT (_I2C_IFS_ACK_DEFAULT << 6) 05522 #define I2C_IFS_NACK (0x1UL << 7) 05523 #define _I2C_IFS_NACK_SHIFT 7 05524 #define _I2C_IFS_NACK_MASK 0x80UL 05525 #define _I2C_IFS_NACK_DEFAULT 0x00000000UL 05526 #define I2C_IFS_NACK_DEFAULT (_I2C_IFS_NACK_DEFAULT << 7) 05527 #define I2C_IFS_MSTOP (0x1UL << 8) 05528 #define _I2C_IFS_MSTOP_SHIFT 8 05529 #define _I2C_IFS_MSTOP_MASK 0x100UL 05530 #define _I2C_IFS_MSTOP_DEFAULT 0x00000000UL 05531 #define I2C_IFS_MSTOP_DEFAULT (_I2C_IFS_MSTOP_DEFAULT << 8) 05532 #define I2C_IFS_ARBLOST (0x1UL << 9) 05533 #define _I2C_IFS_ARBLOST_SHIFT 9 05534 #define _I2C_IFS_ARBLOST_MASK 0x200UL 05535 #define _I2C_IFS_ARBLOST_DEFAULT 0x00000000UL 05536 #define I2C_IFS_ARBLOST_DEFAULT (_I2C_IFS_ARBLOST_DEFAULT << 9) 05537 #define I2C_IFS_BUSERR (0x1UL << 10) 05538 #define _I2C_IFS_BUSERR_SHIFT 10 05539 #define _I2C_IFS_BUSERR_MASK 0x400UL 05540 #define _I2C_IFS_BUSERR_DEFAULT 0x00000000UL 05541 #define I2C_IFS_BUSERR_DEFAULT (_I2C_IFS_BUSERR_DEFAULT << 10) 05542 #define I2C_IFS_BUSHOLD (0x1UL << 11) 05543 #define _I2C_IFS_BUSHOLD_SHIFT 11 05544 #define _I2C_IFS_BUSHOLD_MASK 0x800UL 05545 #define _I2C_IFS_BUSHOLD_DEFAULT 0x00000000UL 05546 #define I2C_IFS_BUSHOLD_DEFAULT (_I2C_IFS_BUSHOLD_DEFAULT << 11) 05547 #define I2C_IFS_TXOF (0x1UL << 12) 05548 #define _I2C_IFS_TXOF_SHIFT 12 05549 #define _I2C_IFS_TXOF_MASK 0x1000UL 05550 #define _I2C_IFS_TXOF_DEFAULT 0x00000000UL 05551 #define I2C_IFS_TXOF_DEFAULT (_I2C_IFS_TXOF_DEFAULT << 12) 05552 #define I2C_IFS_RXUF (0x1UL << 13) 05553 #define _I2C_IFS_RXUF_SHIFT 13 05554 #define _I2C_IFS_RXUF_MASK 0x2000UL 05555 #define _I2C_IFS_RXUF_DEFAULT 0x00000000UL 05556 #define I2C_IFS_RXUF_DEFAULT (_I2C_IFS_RXUF_DEFAULT << 13) 05557 #define I2C_IFS_BITO (0x1UL << 14) 05558 #define _I2C_IFS_BITO_SHIFT 14 05559 #define _I2C_IFS_BITO_MASK 0x4000UL 05560 #define _I2C_IFS_BITO_DEFAULT 0x00000000UL 05561 #define I2C_IFS_BITO_DEFAULT (_I2C_IFS_BITO_DEFAULT << 14) 05562 #define I2C_IFS_CLTO (0x1UL << 15) 05563 #define _I2C_IFS_CLTO_SHIFT 15 05564 #define _I2C_IFS_CLTO_MASK 0x8000UL 05565 #define _I2C_IFS_CLTO_DEFAULT 0x00000000UL 05566 #define I2C_IFS_CLTO_DEFAULT (_I2C_IFS_CLTO_DEFAULT << 15) 05567 #define I2C_IFS_SSTOP (0x1UL << 16) 05568 #define _I2C_IFS_SSTOP_SHIFT 16 05569 #define _I2C_IFS_SSTOP_MASK 0x10000UL 05570 #define _I2C_IFS_SSTOP_DEFAULT 0x00000000UL 05571 #define I2C_IFS_SSTOP_DEFAULT (_I2C_IFS_SSTOP_DEFAULT << 16) 05573 /* Bit fields for I2C IFC */ 05574 #define _I2C_IFC_RESETVALUE 0x00000000UL 05575 #define _I2C_IFC_MASK 0x0001FFFFUL 05576 #define I2C_IFC_START (0x1UL << 0) 05577 #define _I2C_IFC_START_SHIFT 0 05578 #define _I2C_IFC_START_MASK 0x1UL 05579 #define _I2C_IFC_START_DEFAULT 0x00000000UL 05580 #define I2C_IFC_START_DEFAULT (_I2C_IFC_START_DEFAULT << 0) 05581 #define I2C_IFC_RSTART (0x1UL << 1) 05582 #define _I2C_IFC_RSTART_SHIFT 1 05583 #define _I2C_IFC_RSTART_MASK 0x2UL 05584 #define _I2C_IFC_RSTART_DEFAULT 0x00000000UL 05585 #define I2C_IFC_RSTART_DEFAULT (_I2C_IFC_RSTART_DEFAULT << 1) 05586 #define I2C_IFC_ADDR (0x1UL << 2) 05587 #define _I2C_IFC_ADDR_SHIFT 2 05588 #define _I2C_IFC_ADDR_MASK 0x4UL 05589 #define _I2C_IFC_ADDR_DEFAULT 0x00000000UL 05590 #define I2C_IFC_ADDR_DEFAULT (_I2C_IFC_ADDR_DEFAULT << 2) 05591 #define I2C_IFC_TXC (0x1UL << 3) 05592 #define _I2C_IFC_TXC_SHIFT 3 05593 #define _I2C_IFC_TXC_MASK 0x8UL 05594 #define _I2C_IFC_TXC_DEFAULT 0x00000000UL 05595 #define I2C_IFC_TXC_DEFAULT (_I2C_IFC_TXC_DEFAULT << 3) 05596 #define I2C_IFC_ACK (0x1UL << 6) 05597 #define _I2C_IFC_ACK_SHIFT 6 05598 #define _I2C_IFC_ACK_MASK 0x40UL 05599 #define _I2C_IFC_ACK_DEFAULT 0x00000000UL 05600 #define I2C_IFC_ACK_DEFAULT (_I2C_IFC_ACK_DEFAULT << 6) 05601 #define I2C_IFC_NACK (0x1UL << 7) 05602 #define _I2C_IFC_NACK_SHIFT 7 05603 #define _I2C_IFC_NACK_MASK 0x80UL 05604 #define _I2C_IFC_NACK_DEFAULT 0x00000000UL 05605 #define I2C_IFC_NACK_DEFAULT (_I2C_IFC_NACK_DEFAULT << 7) 05606 #define I2C_IFC_MSTOP (0x1UL << 8) 05607 #define _I2C_IFC_MSTOP_SHIFT 8 05608 #define _I2C_IFC_MSTOP_MASK 0x100UL 05609 #define _I2C_IFC_MSTOP_DEFAULT 0x00000000UL 05610 #define I2C_IFC_MSTOP_DEFAULT (_I2C_IFC_MSTOP_DEFAULT << 8) 05611 #define I2C_IFC_ARBLOST (0x1UL << 9) 05612 #define _I2C_IFC_ARBLOST_SHIFT 9 05613 #define _I2C_IFC_ARBLOST_MASK 0x200UL 05614 #define _I2C_IFC_ARBLOST_DEFAULT 0x00000000UL 05615 #define I2C_IFC_ARBLOST_DEFAULT (_I2C_IFC_ARBLOST_DEFAULT << 9) 05616 #define I2C_IFC_BUSERR (0x1UL << 10) 05617 #define _I2C_IFC_BUSERR_SHIFT 10 05618 #define _I2C_IFC_BUSERR_MASK 0x400UL 05619 #define _I2C_IFC_BUSERR_DEFAULT 0x00000000UL 05620 #define I2C_IFC_BUSERR_DEFAULT (_I2C_IFC_BUSERR_DEFAULT << 10) 05621 #define I2C_IFC_BUSHOLD (0x1UL << 11) 05622 #define _I2C_IFC_BUSHOLD_SHIFT 11 05623 #define _I2C_IFC_BUSHOLD_MASK 0x800UL 05624 #define _I2C_IFC_BUSHOLD_DEFAULT 0x00000000UL 05625 #define I2C_IFC_BUSHOLD_DEFAULT (_I2C_IFC_BUSHOLD_DEFAULT << 11) 05626 #define I2C_IFC_TXOF (0x1UL << 12) 05627 #define _I2C_IFC_TXOF_SHIFT 12 05628 #define _I2C_IFC_TXOF_MASK 0x1000UL 05629 #define _I2C_IFC_TXOF_DEFAULT 0x00000000UL 05630 #define I2C_IFC_TXOF_DEFAULT (_I2C_IFC_TXOF_DEFAULT << 12) 05631 #define I2C_IFC_RXUF (0x1UL << 13) 05632 #define _I2C_IFC_RXUF_SHIFT 13 05633 #define _I2C_IFC_RXUF_MASK 0x2000UL 05634 #define _I2C_IFC_RXUF_DEFAULT 0x00000000UL 05635 #define I2C_IFC_RXUF_DEFAULT (_I2C_IFC_RXUF_DEFAULT << 13) 05636 #define I2C_IFC_BITO (0x1UL << 14) 05637 #define _I2C_IFC_BITO_SHIFT 14 05638 #define _I2C_IFC_BITO_MASK 0x4000UL 05639 #define _I2C_IFC_BITO_DEFAULT 0x00000000UL 05640 #define I2C_IFC_BITO_DEFAULT (_I2C_IFC_BITO_DEFAULT << 14) 05641 #define I2C_IFC_CLTO (0x1UL << 15) 05642 #define _I2C_IFC_CLTO_SHIFT 15 05643 #define _I2C_IFC_CLTO_MASK 0x8000UL 05644 #define _I2C_IFC_CLTO_DEFAULT 0x00000000UL 05645 #define I2C_IFC_CLTO_DEFAULT (_I2C_IFC_CLTO_DEFAULT << 15) 05646 #define I2C_IFC_SSTOP (0x1UL << 16) 05647 #define _I2C_IFC_SSTOP_SHIFT 16 05648 #define _I2C_IFC_SSTOP_MASK 0x10000UL 05649 #define _I2C_IFC_SSTOP_DEFAULT 0x00000000UL 05650 #define I2C_IFC_SSTOP_DEFAULT (_I2C_IFC_SSTOP_DEFAULT << 16) 05652 /* Bit fields for I2C IEN */ 05653 #define _I2C_IEN_RESETVALUE 0x00000000UL 05654 #define _I2C_IEN_MASK 0x0001FFFFUL 05655 #define I2C_IEN_START (0x1UL << 0) 05656 #define _I2C_IEN_START_SHIFT 0 05657 #define _I2C_IEN_START_MASK 0x1UL 05658 #define _I2C_IEN_START_DEFAULT 0x00000000UL 05659 #define I2C_IEN_START_DEFAULT (_I2C_IEN_START_DEFAULT << 0) 05660 #define I2C_IEN_RSTART (0x1UL << 1) 05661 #define _I2C_IEN_RSTART_SHIFT 1 05662 #define _I2C_IEN_RSTART_MASK 0x2UL 05663 #define _I2C_IEN_RSTART_DEFAULT 0x00000000UL 05664 #define I2C_IEN_RSTART_DEFAULT (_I2C_IEN_RSTART_DEFAULT << 1) 05665 #define I2C_IEN_ADDR (0x1UL << 2) 05666 #define _I2C_IEN_ADDR_SHIFT 2 05667 #define _I2C_IEN_ADDR_MASK 0x4UL 05668 #define _I2C_IEN_ADDR_DEFAULT 0x00000000UL 05669 #define I2C_IEN_ADDR_DEFAULT (_I2C_IEN_ADDR_DEFAULT << 2) 05670 #define I2C_IEN_TXC (0x1UL << 3) 05671 #define _I2C_IEN_TXC_SHIFT 3 05672 #define _I2C_IEN_TXC_MASK 0x8UL 05673 #define _I2C_IEN_TXC_DEFAULT 0x00000000UL 05674 #define I2C_IEN_TXC_DEFAULT (_I2C_IEN_TXC_DEFAULT << 3) 05675 #define I2C_IEN_TXBL (0x1UL << 4) 05676 #define _I2C_IEN_TXBL_SHIFT 4 05677 #define _I2C_IEN_TXBL_MASK 0x10UL 05678 #define _I2C_IEN_TXBL_DEFAULT 0x00000000UL 05679 #define I2C_IEN_TXBL_DEFAULT (_I2C_IEN_TXBL_DEFAULT << 4) 05680 #define I2C_IEN_RXDATAV (0x1UL << 5) 05681 #define _I2C_IEN_RXDATAV_SHIFT 5 05682 #define _I2C_IEN_RXDATAV_MASK 0x20UL 05683 #define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL 05684 #define I2C_IEN_RXDATAV_DEFAULT (_I2C_IEN_RXDATAV_DEFAULT << 5) 05685 #define I2C_IEN_ACK (0x1UL << 6) 05686 #define _I2C_IEN_ACK_SHIFT 6 05687 #define _I2C_IEN_ACK_MASK 0x40UL 05688 #define _I2C_IEN_ACK_DEFAULT 0x00000000UL 05689 #define I2C_IEN_ACK_DEFAULT (_I2C_IEN_ACK_DEFAULT << 6) 05690 #define I2C_IEN_NACK (0x1UL << 7) 05691 #define _I2C_IEN_NACK_SHIFT 7 05692 #define _I2C_IEN_NACK_MASK 0x80UL 05693 #define _I2C_IEN_NACK_DEFAULT 0x00000000UL 05694 #define I2C_IEN_NACK_DEFAULT (_I2C_IEN_NACK_DEFAULT << 7) 05695 #define I2C_IEN_MSTOP (0x1UL << 8) 05696 #define _I2C_IEN_MSTOP_SHIFT 8 05697 #define _I2C_IEN_MSTOP_MASK 0x100UL 05698 #define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL 05699 #define I2C_IEN_MSTOP_DEFAULT (_I2C_IEN_MSTOP_DEFAULT << 8) 05700 #define I2C_IEN_ARBLOST (0x1UL << 9) 05701 #define _I2C_IEN_ARBLOST_SHIFT 9 05702 #define _I2C_IEN_ARBLOST_MASK 0x200UL 05703 #define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL 05704 #define I2C_IEN_ARBLOST_DEFAULT (_I2C_IEN_ARBLOST_DEFAULT << 9) 05705 #define I2C_IEN_BUSERR (0x1UL << 10) 05706 #define _I2C_IEN_BUSERR_SHIFT 10 05707 #define _I2C_IEN_BUSERR_MASK 0x400UL 05708 #define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL 05709 #define I2C_IEN_BUSERR_DEFAULT (_I2C_IEN_BUSERR_DEFAULT << 10) 05710 #define I2C_IEN_BUSHOLD (0x1UL << 11) 05711 #define _I2C_IEN_BUSHOLD_SHIFT 11 05712 #define _I2C_IEN_BUSHOLD_MASK 0x800UL 05713 #define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL 05714 #define I2C_IEN_BUSHOLD_DEFAULT (_I2C_IEN_BUSHOLD_DEFAULT << 11) 05715 #define I2C_IEN_TXOF (0x1UL << 12) 05716 #define _I2C_IEN_TXOF_SHIFT 12 05717 #define _I2C_IEN_TXOF_MASK 0x1000UL 05718 #define _I2C_IEN_TXOF_DEFAULT 0x00000000UL 05719 #define I2C_IEN_TXOF_DEFAULT (_I2C_IEN_TXOF_DEFAULT << 12) 05720 #define I2C_IEN_RXUF (0x1UL << 13) 05721 #define _I2C_IEN_RXUF_SHIFT 13 05722 #define _I2C_IEN_RXUF_MASK 0x2000UL 05723 #define _I2C_IEN_RXUF_DEFAULT 0x00000000UL 05724 #define I2C_IEN_RXUF_DEFAULT (_I2C_IEN_RXUF_DEFAULT << 13) 05725 #define I2C_IEN_BITO (0x1UL << 14) 05726 #define _I2C_IEN_BITO_SHIFT 14 05727 #define _I2C_IEN_BITO_MASK 0x4000UL 05728 #define _I2C_IEN_BITO_DEFAULT 0x00000000UL 05729 #define I2C_IEN_BITO_DEFAULT (_I2C_IEN_BITO_DEFAULT << 14) 05730 #define I2C_IEN_CLTO (0x1UL << 15) 05731 #define _I2C_IEN_CLTO_SHIFT 15 05732 #define _I2C_IEN_CLTO_MASK 0x8000UL 05733 #define _I2C_IEN_CLTO_DEFAULT 0x00000000UL 05734 #define I2C_IEN_CLTO_DEFAULT (_I2C_IEN_CLTO_DEFAULT << 15) 05735 #define I2C_IEN_SSTOP (0x1UL << 16) 05736 #define _I2C_IEN_SSTOP_SHIFT 16 05737 #define _I2C_IEN_SSTOP_MASK 0x10000UL 05738 #define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL 05739 #define I2C_IEN_SSTOP_DEFAULT (_I2C_IEN_SSTOP_DEFAULT << 16) 05741 /* Bit fields for I2C ROUTE */ 05742 #define _I2C_ROUTE_RESETVALUE 0x00000000UL 05743 #define _I2C_ROUTE_MASK 0x00000303UL 05744 #define I2C_ROUTE_SDAPEN (0x1UL << 0) 05745 #define _I2C_ROUTE_SDAPEN_SHIFT 0 05746 #define _I2C_ROUTE_SDAPEN_MASK 0x1UL 05747 #define _I2C_ROUTE_SDAPEN_DEFAULT 0x00000000UL 05748 #define I2C_ROUTE_SDAPEN_DEFAULT (_I2C_ROUTE_SDAPEN_DEFAULT << 0) 05749 #define I2C_ROUTE_SCLPEN (0x1UL << 1) 05750 #define _I2C_ROUTE_SCLPEN_SHIFT 1 05751 #define _I2C_ROUTE_SCLPEN_MASK 0x2UL 05752 #define _I2C_ROUTE_SCLPEN_DEFAULT 0x00000000UL 05753 #define I2C_ROUTE_SCLPEN_DEFAULT (_I2C_ROUTE_SCLPEN_DEFAULT << 1) 05754 #define _I2C_ROUTE_LOCATION_SHIFT 8 05755 #define _I2C_ROUTE_LOCATION_MASK 0x300UL 05756 #define _I2C_ROUTE_LOCATION_DEFAULT 0x00000000UL 05757 #define _I2C_ROUTE_LOCATION_LOC0 0x00000000UL 05758 #define _I2C_ROUTE_LOCATION_LOC1 0x00000001UL 05759 #define _I2C_ROUTE_LOCATION_LOC2 0x00000002UL 05760 #define _I2C_ROUTE_LOCATION_LOC3 0x00000003UL 05761 #define I2C_ROUTE_LOCATION_DEFAULT (_I2C_ROUTE_LOCATION_DEFAULT << 8) 05762 #define I2C_ROUTE_LOCATION_LOC0 (_I2C_ROUTE_LOCATION_LOC0 << 8) 05763 #define I2C_ROUTE_LOCATION_LOC1 (_I2C_ROUTE_LOCATION_LOC1 << 8) 05764 #define I2C_ROUTE_LOCATION_LOC2 (_I2C_ROUTE_LOCATION_LOC2 << 8) 05765 #define I2C_ROUTE_LOCATION_LOC3 (_I2C_ROUTE_LOCATION_LOC3 << 8) 05771 /**************************************************************************/ 05776 /* Bit fields for ADC CTRL */ 05777 #define _ADC_CTRL_RESETVALUE 0x001F0000UL 05778 #define _ADC_CTRL_MASK 0x0F1F7F3BUL 05779 #define _ADC_CTRL_WARMUPMODE_SHIFT 0 05780 #define _ADC_CTRL_WARMUPMODE_MASK 0x3UL 05781 #define _ADC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL 05782 #define _ADC_CTRL_WARMUPMODE_NORMAL 0x00000000UL 05783 #define _ADC_CTRL_WARMUPMODE_FASTBG 0x00000001UL 05784 #define _ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM 0x00000002UL 05785 #define _ADC_CTRL_WARMUPMODE_KEEPADCWARM 0x00000003UL 05786 #define ADC_CTRL_WARMUPMODE_DEFAULT (_ADC_CTRL_WARMUPMODE_DEFAULT << 0) 05787 #define ADC_CTRL_WARMUPMODE_NORMAL (_ADC_CTRL_WARMUPMODE_NORMAL << 0) 05788 #define ADC_CTRL_WARMUPMODE_FASTBG (_ADC_CTRL_WARMUPMODE_FASTBG << 0) 05789 #define ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM (_ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM << 0) 05790 #define ADC_CTRL_WARMUPMODE_KEEPADCWARM (_ADC_CTRL_WARMUPMODE_KEEPADCWARM << 0) 05791 #define ADC_CTRL_TAILGATE (0x1UL << 3) 05792 #define _ADC_CTRL_TAILGATE_SHIFT 3 05793 #define _ADC_CTRL_TAILGATE_MASK 0x8UL 05794 #define _ADC_CTRL_TAILGATE_DEFAULT 0x00000000UL 05795 #define ADC_CTRL_TAILGATE_DEFAULT (_ADC_CTRL_TAILGATE_DEFAULT << 3) 05796 #define _ADC_CTRL_LPFMODE_SHIFT 4 05797 #define _ADC_CTRL_LPFMODE_MASK 0x30UL 05798 #define _ADC_CTRL_LPFMODE_DEFAULT 0x00000000UL 05799 #define _ADC_CTRL_LPFMODE_BYPASS 0x00000000UL 05800 #define _ADC_CTRL_LPFMODE_DECAP 0x00000001UL 05801 #define _ADC_CTRL_LPFMODE_RCFILT 0x00000002UL 05802 #define ADC_CTRL_LPFMODE_DEFAULT (_ADC_CTRL_LPFMODE_DEFAULT << 4) 05803 #define ADC_CTRL_LPFMODE_BYPASS (_ADC_CTRL_LPFMODE_BYPASS << 4) 05804 #define ADC_CTRL_LPFMODE_DECAP (_ADC_CTRL_LPFMODE_DECAP << 4) 05805 #define ADC_CTRL_LPFMODE_RCFILT (_ADC_CTRL_LPFMODE_RCFILT << 4) 05806 #define _ADC_CTRL_PRESC_SHIFT 8 05807 #define _ADC_CTRL_PRESC_MASK 0x7F00UL 05808 #define _ADC_CTRL_PRESC_DEFAULT 0x00000000UL 05809 #define _ADC_CTRL_PRESC_NODIVISION 0x00000000UL 05810 #define ADC_CTRL_PRESC_DEFAULT (_ADC_CTRL_PRESC_DEFAULT << 8) 05811 #define ADC_CTRL_PRESC_NODIVISION (_ADC_CTRL_PRESC_NODIVISION << 8) 05812 #define _ADC_CTRL_TIMEBASE_SHIFT 16 05813 #define _ADC_CTRL_TIMEBASE_MASK 0x1F0000UL 05814 #define _ADC_CTRL_TIMEBASE_DEFAULT 0x0000001FUL 05815 #define ADC_CTRL_TIMEBASE_DEFAULT (_ADC_CTRL_TIMEBASE_DEFAULT << 16) 05816 #define _ADC_CTRL_OVSRSEL_SHIFT 24 05817 #define _ADC_CTRL_OVSRSEL_MASK 0xF000000UL 05818 #define _ADC_CTRL_OVSRSEL_DEFAULT 0x00000000UL 05819 #define _ADC_CTRL_OVSRSEL_X2 0x00000000UL 05820 #define _ADC_CTRL_OVSRSEL_X4 0x00000001UL 05821 #define _ADC_CTRL_OVSRSEL_X8 0x00000002UL 05822 #define _ADC_CTRL_OVSRSEL_X16 0x00000003UL 05823 #define _ADC_CTRL_OVSRSEL_X32 0x00000004UL 05824 #define _ADC_CTRL_OVSRSEL_X64 0x00000005UL 05825 #define _ADC_CTRL_OVSRSEL_X128 0x00000006UL 05826 #define _ADC_CTRL_OVSRSEL_X256 0x00000007UL 05827 #define _ADC_CTRL_OVSRSEL_X512 0x00000008UL 05828 #define _ADC_CTRL_OVSRSEL_X1024 0x00000009UL 05829 #define _ADC_CTRL_OVSRSEL_X2048 0x0000000AUL 05830 #define _ADC_CTRL_OVSRSEL_X4096 0x0000000BUL 05831 #define ADC_CTRL_OVSRSEL_DEFAULT (_ADC_CTRL_OVSRSEL_DEFAULT << 24) 05832 #define ADC_CTRL_OVSRSEL_X2 (_ADC_CTRL_OVSRSEL_X2 << 24) 05833 #define ADC_CTRL_OVSRSEL_X4 (_ADC_CTRL_OVSRSEL_X4 << 24) 05834 #define ADC_CTRL_OVSRSEL_X8 (_ADC_CTRL_OVSRSEL_X8 << 24) 05835 #define ADC_CTRL_OVSRSEL_X16 (_ADC_CTRL_OVSRSEL_X16 << 24) 05836 #define ADC_CTRL_OVSRSEL_X32 (_ADC_CTRL_OVSRSEL_X32 << 24) 05837 #define ADC_CTRL_OVSRSEL_X64 (_ADC_CTRL_OVSRSEL_X64 << 24) 05838 #define ADC_CTRL_OVSRSEL_X128 (_ADC_CTRL_OVSRSEL_X128 << 24) 05839 #define ADC_CTRL_OVSRSEL_X256 (_ADC_CTRL_OVSRSEL_X256 << 24) 05840 #define ADC_CTRL_OVSRSEL_X512 (_ADC_CTRL_OVSRSEL_X512 << 24) 05841 #define ADC_CTRL_OVSRSEL_X1024 (_ADC_CTRL_OVSRSEL_X1024 << 24) 05842 #define ADC_CTRL_OVSRSEL_X2048 (_ADC_CTRL_OVSRSEL_X2048 << 24) 05843 #define ADC_CTRL_OVSRSEL_X4096 (_ADC_CTRL_OVSRSEL_X4096 << 24) 05845 /* Bit fields for ADC CMD */ 05846 #define _ADC_CMD_RESETVALUE 0x00000000UL 05847 #define _ADC_CMD_MASK 0x0000000FUL 05848 #define ADC_CMD_SINGLESTART (0x1UL << 0) 05849 #define _ADC_CMD_SINGLESTART_SHIFT 0 05850 #define _ADC_CMD_SINGLESTART_MASK 0x1UL 05851 #define _ADC_CMD_SINGLESTART_DEFAULT 0x00000000UL 05852 #define ADC_CMD_SINGLESTART_DEFAULT (_ADC_CMD_SINGLESTART_DEFAULT << 0) 05853 #define ADC_CMD_SINGLESTOP (0x1UL << 1) 05854 #define _ADC_CMD_SINGLESTOP_SHIFT 1 05855 #define _ADC_CMD_SINGLESTOP_MASK 0x2UL 05856 #define _ADC_CMD_SINGLESTOP_DEFAULT 0x00000000UL 05857 #define ADC_CMD_SINGLESTOP_DEFAULT (_ADC_CMD_SINGLESTOP_DEFAULT << 1) 05858 #define ADC_CMD_SCANSTART (0x1UL << 2) 05859 #define _ADC_CMD_SCANSTART_SHIFT 2 05860 #define _ADC_CMD_SCANSTART_MASK 0x4UL 05861 #define _ADC_CMD_SCANSTART_DEFAULT 0x00000000UL 05862 #define ADC_CMD_SCANSTART_DEFAULT (_ADC_CMD_SCANSTART_DEFAULT << 2) 05863 #define ADC_CMD_SCANSTOP (0x1UL << 3) 05864 #define _ADC_CMD_SCANSTOP_SHIFT 3 05865 #define _ADC_CMD_SCANSTOP_MASK 0x8UL 05866 #define _ADC_CMD_SCANSTOP_DEFAULT 0x00000000UL 05867 #define ADC_CMD_SCANSTOP_DEFAULT (_ADC_CMD_SCANSTOP_DEFAULT << 3) 05869 /* Bit fields for ADC STATUS */ 05870 #define _ADC_STATUS_RESETVALUE 0x00000000UL 05871 #define _ADC_STATUS_MASK 0x07031303UL 05872 #define ADC_STATUS_SINGLEACT (0x1UL << 0) 05873 #define _ADC_STATUS_SINGLEACT_SHIFT 0 05874 #define _ADC_STATUS_SINGLEACT_MASK 0x1UL 05875 #define _ADC_STATUS_SINGLEACT_DEFAULT 0x00000000UL 05876 #define ADC_STATUS_SINGLEACT_DEFAULT (_ADC_STATUS_SINGLEACT_DEFAULT << 0) 05877 #define ADC_STATUS_SCANACT (0x1UL << 1) 05878 #define _ADC_STATUS_SCANACT_SHIFT 1 05879 #define _ADC_STATUS_SCANACT_MASK 0x2UL 05880 #define _ADC_STATUS_SCANACT_DEFAULT 0x00000000UL 05881 #define ADC_STATUS_SCANACT_DEFAULT (_ADC_STATUS_SCANACT_DEFAULT << 1) 05882 #define ADC_STATUS_SINGLEREFWARM (0x1UL << 8) 05883 #define _ADC_STATUS_SINGLEREFWARM_SHIFT 8 05884 #define _ADC_STATUS_SINGLEREFWARM_MASK 0x100UL 05885 #define _ADC_STATUS_SINGLEREFWARM_DEFAULT 0x00000000UL 05886 #define ADC_STATUS_SINGLEREFWARM_DEFAULT (_ADC_STATUS_SINGLEREFWARM_DEFAULT << 8) 05887 #define ADC_STATUS_SCANREFWARM (0x1UL << 9) 05888 #define _ADC_STATUS_SCANREFWARM_SHIFT 9 05889 #define _ADC_STATUS_SCANREFWARM_MASK 0x200UL 05890 #define _ADC_STATUS_SCANREFWARM_DEFAULT 0x00000000UL 05891 #define ADC_STATUS_SCANREFWARM_DEFAULT (_ADC_STATUS_SCANREFWARM_DEFAULT << 9) 05892 #define ADC_STATUS_WARM (0x1UL << 12) 05893 #define _ADC_STATUS_WARM_SHIFT 12 05894 #define _ADC_STATUS_WARM_MASK 0x1000UL 05895 #define _ADC_STATUS_WARM_DEFAULT 0x00000000UL 05896 #define ADC_STATUS_WARM_DEFAULT (_ADC_STATUS_WARM_DEFAULT << 12) 05897 #define ADC_STATUS_SINGLEDV (0x1UL << 16) 05898 #define _ADC_STATUS_SINGLEDV_SHIFT 16 05899 #define _ADC_STATUS_SINGLEDV_MASK 0x10000UL 05900 #define _ADC_STATUS_SINGLEDV_DEFAULT 0x00000000UL 05901 #define ADC_STATUS_SINGLEDV_DEFAULT (_ADC_STATUS_SINGLEDV_DEFAULT << 16) 05902 #define ADC_STATUS_SCANDV (0x1UL << 17) 05903 #define _ADC_STATUS_SCANDV_SHIFT 17 05904 #define _ADC_STATUS_SCANDV_MASK 0x20000UL 05905 #define _ADC_STATUS_SCANDV_DEFAULT 0x00000000UL 05906 #define ADC_STATUS_SCANDV_DEFAULT (_ADC_STATUS_SCANDV_DEFAULT << 17) 05907 #define _ADC_STATUS_SCANDATASRC_SHIFT 24 05908 #define _ADC_STATUS_SCANDATASRC_MASK 0x7000000UL 05909 #define _ADC_STATUS_SCANDATASRC_DEFAULT 0x00000000UL 05910 #define _ADC_STATUS_SCANDATASRC_CH0 0x00000000UL 05911 #define _ADC_STATUS_SCANDATASRC_CH1 0x00000001UL 05912 #define _ADC_STATUS_SCANDATASRC_CH2 0x00000002UL 05913 #define _ADC_STATUS_SCANDATASRC_CH3 0x00000003UL 05914 #define _ADC_STATUS_SCANDATASRC_CH4 0x00000004UL 05915 #define _ADC_STATUS_SCANDATASRC_CH5 0x00000005UL 05916 #define _ADC_STATUS_SCANDATASRC_CH6 0x00000006UL 05917 #define _ADC_STATUS_SCANDATASRC_CH7 0x00000007UL 05918 #define ADC_STATUS_SCANDATASRC_DEFAULT (_ADC_STATUS_SCANDATASRC_DEFAULT << 24) 05919 #define ADC_STATUS_SCANDATASRC_CH0 (_ADC_STATUS_SCANDATASRC_CH0 << 24) 05920 #define ADC_STATUS_SCANDATASRC_CH1 (_ADC_STATUS_SCANDATASRC_CH1 << 24) 05921 #define ADC_STATUS_SCANDATASRC_CH2 (_ADC_STATUS_SCANDATASRC_CH2 << 24) 05922 #define ADC_STATUS_SCANDATASRC_CH3 (_ADC_STATUS_SCANDATASRC_CH3 << 24) 05923 #define ADC_STATUS_SCANDATASRC_CH4 (_ADC_STATUS_SCANDATASRC_CH4 << 24) 05924 #define ADC_STATUS_SCANDATASRC_CH5 (_ADC_STATUS_SCANDATASRC_CH5 << 24) 05925 #define ADC_STATUS_SCANDATASRC_CH6 (_ADC_STATUS_SCANDATASRC_CH6 << 24) 05926 #define ADC_STATUS_SCANDATASRC_CH7 (_ADC_STATUS_SCANDATASRC_CH7 << 24) 05928 /* Bit fields for ADC SINGLECTRL */ 05929 #define _ADC_SINGLECTRL_RESETVALUE 0x00000000UL 05930 #define _ADC_SINGLECTRL_MASK 0x71F70F37UL 05931 #define ADC_SINGLECTRL_REP (0x1UL << 0) 05932 #define _ADC_SINGLECTRL_REP_SHIFT 0 05933 #define _ADC_SINGLECTRL_REP_MASK 0x1UL 05934 #define _ADC_SINGLECTRL_REP_DEFAULT 0x00000000UL 05935 #define ADC_SINGLECTRL_REP_DEFAULT (_ADC_SINGLECTRL_REP_DEFAULT << 0) 05936 #define ADC_SINGLECTRL_DIFF (0x1UL << 1) 05937 #define _ADC_SINGLECTRL_DIFF_SHIFT 1 05938 #define _ADC_SINGLECTRL_DIFF_MASK 0x2UL 05939 #define _ADC_SINGLECTRL_DIFF_DEFAULT 0x00000000UL 05940 #define ADC_SINGLECTRL_DIFF_DEFAULT (_ADC_SINGLECTRL_DIFF_DEFAULT << 1) 05941 #define ADC_SINGLECTRL_ADJ (0x1UL << 2) 05942 #define _ADC_SINGLECTRL_ADJ_SHIFT 2 05943 #define _ADC_SINGLECTRL_ADJ_MASK 0x4UL 05944 #define _ADC_SINGLECTRL_ADJ_DEFAULT 0x00000000UL 05945 #define _ADC_SINGLECTRL_ADJ_RIGHT 0x00000000UL 05946 #define _ADC_SINGLECTRL_ADJ_LEFT 0x00000001UL 05947 #define ADC_SINGLECTRL_ADJ_DEFAULT (_ADC_SINGLECTRL_ADJ_DEFAULT << 2) 05948 #define ADC_SINGLECTRL_ADJ_RIGHT (_ADC_SINGLECTRL_ADJ_RIGHT << 2) 05949 #define ADC_SINGLECTRL_ADJ_LEFT (_ADC_SINGLECTRL_ADJ_LEFT << 2) 05950 #define _ADC_SINGLECTRL_RES_SHIFT 4 05951 #define _ADC_SINGLECTRL_RES_MASK 0x30UL 05952 #define _ADC_SINGLECTRL_RES_DEFAULT 0x00000000UL 05953 #define _ADC_SINGLECTRL_RES_12BIT 0x00000000UL 05954 #define _ADC_SINGLECTRL_RES_8BIT 0x00000001UL 05955 #define _ADC_SINGLECTRL_RES_6BIT 0x00000002UL 05956 #define _ADC_SINGLECTRL_RES_OVS 0x00000003UL 05957 #define ADC_SINGLECTRL_RES_DEFAULT (_ADC_SINGLECTRL_RES_DEFAULT << 4) 05958 #define ADC_SINGLECTRL_RES_12BIT (_ADC_SINGLECTRL_RES_12BIT << 4) 05959 #define ADC_SINGLECTRL_RES_8BIT (_ADC_SINGLECTRL_RES_8BIT << 4) 05960 #define ADC_SINGLECTRL_RES_6BIT (_ADC_SINGLECTRL_RES_6BIT << 4) 05961 #define ADC_SINGLECTRL_RES_OVS (_ADC_SINGLECTRL_RES_OVS << 4) 05962 #define _ADC_SINGLECTRL_INPUTSEL_SHIFT 8 05963 #define _ADC_SINGLECTRL_INPUTSEL_MASK 0xF00UL 05964 #define _ADC_SINGLECTRL_INPUTSEL_DEFAULT 0x00000000UL 05965 #define _ADC_SINGLECTRL_INPUTSEL_CH0 0x00000000UL 05966 #define _ADC_SINGLECTRL_INPUTSEL_CH0CH1 0x00000000UL 05967 #define _ADC_SINGLECTRL_INPUTSEL_CH1 0x00000001UL 05968 #define _ADC_SINGLECTRL_INPUTSEL_CH2CH3 0x00000001UL 05969 #define _ADC_SINGLECTRL_INPUTSEL_CH2 0x00000002UL 05970 #define _ADC_SINGLECTRL_INPUTSEL_CH4CH5 0x00000002UL 05971 #define _ADC_SINGLECTRL_INPUTSEL_CH6CH7 0x00000003UL 05972 #define _ADC_SINGLECTRL_INPUTSEL_CH3 0x00000003UL 05973 #define _ADC_SINGLECTRL_INPUTSEL_CH4 0x00000004UL 05974 #define _ADC_SINGLECTRL_INPUTSEL_DIFF0 0x00000004UL 05975 #define _ADC_SINGLECTRL_INPUTSEL_CH5 0x00000005UL 05976 #define _ADC_SINGLECTRL_INPUTSEL_CH6 0x00000006UL 05977 #define _ADC_SINGLECTRL_INPUTSEL_CH7 0x00000007UL 05978 #define _ADC_SINGLECTRL_INPUTSEL_TEMP 0x00000008UL 05979 #define _ADC_SINGLECTRL_INPUTSEL_VDDDIV3 0x00000009UL 05980 #define _ADC_SINGLECTRL_INPUTSEL_VDD 0x0000000AUL 05981 #define _ADC_SINGLECTRL_INPUTSEL_VSS 0x0000000BUL 05982 #define _ADC_SINGLECTRL_INPUTSEL_VREFDIV2 0x0000000CUL 05983 #define _ADC_SINGLECTRL_INPUTSEL_DAC0OUT0 0x0000000DUL 05984 #define _ADC_SINGLECTRL_INPUTSEL_DAC0OUT1 0x0000000EUL 05985 #define ADC_SINGLECTRL_INPUTSEL_DEFAULT (_ADC_SINGLECTRL_INPUTSEL_DEFAULT << 8) 05986 #define ADC_SINGLECTRL_INPUTSEL_CH0 (_ADC_SINGLECTRL_INPUTSEL_CH0 << 8) 05987 #define ADC_SINGLECTRL_INPUTSEL_CH0CH1 (_ADC_SINGLECTRL_INPUTSEL_CH0CH1 << 8) 05988 #define ADC_SINGLECTRL_INPUTSEL_CH1 (_ADC_SINGLECTRL_INPUTSEL_CH1 << 8) 05989 #define ADC_SINGLECTRL_INPUTSEL_CH2CH3 (_ADC_SINGLECTRL_INPUTSEL_CH2CH3 << 8) 05990 #define ADC_SINGLECTRL_INPUTSEL_CH2 (_ADC_SINGLECTRL_INPUTSEL_CH2 << 8) 05991 #define ADC_SINGLECTRL_INPUTSEL_CH4CH5 (_ADC_SINGLECTRL_INPUTSEL_CH4CH5 << 8) 05992 #define ADC_SINGLECTRL_INPUTSEL_CH6CH7 (_ADC_SINGLECTRL_INPUTSEL_CH6CH7 << 8) 05993 #define ADC_SINGLECTRL_INPUTSEL_CH3 (_ADC_SINGLECTRL_INPUTSEL_CH3 << 8) 05994 #define ADC_SINGLECTRL_INPUTSEL_CH4 (_ADC_SINGLECTRL_INPUTSEL_CH4 << 8) 05995 #define ADC_SINGLECTRL_INPUTSEL_DIFF0 (_ADC_SINGLECTRL_INPUTSEL_DIFF0 << 8) 05996 #define ADC_SINGLECTRL_INPUTSEL_CH5 (_ADC_SINGLECTRL_INPUTSEL_CH5 << 8) 05997 #define ADC_SINGLECTRL_INPUTSEL_CH6 (_ADC_SINGLECTRL_INPUTSEL_CH6 << 8) 05998 #define ADC_SINGLECTRL_INPUTSEL_CH7 (_ADC_SINGLECTRL_INPUTSEL_CH7 << 8) 05999 #define ADC_SINGLECTRL_INPUTSEL_TEMP (_ADC_SINGLECTRL_INPUTSEL_TEMP << 8) 06000 #define ADC_SINGLECTRL_INPUTSEL_VDDDIV3 (_ADC_SINGLECTRL_INPUTSEL_VDDDIV3 << 8) 06001 #define ADC_SINGLECTRL_INPUTSEL_VDD (_ADC_SINGLECTRL_INPUTSEL_VDD << 8) 06002 #define ADC_SINGLECTRL_INPUTSEL_VSS (_ADC_SINGLECTRL_INPUTSEL_VSS << 8) 06003 #define ADC_SINGLECTRL_INPUTSEL_VREFDIV2 (_ADC_SINGLECTRL_INPUTSEL_VREFDIV2 << 8) 06004 #define ADC_SINGLECTRL_INPUTSEL_DAC0OUT0 (_ADC_SINGLECTRL_INPUTSEL_DAC0OUT0 << 8) 06005 #define ADC_SINGLECTRL_INPUTSEL_DAC0OUT1 (_ADC_SINGLECTRL_INPUTSEL_DAC0OUT1 << 8) 06006 #define _ADC_SINGLECTRL_REF_SHIFT 16 06007 #define _ADC_SINGLECTRL_REF_MASK 0x70000UL 06008 #define _ADC_SINGLECTRL_REF_DEFAULT 0x00000000UL 06009 #define _ADC_SINGLECTRL_REF_1V25 0x00000000UL 06010 #define _ADC_SINGLECTRL_REF_2V5 0x00000001UL 06011 #define _ADC_SINGLECTRL_REF_VDD 0x00000002UL 06012 #define _ADC_SINGLECTRL_REF_5VDIFF 0x00000003UL 06013 #define _ADC_SINGLECTRL_REF_EXTSINGLE 0x00000004UL 06014 #define _ADC_SINGLECTRL_REF_2XEXTDIFF 0x00000005UL 06015 #define _ADC_SINGLECTRL_REF_2XVDD 0x00000006UL 06016 #define ADC_SINGLECTRL_REF_DEFAULT (_ADC_SINGLECTRL_REF_DEFAULT << 16) 06017 #define ADC_SINGLECTRL_REF_1V25 (_ADC_SINGLECTRL_REF_1V25 << 16) 06018 #define ADC_SINGLECTRL_REF_2V5 (_ADC_SINGLECTRL_REF_2V5 << 16) 06019 #define ADC_SINGLECTRL_REF_VDD (_ADC_SINGLECTRL_REF_VDD << 16) 06020 #define ADC_SINGLECTRL_REF_5VDIFF (_ADC_SINGLECTRL_REF_5VDIFF << 16) 06021 #define ADC_SINGLECTRL_REF_EXTSINGLE (_ADC_SINGLECTRL_REF_EXTSINGLE << 16) 06022 #define ADC_SINGLECTRL_REF_2XEXTDIFF (_ADC_SINGLECTRL_REF_2XEXTDIFF << 16) 06023 #define ADC_SINGLECTRL_REF_2XVDD (_ADC_SINGLECTRL_REF_2XVDD << 16) 06024 #define _ADC_SINGLECTRL_AT_SHIFT 20 06025 #define _ADC_SINGLECTRL_AT_MASK 0xF00000UL 06026 #define _ADC_SINGLECTRL_AT_DEFAULT 0x00000000UL 06027 #define _ADC_SINGLECTRL_AT_1CYCLE 0x00000000UL 06028 #define _ADC_SINGLECTRL_AT_2CYCLES 0x00000001UL 06029 #define _ADC_SINGLECTRL_AT_4CYCLES 0x00000002UL 06030 #define _ADC_SINGLECTRL_AT_8CYCLES 0x00000003UL 06031 #define _ADC_SINGLECTRL_AT_16CYCLES 0x00000004UL 06032 #define _ADC_SINGLECTRL_AT_32CYCLES 0x00000005UL 06033 #define _ADC_SINGLECTRL_AT_64CYCLES 0x00000006UL 06034 #define _ADC_SINGLECTRL_AT_128CYCLES 0x00000007UL 06035 #define _ADC_SINGLECTRL_AT_256CYCLES 0x00000008UL 06036 #define ADC_SINGLECTRL_AT_DEFAULT (_ADC_SINGLECTRL_AT_DEFAULT << 20) 06037 #define ADC_SINGLECTRL_AT_1CYCLE (_ADC_SINGLECTRL_AT_1CYCLE << 20) 06038 #define ADC_SINGLECTRL_AT_2CYCLES (_ADC_SINGLECTRL_AT_2CYCLES << 20) 06039 #define ADC_SINGLECTRL_AT_4CYCLES (_ADC_SINGLECTRL_AT_4CYCLES << 20) 06040 #define ADC_SINGLECTRL_AT_8CYCLES (_ADC_SINGLECTRL_AT_8CYCLES << 20) 06041 #define ADC_SINGLECTRL_AT_16CYCLES (_ADC_SINGLECTRL_AT_16CYCLES << 20) 06042 #define ADC_SINGLECTRL_AT_32CYCLES (_ADC_SINGLECTRL_AT_32CYCLES << 20) 06043 #define ADC_SINGLECTRL_AT_64CYCLES (_ADC_SINGLECTRL_AT_64CYCLES << 20) 06044 #define ADC_SINGLECTRL_AT_128CYCLES (_ADC_SINGLECTRL_AT_128CYCLES << 20) 06045 #define ADC_SINGLECTRL_AT_256CYCLES (_ADC_SINGLECTRL_AT_256CYCLES << 20) 06046 #define ADC_SINGLECTRL_PRSEN (0x1UL << 24) 06047 #define _ADC_SINGLECTRL_PRSEN_SHIFT 24 06048 #define _ADC_SINGLECTRL_PRSEN_MASK 0x1000000UL 06049 #define _ADC_SINGLECTRL_PRSEN_DEFAULT 0x00000000UL 06050 #define ADC_SINGLECTRL_PRSEN_DEFAULT (_ADC_SINGLECTRL_PRSEN_DEFAULT << 24) 06051 #define _ADC_SINGLECTRL_PRSSEL_SHIFT 28 06052 #define _ADC_SINGLECTRL_PRSSEL_MASK 0x70000000UL 06053 #define _ADC_SINGLECTRL_PRSSEL_DEFAULT 0x00000000UL 06054 #define _ADC_SINGLECTRL_PRSSEL_PRSCH0 0x00000000UL 06055 #define _ADC_SINGLECTRL_PRSSEL_PRSCH1 0x00000001UL 06056 #define _ADC_SINGLECTRL_PRSSEL_PRSCH2 0x00000002UL 06057 #define _ADC_SINGLECTRL_PRSSEL_PRSCH3 0x00000003UL 06058 #define _ADC_SINGLECTRL_PRSSEL_PRSCH4 0x00000004UL 06059 #define _ADC_SINGLECTRL_PRSSEL_PRSCH5 0x00000005UL 06060 #define _ADC_SINGLECTRL_PRSSEL_PRSCH6 0x00000006UL 06061 #define _ADC_SINGLECTRL_PRSSEL_PRSCH7 0x00000007UL 06062 #define ADC_SINGLECTRL_PRSSEL_DEFAULT (_ADC_SINGLECTRL_PRSSEL_DEFAULT << 28) 06063 #define ADC_SINGLECTRL_PRSSEL_PRSCH0 (_ADC_SINGLECTRL_PRSSEL_PRSCH0 << 28) 06064 #define ADC_SINGLECTRL_PRSSEL_PRSCH1 (_ADC_SINGLECTRL_PRSSEL_PRSCH1 << 28) 06065 #define ADC_SINGLECTRL_PRSSEL_PRSCH2 (_ADC_SINGLECTRL_PRSSEL_PRSCH2 << 28) 06066 #define ADC_SINGLECTRL_PRSSEL_PRSCH3 (_ADC_SINGLECTRL_PRSSEL_PRSCH3 << 28) 06067 #define ADC_SINGLECTRL_PRSSEL_PRSCH4 (_ADC_SINGLECTRL_PRSSEL_PRSCH4 << 28) 06068 #define ADC_SINGLECTRL_PRSSEL_PRSCH5 (_ADC_SINGLECTRL_PRSSEL_PRSCH5 << 28) 06069 #define ADC_SINGLECTRL_PRSSEL_PRSCH6 (_ADC_SINGLECTRL_PRSSEL_PRSCH6 << 28) 06070 #define ADC_SINGLECTRL_PRSSEL_PRSCH7 (_ADC_SINGLECTRL_PRSSEL_PRSCH7 << 28) 06072 /* Bit fields for ADC SCANCTRL */ 06073 #define _ADC_SCANCTRL_RESETVALUE 0x00000000UL 06074 #define _ADC_SCANCTRL_MASK 0x71F7FF37UL 06075 #define ADC_SCANCTRL_REP (0x1UL << 0) 06076 #define _ADC_SCANCTRL_REP_SHIFT 0 06077 #define _ADC_SCANCTRL_REP_MASK 0x1UL 06078 #define _ADC_SCANCTRL_REP_DEFAULT 0x00000000UL 06079 #define ADC_SCANCTRL_REP_DEFAULT (_ADC_SCANCTRL_REP_DEFAULT << 0) 06080 #define ADC_SCANCTRL_DIFF (0x1UL << 1) 06081 #define _ADC_SCANCTRL_DIFF_SHIFT 1 06082 #define _ADC_SCANCTRL_DIFF_MASK 0x2UL 06083 #define _ADC_SCANCTRL_DIFF_DEFAULT 0x00000000UL 06084 #define ADC_SCANCTRL_DIFF_DEFAULT (_ADC_SCANCTRL_DIFF_DEFAULT << 1) 06085 #define ADC_SCANCTRL_ADJ (0x1UL << 2) 06086 #define _ADC_SCANCTRL_ADJ_SHIFT 2 06087 #define _ADC_SCANCTRL_ADJ_MASK 0x4UL 06088 #define _ADC_SCANCTRL_ADJ_DEFAULT 0x00000000UL 06089 #define _ADC_SCANCTRL_ADJ_RIGHT 0x00000000UL 06090 #define _ADC_SCANCTRL_ADJ_LEFT 0x00000001UL 06091 #define ADC_SCANCTRL_ADJ_DEFAULT (_ADC_SCANCTRL_ADJ_DEFAULT << 2) 06092 #define ADC_SCANCTRL_ADJ_RIGHT (_ADC_SCANCTRL_ADJ_RIGHT << 2) 06093 #define ADC_SCANCTRL_ADJ_LEFT (_ADC_SCANCTRL_ADJ_LEFT << 2) 06094 #define _ADC_SCANCTRL_RES_SHIFT 4 06095 #define _ADC_SCANCTRL_RES_MASK 0x30UL 06096 #define _ADC_SCANCTRL_RES_DEFAULT 0x00000000UL 06097 #define _ADC_SCANCTRL_RES_12BIT 0x00000000UL 06098 #define _ADC_SCANCTRL_RES_8BIT 0x00000001UL 06099 #define _ADC_SCANCTRL_RES_6BIT 0x00000002UL 06100 #define _ADC_SCANCTRL_RES_OVS 0x00000003UL 06101 #define ADC_SCANCTRL_RES_DEFAULT (_ADC_SCANCTRL_RES_DEFAULT << 4) 06102 #define ADC_SCANCTRL_RES_12BIT (_ADC_SCANCTRL_RES_12BIT << 4) 06103 #define ADC_SCANCTRL_RES_8BIT (_ADC_SCANCTRL_RES_8BIT << 4) 06104 #define ADC_SCANCTRL_RES_6BIT (_ADC_SCANCTRL_RES_6BIT << 4) 06105 #define ADC_SCANCTRL_RES_OVS (_ADC_SCANCTRL_RES_OVS << 4) 06106 #define _ADC_SCANCTRL_INPUTMASK_SHIFT 8 06107 #define _ADC_SCANCTRL_INPUTMASK_MASK 0xFF00UL 06108 #define _ADC_SCANCTRL_INPUTMASK_DEFAULT 0x00000000UL 06109 #define _ADC_SCANCTRL_INPUTMASK_CH0 0x00000001UL 06110 #define _ADC_SCANCTRL_INPUTMASK_CH0CH1 0x00000001UL 06111 #define _ADC_SCANCTRL_INPUTMASK_CH1 0x00000002UL 06112 #define _ADC_SCANCTRL_INPUTMASK_CH2CH3 0x00000002UL 06113 #define _ADC_SCANCTRL_INPUTMASK_CH2 0x00000004UL 06114 #define _ADC_SCANCTRL_INPUTMASK_CH4CH5 0x00000004UL 06115 #define _ADC_SCANCTRL_INPUTMASK_CH6CH7 0x00000008UL 06116 #define _ADC_SCANCTRL_INPUTMASK_CH3 0x00000008UL 06117 #define _ADC_SCANCTRL_INPUTMASK_CH4 0x00000010UL 06118 #define _ADC_SCANCTRL_INPUTMASK_CH5 0x00000020UL 06119 #define _ADC_SCANCTRL_INPUTMASK_CH6 0x00000040UL 06120 #define _ADC_SCANCTRL_INPUTMASK_CH7 0x00000080UL 06121 #define ADC_SCANCTRL_INPUTMASK_DEFAULT (_ADC_SCANCTRL_INPUTMASK_DEFAULT << 8) 06122 #define ADC_SCANCTRL_INPUTMASK_CH0 (_ADC_SCANCTRL_INPUTMASK_CH0 << 8) 06123 #define ADC_SCANCTRL_INPUTMASK_CH0CH1 (_ADC_SCANCTRL_INPUTMASK_CH0CH1 << 8) 06124 #define ADC_SCANCTRL_INPUTMASK_CH1 (_ADC_SCANCTRL_INPUTMASK_CH1 << 8) 06125 #define ADC_SCANCTRL_INPUTMASK_CH2CH3 (_ADC_SCANCTRL_INPUTMASK_CH2CH3 << 8) 06126 #define ADC_SCANCTRL_INPUTMASK_CH2 (_ADC_SCANCTRL_INPUTMASK_CH2 << 8) 06127 #define ADC_SCANCTRL_INPUTMASK_CH4CH5 (_ADC_SCANCTRL_INPUTMASK_CH4CH5 << 8) 06128 #define ADC_SCANCTRL_INPUTMASK_CH6CH7 (_ADC_SCANCTRL_INPUTMASK_CH6CH7 << 8) 06129 #define ADC_SCANCTRL_INPUTMASK_CH3 (_ADC_SCANCTRL_INPUTMASK_CH3 << 8) 06130 #define ADC_SCANCTRL_INPUTMASK_CH4 (_ADC_SCANCTRL_INPUTMASK_CH4 << 8) 06131 #define ADC_SCANCTRL_INPUTMASK_CH5 (_ADC_SCANCTRL_INPUTMASK_CH5 << 8) 06132 #define ADC_SCANCTRL_INPUTMASK_CH6 (_ADC_SCANCTRL_INPUTMASK_CH6 << 8) 06133 #define ADC_SCANCTRL_INPUTMASK_CH7 (_ADC_SCANCTRL_INPUTMASK_CH7 << 8) 06134 #define _ADC_SCANCTRL_REF_SHIFT 16 06135 #define _ADC_SCANCTRL_REF_MASK 0x70000UL 06136 #define _ADC_SCANCTRL_REF_DEFAULT 0x00000000UL 06137 #define _ADC_SCANCTRL_REF_1V25 0x00000000UL 06138 #define _ADC_SCANCTRL_REF_2V5 0x00000001UL 06139 #define _ADC_SCANCTRL_REF_VDD 0x00000002UL 06140 #define _ADC_SCANCTRL_REF_5VDIFF 0x00000003UL 06141 #define _ADC_SCANCTRL_REF_EXTSINGLE 0x00000004UL 06142 #define _ADC_SCANCTRL_REF_2XEXTDIFF 0x00000005UL 06143 #define _ADC_SCANCTRL_REF_2XVDD 0x00000006UL 06144 #define ADC_SCANCTRL_REF_DEFAULT (_ADC_SCANCTRL_REF_DEFAULT << 16) 06145 #define ADC_SCANCTRL_REF_1V25 (_ADC_SCANCTRL_REF_1V25 << 16) 06146 #define ADC_SCANCTRL_REF_2V5 (_ADC_SCANCTRL_REF_2V5 << 16) 06147 #define ADC_SCANCTRL_REF_VDD (_ADC_SCANCTRL_REF_VDD << 16) 06148 #define ADC_SCANCTRL_REF_5VDIFF (_ADC_SCANCTRL_REF_5VDIFF << 16) 06149 #define ADC_SCANCTRL_REF_EXTSINGLE (_ADC_SCANCTRL_REF_EXTSINGLE << 16) 06150 #define ADC_SCANCTRL_REF_2XEXTDIFF (_ADC_SCANCTRL_REF_2XEXTDIFF << 16) 06151 #define ADC_SCANCTRL_REF_2XVDD (_ADC_SCANCTRL_REF_2XVDD << 16) 06152 #define _ADC_SCANCTRL_AT_SHIFT 20 06153 #define _ADC_SCANCTRL_AT_MASK 0xF00000UL 06154 #define _ADC_SCANCTRL_AT_DEFAULT 0x00000000UL 06155 #define _ADC_SCANCTRL_AT_1CYCLE 0x00000000UL 06156 #define _ADC_SCANCTRL_AT_2CYCLES 0x00000001UL 06157 #define _ADC_SCANCTRL_AT_4CYCLES 0x00000002UL 06158 #define _ADC_SCANCTRL_AT_8CYCLES 0x00000003UL 06159 #define _ADC_SCANCTRL_AT_16CYCLES 0x00000004UL 06160 #define _ADC_SCANCTRL_AT_32CYCLES 0x00000005UL 06161 #define _ADC_SCANCTRL_AT_64CYCLES 0x00000006UL 06162 #define _ADC_SCANCTRL_AT_128CYCLES 0x00000007UL 06163 #define _ADC_SCANCTRL_AT_256CYCLES 0x00000008UL 06164 #define ADC_SCANCTRL_AT_DEFAULT (_ADC_SCANCTRL_AT_DEFAULT << 20) 06165 #define ADC_SCANCTRL_AT_1CYCLE (_ADC_SCANCTRL_AT_1CYCLE << 20) 06166 #define ADC_SCANCTRL_AT_2CYCLES (_ADC_SCANCTRL_AT_2CYCLES << 20) 06167 #define ADC_SCANCTRL_AT_4CYCLES (_ADC_SCANCTRL_AT_4CYCLES << 20) 06168 #define ADC_SCANCTRL_AT_8CYCLES (_ADC_SCANCTRL_AT_8CYCLES << 20) 06169 #define ADC_SCANCTRL_AT_16CYCLES (_ADC_SCANCTRL_AT_16CYCLES << 20) 06170 #define ADC_SCANCTRL_AT_32CYCLES (_ADC_SCANCTRL_AT_32CYCLES << 20) 06171 #define ADC_SCANCTRL_AT_64CYCLES (_ADC_SCANCTRL_AT_64CYCLES << 20) 06172 #define ADC_SCANCTRL_AT_128CYCLES (_ADC_SCANCTRL_AT_128CYCLES << 20) 06173 #define ADC_SCANCTRL_AT_256CYCLES (_ADC_SCANCTRL_AT_256CYCLES << 20) 06174 #define ADC_SCANCTRL_PRSEN (0x1UL << 24) 06175 #define _ADC_SCANCTRL_PRSEN_SHIFT 24 06176 #define _ADC_SCANCTRL_PRSEN_MASK 0x1000000UL 06177 #define _ADC_SCANCTRL_PRSEN_DEFAULT 0x00000000UL 06178 #define ADC_SCANCTRL_PRSEN_DEFAULT (_ADC_SCANCTRL_PRSEN_DEFAULT << 24) 06179 #define _ADC_SCANCTRL_PRSSEL_SHIFT 28 06180 #define _ADC_SCANCTRL_PRSSEL_MASK 0x70000000UL 06181 #define _ADC_SCANCTRL_PRSSEL_DEFAULT 0x00000000UL 06182 #define _ADC_SCANCTRL_PRSSEL_PRSCH0 0x00000000UL 06183 #define _ADC_SCANCTRL_PRSSEL_PRSCH1 0x00000001UL 06184 #define _ADC_SCANCTRL_PRSSEL_PRSCH2 0x00000002UL 06185 #define _ADC_SCANCTRL_PRSSEL_PRSCH3 0x00000003UL 06186 #define _ADC_SCANCTRL_PRSSEL_PRSCH4 0x00000004UL 06187 #define _ADC_SCANCTRL_PRSSEL_PRSCH5 0x00000005UL 06188 #define _ADC_SCANCTRL_PRSSEL_PRSCH6 0x00000006UL 06189 #define _ADC_SCANCTRL_PRSSEL_PRSCH7 0x00000007UL 06190 #define ADC_SCANCTRL_PRSSEL_DEFAULT (_ADC_SCANCTRL_PRSSEL_DEFAULT << 28) 06191 #define ADC_SCANCTRL_PRSSEL_PRSCH0 (_ADC_SCANCTRL_PRSSEL_PRSCH0 << 28) 06192 #define ADC_SCANCTRL_PRSSEL_PRSCH1 (_ADC_SCANCTRL_PRSSEL_PRSCH1 << 28) 06193 #define ADC_SCANCTRL_PRSSEL_PRSCH2 (_ADC_SCANCTRL_PRSSEL_PRSCH2 << 28) 06194 #define ADC_SCANCTRL_PRSSEL_PRSCH3 (_ADC_SCANCTRL_PRSSEL_PRSCH3 << 28) 06195 #define ADC_SCANCTRL_PRSSEL_PRSCH4 (_ADC_SCANCTRL_PRSSEL_PRSCH4 << 28) 06196 #define ADC_SCANCTRL_PRSSEL_PRSCH5 (_ADC_SCANCTRL_PRSSEL_PRSCH5 << 28) 06197 #define ADC_SCANCTRL_PRSSEL_PRSCH6 (_ADC_SCANCTRL_PRSSEL_PRSCH6 << 28) 06198 #define ADC_SCANCTRL_PRSSEL_PRSCH7 (_ADC_SCANCTRL_PRSSEL_PRSCH7 << 28) 06200 /* Bit fields for ADC IEN */ 06201 #define _ADC_IEN_RESETVALUE 0x00000000UL 06202 #define _ADC_IEN_MASK 0x00000303UL 06203 #define ADC_IEN_SINGLE (0x1UL << 0) 06204 #define _ADC_IEN_SINGLE_SHIFT 0 06205 #define _ADC_IEN_SINGLE_MASK 0x1UL 06206 #define _ADC_IEN_SINGLE_DEFAULT 0x00000000UL 06207 #define ADC_IEN_SINGLE_DEFAULT (_ADC_IEN_SINGLE_DEFAULT << 0) 06208 #define ADC_IEN_SCAN (0x1UL << 1) 06209 #define _ADC_IEN_SCAN_SHIFT 1 06210 #define _ADC_IEN_SCAN_MASK 0x2UL 06211 #define _ADC_IEN_SCAN_DEFAULT 0x00000000UL 06212 #define ADC_IEN_SCAN_DEFAULT (_ADC_IEN_SCAN_DEFAULT << 1) 06213 #define ADC_IEN_SINGLEOF (0x1UL << 8) 06214 #define _ADC_IEN_SINGLEOF_SHIFT 8 06215 #define _ADC_IEN_SINGLEOF_MASK 0x100UL 06216 #define _ADC_IEN_SINGLEOF_DEFAULT 0x00000000UL 06217 #define ADC_IEN_SINGLEOF_DEFAULT (_ADC_IEN_SINGLEOF_DEFAULT << 8) 06218 #define ADC_IEN_SCANOF (0x1UL << 9) 06219 #define _ADC_IEN_SCANOF_SHIFT 9 06220 #define _ADC_IEN_SCANOF_MASK 0x200UL 06221 #define _ADC_IEN_SCANOF_DEFAULT 0x00000000UL 06222 #define ADC_IEN_SCANOF_DEFAULT (_ADC_IEN_SCANOF_DEFAULT << 9) 06224 /* Bit fields for ADC IF */ 06225 #define _ADC_IF_RESETVALUE 0x00000000UL 06226 #define _ADC_IF_MASK 0x00000303UL 06227 #define ADC_IF_SINGLE (0x1UL << 0) 06228 #define _ADC_IF_SINGLE_SHIFT 0 06229 #define _ADC_IF_SINGLE_MASK 0x1UL 06230 #define _ADC_IF_SINGLE_DEFAULT 0x00000000UL 06231 #define ADC_IF_SINGLE_DEFAULT (_ADC_IF_SINGLE_DEFAULT << 0) 06232 #define ADC_IF_SCAN (0x1UL << 1) 06233 #define _ADC_IF_SCAN_SHIFT 1 06234 #define _ADC_IF_SCAN_MASK 0x2UL 06235 #define _ADC_IF_SCAN_DEFAULT 0x00000000UL 06236 #define ADC_IF_SCAN_DEFAULT (_ADC_IF_SCAN_DEFAULT << 1) 06237 #define ADC_IF_SINGLEOF (0x1UL << 8) 06238 #define _ADC_IF_SINGLEOF_SHIFT 8 06239 #define _ADC_IF_SINGLEOF_MASK 0x100UL 06240 #define _ADC_IF_SINGLEOF_DEFAULT 0x00000000UL 06241 #define ADC_IF_SINGLEOF_DEFAULT (_ADC_IF_SINGLEOF_DEFAULT << 8) 06242 #define ADC_IF_SCANOF (0x1UL << 9) 06243 #define _ADC_IF_SCANOF_SHIFT 9 06244 #define _ADC_IF_SCANOF_MASK 0x200UL 06245 #define _ADC_IF_SCANOF_DEFAULT 0x00000000UL 06246 #define ADC_IF_SCANOF_DEFAULT (_ADC_IF_SCANOF_DEFAULT << 9) 06248 /* Bit fields for ADC IFS */ 06249 #define _ADC_IFS_RESETVALUE 0x00000000UL 06250 #define _ADC_IFS_MASK 0x00000303UL 06251 #define ADC_IFS_SINGLE (0x1UL << 0) 06252 #define _ADC_IFS_SINGLE_SHIFT 0 06253 #define _ADC_IFS_SINGLE_MASK 0x1UL 06254 #define _ADC_IFS_SINGLE_DEFAULT 0x00000000UL 06255 #define ADC_IFS_SINGLE_DEFAULT (_ADC_IFS_SINGLE_DEFAULT << 0) 06256 #define ADC_IFS_SCAN (0x1UL << 1) 06257 #define _ADC_IFS_SCAN_SHIFT 1 06258 #define _ADC_IFS_SCAN_MASK 0x2UL 06259 #define _ADC_IFS_SCAN_DEFAULT 0x00000000UL 06260 #define ADC_IFS_SCAN_DEFAULT (_ADC_IFS_SCAN_DEFAULT << 1) 06261 #define ADC_IFS_SINGLEOF (0x1UL << 8) 06262 #define _ADC_IFS_SINGLEOF_SHIFT 8 06263 #define _ADC_IFS_SINGLEOF_MASK 0x100UL 06264 #define _ADC_IFS_SINGLEOF_DEFAULT 0x00000000UL 06265 #define ADC_IFS_SINGLEOF_DEFAULT (_ADC_IFS_SINGLEOF_DEFAULT << 8) 06266 #define ADC_IFS_SCANOF (0x1UL << 9) 06267 #define _ADC_IFS_SCANOF_SHIFT 9 06268 #define _ADC_IFS_SCANOF_MASK 0x200UL 06269 #define _ADC_IFS_SCANOF_DEFAULT 0x00000000UL 06270 #define ADC_IFS_SCANOF_DEFAULT (_ADC_IFS_SCANOF_DEFAULT << 9) 06272 /* Bit fields for ADC IFC */ 06273 #define _ADC_IFC_RESETVALUE 0x00000000UL 06274 #define _ADC_IFC_MASK 0x00000303UL 06275 #define ADC_IFC_SINGLE (0x1UL << 0) 06276 #define _ADC_IFC_SINGLE_SHIFT 0 06277 #define _ADC_IFC_SINGLE_MASK 0x1UL 06278 #define _ADC_IFC_SINGLE_DEFAULT 0x00000000UL 06279 #define ADC_IFC_SINGLE_DEFAULT (_ADC_IFC_SINGLE_DEFAULT << 0) 06280 #define ADC_IFC_SCAN (0x1UL << 1) 06281 #define _ADC_IFC_SCAN_SHIFT 1 06282 #define _ADC_IFC_SCAN_MASK 0x2UL 06283 #define _ADC_IFC_SCAN_DEFAULT 0x00000000UL 06284 #define ADC_IFC_SCAN_DEFAULT (_ADC_IFC_SCAN_DEFAULT << 1) 06285 #define ADC_IFC_SINGLEOF (0x1UL << 8) 06286 #define _ADC_IFC_SINGLEOF_SHIFT 8 06287 #define _ADC_IFC_SINGLEOF_MASK 0x100UL 06288 #define _ADC_IFC_SINGLEOF_DEFAULT 0x00000000UL 06289 #define ADC_IFC_SINGLEOF_DEFAULT (_ADC_IFC_SINGLEOF_DEFAULT << 8) 06290 #define ADC_IFC_SCANOF (0x1UL << 9) 06291 #define _ADC_IFC_SCANOF_SHIFT 9 06292 #define _ADC_IFC_SCANOF_MASK 0x200UL 06293 #define _ADC_IFC_SCANOF_DEFAULT 0x00000000UL 06294 #define ADC_IFC_SCANOF_DEFAULT (_ADC_IFC_SCANOF_DEFAULT << 9) 06296 /* Bit fields for ADC SINGLEDATA */ 06297 #define _ADC_SINGLEDATA_RESETVALUE 0x00000000UL 06298 #define _ADC_SINGLEDATA_MASK 0xFFFFFFFFUL 06299 #define _ADC_SINGLEDATA_DATA_SHIFT 0 06300 #define _ADC_SINGLEDATA_DATA_MASK 0xFFFFFFFFUL 06301 #define _ADC_SINGLEDATA_DATA_DEFAULT 0x00000000UL 06302 #define ADC_SINGLEDATA_DATA_DEFAULT (_ADC_SINGLEDATA_DATA_DEFAULT << 0) 06304 /* Bit fields for ADC SCANDATA */ 06305 #define _ADC_SCANDATA_RESETVALUE 0x00000000UL 06306 #define _ADC_SCANDATA_MASK 0xFFFFFFFFUL 06307 #define _ADC_SCANDATA_DATA_SHIFT 0 06308 #define _ADC_SCANDATA_DATA_MASK 0xFFFFFFFFUL 06309 #define _ADC_SCANDATA_DATA_DEFAULT 0x00000000UL 06310 #define ADC_SCANDATA_DATA_DEFAULT (_ADC_SCANDATA_DATA_DEFAULT << 0) 06312 /* Bit fields for ADC SINGLEDATAP */ 06313 #define _ADC_SINGLEDATAP_RESETVALUE 0x00000000UL 06314 #define _ADC_SINGLEDATAP_MASK 0xFFFFFFFFUL 06315 #define _ADC_SINGLEDATAP_DATAP_SHIFT 0 06316 #define _ADC_SINGLEDATAP_DATAP_MASK 0xFFFFFFFFUL 06317 #define _ADC_SINGLEDATAP_DATAP_DEFAULT 0x00000000UL 06318 #define ADC_SINGLEDATAP_DATAP_DEFAULT (_ADC_SINGLEDATAP_DATAP_DEFAULT << 0) 06320 /* Bit fields for ADC SCANDATAP */ 06321 #define _ADC_SCANDATAP_RESETVALUE 0x00000000UL 06322 #define _ADC_SCANDATAP_MASK 0xFFFFFFFFUL 06323 #define _ADC_SCANDATAP_DATAP_SHIFT 0 06324 #define _ADC_SCANDATAP_DATAP_MASK 0xFFFFFFFFUL 06325 #define _ADC_SCANDATAP_DATAP_DEFAULT 0x00000000UL 06326 #define ADC_SCANDATAP_DATAP_DEFAULT (_ADC_SCANDATAP_DATAP_DEFAULT << 0) 06328 /* Bit fields for ADC CAL */ 06329 #define _ADC_CAL_RESETVALUE 0x3F003F00UL 06330 #define _ADC_CAL_MASK 0x7F7F7F7FUL 06331 #define _ADC_CAL_SINGLEOFFSET_SHIFT 0 06332 #define _ADC_CAL_SINGLEOFFSET_MASK 0x7FUL 06333 #define _ADC_CAL_SINGLEOFFSET_DEFAULT 0x00000000UL 06334 #define ADC_CAL_SINGLEOFFSET_DEFAULT (_ADC_CAL_SINGLEOFFSET_DEFAULT << 0) 06335 #define _ADC_CAL_SINGLEGAIN_SHIFT 8 06336 #define _ADC_CAL_SINGLEGAIN_MASK 0x7F00UL 06337 #define _ADC_CAL_SINGLEGAIN_DEFAULT 0x0000003FUL 06338 #define ADC_CAL_SINGLEGAIN_DEFAULT (_ADC_CAL_SINGLEGAIN_DEFAULT << 8) 06339 #define _ADC_CAL_SCANOFFSET_SHIFT 16 06340 #define _ADC_CAL_SCANOFFSET_MASK 0x7F0000UL 06341 #define _ADC_CAL_SCANOFFSET_DEFAULT 0x00000000UL 06342 #define ADC_CAL_SCANOFFSET_DEFAULT (_ADC_CAL_SCANOFFSET_DEFAULT << 16) 06343 #define _ADC_CAL_SCANGAIN_SHIFT 24 06344 #define _ADC_CAL_SCANGAIN_MASK 0x7F000000UL 06345 #define _ADC_CAL_SCANGAIN_DEFAULT 0x0000003FUL 06346 #define ADC_CAL_SCANGAIN_DEFAULT (_ADC_CAL_SCANGAIN_DEFAULT << 24) 06348 /* Bit fields for ADC BIASPROG */ 06349 #define _ADC_BIASPROG_RESETVALUE 0x00000747UL 06350 #define _ADC_BIASPROG_MASK 0x00000F4FUL 06351 #define _ADC_BIASPROG_BIASPROG_SHIFT 0 06352 #define _ADC_BIASPROG_BIASPROG_MASK 0xFUL 06353 #define _ADC_BIASPROG_BIASPROG_DEFAULT 0x00000007UL 06354 #define ADC_BIASPROG_BIASPROG_DEFAULT (_ADC_BIASPROG_BIASPROG_DEFAULT << 0) 06355 #define ADC_BIASPROG_HALFBIAS (0x1UL << 6) 06356 #define _ADC_BIASPROG_HALFBIAS_SHIFT 6 06357 #define _ADC_BIASPROG_HALFBIAS_MASK 0x40UL 06358 #define _ADC_BIASPROG_HALFBIAS_DEFAULT 0x00000001UL 06359 #define ADC_BIASPROG_HALFBIAS_DEFAULT (_ADC_BIASPROG_HALFBIAS_DEFAULT << 6) 06360 #define _ADC_BIASPROG_COMPBIAS_SHIFT 8 06361 #define _ADC_BIASPROG_COMPBIAS_MASK 0xF00UL 06362 #define _ADC_BIASPROG_COMPBIAS_DEFAULT 0x00000007UL 06363 #define ADC_BIASPROG_COMPBIAS_DEFAULT (_ADC_BIASPROG_COMPBIAS_DEFAULT << 8) 06369 /**************************************************************************/ 06374 /* Bit fields for DAC CTRL */ 06375 #define _DAC_CTRL_RESETVALUE 0x00000010UL 06376 #define _DAC_CTRL_MASK 0x0037D3FFUL 06377 #define DAC_CTRL_DIFF (0x1UL << 0) 06378 #define _DAC_CTRL_DIFF_SHIFT 0 06379 #define _DAC_CTRL_DIFF_MASK 0x1UL 06380 #define _DAC_CTRL_DIFF_DEFAULT 0x00000000UL 06381 #define DAC_CTRL_DIFF_DEFAULT (_DAC_CTRL_DIFF_DEFAULT << 0) 06382 #define DAC_CTRL_SINEMODE (0x1UL << 1) 06383 #define _DAC_CTRL_SINEMODE_SHIFT 1 06384 #define _DAC_CTRL_SINEMODE_MASK 0x2UL 06385 #define _DAC_CTRL_SINEMODE_DEFAULT 0x00000000UL 06386 #define DAC_CTRL_SINEMODE_DEFAULT (_DAC_CTRL_SINEMODE_DEFAULT << 1) 06387 #define _DAC_CTRL_CONVMODE_SHIFT 2 06388 #define _DAC_CTRL_CONVMODE_MASK 0xCUL 06389 #define _DAC_CTRL_CONVMODE_DEFAULT 0x00000000UL 06390 #define _DAC_CTRL_CONVMODE_CONTINUOUS 0x00000000UL 06391 #define _DAC_CTRL_CONVMODE_SAMPLEHOLD 0x00000001UL 06392 #define _DAC_CTRL_CONVMODE_SAMPLEOFF 0x00000002UL 06393 #define DAC_CTRL_CONVMODE_DEFAULT (_DAC_CTRL_CONVMODE_DEFAULT << 2) 06394 #define DAC_CTRL_CONVMODE_CONTINUOUS (_DAC_CTRL_CONVMODE_CONTINUOUS << 2) 06395 #define DAC_CTRL_CONVMODE_SAMPLEHOLD (_DAC_CTRL_CONVMODE_SAMPLEHOLD << 2) 06396 #define DAC_CTRL_CONVMODE_SAMPLEOFF (_DAC_CTRL_CONVMODE_SAMPLEOFF << 2) 06397 #define _DAC_CTRL_OUTMODE_SHIFT 4 06398 #define _DAC_CTRL_OUTMODE_MASK 0x30UL 06399 #define _DAC_CTRL_OUTMODE_DISABLE 0x00000000UL 06400 #define _DAC_CTRL_OUTMODE_DEFAULT 0x00000001UL 06401 #define _DAC_CTRL_OUTMODE_PIN 0x00000001UL 06402 #define _DAC_CTRL_OUTMODE_ADC 0x00000002UL 06403 #define _DAC_CTRL_OUTMODE_PINADC 0x00000003UL 06404 #define DAC_CTRL_OUTMODE_DISABLE (_DAC_CTRL_OUTMODE_DISABLE << 4) 06405 #define DAC_CTRL_OUTMODE_DEFAULT (_DAC_CTRL_OUTMODE_DEFAULT << 4) 06406 #define DAC_CTRL_OUTMODE_PIN (_DAC_CTRL_OUTMODE_PIN << 4) 06407 #define DAC_CTRL_OUTMODE_ADC (_DAC_CTRL_OUTMODE_ADC << 4) 06408 #define DAC_CTRL_OUTMODE_PINADC (_DAC_CTRL_OUTMODE_PINADC << 4) 06409 #define DAC_CTRL_OUTENPRS (0x1UL << 6) 06410 #define _DAC_CTRL_OUTENPRS_SHIFT 6 06411 #define _DAC_CTRL_OUTENPRS_MASK 0x40UL 06412 #define _DAC_CTRL_OUTENPRS_DEFAULT 0x00000000UL 06413 #define DAC_CTRL_OUTENPRS_DEFAULT (_DAC_CTRL_OUTENPRS_DEFAULT << 6) 06414 #define DAC_CTRL_CH0PRESCRST (0x1UL << 7) 06415 #define _DAC_CTRL_CH0PRESCRST_SHIFT 7 06416 #define _DAC_CTRL_CH0PRESCRST_MASK 0x80UL 06417 #define _DAC_CTRL_CH0PRESCRST_DEFAULT 0x00000000UL 06418 #define DAC_CTRL_CH0PRESCRST_DEFAULT (_DAC_CTRL_CH0PRESCRST_DEFAULT << 7) 06419 #define _DAC_CTRL_REFSEL_SHIFT 8 06420 #define _DAC_CTRL_REFSEL_MASK 0x300UL 06421 #define _DAC_CTRL_REFSEL_DEFAULT 0x00000000UL 06422 #define _DAC_CTRL_REFSEL_1V25 0x00000000UL 06423 #define _DAC_CTRL_REFSEL_2V5 0x00000001UL 06424 #define _DAC_CTRL_REFSEL_VDD 0x00000002UL 06425 #define DAC_CTRL_REFSEL_DEFAULT (_DAC_CTRL_REFSEL_DEFAULT << 8) 06426 #define DAC_CTRL_REFSEL_1V25 (_DAC_CTRL_REFSEL_1V25 << 8) 06427 #define DAC_CTRL_REFSEL_2V5 (_DAC_CTRL_REFSEL_2V5 << 8) 06428 #define DAC_CTRL_REFSEL_VDD (_DAC_CTRL_REFSEL_VDD << 8) 06429 #define DAC_CTRL_LPFEN (0x1UL << 12) 06430 #define _DAC_CTRL_LPFEN_SHIFT 12 06431 #define _DAC_CTRL_LPFEN_MASK 0x1000UL 06432 #define _DAC_CTRL_LPFEN_DEFAULT 0x00000000UL 06433 #define DAC_CTRL_LPFEN_DEFAULT (_DAC_CTRL_LPFEN_DEFAULT << 12) 06434 #define _DAC_CTRL_LPFFREQ_SHIFT 14 06435 #define _DAC_CTRL_LPFFREQ_MASK 0xC000UL 06436 #define _DAC_CTRL_LPFFREQ_DEFAULT 0x00000000UL 06437 #define _DAC_CTRL_LPFFREQ_FREQ0 0x00000000UL 06438 #define _DAC_CTRL_LPFFREQ_FREQ1 0x00000001UL 06439 #define _DAC_CTRL_LPFFREQ_FREQ2 0x00000002UL 06440 #define _DAC_CTRL_LPFFREQ_FREQ3 0x00000003UL 06441 #define DAC_CTRL_LPFFREQ_DEFAULT (_DAC_CTRL_LPFFREQ_DEFAULT << 14) 06442 #define DAC_CTRL_LPFFREQ_FREQ0 (_DAC_CTRL_LPFFREQ_FREQ0 << 14) 06443 #define DAC_CTRL_LPFFREQ_FREQ1 (_DAC_CTRL_LPFFREQ_FREQ1 << 14) 06444 #define DAC_CTRL_LPFFREQ_FREQ2 (_DAC_CTRL_LPFFREQ_FREQ2 << 14) 06445 #define DAC_CTRL_LPFFREQ_FREQ3 (_DAC_CTRL_LPFFREQ_FREQ3 << 14) 06446 #define _DAC_CTRL_PRESC_SHIFT 16 06447 #define _DAC_CTRL_PRESC_MASK 0x70000UL 06448 #define _DAC_CTRL_PRESC_DEFAULT 0x00000000UL 06449 #define _DAC_CTRL_PRESC_NODIVISION 0x00000000UL 06450 #define DAC_CTRL_PRESC_DEFAULT (_DAC_CTRL_PRESC_DEFAULT << 16) 06451 #define DAC_CTRL_PRESC_NODIVISION (_DAC_CTRL_PRESC_NODIVISION << 16) 06452 #define _DAC_CTRL_REFRSEL_SHIFT 20 06453 #define _DAC_CTRL_REFRSEL_MASK 0x300000UL 06454 #define _DAC_CTRL_REFRSEL_DEFAULT 0x00000000UL 06455 #define _DAC_CTRL_REFRSEL_8CYCLES 0x00000000UL 06456 #define _DAC_CTRL_REFRSEL_16CYCLES 0x00000001UL 06457 #define _DAC_CTRL_REFRSEL_32CYCLES 0x00000002UL 06458 #define _DAC_CTRL_REFRSEL_64CYCLES 0x00000003UL 06459 #define DAC_CTRL_REFRSEL_DEFAULT (_DAC_CTRL_REFRSEL_DEFAULT << 20) 06460 #define DAC_CTRL_REFRSEL_8CYCLES (_DAC_CTRL_REFRSEL_8CYCLES << 20) 06461 #define DAC_CTRL_REFRSEL_16CYCLES (_DAC_CTRL_REFRSEL_16CYCLES << 20) 06462 #define DAC_CTRL_REFRSEL_32CYCLES (_DAC_CTRL_REFRSEL_32CYCLES << 20) 06463 #define DAC_CTRL_REFRSEL_64CYCLES (_DAC_CTRL_REFRSEL_64CYCLES << 20) 06465 /* Bit fields for DAC STATUS */ 06466 #define _DAC_STATUS_RESETVALUE 0x00000000UL 06467 #define _DAC_STATUS_MASK 0x00000003UL 06468 #define DAC_STATUS_CH0DV (0x1UL << 0) 06469 #define _DAC_STATUS_CH0DV_SHIFT 0 06470 #define _DAC_STATUS_CH0DV_MASK 0x1UL 06471 #define _DAC_STATUS_CH0DV_DEFAULT 0x00000000UL 06472 #define DAC_STATUS_CH0DV_DEFAULT (_DAC_STATUS_CH0DV_DEFAULT << 0) 06473 #define DAC_STATUS_CH1DV (0x1UL << 1) 06474 #define _DAC_STATUS_CH1DV_SHIFT 1 06475 #define _DAC_STATUS_CH1DV_MASK 0x2UL 06476 #define _DAC_STATUS_CH1DV_DEFAULT 0x00000000UL 06477 #define DAC_STATUS_CH1DV_DEFAULT (_DAC_STATUS_CH1DV_DEFAULT << 1) 06479 /* Bit fields for DAC CH0CTRL */ 06480 #define _DAC_CH0CTRL_RESETVALUE 0x00000000UL 06481 #define _DAC_CH0CTRL_MASK 0x00000077UL 06482 #define DAC_CH0CTRL_EN (0x1UL << 0) 06483 #define _DAC_CH0CTRL_EN_SHIFT 0 06484 #define _DAC_CH0CTRL_EN_MASK 0x1UL 06485 #define _DAC_CH0CTRL_EN_DEFAULT 0x00000000UL 06486 #define DAC_CH0CTRL_EN_DEFAULT (_DAC_CH0CTRL_EN_DEFAULT << 0) 06487 #define DAC_CH0CTRL_REFREN (0x1UL << 1) 06488 #define _DAC_CH0CTRL_REFREN_SHIFT 1 06489 #define _DAC_CH0CTRL_REFREN_MASK 0x2UL 06490 #define _DAC_CH0CTRL_REFREN_DEFAULT 0x00000000UL 06491 #define DAC_CH0CTRL_REFREN_DEFAULT (_DAC_CH0CTRL_REFREN_DEFAULT << 1) 06492 #define DAC_CH0CTRL_PRSEN (0x1UL << 2) 06493 #define _DAC_CH0CTRL_PRSEN_SHIFT 2 06494 #define _DAC_CH0CTRL_PRSEN_MASK 0x4UL 06495 #define _DAC_CH0CTRL_PRSEN_DEFAULT 0x00000000UL 06496 #define DAC_CH0CTRL_PRSEN_DEFAULT (_DAC_CH0CTRL_PRSEN_DEFAULT << 2) 06497 #define _DAC_CH0CTRL_PRSSEL_SHIFT 4 06498 #define _DAC_CH0CTRL_PRSSEL_MASK 0x70UL 06499 #define _DAC_CH0CTRL_PRSSEL_DEFAULT 0x00000000UL 06500 #define _DAC_CH0CTRL_PRSSEL_PRSCH0 0x00000000UL 06501 #define _DAC_CH0CTRL_PRSSEL_PRSCH1 0x00000001UL 06502 #define _DAC_CH0CTRL_PRSSEL_PRSCH2 0x00000002UL 06503 #define _DAC_CH0CTRL_PRSSEL_PRSCH3 0x00000003UL 06504 #define _DAC_CH0CTRL_PRSSEL_PRSCH4 0x00000004UL 06505 #define _DAC_CH0CTRL_PRSSEL_PRSCH5 0x00000005UL 06506 #define _DAC_CH0CTRL_PRSSEL_PRSCH6 0x00000006UL 06507 #define _DAC_CH0CTRL_PRSSEL_PRSCH7 0x00000007UL 06508 #define DAC_CH0CTRL_PRSSEL_DEFAULT (_DAC_CH0CTRL_PRSSEL_DEFAULT << 4) 06509 #define DAC_CH0CTRL_PRSSEL_PRSCH0 (_DAC_CH0CTRL_PRSSEL_PRSCH0 << 4) 06510 #define DAC_CH0CTRL_PRSSEL_PRSCH1 (_DAC_CH0CTRL_PRSSEL_PRSCH1 << 4) 06511 #define DAC_CH0CTRL_PRSSEL_PRSCH2 (_DAC_CH0CTRL_PRSSEL_PRSCH2 << 4) 06512 #define DAC_CH0CTRL_PRSSEL_PRSCH3 (_DAC_CH0CTRL_PRSSEL_PRSCH3 << 4) 06513 #define DAC_CH0CTRL_PRSSEL_PRSCH4 (_DAC_CH0CTRL_PRSSEL_PRSCH4 << 4) 06514 #define DAC_CH0CTRL_PRSSEL_PRSCH5 (_DAC_CH0CTRL_PRSSEL_PRSCH5 << 4) 06515 #define DAC_CH0CTRL_PRSSEL_PRSCH6 (_DAC_CH0CTRL_PRSSEL_PRSCH6 << 4) 06516 #define DAC_CH0CTRL_PRSSEL_PRSCH7 (_DAC_CH0CTRL_PRSSEL_PRSCH7 << 4) 06518 /* Bit fields for DAC CH1CTRL */ 06519 #define _DAC_CH1CTRL_RESETVALUE 0x00000000UL 06520 #define _DAC_CH1CTRL_MASK 0x00000077UL 06521 #define DAC_CH1CTRL_EN (0x1UL << 0) 06522 #define _DAC_CH1CTRL_EN_SHIFT 0 06523 #define _DAC_CH1CTRL_EN_MASK 0x1UL 06524 #define _DAC_CH1CTRL_EN_DEFAULT 0x00000000UL 06525 #define DAC_CH1CTRL_EN_DEFAULT (_DAC_CH1CTRL_EN_DEFAULT << 0) 06526 #define DAC_CH1CTRL_REFREN (0x1UL << 1) 06527 #define _DAC_CH1CTRL_REFREN_SHIFT 1 06528 #define _DAC_CH1CTRL_REFREN_MASK 0x2UL 06529 #define _DAC_CH1CTRL_REFREN_DEFAULT 0x00000000UL 06530 #define DAC_CH1CTRL_REFREN_DEFAULT (_DAC_CH1CTRL_REFREN_DEFAULT << 1) 06531 #define DAC_CH1CTRL_PRSEN (0x1UL << 2) 06532 #define _DAC_CH1CTRL_PRSEN_SHIFT 2 06533 #define _DAC_CH1CTRL_PRSEN_MASK 0x4UL 06534 #define _DAC_CH1CTRL_PRSEN_DEFAULT 0x00000000UL 06535 #define DAC_CH1CTRL_PRSEN_DEFAULT (_DAC_CH1CTRL_PRSEN_DEFAULT << 2) 06536 #define _DAC_CH1CTRL_PRSSEL_SHIFT 4 06537 #define _DAC_CH1CTRL_PRSSEL_MASK 0x70UL 06538 #define _DAC_CH1CTRL_PRSSEL_DEFAULT 0x00000000UL 06539 #define _DAC_CH1CTRL_PRSSEL_PRSCH0 0x00000000UL 06540 #define _DAC_CH1CTRL_PRSSEL_PRSCH1 0x00000001UL 06541 #define _DAC_CH1CTRL_PRSSEL_PRSCH2 0x00000002UL 06542 #define _DAC_CH1CTRL_PRSSEL_PRSCH3 0x00000003UL 06543 #define _DAC_CH1CTRL_PRSSEL_PRSCH4 0x00000004UL 06544 #define _DAC_CH1CTRL_PRSSEL_PRSCH5 0x00000005UL 06545 #define _DAC_CH1CTRL_PRSSEL_PRSCH6 0x00000006UL 06546 #define _DAC_CH1CTRL_PRSSEL_PRSCH7 0x00000007UL 06547 #define DAC_CH1CTRL_PRSSEL_DEFAULT (_DAC_CH1CTRL_PRSSEL_DEFAULT << 4) 06548 #define DAC_CH1CTRL_PRSSEL_PRSCH0 (_DAC_CH1CTRL_PRSSEL_PRSCH0 << 4) 06549 #define DAC_CH1CTRL_PRSSEL_PRSCH1 (_DAC_CH1CTRL_PRSSEL_PRSCH1 << 4) 06550 #define DAC_CH1CTRL_PRSSEL_PRSCH2 (_DAC_CH1CTRL_PRSSEL_PRSCH2 << 4) 06551 #define DAC_CH1CTRL_PRSSEL_PRSCH3 (_DAC_CH1CTRL_PRSSEL_PRSCH3 << 4) 06552 #define DAC_CH1CTRL_PRSSEL_PRSCH4 (_DAC_CH1CTRL_PRSSEL_PRSCH4 << 4) 06553 #define DAC_CH1CTRL_PRSSEL_PRSCH5 (_DAC_CH1CTRL_PRSSEL_PRSCH5 << 4) 06554 #define DAC_CH1CTRL_PRSSEL_PRSCH6 (_DAC_CH1CTRL_PRSSEL_PRSCH6 << 4) 06555 #define DAC_CH1CTRL_PRSSEL_PRSCH7 (_DAC_CH1CTRL_PRSSEL_PRSCH7 << 4) 06557 /* Bit fields for DAC IEN */ 06558 #define _DAC_IEN_RESETVALUE 0x00000000UL 06559 #define _DAC_IEN_MASK 0x00000033UL 06560 #define DAC_IEN_CH0 (0x1UL << 0) 06561 #define _DAC_IEN_CH0_SHIFT 0 06562 #define _DAC_IEN_CH0_MASK 0x1UL 06563 #define _DAC_IEN_CH0_DEFAULT 0x00000000UL 06564 #define DAC_IEN_CH0_DEFAULT (_DAC_IEN_CH0_DEFAULT << 0) 06565 #define DAC_IEN_CH1 (0x1UL << 1) 06566 #define _DAC_IEN_CH1_SHIFT 1 06567 #define _DAC_IEN_CH1_MASK 0x2UL 06568 #define _DAC_IEN_CH1_DEFAULT 0x00000000UL 06569 #define DAC_IEN_CH1_DEFAULT (_DAC_IEN_CH1_DEFAULT << 1) 06570 #define DAC_IEN_CH0UF (0x1UL << 4) 06571 #define _DAC_IEN_CH0UF_SHIFT 4 06572 #define _DAC_IEN_CH0UF_MASK 0x10UL 06573 #define _DAC_IEN_CH0UF_DEFAULT 0x00000000UL 06574 #define DAC_IEN_CH0UF_DEFAULT (_DAC_IEN_CH0UF_DEFAULT << 4) 06575 #define DAC_IEN_CH1UF (0x1UL << 5) 06576 #define _DAC_IEN_CH1UF_SHIFT 5 06577 #define _DAC_IEN_CH1UF_MASK 0x20UL 06578 #define _DAC_IEN_CH1UF_DEFAULT 0x00000000UL 06579 #define DAC_IEN_CH1UF_DEFAULT (_DAC_IEN_CH1UF_DEFAULT << 5) 06581 /* Bit fields for DAC IF */ 06582 #define _DAC_IF_RESETVALUE 0x00000000UL 06583 #define _DAC_IF_MASK 0x00000033UL 06584 #define DAC_IF_CH0 (0x1UL << 0) 06585 #define _DAC_IF_CH0_SHIFT 0 06586 #define _DAC_IF_CH0_MASK 0x1UL 06587 #define _DAC_IF_CH0_DEFAULT 0x00000000UL 06588 #define DAC_IF_CH0_DEFAULT (_DAC_IF_CH0_DEFAULT << 0) 06589 #define DAC_IF_CH1 (0x1UL << 1) 06590 #define _DAC_IF_CH1_SHIFT 1 06591 #define _DAC_IF_CH1_MASK 0x2UL 06592 #define _DAC_IF_CH1_DEFAULT 0x00000000UL 06593 #define DAC_IF_CH1_DEFAULT (_DAC_IF_CH1_DEFAULT << 1) 06594 #define DAC_IF_CH0UF (0x1UL << 4) 06595 #define _DAC_IF_CH0UF_SHIFT 4 06596 #define _DAC_IF_CH0UF_MASK 0x10UL 06597 #define _DAC_IF_CH0UF_DEFAULT 0x00000000UL 06598 #define DAC_IF_CH0UF_DEFAULT (_DAC_IF_CH0UF_DEFAULT << 4) 06599 #define DAC_IF_CH1UF (0x1UL << 5) 06600 #define _DAC_IF_CH1UF_SHIFT 5 06601 #define _DAC_IF_CH1UF_MASK 0x20UL 06602 #define _DAC_IF_CH1UF_DEFAULT 0x00000000UL 06603 #define DAC_IF_CH1UF_DEFAULT (_DAC_IF_CH1UF_DEFAULT << 5) 06605 /* Bit fields for DAC IFS */ 06606 #define _DAC_IFS_RESETVALUE 0x00000000UL 06607 #define _DAC_IFS_MASK 0x00000033UL 06608 #define DAC_IFS_CH0 (0x1UL << 0) 06609 #define _DAC_IFS_CH0_SHIFT 0 06610 #define _DAC_IFS_CH0_MASK 0x1UL 06611 #define _DAC_IFS_CH0_DEFAULT 0x00000000UL 06612 #define DAC_IFS_CH0_DEFAULT (_DAC_IFS_CH0_DEFAULT << 0) 06613 #define DAC_IFS_CH1 (0x1UL << 1) 06614 #define _DAC_IFS_CH1_SHIFT 1 06615 #define _DAC_IFS_CH1_MASK 0x2UL 06616 #define _DAC_IFS_CH1_DEFAULT 0x00000000UL 06617 #define DAC_IFS_CH1_DEFAULT (_DAC_IFS_CH1_DEFAULT << 1) 06618 #define DAC_IFS_CH0UF (0x1UL << 4) 06619 #define _DAC_IFS_CH0UF_SHIFT 4 06620 #define _DAC_IFS_CH0UF_MASK 0x10UL 06621 #define _DAC_IFS_CH0UF_DEFAULT 0x00000000UL 06622 #define DAC_IFS_CH0UF_DEFAULT (_DAC_IFS_CH0UF_DEFAULT << 4) 06623 #define DAC_IFS_CH1UF (0x1UL << 5) 06624 #define _DAC_IFS_CH1UF_SHIFT 5 06625 #define _DAC_IFS_CH1UF_MASK 0x20UL 06626 #define _DAC_IFS_CH1UF_DEFAULT 0x00000000UL 06627 #define DAC_IFS_CH1UF_DEFAULT (_DAC_IFS_CH1UF_DEFAULT << 5) 06629 /* Bit fields for DAC IFC */ 06630 #define _DAC_IFC_RESETVALUE 0x00000000UL 06631 #define _DAC_IFC_MASK 0x00000033UL 06632 #define DAC_IFC_CH0 (0x1UL << 0) 06633 #define _DAC_IFC_CH0_SHIFT 0 06634 #define _DAC_IFC_CH0_MASK 0x1UL 06635 #define _DAC_IFC_CH0_DEFAULT 0x00000000UL 06636 #define DAC_IFC_CH0_DEFAULT (_DAC_IFC_CH0_DEFAULT << 0) 06637 #define DAC_IFC_CH1 (0x1UL << 1) 06638 #define _DAC_IFC_CH1_SHIFT 1 06639 #define _DAC_IFC_CH1_MASK 0x2UL 06640 #define _DAC_IFC_CH1_DEFAULT 0x00000000UL 06641 #define DAC_IFC_CH1_DEFAULT (_DAC_IFC_CH1_DEFAULT << 1) 06642 #define DAC_IFC_CH0UF (0x1UL << 4) 06643 #define _DAC_IFC_CH0UF_SHIFT 4 06644 #define _DAC_IFC_CH0UF_MASK 0x10UL 06645 #define _DAC_IFC_CH0UF_DEFAULT 0x00000000UL 06646 #define DAC_IFC_CH0UF_DEFAULT (_DAC_IFC_CH0UF_DEFAULT << 4) 06647 #define DAC_IFC_CH1UF (0x1UL << 5) 06648 #define _DAC_IFC_CH1UF_SHIFT 5 06649 #define _DAC_IFC_CH1UF_MASK 0x20UL 06650 #define _DAC_IFC_CH1UF_DEFAULT 0x00000000UL 06651 #define DAC_IFC_CH1UF_DEFAULT (_DAC_IFC_CH1UF_DEFAULT << 5) 06653 /* Bit fields for DAC CH0DATA */ 06654 #define _DAC_CH0DATA_RESETVALUE 0x00000000UL 06655 #define _DAC_CH0DATA_MASK 0x00000FFFUL 06656 #define _DAC_CH0DATA_DATA_SHIFT 0 06657 #define _DAC_CH0DATA_DATA_MASK 0xFFFUL 06658 #define _DAC_CH0DATA_DATA_DEFAULT 0x00000000UL 06659 #define DAC_CH0DATA_DATA_DEFAULT (_DAC_CH0DATA_DATA_DEFAULT << 0) 06661 /* Bit fields for DAC CH1DATA */ 06662 #define _DAC_CH1DATA_RESETVALUE 0x00000000UL 06663 #define _DAC_CH1DATA_MASK 0x00000FFFUL 06664 #define _DAC_CH1DATA_DATA_SHIFT 0 06665 #define _DAC_CH1DATA_DATA_MASK 0xFFFUL 06666 #define _DAC_CH1DATA_DATA_DEFAULT 0x00000000UL 06667 #define DAC_CH1DATA_DATA_DEFAULT (_DAC_CH1DATA_DATA_DEFAULT << 0) 06669 /* Bit fields for DAC COMBDATA */ 06670 #define _DAC_COMBDATA_RESETVALUE 0x00000000UL 06671 #define _DAC_COMBDATA_MASK 0x0FFF0FFFUL 06672 #define _DAC_COMBDATA_CH0DATA_SHIFT 0 06673 #define _DAC_COMBDATA_CH0DATA_MASK 0xFFFUL 06674 #define _DAC_COMBDATA_CH0DATA_DEFAULT 0x00000000UL 06675 #define DAC_COMBDATA_CH0DATA_DEFAULT (_DAC_COMBDATA_CH0DATA_DEFAULT << 0) 06676 #define _DAC_COMBDATA_CH1DATA_SHIFT 16 06677 #define _DAC_COMBDATA_CH1DATA_MASK 0xFFF0000UL 06678 #define _DAC_COMBDATA_CH1DATA_DEFAULT 0x00000000UL 06679 #define DAC_COMBDATA_CH1DATA_DEFAULT (_DAC_COMBDATA_CH1DATA_DEFAULT << 16) 06681 /* Bit fields for DAC CAL */ 06682 #define _DAC_CAL_RESETVALUE 0x00400000UL 06683 #define _DAC_CAL_MASK 0x007F3F3FUL 06684 #define _DAC_CAL_CH0OFFSET_SHIFT 0 06685 #define _DAC_CAL_CH0OFFSET_MASK 0x3FUL 06686 #define _DAC_CAL_CH0OFFSET_DEFAULT 0x00000000UL 06687 #define DAC_CAL_CH0OFFSET_DEFAULT (_DAC_CAL_CH0OFFSET_DEFAULT << 0) 06688 #define _DAC_CAL_CH1OFFSET_SHIFT 8 06689 #define _DAC_CAL_CH1OFFSET_MASK 0x3F00UL 06690 #define _DAC_CAL_CH1OFFSET_DEFAULT 0x00000000UL 06691 #define DAC_CAL_CH1OFFSET_DEFAULT (_DAC_CAL_CH1OFFSET_DEFAULT << 8) 06692 #define _DAC_CAL_GAIN_SHIFT 16 06693 #define _DAC_CAL_GAIN_MASK 0x7F0000UL 06694 #define _DAC_CAL_GAIN_DEFAULT 0x00000040UL 06695 #define DAC_CAL_GAIN_DEFAULT (_DAC_CAL_GAIN_DEFAULT << 16) 06697 /* Bit fields for DAC BIASPROG */ 06698 #define _DAC_BIASPROG_RESETVALUE 0x00000047UL 06699 #define _DAC_BIASPROG_MASK 0x0000004FUL 06700 #define _DAC_BIASPROG_BIASPROG_SHIFT 0 06701 #define _DAC_BIASPROG_BIASPROG_MASK 0xFUL 06702 #define _DAC_BIASPROG_BIASPROG_DEFAULT 0x00000007UL 06703 #define DAC_BIASPROG_BIASPROG_DEFAULT (_DAC_BIASPROG_BIASPROG_DEFAULT << 0) 06704 #define DAC_BIASPROG_HALFBIAS (0x1UL << 6) 06705 #define _DAC_BIASPROG_HALFBIAS_SHIFT 6 06706 #define _DAC_BIASPROG_HALFBIAS_MASK 0x40UL 06707 #define _DAC_BIASPROG_HALFBIAS_DEFAULT 0x00000001UL 06708 #define DAC_BIASPROG_HALFBIAS_DEFAULT (_DAC_BIASPROG_HALFBIAS_DEFAULT << 6) 06714 /**************************************************************************/ 06719 /* Bit fields for ACMP CTRL */ 06720 #define _ACMP_CTRL_RESETVALUE 0x47000000UL 06721 #define _ACMP_CTRL_MASK 0xCF03077FUL 06722 #define ACMP_CTRL_EN (0x1UL << 0) 06723 #define _ACMP_CTRL_EN_SHIFT 0 06724 #define _ACMP_CTRL_EN_MASK 0x1UL 06725 #define _ACMP_CTRL_EN_DEFAULT 0x00000000UL 06726 #define ACMP_CTRL_EN_DEFAULT (_ACMP_CTRL_EN_DEFAULT << 0) 06727 #define ACMP_CTRL_MUXEN (0x1UL << 1) 06728 #define _ACMP_CTRL_MUXEN_SHIFT 1 06729 #define _ACMP_CTRL_MUXEN_MASK 0x2UL 06730 #define _ACMP_CTRL_MUXEN_DEFAULT 0x00000000UL 06731 #define ACMP_CTRL_MUXEN_DEFAULT (_ACMP_CTRL_MUXEN_DEFAULT << 1) 06732 #define ACMP_CTRL_INACTVAL (0x1UL << 2) 06733 #define _ACMP_CTRL_INACTVAL_SHIFT 2 06734 #define _ACMP_CTRL_INACTVAL_MASK 0x4UL 06735 #define _ACMP_CTRL_INACTVAL_DEFAULT 0x00000000UL 06736 #define _ACMP_CTRL_INACTVAL_LOW 0x00000000UL 06737 #define _ACMP_CTRL_INACTVAL_HIGH 0x00000001UL 06738 #define ACMP_CTRL_INACTVAL_DEFAULT (_ACMP_CTRL_INACTVAL_DEFAULT << 2) 06739 #define ACMP_CTRL_INACTVAL_LOW (_ACMP_CTRL_INACTVAL_LOW << 2) 06740 #define ACMP_CTRL_INACTVAL_HIGH (_ACMP_CTRL_INACTVAL_HIGH << 2) 06741 #define ACMP_CTRL_GPIOINV (0x1UL << 3) 06742 #define _ACMP_CTRL_GPIOINV_SHIFT 3 06743 #define _ACMP_CTRL_GPIOINV_MASK 0x8UL 06744 #define _ACMP_CTRL_GPIOINV_DEFAULT 0x00000000UL 06745 #define _ACMP_CTRL_GPIOINV_NOTINV 0x00000000UL 06746 #define _ACMP_CTRL_GPIOINV_INV 0x00000001UL 06747 #define ACMP_CTRL_GPIOINV_DEFAULT (_ACMP_CTRL_GPIOINV_DEFAULT << 3) 06748 #define ACMP_CTRL_GPIOINV_NOTINV (_ACMP_CTRL_GPIOINV_NOTINV << 3) 06749 #define ACMP_CTRL_GPIOINV_INV (_ACMP_CTRL_GPIOINV_INV << 3) 06750 #define _ACMP_CTRL_HYSTSEL_SHIFT 4 06751 #define _ACMP_CTRL_HYSTSEL_MASK 0x70UL 06752 #define _ACMP_CTRL_HYSTSEL_DEFAULT 0x00000000UL 06753 #define _ACMP_CTRL_HYSTSEL_HYST0 0x00000000UL 06754 #define _ACMP_CTRL_HYSTSEL_HYST1 0x00000001UL 06755 #define _ACMP_CTRL_HYSTSEL_HYST2 0x00000002UL 06756 #define _ACMP_CTRL_HYSTSEL_HYST3 0x00000003UL 06757 #define _ACMP_CTRL_HYSTSEL_HYST4 0x00000004UL 06758 #define _ACMP_CTRL_HYSTSEL_HYST5 0x00000005UL 06759 #define _ACMP_CTRL_HYSTSEL_HYST6 0x00000006UL 06760 #define _ACMP_CTRL_HYSTSEL_HYST7 0x00000007UL 06761 #define ACMP_CTRL_HYSTSEL_DEFAULT (_ACMP_CTRL_HYSTSEL_DEFAULT << 4) 06762 #define ACMP_CTRL_HYSTSEL_HYST0 (_ACMP_CTRL_HYSTSEL_HYST0 << 4) 06763 #define ACMP_CTRL_HYSTSEL_HYST1 (_ACMP_CTRL_HYSTSEL_HYST1 << 4) 06764 #define ACMP_CTRL_HYSTSEL_HYST2 (_ACMP_CTRL_HYSTSEL_HYST2 << 4) 06765 #define ACMP_CTRL_HYSTSEL_HYST3 (_ACMP_CTRL_HYSTSEL_HYST3 << 4) 06766 #define ACMP_CTRL_HYSTSEL_HYST4 (_ACMP_CTRL_HYSTSEL_HYST4 << 4) 06767 #define ACMP_CTRL_HYSTSEL_HYST5 (_ACMP_CTRL_HYSTSEL_HYST5 << 4) 06768 #define ACMP_CTRL_HYSTSEL_HYST6 (_ACMP_CTRL_HYSTSEL_HYST6 << 4) 06769 #define ACMP_CTRL_HYSTSEL_HYST7 (_ACMP_CTRL_HYSTSEL_HYST7 << 4) 06770 #define _ACMP_CTRL_WARMTIME_SHIFT 8 06771 #define _ACMP_CTRL_WARMTIME_MASK 0x700UL 06772 #define _ACMP_CTRL_WARMTIME_DEFAULT 0x00000000UL 06773 #define _ACMP_CTRL_WARMTIME_4CYCLES 0x00000000UL 06774 #define _ACMP_CTRL_WARMTIME_8CYCLES 0x00000001UL 06775 #define _ACMP_CTRL_WARMTIME_16CYCLES 0x00000002UL 06776 #define _ACMP_CTRL_WARMTIME_32CYCLES 0x00000003UL 06777 #define _ACMP_CTRL_WARMTIME_64CYCLES 0x00000004UL 06778 #define _ACMP_CTRL_WARMTIME_128CYCLES 0x00000005UL 06779 #define _ACMP_CTRL_WARMTIME_256CYCLES 0x00000006UL 06780 #define _ACMP_CTRL_WARMTIME_512CYCLES 0x00000007UL 06781 #define ACMP_CTRL_WARMTIME_DEFAULT (_ACMP_CTRL_WARMTIME_DEFAULT << 8) 06782 #define ACMP_CTRL_WARMTIME_4CYCLES (_ACMP_CTRL_WARMTIME_4CYCLES << 8) 06783 #define ACMP_CTRL_WARMTIME_8CYCLES (_ACMP_CTRL_WARMTIME_8CYCLES << 8) 06784 #define ACMP_CTRL_WARMTIME_16CYCLES (_ACMP_CTRL_WARMTIME_16CYCLES << 8) 06785 #define ACMP_CTRL_WARMTIME_32CYCLES (_ACMP_CTRL_WARMTIME_32CYCLES << 8) 06786 #define ACMP_CTRL_WARMTIME_64CYCLES (_ACMP_CTRL_WARMTIME_64CYCLES << 8) 06787 #define ACMP_CTRL_WARMTIME_128CYCLES (_ACMP_CTRL_WARMTIME_128CYCLES << 8) 06788 #define ACMP_CTRL_WARMTIME_256CYCLES (_ACMP_CTRL_WARMTIME_256CYCLES << 8) 06789 #define ACMP_CTRL_WARMTIME_512CYCLES (_ACMP_CTRL_WARMTIME_512CYCLES << 8) 06790 #define ACMP_CTRL_IRISE (0x1UL << 16) 06791 #define _ACMP_CTRL_IRISE_SHIFT 16 06792 #define _ACMP_CTRL_IRISE_MASK 0x10000UL 06793 #define _ACMP_CTRL_IRISE_DEFAULT 0x00000000UL 06794 #define _ACMP_CTRL_IRISE_DISABLED 0x00000000UL 06795 #define _ACMP_CTRL_IRISE_ENABLED 0x00000001UL 06796 #define ACMP_CTRL_IRISE_DEFAULT (_ACMP_CTRL_IRISE_DEFAULT << 16) 06797 #define ACMP_CTRL_IRISE_DISABLED (_ACMP_CTRL_IRISE_DISABLED << 16) 06798 #define ACMP_CTRL_IRISE_ENABLED (_ACMP_CTRL_IRISE_ENABLED << 16) 06799 #define ACMP_CTRL_IFALL (0x1UL << 17) 06800 #define _ACMP_CTRL_IFALL_SHIFT 17 06801 #define _ACMP_CTRL_IFALL_MASK 0x20000UL 06802 #define _ACMP_CTRL_IFALL_DEFAULT 0x00000000UL 06803 #define _ACMP_CTRL_IFALL_DISABLED 0x00000000UL 06804 #define _ACMP_CTRL_IFALL_ENABLED 0x00000001UL 06805 #define ACMP_CTRL_IFALL_DEFAULT (_ACMP_CTRL_IFALL_DEFAULT << 17) 06806 #define ACMP_CTRL_IFALL_DISABLED (_ACMP_CTRL_IFALL_DISABLED << 17) 06807 #define ACMP_CTRL_IFALL_ENABLED (_ACMP_CTRL_IFALL_ENABLED << 17) 06808 #define _ACMP_CTRL_BIASPROG_SHIFT 24 06809 #define _ACMP_CTRL_BIASPROG_MASK 0xF000000UL 06810 #define _ACMP_CTRL_BIASPROG_DEFAULT 0x00000007UL 06811 #define ACMP_CTRL_BIASPROG_DEFAULT (_ACMP_CTRL_BIASPROG_DEFAULT << 24) 06812 #define ACMP_CTRL_HALFBIAS (0x1UL << 30) 06813 #define _ACMP_CTRL_HALFBIAS_SHIFT 30 06814 #define _ACMP_CTRL_HALFBIAS_MASK 0x40000000UL 06815 #define _ACMP_CTRL_HALFBIAS_DEFAULT 0x00000001UL 06816 #define ACMP_CTRL_HALFBIAS_DEFAULT (_ACMP_CTRL_HALFBIAS_DEFAULT << 30) 06817 #define ACMP_CTRL_FULLBIAS (0x1UL << 31) 06818 #define _ACMP_CTRL_FULLBIAS_SHIFT 31 06819 #define _ACMP_CTRL_FULLBIAS_MASK 0x80000000UL 06820 #define _ACMP_CTRL_FULLBIAS_DEFAULT 0x00000000UL 06821 #define ACMP_CTRL_FULLBIAS_DEFAULT (_ACMP_CTRL_FULLBIAS_DEFAULT << 31) 06823 /* Bit fields for ACMP INPUTSEL */ 06824 #define _ACMP_INPUTSEL_RESETVALUE 0x00010080UL 06825 #define _ACMP_INPUTSEL_MASK 0x31013FF7UL 06826 #define _ACMP_INPUTSEL_POSSEL_SHIFT 0 06827 #define _ACMP_INPUTSEL_POSSEL_MASK 0x7UL 06828 #define _ACMP_INPUTSEL_POSSEL_DEFAULT 0x00000000UL 06829 #define _ACMP_INPUTSEL_POSSEL_CH0 0x00000000UL 06830 #define _ACMP_INPUTSEL_POSSEL_CH1 0x00000001UL 06831 #define _ACMP_INPUTSEL_POSSEL_CH2 0x00000002UL 06832 #define _ACMP_INPUTSEL_POSSEL_CH3 0x00000003UL 06833 #define _ACMP_INPUTSEL_POSSEL_CH4 0x00000004UL 06834 #define _ACMP_INPUTSEL_POSSEL_CH5 0x00000005UL 06835 #define _ACMP_INPUTSEL_POSSEL_CH6 0x00000006UL 06836 #define _ACMP_INPUTSEL_POSSEL_CH7 0x00000007UL 06837 #define ACMP_INPUTSEL_POSSEL_DEFAULT (_ACMP_INPUTSEL_POSSEL_DEFAULT << 0) 06838 #define ACMP_INPUTSEL_POSSEL_CH0 (_ACMP_INPUTSEL_POSSEL_CH0 << 0) 06839 #define ACMP_INPUTSEL_POSSEL_CH1 (_ACMP_INPUTSEL_POSSEL_CH1 << 0) 06840 #define ACMP_INPUTSEL_POSSEL_CH2 (_ACMP_INPUTSEL_POSSEL_CH2 << 0) 06841 #define ACMP_INPUTSEL_POSSEL_CH3 (_ACMP_INPUTSEL_POSSEL_CH3 << 0) 06842 #define ACMP_INPUTSEL_POSSEL_CH4 (_ACMP_INPUTSEL_POSSEL_CH4 << 0) 06843 #define ACMP_INPUTSEL_POSSEL_CH5 (_ACMP_INPUTSEL_POSSEL_CH5 << 0) 06844 #define ACMP_INPUTSEL_POSSEL_CH6 (_ACMP_INPUTSEL_POSSEL_CH6 << 0) 06845 #define ACMP_INPUTSEL_POSSEL_CH7 (_ACMP_INPUTSEL_POSSEL_CH7 << 0) 06846 #define _ACMP_INPUTSEL_NEGSEL_SHIFT 4 06847 #define _ACMP_INPUTSEL_NEGSEL_MASK 0xF0UL 06848 #define _ACMP_INPUTSEL_NEGSEL_CH0 0x00000000UL 06849 #define _ACMP_INPUTSEL_NEGSEL_CH1 0x00000001UL 06850 #define _ACMP_INPUTSEL_NEGSEL_CH2 0x00000002UL 06851 #define _ACMP_INPUTSEL_NEGSEL_CH3 0x00000003UL 06852 #define _ACMP_INPUTSEL_NEGSEL_CH4 0x00000004UL 06853 #define _ACMP_INPUTSEL_NEGSEL_CH5 0x00000005UL 06854 #define _ACMP_INPUTSEL_NEGSEL_CH6 0x00000006UL 06855 #define _ACMP_INPUTSEL_NEGSEL_CH7 0x00000007UL 06856 #define _ACMP_INPUTSEL_NEGSEL_DEFAULT 0x00000008UL 06857 #define _ACMP_INPUTSEL_NEGSEL_1V25 0x00000008UL 06858 #define _ACMP_INPUTSEL_NEGSEL_2V5 0x00000009UL 06859 #define _ACMP_INPUTSEL_NEGSEL_VDD 0x0000000AUL 06860 #define _ACMP_INPUTSEL_NEGSEL_CAPSENSE 0x0000000BUL 06861 #define ACMP_INPUTSEL_NEGSEL_CH0 (_ACMP_INPUTSEL_NEGSEL_CH0 << 4) 06862 #define ACMP_INPUTSEL_NEGSEL_CH1 (_ACMP_INPUTSEL_NEGSEL_CH1 << 4) 06863 #define ACMP_INPUTSEL_NEGSEL_CH2 (_ACMP_INPUTSEL_NEGSEL_CH2 << 4) 06864 #define ACMP_INPUTSEL_NEGSEL_CH3 (_ACMP_INPUTSEL_NEGSEL_CH3 << 4) 06865 #define ACMP_INPUTSEL_NEGSEL_CH4 (_ACMP_INPUTSEL_NEGSEL_CH4 << 4) 06866 #define ACMP_INPUTSEL_NEGSEL_CH5 (_ACMP_INPUTSEL_NEGSEL_CH5 << 4) 06867 #define ACMP_INPUTSEL_NEGSEL_CH6 (_ACMP_INPUTSEL_NEGSEL_CH6 << 4) 06868 #define ACMP_INPUTSEL_NEGSEL_CH7 (_ACMP_INPUTSEL_NEGSEL_CH7 << 4) 06869 #define ACMP_INPUTSEL_NEGSEL_DEFAULT (_ACMP_INPUTSEL_NEGSEL_DEFAULT << 4) 06870 #define ACMP_INPUTSEL_NEGSEL_1V25 (_ACMP_INPUTSEL_NEGSEL_1V25 << 4) 06871 #define ACMP_INPUTSEL_NEGSEL_2V5 (_ACMP_INPUTSEL_NEGSEL_2V5 << 4) 06872 #define ACMP_INPUTSEL_NEGSEL_VDD (_ACMP_INPUTSEL_NEGSEL_VDD << 4) 06873 #define ACMP_INPUTSEL_NEGSEL_CAPSENSE (_ACMP_INPUTSEL_NEGSEL_CAPSENSE << 4) 06874 #define _ACMP_INPUTSEL_VDDLEVEL_SHIFT 8 06875 #define _ACMP_INPUTSEL_VDDLEVEL_MASK 0x3F00UL 06876 #define _ACMP_INPUTSEL_VDDLEVEL_DEFAULT 0x00000000UL 06877 #define ACMP_INPUTSEL_VDDLEVEL_DEFAULT (_ACMP_INPUTSEL_VDDLEVEL_DEFAULT << 8) 06878 #define ACMP_INPUTSEL_LPREF (0x1UL << 16) 06879 #define _ACMP_INPUTSEL_LPREF_SHIFT 16 06880 #define _ACMP_INPUTSEL_LPREF_MASK 0x10000UL 06881 #define _ACMP_INPUTSEL_LPREF_DEFAULT 0x00000001UL 06882 #define ACMP_INPUTSEL_LPREF_DEFAULT (_ACMP_INPUTSEL_LPREF_DEFAULT << 16) 06883 #define ACMP_INPUTSEL_CSRESEN (0x1UL << 24) 06884 #define _ACMP_INPUTSEL_CSRESEN_SHIFT 24 06885 #define _ACMP_INPUTSEL_CSRESEN_MASK 0x1000000UL 06886 #define _ACMP_INPUTSEL_CSRESEN_DEFAULT 0x00000000UL 06887 #define ACMP_INPUTSEL_CSRESEN_DEFAULT (_ACMP_INPUTSEL_CSRESEN_DEFAULT << 24) 06888 #define _ACMP_INPUTSEL_CSRESSEL_SHIFT 28 06889 #define _ACMP_INPUTSEL_CSRESSEL_MASK 0x30000000UL 06890 #define _ACMP_INPUTSEL_CSRESSEL_DEFAULT 0x00000000UL 06891 #define _ACMP_INPUTSEL_CSRESSEL_RES0 0x00000000UL 06892 #define _ACMP_INPUTSEL_CSRESSEL_RES1 0x00000001UL 06893 #define _ACMP_INPUTSEL_CSRESSEL_RES2 0x00000002UL 06894 #define _ACMP_INPUTSEL_CSRESSEL_RES3 0x00000003UL 06895 #define ACMP_INPUTSEL_CSRESSEL_DEFAULT (_ACMP_INPUTSEL_CSRESSEL_DEFAULT << 28) 06896 #define ACMP_INPUTSEL_CSRESSEL_RES0 (_ACMP_INPUTSEL_CSRESSEL_RES0 << 28) 06897 #define ACMP_INPUTSEL_CSRESSEL_RES1 (_ACMP_INPUTSEL_CSRESSEL_RES1 << 28) 06898 #define ACMP_INPUTSEL_CSRESSEL_RES2 (_ACMP_INPUTSEL_CSRESSEL_RES2 << 28) 06899 #define ACMP_INPUTSEL_CSRESSEL_RES3 (_ACMP_INPUTSEL_CSRESSEL_RES3 << 28) 06901 /* Bit fields for ACMP STATUS */ 06902 #define _ACMP_STATUS_RESETVALUE 0x00000000UL 06903 #define _ACMP_STATUS_MASK 0x00000003UL 06904 #define ACMP_STATUS_ACMPACT (0x1UL << 0) 06905 #define _ACMP_STATUS_ACMPACT_SHIFT 0 06906 #define _ACMP_STATUS_ACMPACT_MASK 0x1UL 06907 #define _ACMP_STATUS_ACMPACT_DEFAULT 0x00000000UL 06908 #define ACMP_STATUS_ACMPACT_DEFAULT (_ACMP_STATUS_ACMPACT_DEFAULT << 0) 06909 #define ACMP_STATUS_ACMPOUT (0x1UL << 1) 06910 #define _ACMP_STATUS_ACMPOUT_SHIFT 1 06911 #define _ACMP_STATUS_ACMPOUT_MASK 0x2UL 06912 #define _ACMP_STATUS_ACMPOUT_DEFAULT 0x00000000UL 06913 #define ACMP_STATUS_ACMPOUT_DEFAULT (_ACMP_STATUS_ACMPOUT_DEFAULT << 1) 06915 /* Bit fields for ACMP IEN */ 06916 #define _ACMP_IEN_RESETVALUE 0x00000000UL 06917 #define _ACMP_IEN_MASK 0x00000003UL 06918 #define ACMP_IEN_EDGE (0x1UL << 0) 06919 #define _ACMP_IEN_EDGE_SHIFT 0 06920 #define _ACMP_IEN_EDGE_MASK 0x1UL 06921 #define _ACMP_IEN_EDGE_DEFAULT 0x00000000UL 06922 #define ACMP_IEN_EDGE_DEFAULT (_ACMP_IEN_EDGE_DEFAULT << 0) 06923 #define ACMP_IEN_WARMUP (0x1UL << 1) 06924 #define _ACMP_IEN_WARMUP_SHIFT 1 06925 #define _ACMP_IEN_WARMUP_MASK 0x2UL 06926 #define _ACMP_IEN_WARMUP_DEFAULT 0x00000000UL 06927 #define ACMP_IEN_WARMUP_DEFAULT (_ACMP_IEN_WARMUP_DEFAULT << 1) 06929 /* Bit fields for ACMP IF */ 06930 #define _ACMP_IF_RESETVALUE 0x00000000UL 06931 #define _ACMP_IF_MASK 0x00000003UL 06932 #define ACMP_IF_EDGE (0x1UL << 0) 06933 #define _ACMP_IF_EDGE_SHIFT 0 06934 #define _ACMP_IF_EDGE_MASK 0x1UL 06935 #define _ACMP_IF_EDGE_DEFAULT 0x00000000UL 06936 #define ACMP_IF_EDGE_DEFAULT (_ACMP_IF_EDGE_DEFAULT << 0) 06937 #define ACMP_IF_WARMUP (0x1UL << 1) 06938 #define _ACMP_IF_WARMUP_SHIFT 1 06939 #define _ACMP_IF_WARMUP_MASK 0x2UL 06940 #define _ACMP_IF_WARMUP_DEFAULT 0x00000000UL 06941 #define ACMP_IF_WARMUP_DEFAULT (_ACMP_IF_WARMUP_DEFAULT << 1) 06943 /* Bit fields for ACMP IFS */ 06944 #define _ACMP_IFS_RESETVALUE 0x00000000UL 06945 #define _ACMP_IFS_MASK 0x00000003UL 06946 #define ACMP_IFS_EDGE (0x1UL << 0) 06947 #define _ACMP_IFS_EDGE_SHIFT 0 06948 #define _ACMP_IFS_EDGE_MASK 0x1UL 06949 #define _ACMP_IFS_EDGE_DEFAULT 0x00000000UL 06950 #define ACMP_IFS_EDGE_DEFAULT (_ACMP_IFS_EDGE_DEFAULT << 0) 06951 #define ACMP_IFS_WARMUP (0x1UL << 1) 06952 #define _ACMP_IFS_WARMUP_SHIFT 1 06953 #define _ACMP_IFS_WARMUP_MASK 0x2UL 06954 #define _ACMP_IFS_WARMUP_DEFAULT 0x00000000UL 06955 #define ACMP_IFS_WARMUP_DEFAULT (_ACMP_IFS_WARMUP_DEFAULT << 1) 06957 /* Bit fields for ACMP IFC */ 06958 #define _ACMP_IFC_RESETVALUE 0x00000000UL 06959 #define _ACMP_IFC_MASK 0x00000003UL 06960 #define ACMP_IFC_EDGE (0x1UL << 0) 06961 #define _ACMP_IFC_EDGE_SHIFT 0 06962 #define _ACMP_IFC_EDGE_MASK 0x1UL 06963 #define _ACMP_IFC_EDGE_DEFAULT 0x00000000UL 06964 #define ACMP_IFC_EDGE_DEFAULT (_ACMP_IFC_EDGE_DEFAULT << 0) 06965 #define ACMP_IFC_WARMUP (0x1UL << 1) 06966 #define _ACMP_IFC_WARMUP_SHIFT 1 06967 #define _ACMP_IFC_WARMUP_MASK 0x2UL 06968 #define _ACMP_IFC_WARMUP_DEFAULT 0x00000000UL 06969 #define ACMP_IFC_WARMUP_DEFAULT (_ACMP_IFC_WARMUP_DEFAULT << 1) 06971 /* Bit fields for ACMP ROUTE */ 06972 #define _ACMP_ROUTE_RESETVALUE 0x00000000UL 06973 #define _ACMP_ROUTE_MASK 0x00000301UL 06974 #define ACMP_ROUTE_ACMPPEN (0x1UL << 0) 06975 #define _ACMP_ROUTE_ACMPPEN_SHIFT 0 06976 #define _ACMP_ROUTE_ACMPPEN_MASK 0x1UL 06977 #define _ACMP_ROUTE_ACMPPEN_DEFAULT 0x00000000UL 06978 #define ACMP_ROUTE_ACMPPEN_DEFAULT (_ACMP_ROUTE_ACMPPEN_DEFAULT << 0) 06979 #define _ACMP_ROUTE_LOCATION_SHIFT 8 06980 #define _ACMP_ROUTE_LOCATION_MASK 0x300UL 06981 #define _ACMP_ROUTE_LOCATION_DEFAULT 0x00000000UL 06982 #define _ACMP_ROUTE_LOCATION_LOC0 0x00000000UL 06983 #define _ACMP_ROUTE_LOCATION_LOC1 0x00000001UL 06984 #define _ACMP_ROUTE_LOCATION_LOC2 0x00000002UL 06985 #define _ACMP_ROUTE_LOCATION_LOC3 0x00000003UL 06986 #define ACMP_ROUTE_LOCATION_DEFAULT (_ACMP_ROUTE_LOCATION_DEFAULT << 8) 06987 #define ACMP_ROUTE_LOCATION_LOC0 (_ACMP_ROUTE_LOCATION_LOC0 << 8) 06988 #define ACMP_ROUTE_LOCATION_LOC1 (_ACMP_ROUTE_LOCATION_LOC1 << 8) 06989 #define ACMP_ROUTE_LOCATION_LOC2 (_ACMP_ROUTE_LOCATION_LOC2 << 8) 06990 #define ACMP_ROUTE_LOCATION_LOC3 (_ACMP_ROUTE_LOCATION_LOC3 << 8) 06996 /**************************************************************************/ 07001 /* Bit fields for MSC CTRL */ 07002 #define _MSC_CTRL_RESETVALUE 0x00000001UL 07003 #define _MSC_CTRL_MASK 0x00000001UL 07004 #define MSC_CTRL_BUSFAULT (0x1UL << 0) 07005 #define _MSC_CTRL_BUSFAULT_SHIFT 0 07006 #define _MSC_CTRL_BUSFAULT_MASK 0x1UL 07007 #define _MSC_CTRL_BUSFAULT_GENERATE 0x00000000UL 07008 #define _MSC_CTRL_BUSFAULT_DEFAULT 0x00000001UL 07009 #define _MSC_CTRL_BUSFAULT_IGNORE 0x00000001UL 07010 #define MSC_CTRL_BUSFAULT_GENERATE (_MSC_CTRL_BUSFAULT_GENERATE << 0) 07011 #define MSC_CTRL_BUSFAULT_DEFAULT (_MSC_CTRL_BUSFAULT_DEFAULT << 0) 07012 #define MSC_CTRL_BUSFAULT_IGNORE (_MSC_CTRL_BUSFAULT_IGNORE << 0) 07014 /* Bit fields for MSC READCTRL */ 07015 #define _MSC_READCTRL_RESETVALUE 0x00000001UL 07016 #define _MSC_READCTRL_MASK 0x00000007UL 07017 #define _MSC_READCTRL_MODE_SHIFT 0 07018 #define _MSC_READCTRL_MODE_MASK 0x7UL 07019 #define _MSC_READCTRL_MODE_WS0 0x00000000UL 07020 #define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL 07021 #define _MSC_READCTRL_MODE_WS1 0x00000001UL 07022 #define _MSC_READCTRL_MODE_WS0SCBTP 0x00000002UL 07023 #define _MSC_READCTRL_MODE_WS1SCBTP 0x00000003UL 07024 #define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 0) 07025 #define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 0) 07026 #define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 0) 07027 #define MSC_READCTRL_MODE_WS0SCBTP (_MSC_READCTRL_MODE_WS0SCBTP << 0) 07028 #define MSC_READCTRL_MODE_WS1SCBTP (_MSC_READCTRL_MODE_WS1SCBTP << 0) 07030 /* Bit fields for MSC WRITECTRL */ 07031 #define _MSC_WRITECTRL_RESETVALUE 0x00000000UL 07032 #define _MSC_WRITECTRL_MASK 0x00000003UL 07033 #define MSC_WRITECTRL_WREN (0x1UL << 0) 07034 #define _MSC_WRITECTRL_WREN_SHIFT 0 07035 #define _MSC_WRITECTRL_WREN_MASK 0x1UL 07036 #define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL 07037 #define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) 07038 #define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) 07039 #define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 07040 #define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL 07041 #define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL 07042 #define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) 07044 /* Bit fields for MSC WRITECMD */ 07045 #define _MSC_WRITECMD_RESETVALUE 0x00000000UL 07046 #define _MSC_WRITECMD_MASK 0x0000001FUL 07047 #define MSC_WRITECMD_LADDRIM (0x1UL << 0) 07048 #define _MSC_WRITECMD_LADDRIM_SHIFT 0 07049 #define _MSC_WRITECMD_LADDRIM_MASK 0x1UL 07050 #define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL 07051 #define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) 07052 #define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) 07053 #define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 07054 #define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL 07055 #define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL 07056 #define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) 07057 #define MSC_WRITECMD_WRITEEND (0x1UL << 2) 07058 #define _MSC_WRITECMD_WRITEEND_SHIFT 2 07059 #define _MSC_WRITECMD_WRITEEND_MASK 0x4UL 07060 #define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL 07061 #define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) 07062 #define MSC_WRITECMD_WRITEONCE (0x1UL << 3) 07063 #define _MSC_WRITECMD_WRITEONCE_SHIFT 3 07064 #define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL 07065 #define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL 07066 #define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) 07067 #define MSC_WRITECMD_WRITETRIG (0x1UL << 4) 07068 #define _MSC_WRITECMD_WRITETRIG_SHIFT 4 07069 #define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL 07070 #define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL 07071 #define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) 07073 /* Bit fields for MSC ADDRB */ 07074 #define _MSC_ADDRB_RESETVALUE 0x00000000UL 07075 #define _MSC_ADDRB_MASK 0xFFFFFFFFUL 07076 #define _MSC_ADDRB_ADDRB_SHIFT 0 07077 #define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL 07078 #define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL 07079 #define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) 07081 /* Bit fields for MSC WDATA */ 07082 #define _MSC_WDATA_RESETVALUE 0x00000000UL 07083 #define _MSC_WDATA_MASK 0xFFFFFFFFUL 07084 #define _MSC_WDATA_WDATA_SHIFT 0 07085 #define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL 07086 #define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL 07087 #define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) 07089 /* Bit fields for MSC STATUS */ 07090 #define _MSC_STATUS_RESETVALUE 0x00000008UL 07091 #define _MSC_STATUS_MASK 0x0000003FUL 07092 #define MSC_STATUS_BUSY (0x1UL << 0) 07093 #define _MSC_STATUS_BUSY_SHIFT 0 07094 #define _MSC_STATUS_BUSY_MASK 0x1UL 07095 #define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL 07096 #define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) 07097 #define MSC_STATUS_LOCKED (0x1UL << 1) 07098 #define _MSC_STATUS_LOCKED_SHIFT 1 07099 #define _MSC_STATUS_LOCKED_MASK 0x2UL 07100 #define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL 07101 #define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) 07102 #define MSC_STATUS_INVADDR (0x1UL << 2) 07103 #define _MSC_STATUS_INVADDR_SHIFT 2 07104 #define _MSC_STATUS_INVADDR_MASK 0x4UL 07105 #define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL 07106 #define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) 07107 #define MSC_STATUS_WDATAREADY (0x1UL << 3) 07108 #define _MSC_STATUS_WDATAREADY_SHIFT 3 07109 #define _MSC_STATUS_WDATAREADY_MASK 0x8UL 07110 #define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL 07111 #define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) 07112 #define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) 07113 #define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 07114 #define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL 07115 #define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL 07116 #define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) 07117 #define MSC_STATUS_ERASEABORTED (0x1UL << 5) 07118 #define _MSC_STATUS_ERASEABORTED_SHIFT 5 07119 #define _MSC_STATUS_ERASEABORTED_MASK 0x20UL 07120 #define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL 07121 #define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) 07123 /* Bit fields for MSC IF */ 07124 #define _MSC_IF_RESETVALUE 0x00000000UL 07125 #define _MSC_IF_MASK 0x00000003UL 07126 #define MSC_IF_ERASE (0x1UL << 0) 07127 #define _MSC_IF_ERASE_SHIFT 0 07128 #define _MSC_IF_ERASE_MASK 0x1UL 07129 #define _MSC_IF_ERASE_DEFAULT 0x00000000UL 07130 #define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) 07131 #define MSC_IF_WRITE (0x1UL << 1) 07132 #define _MSC_IF_WRITE_SHIFT 1 07133 #define _MSC_IF_WRITE_MASK 0x2UL 07134 #define _MSC_IF_WRITE_DEFAULT 0x00000000UL 07135 #define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) 07137 /* Bit fields for MSC IFS */ 07138 #define _MSC_IFS_RESETVALUE 0x00000000UL 07139 #define _MSC_IFS_MASK 0x00000003UL 07140 #define MSC_IFS_ERASE (0x1UL << 0) 07141 #define _MSC_IFS_ERASE_SHIFT 0 07142 #define _MSC_IFS_ERASE_MASK 0x1UL 07143 #define _MSC_IFS_ERASE_DEFAULT 0x00000000UL 07144 #define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) 07145 #define MSC_IFS_WRITE (0x1UL << 1) 07146 #define _MSC_IFS_WRITE_SHIFT 1 07147 #define _MSC_IFS_WRITE_MASK 0x2UL 07148 #define _MSC_IFS_WRITE_DEFAULT 0x00000000UL 07149 #define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) 07151 /* Bit fields for MSC IFC */ 07152 #define _MSC_IFC_RESETVALUE 0x00000000UL 07153 #define _MSC_IFC_MASK 0x00000003UL 07154 #define MSC_IFC_ERASE (0x1UL << 0) 07155 #define _MSC_IFC_ERASE_SHIFT 0 07156 #define _MSC_IFC_ERASE_MASK 0x1UL 07157 #define _MSC_IFC_ERASE_DEFAULT 0x00000000UL 07158 #define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) 07159 #define MSC_IFC_WRITE (0x1UL << 1) 07160 #define _MSC_IFC_WRITE_SHIFT 1 07161 #define _MSC_IFC_WRITE_MASK 0x2UL 07162 #define _MSC_IFC_WRITE_DEFAULT 0x00000000UL 07163 #define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) 07165 /* Bit fields for MSC IEN */ 07166 #define _MSC_IEN_RESETVALUE 0x00000000UL 07167 #define _MSC_IEN_MASK 0x00000003UL 07168 #define MSC_IEN_ERASE (0x1UL << 0) 07169 #define _MSC_IEN_ERASE_SHIFT 0 07170 #define _MSC_IEN_ERASE_MASK 0x1UL 07171 #define _MSC_IEN_ERASE_DEFAULT 0x00000000UL 07172 #define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) 07173 #define MSC_IEN_WRITE (0x1UL << 1) 07174 #define _MSC_IEN_WRITE_SHIFT 1 07175 #define _MSC_IEN_WRITE_MASK 0x2UL 07176 #define _MSC_IEN_WRITE_DEFAULT 0x00000000UL 07177 #define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) 07179 /* Bit fields for MSC LOCK */ 07180 #define _MSC_LOCK_RESETVALUE 0x00000000UL 07181 #define _MSC_LOCK_MASK 0x0000FFFFUL 07182 #define _MSC_LOCK_LOCKKEY_SHIFT 0 07183 #define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL 07184 #define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL 07185 #define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL 07186 #define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL 07187 #define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL 07188 #define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL 07189 #define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) 07190 #define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) 07191 #define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) 07192 #define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) 07193 #define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) 07199 /**************************************************************************/ 07204 /* Bit fields for EMU CTRL */ 07205 #define _EMU_CTRL_RESETVALUE 0x00000000UL 07206 #define _EMU_CTRL_MASK 0x0000000FUL 07207 #define EMU_CTRL_EMVREG (0x1UL << 0) 07208 #define _EMU_CTRL_EMVREG_SHIFT 0 07209 #define _EMU_CTRL_EMVREG_MASK 0x1UL 07210 #define _EMU_CTRL_EMVREG_DEFAULT 0x00000000UL 07211 #define _EMU_CTRL_EMVREG_REDUCED 0x00000000UL 07212 #define _EMU_CTRL_EMVREG_FULL 0x00000001UL 07213 #define EMU_CTRL_EMVREG_DEFAULT (_EMU_CTRL_EMVREG_DEFAULT << 0) 07214 #define EMU_CTRL_EMVREG_REDUCED (_EMU_CTRL_EMVREG_REDUCED << 0) 07215 #define EMU_CTRL_EMVREG_FULL (_EMU_CTRL_EMVREG_FULL << 0) 07216 #define EMU_CTRL_EM2BLOCK (0x1UL << 1) 07217 #define _EMU_CTRL_EM2BLOCK_SHIFT 1 07218 #define _EMU_CTRL_EM2BLOCK_MASK 0x2UL 07219 #define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL 07220 #define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) 07221 #define _EMU_CTRL_EM4CTRL_SHIFT 2 07222 #define _EMU_CTRL_EM4CTRL_MASK 0xCUL 07223 #define _EMU_CTRL_EM4CTRL_DEFAULT 0x00000000UL 07224 #define EMU_CTRL_EM4CTRL_DEFAULT (_EMU_CTRL_EM4CTRL_DEFAULT << 2) 07226 /* Bit fields for EMU MEMCTRL */ 07227 #define _EMU_MEMCTRL_RESETVALUE 0x00000000UL 07228 #define _EMU_MEMCTRL_MASK 0x00000007UL 07229 #define _EMU_MEMCTRL_POWERDOWN_SHIFT 0 07230 #define _EMU_MEMCTRL_POWERDOWN_MASK 0x7UL 07231 #define _EMU_MEMCTRL_POWERDOWN_DEFAULT 0x00000000UL 07232 #define _EMU_MEMCTRL_POWERDOWN_BLK3 0x00000004UL 07233 #define _EMU_MEMCTRL_POWERDOWN_BLK23 0x00000006UL 07234 #define _EMU_MEMCTRL_POWERDOWN_BLK123 0x00000007UL 07235 #define EMU_MEMCTRL_POWERDOWN_DEFAULT (_EMU_MEMCTRL_POWERDOWN_DEFAULT << 0) 07236 #define EMU_MEMCTRL_POWERDOWN_BLK3 (_EMU_MEMCTRL_POWERDOWN_BLK3 << 0) 07237 #define EMU_MEMCTRL_POWERDOWN_BLK23 (_EMU_MEMCTRL_POWERDOWN_BLK23 << 0) 07238 #define EMU_MEMCTRL_POWERDOWN_BLK123 (_EMU_MEMCTRL_POWERDOWN_BLK123 << 0) 07240 /* Bit fields for EMU LOCK */ 07241 #define _EMU_LOCK_RESETVALUE 0x00000000UL 07242 #define _EMU_LOCK_MASK 0x0000FFFFUL 07243 #define _EMU_LOCK_LOCKKEY_SHIFT 0 07244 #define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL 07245 #define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL 07246 #define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL 07247 #define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL 07248 #define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL 07249 #define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL 07250 #define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) 07251 #define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) 07252 #define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) 07253 #define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) 07254 #define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) 07256 /* Bit fields for EMU AUXCTRL */ 07257 #define _EMU_AUXCTRL_RESETVALUE 0x00000000UL 07258 #define _EMU_AUXCTRL_MASK 0x00000001UL 07259 #define EMU_AUXCTRL_HRCCLR (0x1UL << 0) 07260 #define _EMU_AUXCTRL_HRCCLR_SHIFT 0 07261 #define _EMU_AUXCTRL_HRCCLR_MASK 0x1UL 07262 #define _EMU_AUXCTRL_HRCCLR_DEFAULT 0x00000000UL 07263 #define EMU_AUXCTRL_HRCCLR_DEFAULT (_EMU_AUXCTRL_HRCCLR_DEFAULT << 0) 07269 /**************************************************************************/ 07274 /* Bit fields for RMU CTRL */ 07275 #define _RMU_CTRL_RESETVALUE 0x00000000UL 07276 #define _RMU_CTRL_MASK 0x00000001UL 07277 #define RMU_CTRL_LOCKUPRDIS (0x1UL << 0) 07278 #define _RMU_CTRL_LOCKUPRDIS_SHIFT 0 07279 #define _RMU_CTRL_LOCKUPRDIS_MASK 0x1UL 07280 #define _RMU_CTRL_LOCKUPRDIS_DEFAULT 0x00000000UL 07281 #define RMU_CTRL_LOCKUPRDIS_DEFAULT (_RMU_CTRL_LOCKUPRDIS_DEFAULT << 0) 07283 /* Bit fields for RMU RSTCAUSE */ 07284 #define _RMU_RSTCAUSE_RESETVALUE 0x00000000UL 07285 #define _RMU_RSTCAUSE_MASK 0x0000007FUL 07286 #define RMU_RSTCAUSE_PORST (0x1UL << 0) 07287 #define _RMU_RSTCAUSE_PORST_SHIFT 0 07288 #define _RMU_RSTCAUSE_PORST_MASK 0x1UL 07289 #define _RMU_RSTCAUSE_PORST_DEFAULT 0x00000000UL 07290 #define RMU_RSTCAUSE_PORST_DEFAULT (_RMU_RSTCAUSE_PORST_DEFAULT << 0) 07291 #define RMU_RSTCAUSE_BODUNREGRST (0x1UL << 1) 07292 #define _RMU_RSTCAUSE_BODUNREGRST_SHIFT 1 07293 #define _RMU_RSTCAUSE_BODUNREGRST_MASK 0x2UL 07294 #define _RMU_RSTCAUSE_BODUNREGRST_DEFAULT 0x00000000UL 07295 #define RMU_RSTCAUSE_BODUNREGRST_DEFAULT (_RMU_RSTCAUSE_BODUNREGRST_DEFAULT << 1) 07296 #define RMU_RSTCAUSE_BODREGRST (0x1UL << 2) 07297 #define _RMU_RSTCAUSE_BODREGRST_SHIFT 2 07298 #define _RMU_RSTCAUSE_BODREGRST_MASK 0x4UL 07299 #define _RMU_RSTCAUSE_BODREGRST_DEFAULT 0x00000000UL 07300 #define RMU_RSTCAUSE_BODREGRST_DEFAULT (_RMU_RSTCAUSE_BODREGRST_DEFAULT << 2) 07301 #define RMU_RSTCAUSE_EXTRST (0x1UL << 3) 07302 #define _RMU_RSTCAUSE_EXTRST_SHIFT 3 07303 #define _RMU_RSTCAUSE_EXTRST_MASK 0x8UL 07304 #define _RMU_RSTCAUSE_EXTRST_DEFAULT 0x00000000UL 07305 #define RMU_RSTCAUSE_EXTRST_DEFAULT (_RMU_RSTCAUSE_EXTRST_DEFAULT << 3) 07306 #define RMU_RSTCAUSE_WDOGRST (0x1UL << 4) 07307 #define _RMU_RSTCAUSE_WDOGRST_SHIFT 4 07308 #define _RMU_RSTCAUSE_WDOGRST_MASK 0x10UL 07309 #define _RMU_RSTCAUSE_WDOGRST_DEFAULT 0x00000000UL 07310 #define RMU_RSTCAUSE_WDOGRST_DEFAULT (_RMU_RSTCAUSE_WDOGRST_DEFAULT << 4) 07311 #define RMU_RSTCAUSE_LOCKUPRST (0x1UL << 5) 07312 #define _RMU_RSTCAUSE_LOCKUPRST_SHIFT 5 07313 #define _RMU_RSTCAUSE_LOCKUPRST_MASK 0x20UL 07314 #define _RMU_RSTCAUSE_LOCKUPRST_DEFAULT 0x00000000UL 07315 #define RMU_RSTCAUSE_LOCKUPRST_DEFAULT (_RMU_RSTCAUSE_LOCKUPRST_DEFAULT << 5) 07316 #define RMU_RSTCAUSE_SYSREQRST (0x1UL << 6) 07317 #define _RMU_RSTCAUSE_SYSREQRST_SHIFT 6 07318 #define _RMU_RSTCAUSE_SYSREQRST_MASK 0x40UL 07319 #define _RMU_RSTCAUSE_SYSREQRST_DEFAULT 0x00000000UL 07320 #define RMU_RSTCAUSE_SYSREQRST_DEFAULT (_RMU_RSTCAUSE_SYSREQRST_DEFAULT << 6) 07322 /* Bit fields for RMU CMD */ 07323 #define _RMU_CMD_RESETVALUE 0x00000000UL 07324 #define _RMU_CMD_MASK 0x00000001UL 07325 #define RMU_CMD_RCCLR (0x1UL << 0) 07326 #define _RMU_CMD_RCCLR_SHIFT 0 07327 #define _RMU_CMD_RCCLR_MASK 0x1UL 07328 #define _RMU_CMD_RCCLR_DEFAULT 0x00000000UL 07329 #define RMU_CMD_RCCLR_DEFAULT (_RMU_CMD_RCCLR_DEFAULT << 0) 07335 /**************************************************************************/ 07340 /* Bit fields for CMU CTRL */ 07341 #define _CMU_CTRL_RESETVALUE 0x000C262CUL 07342 #define _CMU_CTRL_MASK 0x00FE3EEFUL 07343 #define _CMU_CTRL_HFXOMODE_SHIFT 0 07344 #define _CMU_CTRL_HFXOMODE_MASK 0x3UL 07345 #define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL 07346 #define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL 07347 #define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL 07348 #define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL 07349 #define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) 07350 #define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) 07351 #define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) 07352 #define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) 07353 #define _CMU_CTRL_HFXOBOOST_SHIFT 2 07354 #define _CMU_CTRL_HFXOBOOST_MASK 0xCUL 07355 #define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL 07356 #define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL 07357 #define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL 07358 #define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL 07359 #define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL 07360 #define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) 07361 #define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) 07362 #define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) 07363 #define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) 07364 #define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) 07365 #define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 07366 #define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL 07367 #define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL 07368 #define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) 07369 #define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) 07370 #define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 07371 #define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL 07372 #define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL 07373 #define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) 07374 #define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 07375 #define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL 07376 #define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL 07377 #define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL 07378 #define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL 07379 #define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL 07380 #define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL 07381 #define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) 07382 #define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) 07383 #define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) 07384 #define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) 07385 #define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) 07386 #define _CMU_CTRL_LFXOMODE_SHIFT 11 07387 #define _CMU_CTRL_LFXOMODE_MASK 0x1800UL 07388 #define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL 07389 #define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL 07390 #define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL 07391 #define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL 07392 #define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) 07393 #define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) 07394 #define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) 07395 #define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) 07396 #define CMU_CTRL_LFXOBOOST (0x1UL << 13) 07397 #define _CMU_CTRL_LFXOBOOST_SHIFT 13 07398 #define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL 07399 #define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL 07400 #define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL 07401 #define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL 07402 #define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) 07403 #define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) 07404 #define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) 07405 #define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) 07406 #define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 07407 #define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL 07408 #define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL 07409 #define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) 07410 #define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 07411 #define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL 07412 #define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL 07413 #define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL 07414 #define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL 07415 #define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL 07416 #define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL 07417 #define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) 07418 #define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) 07419 #define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) 07420 #define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) 07421 #define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) 07422 #define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 07423 #define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL 07424 #define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL 07425 #define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL 07426 #define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL 07427 #define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL 07428 #define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL 07429 #define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL 07430 #define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL 07431 #define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL 07432 #define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) 07433 #define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) 07434 #define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) 07435 #define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) 07436 #define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) 07437 #define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) 07438 #define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) 07439 #define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) 07440 #define CMU_CTRL_CLKOUTSEL1 (0x1UL << 23) 07441 #define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 07442 #define _CMU_CTRL_CLKOUTSEL1_MASK 0x800000UL 07443 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL 07444 #define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL 07445 #define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL 07446 #define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) 07447 #define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) 07448 #define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) 07450 /* Bit fields for CMU HFCORECLKDIV */ 07451 #define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL 07452 #define _CMU_HFCORECLKDIV_MASK 0x0000000FUL 07453 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 07454 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL 07455 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL 07456 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL 07457 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL 07458 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL 07459 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL 07460 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL 07461 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL 07462 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL 07463 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL 07464 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL 07465 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL 07466 #define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) 07467 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) 07468 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) 07469 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) 07470 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) 07471 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) 07472 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) 07473 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) 07474 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) 07475 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) 07476 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) 07478 /* Bit fields for CMU HFPERCLKDIV */ 07479 #define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL 07480 #define _CMU_HFPERCLKDIV_MASK 0x0000010FUL 07481 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 07482 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL 07483 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL 07484 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL 07485 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL 07486 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL 07487 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL 07488 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL 07489 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL 07490 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL 07491 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL 07492 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL 07493 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL 07494 #define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) 07495 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) 07496 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) 07497 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) 07498 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) 07499 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) 07500 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) 07501 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) 07502 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) 07503 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) 07504 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) 07505 #define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) 07506 #define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 07507 #define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL 07508 #define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL 07509 #define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) 07511 /* Bit fields for CMU HFRCOCTRL */ 07512 #define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL 07513 #define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL 07514 #define _CMU_HFRCOCTRL_TUNING_SHIFT 0 07515 #define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL 07516 #define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL 07517 #define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) 07518 #define _CMU_HFRCOCTRL_BAND_SHIFT 8 07519 #define _CMU_HFRCOCTRL_BAND_MASK 0x700UL 07520 #define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL 07521 #define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL 07522 #define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL 07523 #define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL 07524 #define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL 07525 #define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL 07526 #define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL 07527 #define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) 07528 #define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) 07529 #define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) 07530 #define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) 07531 #define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) 07532 #define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) 07533 #define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) 07534 #define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 07535 #define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL 07536 #define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL 07537 #define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) 07539 /* Bit fields for CMU LFRCOCTRL */ 07540 #define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL 07541 #define _CMU_LFRCOCTRL_MASK 0x0000007FUL 07542 #define _CMU_LFRCOCTRL_TUNING_SHIFT 0 07543 #define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL 07544 #define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL 07545 #define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) 07547 /* Bit fields for CMU AUXHFRCOCTRL */ 07548 #define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL 07549 #define _CMU_AUXHFRCOCTRL_MASK 0x000000FFUL 07550 #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 07551 #define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL 07552 #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL 07553 #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) 07555 /* Bit fields for CMU CALCTRL */ 07556 #define _CMU_CALCTRL_RESETVALUE 0x00000000UL 07557 #define _CMU_CALCTRL_MASK 0x00000007UL 07558 #define _CMU_CALCTRL_REFSEL_SHIFT 0 07559 #define _CMU_CALCTRL_REFSEL_MASK 0x7UL 07560 #define _CMU_CALCTRL_REFSEL_DEFAULT 0x00000000UL 07561 #define _CMU_CALCTRL_REFSEL_HFXO 0x00000000UL 07562 #define _CMU_CALCTRL_REFSEL_LFXO 0x00000001UL 07563 #define _CMU_CALCTRL_REFSEL_HFRCO 0x00000002UL 07564 #define _CMU_CALCTRL_REFSEL_LFRCO 0x00000003UL 07565 #define _CMU_CALCTRL_REFSEL_AUXHFRCO 0x00000004UL 07566 #define CMU_CALCTRL_REFSEL_DEFAULT (_CMU_CALCTRL_REFSEL_DEFAULT << 0) 07567 #define CMU_CALCTRL_REFSEL_HFXO (_CMU_CALCTRL_REFSEL_HFXO << 0) 07568 #define CMU_CALCTRL_REFSEL_LFXO (_CMU_CALCTRL_REFSEL_LFXO << 0) 07569 #define CMU_CALCTRL_REFSEL_HFRCO (_CMU_CALCTRL_REFSEL_HFRCO << 0) 07570 #define CMU_CALCTRL_REFSEL_LFRCO (_CMU_CALCTRL_REFSEL_LFRCO << 0) 07571 #define CMU_CALCTRL_REFSEL_AUXHFRCO (_CMU_CALCTRL_REFSEL_AUXHFRCO << 0) 07573 /* Bit fields for CMU CALCNT */ 07574 #define _CMU_CALCNT_RESETVALUE 0x00000000UL 07575 #define _CMU_CALCNT_MASK 0x000FFFFFUL 07576 #define _CMU_CALCNT_CALCNT_SHIFT 0 07577 #define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL 07578 #define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL 07579 #define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) 07581 /* Bit fields for CMU OSCENCMD */ 07582 #define _CMU_OSCENCMD_RESETVALUE 0x00000000UL 07583 #define _CMU_OSCENCMD_MASK 0x000003FFUL 07584 #define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) 07585 #define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 07586 #define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL 07587 #define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL 07588 #define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) 07589 #define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) 07590 #define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 07591 #define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL 07592 #define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL 07593 #define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) 07594 #define CMU_OSCENCMD_HFXOEN (0x1UL << 2) 07595 #define _CMU_OSCENCMD_HFXOEN_SHIFT 2 07596 #define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL 07597 #define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL 07598 #define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) 07599 #define CMU_OSCENCMD_HFXODIS (0x1UL << 3) 07600 #define _CMU_OSCENCMD_HFXODIS_SHIFT 3 07601 #define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL 07602 #define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL 07603 #define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) 07604 #define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) 07605 #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 07606 #define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL 07607 #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL 07608 #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) 07609 #define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) 07610 #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 07611 #define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL 07612 #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL 07613 #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) 07614 #define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) 07615 #define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 07616 #define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL 07617 #define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL 07618 #define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) 07619 #define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) 07620 #define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 07621 #define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL 07622 #define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL 07623 #define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) 07624 #define CMU_OSCENCMD_LFXOEN (0x1UL << 8) 07625 #define _CMU_OSCENCMD_LFXOEN_SHIFT 8 07626 #define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL 07627 #define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL 07628 #define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) 07629 #define CMU_OSCENCMD_LFXODIS (0x1UL << 9) 07630 #define _CMU_OSCENCMD_LFXODIS_SHIFT 9 07631 #define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL 07632 #define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL 07633 #define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) 07635 /* Bit fields for CMU CMD */ 07636 #define _CMU_CMD_RESETVALUE 0x00000000UL 07637 #define _CMU_CMD_MASK 0x0000000FUL 07638 #define _CMU_CMD_HFCLKSEL_SHIFT 0 07639 #define _CMU_CMD_HFCLKSEL_MASK 0x7UL 07640 #define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL 07641 #define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL 07642 #define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL 07643 #define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL 07644 #define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL 07645 #define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) 07646 #define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) 07647 #define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) 07648 #define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) 07649 #define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) 07650 #define CMU_CMD_CALSTART (0x1UL << 3) 07651 #define _CMU_CMD_CALSTART_SHIFT 3 07652 #define _CMU_CMD_CALSTART_MASK 0x8UL 07653 #define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL 07654 #define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) 07656 /* Bit fields for CMU LFCLKSEL */ 07657 #define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL 07658 #define _CMU_LFCLKSEL_MASK 0x0000000FUL 07659 #define _CMU_LFCLKSEL_LFA_SHIFT 0 07660 #define _CMU_LFCLKSEL_LFA_MASK 0x3UL 07661 #define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL 07662 #define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL 07663 #define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL 07664 #define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL 07665 #define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL 07666 #define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) 07667 #define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) 07668 #define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) 07669 #define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) 07670 #define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) 07671 #define _CMU_LFCLKSEL_LFB_SHIFT 2 07672 #define _CMU_LFCLKSEL_LFB_MASK 0xCUL 07673 #define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL 07674 #define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL 07675 #define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL 07676 #define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL 07677 #define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL 07678 #define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) 07679 #define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) 07680 #define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) 07681 #define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) 07682 #define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) 07684 /* Bit fields for CMU STATUS */ 07685 #define _CMU_STATUS_RESETVALUE 0x00000403UL 07686 #define _CMU_STATUS_MASK 0x00007FFFUL 07687 #define CMU_STATUS_HFRCOENS (0x1UL << 0) 07688 #define _CMU_STATUS_HFRCOENS_SHIFT 0 07689 #define _CMU_STATUS_HFRCOENS_MASK 0x1UL 07690 #define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL 07691 #define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) 07692 #define CMU_STATUS_HFRCORDY (0x1UL << 1) 07693 #define _CMU_STATUS_HFRCORDY_SHIFT 1 07694 #define _CMU_STATUS_HFRCORDY_MASK 0x2UL 07695 #define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL 07696 #define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) 07697 #define CMU_STATUS_HFXOENS (0x1UL << 2) 07698 #define _CMU_STATUS_HFXOENS_SHIFT 2 07699 #define _CMU_STATUS_HFXOENS_MASK 0x4UL 07700 #define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL 07701 #define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) 07702 #define CMU_STATUS_HFXORDY (0x1UL << 3) 07703 #define _CMU_STATUS_HFXORDY_SHIFT 3 07704 #define _CMU_STATUS_HFXORDY_MASK 0x8UL 07705 #define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL 07706 #define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) 07707 #define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) 07708 #define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 07709 #define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL 07710 #define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL 07711 #define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) 07712 #define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) 07713 #define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 07714 #define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL 07715 #define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL 07716 #define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) 07717 #define CMU_STATUS_LFRCOENS (0x1UL << 6) 07718 #define _CMU_STATUS_LFRCOENS_SHIFT 6 07719 #define _CMU_STATUS_LFRCOENS_MASK 0x40UL 07720 #define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL 07721 #define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) 07722 #define CMU_STATUS_LFRCORDY (0x1UL << 7) 07723 #define _CMU_STATUS_LFRCORDY_SHIFT 7 07724 #define _CMU_STATUS_LFRCORDY_MASK 0x80UL 07725 #define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL 07726 #define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) 07727 #define CMU_STATUS_LFXOENS (0x1UL << 8) 07728 #define _CMU_STATUS_LFXOENS_SHIFT 8 07729 #define _CMU_STATUS_LFXOENS_MASK 0x100UL 07730 #define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL 07731 #define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) 07732 #define CMU_STATUS_LFXORDY (0x1UL << 9) 07733 #define _CMU_STATUS_LFXORDY_SHIFT 9 07734 #define _CMU_STATUS_LFXORDY_MASK 0x200UL 07735 #define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL 07736 #define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) 07737 #define CMU_STATUS_HFRCOSEL (0x1UL << 10) 07738 #define _CMU_STATUS_HFRCOSEL_SHIFT 10 07739 #define _CMU_STATUS_HFRCOSEL_MASK 0x400UL 07740 #define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL 07741 #define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) 07742 #define CMU_STATUS_HFXOSEL (0x1UL << 11) 07743 #define _CMU_STATUS_HFXOSEL_SHIFT 11 07744 #define _CMU_STATUS_HFXOSEL_MASK 0x800UL 07745 #define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL 07746 #define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) 07747 #define CMU_STATUS_LFRCOSEL (0x1UL << 12) 07748 #define _CMU_STATUS_LFRCOSEL_SHIFT 12 07749 #define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL 07750 #define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL 07751 #define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) 07752 #define CMU_STATUS_LFXOSEL (0x1UL << 13) 07753 #define _CMU_STATUS_LFXOSEL_SHIFT 13 07754 #define _CMU_STATUS_LFXOSEL_MASK 0x2000UL 07755 #define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL 07756 #define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) 07757 #define CMU_STATUS_CALBSY (0x1UL << 14) 07758 #define _CMU_STATUS_CALBSY_SHIFT 14 07759 #define _CMU_STATUS_CALBSY_MASK 0x4000UL 07760 #define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL 07761 #define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) 07763 /* Bit fields for CMU IF */ 07764 #define _CMU_IF_RESETVALUE 0x00000001UL 07765 #define _CMU_IF_MASK 0x0000003FUL 07766 #define CMU_IF_HFRCORDY (0x1UL << 0) 07767 #define _CMU_IF_HFRCORDY_SHIFT 0 07768 #define _CMU_IF_HFRCORDY_MASK 0x1UL 07769 #define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL 07770 #define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) 07771 #define CMU_IF_HFXORDY (0x1UL << 1) 07772 #define _CMU_IF_HFXORDY_SHIFT 1 07773 #define _CMU_IF_HFXORDY_MASK 0x2UL 07774 #define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL 07775 #define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) 07776 #define CMU_IF_LFRCORDY (0x1UL << 2) 07777 #define _CMU_IF_LFRCORDY_SHIFT 2 07778 #define _CMU_IF_LFRCORDY_MASK 0x4UL 07779 #define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL 07780 #define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) 07781 #define CMU_IF_LFXORDY (0x1UL << 3) 07782 #define _CMU_IF_LFXORDY_SHIFT 3 07783 #define _CMU_IF_LFXORDY_MASK 0x8UL 07784 #define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL 07785 #define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) 07786 #define CMU_IF_AUXHFRCORDY (0x1UL << 4) 07787 #define _CMU_IF_AUXHFRCORDY_SHIFT 4 07788 #define _CMU_IF_AUXHFRCORDY_MASK 0x10UL 07789 #define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL 07790 #define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) 07791 #define CMU_IF_CALRDY (0x1UL << 5) 07792 #define _CMU_IF_CALRDY_SHIFT 5 07793 #define _CMU_IF_CALRDY_MASK 0x20UL 07794 #define _CMU_IF_CALRDY_DEFAULT 0x00000000UL 07795 #define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) 07797 /* Bit fields for CMU IFS */ 07798 #define _CMU_IFS_RESETVALUE 0x00000000UL 07799 #define _CMU_IFS_MASK 0x0000003FUL 07800 #define CMU_IFS_HFRCORDY (0x1UL << 0) 07801 #define _CMU_IFS_HFRCORDY_SHIFT 0 07802 #define _CMU_IFS_HFRCORDY_MASK 0x1UL 07803 #define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL 07804 #define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) 07805 #define CMU_IFS_HFXORDY (0x1UL << 1) 07806 #define _CMU_IFS_HFXORDY_SHIFT 1 07807 #define _CMU_IFS_HFXORDY_MASK 0x2UL 07808 #define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL 07809 #define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) 07810 #define CMU_IFS_LFRCORDY (0x1UL << 2) 07811 #define _CMU_IFS_LFRCORDY_SHIFT 2 07812 #define _CMU_IFS_LFRCORDY_MASK 0x4UL 07813 #define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL 07814 #define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) 07815 #define CMU_IFS_LFXORDY (0x1UL << 3) 07816 #define _CMU_IFS_LFXORDY_SHIFT 3 07817 #define _CMU_IFS_LFXORDY_MASK 0x8UL 07818 #define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL 07819 #define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) 07820 #define CMU_IFS_AUXHFRCORDY (0x1UL << 4) 07821 #define _CMU_IFS_AUXHFRCORDY_SHIFT 4 07822 #define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL 07823 #define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL 07824 #define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) 07825 #define CMU_IFS_CALRDY (0x1UL << 5) 07826 #define _CMU_IFS_CALRDY_SHIFT 5 07827 #define _CMU_IFS_CALRDY_MASK 0x20UL 07828 #define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL 07829 #define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) 07831 /* Bit fields for CMU IFC */ 07832 #define _CMU_IFC_RESETVALUE 0x00000000UL 07833 #define _CMU_IFC_MASK 0x0000003FUL 07834 #define CMU_IFC_HFRCORDY (0x1UL << 0) 07835 #define _CMU_IFC_HFRCORDY_SHIFT 0 07836 #define _CMU_IFC_HFRCORDY_MASK 0x1UL 07837 #define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL 07838 #define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) 07839 #define CMU_IFC_HFXORDY (0x1UL << 1) 07840 #define _CMU_IFC_HFXORDY_SHIFT 1 07841 #define _CMU_IFC_HFXORDY_MASK 0x2UL 07842 #define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL 07843 #define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) 07844 #define CMU_IFC_LFRCORDY (0x1UL << 2) 07845 #define _CMU_IFC_LFRCORDY_SHIFT 2 07846 #define _CMU_IFC_LFRCORDY_MASK 0x4UL 07847 #define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL 07848 #define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) 07849 #define CMU_IFC_LFXORDY (0x1UL << 3) 07850 #define _CMU_IFC_LFXORDY_SHIFT 3 07851 #define _CMU_IFC_LFXORDY_MASK 0x8UL 07852 #define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL 07853 #define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) 07854 #define CMU_IFC_AUXHFRCORDY (0x1UL << 4) 07855 #define _CMU_IFC_AUXHFRCORDY_SHIFT 4 07856 #define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL 07857 #define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL 07858 #define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) 07859 #define CMU_IFC_CALRDY (0x1UL << 5) 07860 #define _CMU_IFC_CALRDY_SHIFT 5 07861 #define _CMU_IFC_CALRDY_MASK 0x20UL 07862 #define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL 07863 #define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) 07865 /* Bit fields for CMU IEN */ 07866 #define _CMU_IEN_RESETVALUE 0x00000000UL 07867 #define _CMU_IEN_MASK 0x0000003FUL 07868 #define CMU_IEN_HFRCORDY (0x1UL << 0) 07869 #define _CMU_IEN_HFRCORDY_SHIFT 0 07870 #define _CMU_IEN_HFRCORDY_MASK 0x1UL 07871 #define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL 07872 #define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) 07873 #define CMU_IEN_HFXORDY (0x1UL << 1) 07874 #define _CMU_IEN_HFXORDY_SHIFT 1 07875 #define _CMU_IEN_HFXORDY_MASK 0x2UL 07876 #define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL 07877 #define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) 07878 #define CMU_IEN_LFRCORDY (0x1UL << 2) 07879 #define _CMU_IEN_LFRCORDY_SHIFT 2 07880 #define _CMU_IEN_LFRCORDY_MASK 0x4UL 07881 #define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL 07882 #define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) 07883 #define CMU_IEN_LFXORDY (0x1UL << 3) 07884 #define _CMU_IEN_LFXORDY_SHIFT 3 07885 #define _CMU_IEN_LFXORDY_MASK 0x8UL 07886 #define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL 07887 #define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) 07888 #define CMU_IEN_AUXHFRCORDY (0x1UL << 4) 07889 #define _CMU_IEN_AUXHFRCORDY_SHIFT 4 07890 #define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL 07891 #define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL 07892 #define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) 07893 #define CMU_IEN_CALRDY (0x1UL << 5) 07894 #define _CMU_IEN_CALRDY_SHIFT 5 07895 #define _CMU_IEN_CALRDY_MASK 0x20UL 07896 #define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL 07897 #define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) 07899 /* Bit fields for CMU HFCORECLKEN0 */ 07900 #define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL 07901 #define _CMU_HFCORECLKEN0_MASK 0x0000000FUL 07902 #define CMU_HFCORECLKEN0_AES (0x1UL << 0) 07903 #define _CMU_HFCORECLKEN0_AES_SHIFT 0 07904 #define _CMU_HFCORECLKEN0_AES_MASK 0x1UL 07905 #define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL 07906 #define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 0) 07907 #define CMU_HFCORECLKEN0_DMA (0x1UL << 1) 07908 #define _CMU_HFCORECLKEN0_DMA_SHIFT 1 07909 #define _CMU_HFCORECLKEN0_DMA_MASK 0x2UL 07910 #define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL 07911 #define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 1) 07912 #define CMU_HFCORECLKEN0_LE (0x1UL << 2) 07913 #define _CMU_HFCORECLKEN0_LE_SHIFT 2 07914 #define _CMU_HFCORECLKEN0_LE_MASK 0x4UL 07915 #define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL 07916 #define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 2) 07917 #define CMU_HFCORECLKEN0_EBI (0x1UL << 3) 07918 #define _CMU_HFCORECLKEN0_EBI_SHIFT 3 07919 #define _CMU_HFCORECLKEN0_EBI_MASK 0x8UL 07920 #define _CMU_HFCORECLKEN0_EBI_DEFAULT 0x00000000UL 07921 #define CMU_HFCORECLKEN0_EBI_DEFAULT (_CMU_HFCORECLKEN0_EBI_DEFAULT << 3) 07923 /* Bit fields for CMU HFPERCLKEN0 */ 07924 #define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL 07925 #define _CMU_HFPERCLKEN0_MASK 0x0000FFFFUL 07926 #define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) 07927 #define _CMU_HFPERCLKEN0_USART0_SHIFT 0 07928 #define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL 07929 #define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL 07930 #define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) 07931 #define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) 07932 #define _CMU_HFPERCLKEN0_USART1_SHIFT 1 07933 #define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL 07934 #define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL 07935 #define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) 07936 #define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) 07937 #define _CMU_HFPERCLKEN0_USART2_SHIFT 2 07938 #define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL 07939 #define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL 07940 #define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) 07941 #define CMU_HFPERCLKEN0_UART0 (0x1UL << 3) 07942 #define _CMU_HFPERCLKEN0_UART0_SHIFT 3 07943 #define _CMU_HFPERCLKEN0_UART0_MASK 0x8UL 07944 #define _CMU_HFPERCLKEN0_UART0_DEFAULT 0x00000000UL 07945 #define CMU_HFPERCLKEN0_UART0_DEFAULT (_CMU_HFPERCLKEN0_UART0_DEFAULT << 3) 07946 #define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 4) 07947 #define _CMU_HFPERCLKEN0_TIMER0_SHIFT 4 07948 #define _CMU_HFPERCLKEN0_TIMER0_MASK 0x10UL 07949 #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL 07950 #define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 4) 07951 #define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 5) 07952 #define _CMU_HFPERCLKEN0_TIMER1_SHIFT 5 07953 #define _CMU_HFPERCLKEN0_TIMER1_MASK 0x20UL 07954 #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL 07955 #define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 5) 07956 #define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 6) 07957 #define _CMU_HFPERCLKEN0_TIMER2_SHIFT 6 07958 #define _CMU_HFPERCLKEN0_TIMER2_MASK 0x40UL 07959 #define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL 07960 #define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 6) 07961 #define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 7) 07962 #define _CMU_HFPERCLKEN0_ACMP0_SHIFT 7 07963 #define _CMU_HFPERCLKEN0_ACMP0_MASK 0x80UL 07964 #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL 07965 #define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 7) 07966 #define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 8) 07967 #define _CMU_HFPERCLKEN0_ACMP1_SHIFT 8 07968 #define _CMU_HFPERCLKEN0_ACMP1_MASK 0x100UL 07969 #define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL 07970 #define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 8) 07971 #define CMU_HFPERCLKEN0_PRS (0x1UL << 10) 07972 #define _CMU_HFPERCLKEN0_PRS_SHIFT 10 07973 #define _CMU_HFPERCLKEN0_PRS_MASK 0x400UL 07974 #define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL 07975 #define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 10) 07976 #define CMU_HFPERCLKEN0_DAC0 (0x1UL << 11) 07977 #define _CMU_HFPERCLKEN0_DAC0_SHIFT 11 07978 #define _CMU_HFPERCLKEN0_DAC0_MASK 0x800UL 07979 #define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL 07980 #define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 11) 07981 #define CMU_HFPERCLKEN0_GPIO (0x1UL << 12) 07982 #define _CMU_HFPERCLKEN0_GPIO_SHIFT 12 07983 #define _CMU_HFPERCLKEN0_GPIO_MASK 0x1000UL 07984 #define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL 07985 #define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 12) 07986 #define CMU_HFPERCLKEN0_VCMP (0x1UL << 13) 07987 #define _CMU_HFPERCLKEN0_VCMP_SHIFT 13 07988 #define _CMU_HFPERCLKEN0_VCMP_MASK 0x2000UL 07989 #define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL 07990 #define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 13) 07991 #define CMU_HFPERCLKEN0_ADC0 (0x1UL << 14) 07992 #define _CMU_HFPERCLKEN0_ADC0_SHIFT 14 07993 #define _CMU_HFPERCLKEN0_ADC0_MASK 0x4000UL 07994 #define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL 07995 #define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 14) 07996 #define CMU_HFPERCLKEN0_I2C0 (0x1UL << 15) 07997 #define _CMU_HFPERCLKEN0_I2C0_SHIFT 15 07998 #define _CMU_HFPERCLKEN0_I2C0_MASK 0x8000UL 07999 #define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL 08000 #define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 15) 08002 /* Bit fields for CMU SYNCBUSY */ 08003 #define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL 08004 #define _CMU_SYNCBUSY_MASK 0x00000055UL 08005 #define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) 08006 #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 08007 #define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL 08008 #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL 08009 #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) 08010 #define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) 08011 #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 08012 #define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL 08013 #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL 08014 #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) 08015 #define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) 08016 #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 08017 #define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL 08018 #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL 08019 #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) 08020 #define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) 08021 #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 08022 #define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL 08023 #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL 08024 #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) 08026 /* Bit fields for CMU FREEZE */ 08027 #define _CMU_FREEZE_RESETVALUE 0x00000000UL 08028 #define _CMU_FREEZE_MASK 0x00000001UL 08029 #define CMU_FREEZE_REGFREEZE (0x1UL << 0) 08030 #define _CMU_FREEZE_REGFREEZE_SHIFT 0 08031 #define _CMU_FREEZE_REGFREEZE_MASK 0x1UL 08032 #define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL 08033 #define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL 08034 #define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL 08035 #define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) 08036 #define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) 08037 #define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) 08039 /* Bit fields for CMU LFACLKEN0 */ 08040 #define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL 08041 #define _CMU_LFACLKEN0_MASK 0x00000007UL 08042 #define CMU_LFACLKEN0_RTC (0x1UL << 0) 08043 #define _CMU_LFACLKEN0_RTC_SHIFT 0 08044 #define _CMU_LFACLKEN0_RTC_MASK 0x1UL 08045 #define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL 08046 #define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 0) 08047 #define CMU_LFACLKEN0_LETIMER0 (0x1UL << 1) 08048 #define _CMU_LFACLKEN0_LETIMER0_SHIFT 1 08049 #define _CMU_LFACLKEN0_LETIMER0_MASK 0x2UL 08050 #define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL 08051 #define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 1) 08052 #define CMU_LFACLKEN0_LCD (0x1UL << 2) 08053 #define _CMU_LFACLKEN0_LCD_SHIFT 2 08054 #define _CMU_LFACLKEN0_LCD_MASK 0x4UL 08055 #define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL 08056 #define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 2) 08058 /* Bit fields for CMU LFBCLKEN0 */ 08059 #define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL 08060 #define _CMU_LFBCLKEN0_MASK 0x00000003UL 08061 #define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) 08062 #define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 08063 #define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL 08064 #define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL 08065 #define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) 08066 #define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) 08067 #define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 08068 #define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL 08069 #define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL 08070 #define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) 08072 /* Bit fields for CMU LFAPRESC0 */ 08073 #define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL 08074 #define _CMU_LFAPRESC0_MASK 0x000003FFUL 08075 #define _CMU_LFAPRESC0_RTC_SHIFT 0 08076 #define _CMU_LFAPRESC0_RTC_MASK 0xFUL 08077 #define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL 08078 #define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL 08079 #define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL 08080 #define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL 08081 #define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL 08082 #define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL 08083 #define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL 08084 #define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL 08085 #define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL 08086 #define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL 08087 #define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL 08088 #define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL 08089 #define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL 08090 #define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL 08091 #define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL 08092 #define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL 08093 #define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 0) 08094 #define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 0) 08095 #define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 0) 08096 #define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 0) 08097 #define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 0) 08098 #define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 0) 08099 #define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 0) 08100 #define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 0) 08101 #define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 0) 08102 #define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 0) 08103 #define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 0) 08104 #define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 0) 08105 #define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 0) 08106 #define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 0) 08107 #define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 0) 08108 #define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 0) 08109 #define _CMU_LFAPRESC0_LETIMER0_SHIFT 4 08110 #define _CMU_LFAPRESC0_LETIMER0_MASK 0xF0UL 08111 #define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL 08112 #define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL 08113 #define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL 08114 #define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL 08115 #define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL 08116 #define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL 08117 #define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL 08118 #define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL 08119 #define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL 08120 #define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL 08121 #define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL 08122 #define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL 08123 #define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL 08124 #define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL 08125 #define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL 08126 #define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL 08127 #define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 4) 08128 #define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 4) 08129 #define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 4) 08130 #define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 4) 08131 #define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 4) 08132 #define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 4) 08133 #define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 4) 08134 #define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 4) 08135 #define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 4) 08136 #define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 4) 08137 #define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 4) 08138 #define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 4) 08139 #define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 4) 08140 #define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 4) 08141 #define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 4) 08142 #define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 4) 08143 #define _CMU_LFAPRESC0_LCD_SHIFT 8 08144 #define _CMU_LFAPRESC0_LCD_MASK 0x300UL 08145 #define _CMU_LFAPRESC0_LCD_DIV16 0x00000000UL 08146 #define _CMU_LFAPRESC0_LCD_DIV32 0x00000001UL 08147 #define _CMU_LFAPRESC0_LCD_DIV64 0x00000002UL 08148 #define _CMU_LFAPRESC0_LCD_DIV128 0x00000003UL 08149 #define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 8) 08150 #define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 8) 08151 #define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 8) 08152 #define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 8) 08154 /* Bit fields for CMU LFBPRESC0 */ 08155 #define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL 08156 #define _CMU_LFBPRESC0_MASK 0x00000033UL 08157 #define _CMU_LFBPRESC0_LEUART0_SHIFT 0 08158 #define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL 08159 #define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL 08160 #define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL 08161 #define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL 08162 #define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL 08163 #define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) 08164 #define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) 08165 #define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) 08166 #define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) 08167 #define _CMU_LFBPRESC0_LEUART1_SHIFT 4 08168 #define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL 08169 #define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL 08170 #define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL 08171 #define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL 08172 #define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL 08173 #define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) 08174 #define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) 08175 #define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) 08176 #define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) 08178 /* Bit fields for CMU PCNTCTRL */ 08179 #define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL 08180 #define _CMU_PCNTCTRL_MASK 0x0000003FUL 08181 #define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) 08182 #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 08183 #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL 08184 #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL 08185 #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) 08186 #define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) 08187 #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 08188 #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL 08189 #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL 08190 #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL 08191 #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL 08192 #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) 08193 #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) 08194 #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) 08195 #define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) 08196 #define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 08197 #define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL 08198 #define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL 08199 #define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) 08200 #define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) 08201 #define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 08202 #define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL 08203 #define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL 08204 #define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL 08205 #define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL 08206 #define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) 08207 #define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) 08208 #define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) 08209 #define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) 08210 #define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 08211 #define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL 08212 #define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL 08213 #define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) 08214 #define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) 08215 #define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 08216 #define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL 08217 #define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL 08218 #define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL 08219 #define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL 08220 #define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) 08221 #define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) 08222 #define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) 08224 /* Bit fields for CMU LCDCTRL */ 08225 #define _CMU_LCDCTRL_RESETVALUE 0x00000020UL 08226 #define _CMU_LCDCTRL_MASK 0x0000007FUL 08227 #define _CMU_LCDCTRL_FDIV_SHIFT 0 08228 #define _CMU_LCDCTRL_FDIV_MASK 0x7UL 08229 #define _CMU_LCDCTRL_FDIV_DEFAULT 0x00000000UL 08230 #define CMU_LCDCTRL_FDIV_DEFAULT (_CMU_LCDCTRL_FDIV_DEFAULT << 0) 08231 #define CMU_LCDCTRL_VBOOSTEN (0x1UL << 3) 08232 #define _CMU_LCDCTRL_VBOOSTEN_SHIFT 3 08233 #define _CMU_LCDCTRL_VBOOSTEN_MASK 0x8UL 08234 #define _CMU_LCDCTRL_VBOOSTEN_DEFAULT 0x00000000UL 08235 #define CMU_LCDCTRL_VBOOSTEN_DEFAULT (_CMU_LCDCTRL_VBOOSTEN_DEFAULT << 3) 08236 #define _CMU_LCDCTRL_VBFDIV_SHIFT 4 08237 #define _CMU_LCDCTRL_VBFDIV_MASK 0x70UL 08238 #define _CMU_LCDCTRL_VBFDIV_DIV1 0x00000000UL 08239 #define _CMU_LCDCTRL_VBFDIV_DIV2 0x00000001UL 08240 #define _CMU_LCDCTRL_VBFDIV_DEFAULT 0x00000002UL 08241 #define _CMU_LCDCTRL_VBFDIV_DIV4 0x00000002UL 08242 #define _CMU_LCDCTRL_VBFDIV_DIV8 0x00000003UL 08243 #define _CMU_LCDCTRL_VBFDIV_DIV16 0x00000004UL 08244 #define _CMU_LCDCTRL_VBFDIV_DIV32 0x00000005UL 08245 #define _CMU_LCDCTRL_VBFDIV_DIV64 0x00000006UL 08246 #define _CMU_LCDCTRL_VBFDIV_DIV128 0x00000007UL 08247 #define CMU_LCDCTRL_VBFDIV_DIV1 (_CMU_LCDCTRL_VBFDIV_DIV1 << 4) 08248 #define CMU_LCDCTRL_VBFDIV_DIV2 (_CMU_LCDCTRL_VBFDIV_DIV2 << 4) 08249 #define CMU_LCDCTRL_VBFDIV_DEFAULT (_CMU_LCDCTRL_VBFDIV_DEFAULT << 4) 08250 #define CMU_LCDCTRL_VBFDIV_DIV4 (_CMU_LCDCTRL_VBFDIV_DIV4 << 4) 08251 #define CMU_LCDCTRL_VBFDIV_DIV8 (_CMU_LCDCTRL_VBFDIV_DIV8 << 4) 08252 #define CMU_LCDCTRL_VBFDIV_DIV16 (_CMU_LCDCTRL_VBFDIV_DIV16 << 4) 08253 #define CMU_LCDCTRL_VBFDIV_DIV32 (_CMU_LCDCTRL_VBFDIV_DIV32 << 4) 08254 #define CMU_LCDCTRL_VBFDIV_DIV64 (_CMU_LCDCTRL_VBFDIV_DIV64 << 4) 08255 #define CMU_LCDCTRL_VBFDIV_DIV128 (_CMU_LCDCTRL_VBFDIV_DIV128 << 4) 08257 /* Bit fields for CMU ROUTE */ 08258 #define _CMU_ROUTE_RESETVALUE 0x00000000UL 08259 #define _CMU_ROUTE_MASK 0x00000007UL 08260 #define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) 08261 #define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 08262 #define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL 08263 #define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL 08264 #define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) 08265 #define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) 08266 #define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 08267 #define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL 08268 #define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL 08269 #define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) 08270 #define CMU_ROUTE_LOCATION (0x1UL << 2) 08271 #define _CMU_ROUTE_LOCATION_SHIFT 2 08272 #define _CMU_ROUTE_LOCATION_MASK 0x4UL 08273 #define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL 08274 #define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL 08275 #define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL 08276 #define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) 08277 #define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) 08278 #define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) 08280 /* Bit fields for CMU LOCK */ 08281 #define _CMU_LOCK_RESETVALUE 0x00000000UL 08282 #define _CMU_LOCK_MASK 0x0000FFFFUL 08283 #define _CMU_LOCK_LOCKKEY_SHIFT 0 08284 #define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL 08285 #define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL 08286 #define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL 08287 #define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL 08288 #define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL 08289 #define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL 08290 #define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) 08291 #define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) 08292 #define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) 08293 #define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) 08294 #define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) 08300 /**************************************************************************/ 08305 /* Bit fields for AES CTRL */ 08306 #define _AES_CTRL_RESETVALUE 0x00000000UL 08307 #define _AES_CTRL_MASK 0x00000037UL 08308 #define AES_CTRL_DECRYPT (0x1UL << 0) 08309 #define _AES_CTRL_DECRYPT_SHIFT 0 08310 #define _AES_CTRL_DECRYPT_MASK 0x1UL 08311 #define _AES_CTRL_DECRYPT_DEFAULT 0x00000000UL 08312 #define AES_CTRL_DECRYPT_DEFAULT (_AES_CTRL_DECRYPT_DEFAULT << 0) 08313 #define AES_CTRL_AES256 (0x1UL << 1) 08314 #define _AES_CTRL_AES256_SHIFT 1 08315 #define _AES_CTRL_AES256_MASK 0x2UL 08316 #define _AES_CTRL_AES256_DEFAULT 0x00000000UL 08317 #define AES_CTRL_AES256_DEFAULT (_AES_CTRL_AES256_DEFAULT << 1) 08318 #define AES_CTRL_KEYBUFEN (0x1UL << 2) 08319 #define _AES_CTRL_KEYBUFEN_SHIFT 2 08320 #define _AES_CTRL_KEYBUFEN_MASK 0x4UL 08321 #define _AES_CTRL_KEYBUFEN_DEFAULT 0x00000000UL 08322 #define AES_CTRL_KEYBUFEN_DEFAULT (_AES_CTRL_KEYBUFEN_DEFAULT << 2) 08323 #define AES_CTRL_DATASTART (0x1UL << 4) 08324 #define _AES_CTRL_DATASTART_SHIFT 4 08325 #define _AES_CTRL_DATASTART_MASK 0x10UL 08326 #define _AES_CTRL_DATASTART_DEFAULT 0x00000000UL 08327 #define AES_CTRL_DATASTART_DEFAULT (_AES_CTRL_DATASTART_DEFAULT << 4) 08328 #define AES_CTRL_XORSTART (0x1UL << 5) 08329 #define _AES_CTRL_XORSTART_SHIFT 5 08330 #define _AES_CTRL_XORSTART_MASK 0x20UL 08331 #define _AES_CTRL_XORSTART_DEFAULT 0x00000000UL 08332 #define AES_CTRL_XORSTART_DEFAULT (_AES_CTRL_XORSTART_DEFAULT << 5) 08334 /* Bit fields for AES CMD */ 08335 #define _AES_CMD_RESETVALUE 0x00000000UL 08336 #define _AES_CMD_MASK 0x00000003UL 08337 #define AES_CMD_START (0x1UL << 0) 08338 #define _AES_CMD_START_SHIFT 0 08339 #define _AES_CMD_START_MASK 0x1UL 08340 #define _AES_CMD_START_DEFAULT 0x00000000UL 08341 #define AES_CMD_START_DEFAULT (_AES_CMD_START_DEFAULT << 0) 08342 #define AES_CMD_STOP (0x1UL << 1) 08343 #define _AES_CMD_STOP_SHIFT 1 08344 #define _AES_CMD_STOP_MASK 0x2UL 08345 #define _AES_CMD_STOP_DEFAULT 0x00000000UL 08346 #define AES_CMD_STOP_DEFAULT (_AES_CMD_STOP_DEFAULT << 1) 08348 /* Bit fields for AES STATUS */ 08349 #define _AES_STATUS_RESETVALUE 0x00000000UL 08350 #define _AES_STATUS_MASK 0x00000001UL 08351 #define AES_STATUS_RUNNING (0x1UL << 0) 08352 #define _AES_STATUS_RUNNING_SHIFT 0 08353 #define _AES_STATUS_RUNNING_MASK 0x1UL 08354 #define _AES_STATUS_RUNNING_DEFAULT 0x00000000UL 08355 #define AES_STATUS_RUNNING_DEFAULT (_AES_STATUS_RUNNING_DEFAULT << 0) 08357 /* Bit fields for AES IEN */ 08358 #define _AES_IEN_RESETVALUE 0x00000000UL 08359 #define _AES_IEN_MASK 0x00000001UL 08360 #define AES_IEN_DONE (0x1UL << 0) 08361 #define _AES_IEN_DONE_SHIFT 0 08362 #define _AES_IEN_DONE_MASK 0x1UL 08363 #define _AES_IEN_DONE_DEFAULT 0x00000000UL 08364 #define AES_IEN_DONE_DEFAULT (_AES_IEN_DONE_DEFAULT << 0) 08366 /* Bit fields for AES IF */ 08367 #define _AES_IF_RESETVALUE 0x00000000UL 08368 #define _AES_IF_MASK 0x00000001UL 08369 #define AES_IF_DONE (0x1UL << 0) 08370 #define _AES_IF_DONE_SHIFT 0 08371 #define _AES_IF_DONE_MASK 0x1UL 08372 #define _AES_IF_DONE_DEFAULT 0x00000000UL 08373 #define AES_IF_DONE_DEFAULT (_AES_IF_DONE_DEFAULT << 0) 08375 /* Bit fields for AES IFS */ 08376 #define _AES_IFS_RESETVALUE 0x00000000UL 08377 #define _AES_IFS_MASK 0x00000001UL 08378 #define AES_IFS_DONE (0x1UL << 0) 08379 #define _AES_IFS_DONE_SHIFT 0 08380 #define _AES_IFS_DONE_MASK 0x1UL 08381 #define _AES_IFS_DONE_DEFAULT 0x00000000UL 08382 #define AES_IFS_DONE_DEFAULT (_AES_IFS_DONE_DEFAULT << 0) 08384 /* Bit fields for AES IFC */ 08385 #define _AES_IFC_RESETVALUE 0x00000000UL 08386 #define _AES_IFC_MASK 0x00000001UL 08387 #define AES_IFC_DONE (0x1UL << 0) 08388 #define _AES_IFC_DONE_SHIFT 0 08389 #define _AES_IFC_DONE_MASK 0x1UL 08390 #define _AES_IFC_DONE_DEFAULT 0x00000000UL 08391 #define AES_IFC_DONE_DEFAULT (_AES_IFC_DONE_DEFAULT << 0) 08393 /* Bit fields for AES DATA */ 08394 #define _AES_DATA_RESETVALUE 0x00000000UL 08395 #define _AES_DATA_MASK 0xFFFFFFFFUL 08396 #define _AES_DATA_DATA_SHIFT 0 08397 #define _AES_DATA_DATA_MASK 0xFFFFFFFFUL 08398 #define _AES_DATA_DATA_DEFAULT 0x00000000UL 08399 #define AES_DATA_DATA_DEFAULT (_AES_DATA_DATA_DEFAULT << 0) 08401 /* Bit fields for AES XORDATA */ 08402 #define _AES_XORDATA_RESETVALUE 0x00000000UL 08403 #define _AES_XORDATA_MASK 0xFFFFFFFFUL 08404 #define _AES_XORDATA_XORDATA_SHIFT 0 08405 #define _AES_XORDATA_XORDATA_MASK 0xFFFFFFFFUL 08406 #define _AES_XORDATA_XORDATA_DEFAULT 0x00000000UL 08407 #define AES_XORDATA_XORDATA_DEFAULT (_AES_XORDATA_XORDATA_DEFAULT << 0) 08409 /* Bit fields for AES KEYLA */ 08410 #define _AES_KEYLA_RESETVALUE 0x00000000UL 08411 #define _AES_KEYLA_MASK 0xFFFFFFFFUL 08412 #define _AES_KEYLA_KEYLA_SHIFT 0 08413 #define _AES_KEYLA_KEYLA_MASK 0xFFFFFFFFUL 08414 #define _AES_KEYLA_KEYLA_DEFAULT 0x00000000UL 08415 #define AES_KEYLA_KEYLA_DEFAULT (_AES_KEYLA_KEYLA_DEFAULT << 0) 08417 /* Bit fields for AES KEYLB */ 08418 #define _AES_KEYLB_RESETVALUE 0x00000000UL 08419 #define _AES_KEYLB_MASK 0xFFFFFFFFUL 08420 #define _AES_KEYLB_KEYLB_SHIFT 0 08421 #define _AES_KEYLB_KEYLB_MASK 0xFFFFFFFFUL 08422 #define _AES_KEYLB_KEYLB_DEFAULT 0x00000000UL 08423 #define AES_KEYLB_KEYLB_DEFAULT (_AES_KEYLB_KEYLB_DEFAULT << 0) 08425 /* Bit fields for AES KEYLC */ 08426 #define _AES_KEYLC_RESETVALUE 0x00000000UL 08427 #define _AES_KEYLC_MASK 0xFFFFFFFFUL 08428 #define _AES_KEYLC_KEYLC_SHIFT 0 08429 #define _AES_KEYLC_KEYLC_MASK 0xFFFFFFFFUL 08430 #define _AES_KEYLC_KEYLC_DEFAULT 0x00000000UL 08431 #define AES_KEYLC_KEYLC_DEFAULT (_AES_KEYLC_KEYLC_DEFAULT << 0) 08433 /* Bit fields for AES KEYLD */ 08434 #define _AES_KEYLD_RESETVALUE 0x00000000UL 08435 #define _AES_KEYLD_MASK 0xFFFFFFFFUL 08436 #define _AES_KEYLD_KEYLD_SHIFT 0 08437 #define _AES_KEYLD_KEYLD_MASK 0xFFFFFFFFUL 08438 #define _AES_KEYLD_KEYLD_DEFAULT 0x00000000UL 08439 #define AES_KEYLD_KEYLD_DEFAULT (_AES_KEYLD_KEYLD_DEFAULT << 0) 08441 /* Bit fields for AES KEYHA */ 08442 #define _AES_KEYHA_RESETVALUE 0x00000000UL 08443 #define _AES_KEYHA_MASK 0xFFFFFFFFUL 08444 #define _AES_KEYHA_KEYHA_SHIFT 0 08445 #define _AES_KEYHA_KEYHA_MASK 0xFFFFFFFFUL 08446 #define _AES_KEYHA_KEYHA_DEFAULT 0x00000000UL 08447 #define AES_KEYHA_KEYHA_DEFAULT (_AES_KEYHA_KEYHA_DEFAULT << 0) 08449 /* Bit fields for AES KEYHB */ 08450 #define _AES_KEYHB_RESETVALUE 0x00000000UL 08451 #define _AES_KEYHB_MASK 0xFFFFFFFFUL 08452 #define _AES_KEYHB_KEYHB_SHIFT 0 08453 #define _AES_KEYHB_KEYHB_MASK 0xFFFFFFFFUL 08454 #define _AES_KEYHB_KEYHB_DEFAULT 0x00000000UL 08455 #define AES_KEYHB_KEYHB_DEFAULT (_AES_KEYHB_KEYHB_DEFAULT << 0) 08457 /* Bit fields for AES KEYHC */ 08458 #define _AES_KEYHC_RESETVALUE 0x00000000UL 08459 #define _AES_KEYHC_MASK 0xFFFFFFFFUL 08460 #define _AES_KEYHC_KEYHC_SHIFT 0 08461 #define _AES_KEYHC_KEYHC_MASK 0xFFFFFFFFUL 08462 #define _AES_KEYHC_KEYHC_DEFAULT 0x00000000UL 08463 #define AES_KEYHC_KEYHC_DEFAULT (_AES_KEYHC_KEYHC_DEFAULT << 0) 08465 /* Bit fields for AES KEYHD */ 08466 #define _AES_KEYHD_RESETVALUE 0x00000000UL 08467 #define _AES_KEYHD_MASK 0xFFFFFFFFUL 08468 #define _AES_KEYHD_KEYHD_SHIFT 0 08469 #define _AES_KEYHD_KEYHD_MASK 0xFFFFFFFFUL 08470 #define _AES_KEYHD_KEYHD_DEFAULT 0x00000000UL 08471 #define AES_KEYHD_KEYHD_DEFAULT (_AES_KEYHD_KEYHD_DEFAULT << 0) 08477 /**************************************************************************/ 08482 /* Bit fields for EBI CTRL */ 08483 #define _EBI_CTRL_RESETVALUE 0x00000000UL 08484 #define _EBI_CTRL_MASK 0x00030F07UL 08485 #define _EBI_CTRL_MODE_SHIFT 0 08486 #define _EBI_CTRL_MODE_MASK 0x7UL 08487 #define _EBI_CTRL_MODE_DEFAULT 0x00000000UL 08488 #define _EBI_CTRL_MODE_D8A8 0x00000000UL 08489 #define _EBI_CTRL_MODE_D16A16ALE 0x00000001UL 08490 #define _EBI_CTRL_MODE_D8A24ALE 0x00000002UL 08491 #define EBI_CTRL_MODE_DEFAULT (_EBI_CTRL_MODE_DEFAULT << 0) 08492 #define EBI_CTRL_MODE_D8A8 (_EBI_CTRL_MODE_D8A8 << 0) 08493 #define EBI_CTRL_MODE_D16A16ALE (_EBI_CTRL_MODE_D16A16ALE << 0) 08494 #define EBI_CTRL_MODE_D8A24ALE (_EBI_CTRL_MODE_D8A24ALE << 0) 08495 #define EBI_CTRL_BANK0EN (0x1UL << 8) 08496 #define _EBI_CTRL_BANK0EN_SHIFT 8 08497 #define _EBI_CTRL_BANK0EN_MASK 0x100UL 08498 #define _EBI_CTRL_BANK0EN_DEFAULT 0x00000000UL 08499 #define EBI_CTRL_BANK0EN_DEFAULT (_EBI_CTRL_BANK0EN_DEFAULT << 8) 08500 #define EBI_CTRL_BANK1EN (0x1UL << 9) 08501 #define _EBI_CTRL_BANK1EN_SHIFT 9 08502 #define _EBI_CTRL_BANK1EN_MASK 0x200UL 08503 #define _EBI_CTRL_BANK1EN_DEFAULT 0x00000000UL 08504 #define EBI_CTRL_BANK1EN_DEFAULT (_EBI_CTRL_BANK1EN_DEFAULT << 9) 08505 #define EBI_CTRL_BANK2EN (0x1UL << 10) 08506 #define _EBI_CTRL_BANK2EN_SHIFT 10 08507 #define _EBI_CTRL_BANK2EN_MASK 0x400UL 08508 #define _EBI_CTRL_BANK2EN_DEFAULT 0x00000000UL 08509 #define EBI_CTRL_BANK2EN_DEFAULT (_EBI_CTRL_BANK2EN_DEFAULT << 10) 08510 #define EBI_CTRL_BANK3EN (0x1UL << 11) 08511 #define _EBI_CTRL_BANK3EN_SHIFT 11 08512 #define _EBI_CTRL_BANK3EN_MASK 0x800UL 08513 #define _EBI_CTRL_BANK3EN_DEFAULT 0x00000000UL 08514 #define EBI_CTRL_BANK3EN_DEFAULT (_EBI_CTRL_BANK3EN_DEFAULT << 11) 08515 #define EBI_CTRL_ARDYEN (0x1UL << 16) 08516 #define _EBI_CTRL_ARDYEN_SHIFT 16 08517 #define _EBI_CTRL_ARDYEN_MASK 0x10000UL 08518 #define _EBI_CTRL_ARDYEN_DEFAULT 0x00000000UL 08519 #define EBI_CTRL_ARDYEN_DEFAULT (_EBI_CTRL_ARDYEN_DEFAULT << 16) 08520 #define EBI_CTRL_ARDYTODIS (0x1UL << 17) 08521 #define _EBI_CTRL_ARDYTODIS_SHIFT 17 08522 #define _EBI_CTRL_ARDYTODIS_MASK 0x20000UL 08523 #define _EBI_CTRL_ARDYTODIS_DEFAULT 0x00000000UL 08524 #define EBI_CTRL_ARDYTODIS_DEFAULT (_EBI_CTRL_ARDYTODIS_DEFAULT << 17) 08526 /* Bit fields for EBI ADDRTIMING */ 08527 #define _EBI_ADDRTIMING_RESETVALUE 0x00000100UL 08528 #define _EBI_ADDRTIMING_MASK 0x00000303UL 08529 #define _EBI_ADDRTIMING_ADDRSETUP_SHIFT 0 08530 #define _EBI_ADDRTIMING_ADDRSETUP_MASK 0x3UL 08531 #define _EBI_ADDRTIMING_ADDRSETUP_DEFAULT 0x00000000UL 08532 #define EBI_ADDRTIMING_ADDRSETUP_DEFAULT (_EBI_ADDRTIMING_ADDRSETUP_DEFAULT << 0) 08533 #define _EBI_ADDRTIMING_ADDRHOLD_SHIFT 8 08534 #define _EBI_ADDRTIMING_ADDRHOLD_MASK 0x300UL 08535 #define _EBI_ADDRTIMING_ADDRHOLD_DEFAULT 0x00000001UL 08536 #define EBI_ADDRTIMING_ADDRHOLD_DEFAULT (_EBI_ADDRTIMING_ADDRHOLD_DEFAULT << 8) 08538 /* Bit fields for EBI RDTIMING */ 08539 #define _EBI_RDTIMING_RESETVALUE 0x00000000UL 08540 #define _EBI_RDTIMING_MASK 0x00030F03UL 08541 #define _EBI_RDTIMING_RDSETUP_SHIFT 0 08542 #define _EBI_RDTIMING_RDSETUP_MASK 0x3UL 08543 #define _EBI_RDTIMING_RDSETUP_DEFAULT 0x00000000UL 08544 #define EBI_RDTIMING_RDSETUP_DEFAULT (_EBI_RDTIMING_RDSETUP_DEFAULT << 0) 08545 #define _EBI_RDTIMING_RDSTRB_SHIFT 8 08546 #define _EBI_RDTIMING_RDSTRB_MASK 0xF00UL 08547 #define _EBI_RDTIMING_RDSTRB_DEFAULT 0x00000000UL 08548 #define EBI_RDTIMING_RDSTRB_DEFAULT (_EBI_RDTIMING_RDSTRB_DEFAULT << 8) 08549 #define _EBI_RDTIMING_RDHOLD_SHIFT 16 08550 #define _EBI_RDTIMING_RDHOLD_MASK 0x30000UL 08551 #define _EBI_RDTIMING_RDHOLD_DEFAULT 0x00000000UL 08552 #define EBI_RDTIMING_RDHOLD_DEFAULT (_EBI_RDTIMING_RDHOLD_DEFAULT << 16) 08554 /* Bit fields for EBI WRTIMING */ 08555 #define _EBI_WRTIMING_RESETVALUE 0x00010000UL 08556 #define _EBI_WRTIMING_MASK 0x00030F03UL 08557 #define _EBI_WRTIMING_WRSETUP_SHIFT 0 08558 #define _EBI_WRTIMING_WRSETUP_MASK 0x3UL 08559 #define _EBI_WRTIMING_WRSETUP_DEFAULT 0x00000000UL 08560 #define EBI_WRTIMING_WRSETUP_DEFAULT (_EBI_WRTIMING_WRSETUP_DEFAULT << 0) 08561 #define _EBI_WRTIMING_WRSTRB_SHIFT 8 08562 #define _EBI_WRTIMING_WRSTRB_MASK 0xF00UL 08563 #define _EBI_WRTIMING_WRSTRB_DEFAULT 0x00000000UL 08564 #define EBI_WRTIMING_WRSTRB_DEFAULT (_EBI_WRTIMING_WRSTRB_DEFAULT << 8) 08565 #define _EBI_WRTIMING_WRHOLD_SHIFT 16 08566 #define _EBI_WRTIMING_WRHOLD_MASK 0x30000UL 08567 #define _EBI_WRTIMING_WRHOLD_DEFAULT 0x00000001UL 08568 #define EBI_WRTIMING_WRHOLD_DEFAULT (_EBI_WRTIMING_WRHOLD_DEFAULT << 16) 08570 /* Bit fields for EBI POLARITY */ 08571 #define _EBI_POLARITY_RESETVALUE 0x00000000UL 08572 #define _EBI_POLARITY_MASK 0x0000001FUL 08573 #define EBI_POLARITY_CSPOL (0x1UL << 0) 08574 #define _EBI_POLARITY_CSPOL_SHIFT 0 08575 #define _EBI_POLARITY_CSPOL_MASK 0x1UL 08576 #define _EBI_POLARITY_CSPOL_DEFAULT 0x00000000UL 08577 #define _EBI_POLARITY_CSPOL_ACTIVELOW 0x00000000UL 08578 #define _EBI_POLARITY_CSPOL_ACTIVEHIGH 0x00000001UL 08579 #define EBI_POLARITY_CSPOL_DEFAULT (_EBI_POLARITY_CSPOL_DEFAULT << 0) 08580 #define EBI_POLARITY_CSPOL_ACTIVELOW (_EBI_POLARITY_CSPOL_ACTIVELOW << 0) 08581 #define EBI_POLARITY_CSPOL_ACTIVEHIGH (_EBI_POLARITY_CSPOL_ACTIVEHIGH << 0) 08582 #define EBI_POLARITY_REPOL (0x1UL << 1) 08583 #define _EBI_POLARITY_REPOL_SHIFT 1 08584 #define _EBI_POLARITY_REPOL_MASK 0x2UL 08585 #define _EBI_POLARITY_REPOL_DEFAULT 0x00000000UL 08586 #define _EBI_POLARITY_REPOL_ACTIVELOW 0x00000000UL 08587 #define _EBI_POLARITY_REPOL_ACTIVEHIGH 0x00000001UL 08588 #define EBI_POLARITY_REPOL_DEFAULT (_EBI_POLARITY_REPOL_DEFAULT << 1) 08589 #define EBI_POLARITY_REPOL_ACTIVELOW (_EBI_POLARITY_REPOL_ACTIVELOW << 1) 08590 #define EBI_POLARITY_REPOL_ACTIVEHIGH (_EBI_POLARITY_REPOL_ACTIVEHIGH << 1) 08591 #define EBI_POLARITY_WEPOL (0x1UL << 2) 08592 #define _EBI_POLARITY_WEPOL_SHIFT 2 08593 #define _EBI_POLARITY_WEPOL_MASK 0x4UL 08594 #define _EBI_POLARITY_WEPOL_DEFAULT 0x00000000UL 08595 #define _EBI_POLARITY_WEPOL_ACTIVELOW 0x00000000UL 08596 #define _EBI_POLARITY_WEPOL_ACTIVEHIGH 0x00000001UL 08597 #define EBI_POLARITY_WEPOL_DEFAULT (_EBI_POLARITY_WEPOL_DEFAULT << 2) 08598 #define EBI_POLARITY_WEPOL_ACTIVELOW (_EBI_POLARITY_WEPOL_ACTIVELOW << 2) 08599 #define EBI_POLARITY_WEPOL_ACTIVEHIGH (_EBI_POLARITY_WEPOL_ACTIVEHIGH << 2) 08600 #define EBI_POLARITY_ALEPOL (0x1UL << 3) 08601 #define _EBI_POLARITY_ALEPOL_SHIFT 3 08602 #define _EBI_POLARITY_ALEPOL_MASK 0x8UL 08603 #define _EBI_POLARITY_ALEPOL_DEFAULT 0x00000000UL 08604 #define _EBI_POLARITY_ALEPOL_ACTIVELOW 0x00000000UL 08605 #define _EBI_POLARITY_ALEPOL_ACTIVEHIGH 0x00000001UL 08606 #define EBI_POLARITY_ALEPOL_DEFAULT (_EBI_POLARITY_ALEPOL_DEFAULT << 3) 08607 #define EBI_POLARITY_ALEPOL_ACTIVELOW (_EBI_POLARITY_ALEPOL_ACTIVELOW << 3) 08608 #define EBI_POLARITY_ALEPOL_ACTIVEHIGH (_EBI_POLARITY_ALEPOL_ACTIVEHIGH << 3) 08609 #define EBI_POLARITY_ARDYPOL (0x1UL << 4) 08610 #define _EBI_POLARITY_ARDYPOL_SHIFT 4 08611 #define _EBI_POLARITY_ARDYPOL_MASK 0x10UL 08612 #define _EBI_POLARITY_ARDYPOL_DEFAULT 0x00000000UL 08613 #define _EBI_POLARITY_ARDYPOL_ACTIVELOW 0x00000000UL 08614 #define _EBI_POLARITY_ARDYPOL_ACTIVEHIGH 0x00000001UL 08615 #define EBI_POLARITY_ARDYPOL_DEFAULT (_EBI_POLARITY_ARDYPOL_DEFAULT << 4) 08616 #define EBI_POLARITY_ARDYPOL_ACTIVELOW (_EBI_POLARITY_ARDYPOL_ACTIVELOW << 4) 08617 #define EBI_POLARITY_ARDYPOL_ACTIVEHIGH (_EBI_POLARITY_ARDYPOL_ACTIVEHIGH << 4) 08619 /* Bit fields for EBI ROUTE */ 08620 #define _EBI_ROUTE_RESETVALUE 0x00000000UL 08621 #define _EBI_ROUTE_MASK 0x0000007FUL 08622 #define EBI_ROUTE_EBIPEN (0x1UL << 0) 08623 #define _EBI_ROUTE_EBIPEN_SHIFT 0 08624 #define _EBI_ROUTE_EBIPEN_MASK 0x1UL 08625 #define _EBI_ROUTE_EBIPEN_DEFAULT 0x00000000UL 08626 #define EBI_ROUTE_EBIPEN_DEFAULT (_EBI_ROUTE_EBIPEN_DEFAULT << 0) 08627 #define EBI_ROUTE_CS0PEN (0x1UL << 1) 08628 #define _EBI_ROUTE_CS0PEN_SHIFT 1 08629 #define _EBI_ROUTE_CS0PEN_MASK 0x2UL 08630 #define _EBI_ROUTE_CS0PEN_DEFAULT 0x00000000UL 08631 #define EBI_ROUTE_CS0PEN_DEFAULT (_EBI_ROUTE_CS0PEN_DEFAULT << 1) 08632 #define EBI_ROUTE_CS1PEN (0x1UL << 2) 08633 #define _EBI_ROUTE_CS1PEN_SHIFT 2 08634 #define _EBI_ROUTE_CS1PEN_MASK 0x4UL 08635 #define _EBI_ROUTE_CS1PEN_DEFAULT 0x00000000UL 08636 #define EBI_ROUTE_CS1PEN_DEFAULT (_EBI_ROUTE_CS1PEN_DEFAULT << 2) 08637 #define EBI_ROUTE_CS2PEN (0x1UL << 3) 08638 #define _EBI_ROUTE_CS2PEN_SHIFT 3 08639 #define _EBI_ROUTE_CS2PEN_MASK 0x8UL 08640 #define _EBI_ROUTE_CS2PEN_DEFAULT 0x00000000UL 08641 #define EBI_ROUTE_CS2PEN_DEFAULT (_EBI_ROUTE_CS2PEN_DEFAULT << 3) 08642 #define EBI_ROUTE_CS3PEN (0x1UL << 4) 08643 #define _EBI_ROUTE_CS3PEN_SHIFT 4 08644 #define _EBI_ROUTE_CS3PEN_MASK 0x10UL 08645 #define _EBI_ROUTE_CS3PEN_DEFAULT 0x00000000UL 08646 #define EBI_ROUTE_CS3PEN_DEFAULT (_EBI_ROUTE_CS3PEN_DEFAULT << 4) 08647 #define EBI_ROUTE_ALEPEN (0x1UL << 5) 08648 #define _EBI_ROUTE_ALEPEN_SHIFT 5 08649 #define _EBI_ROUTE_ALEPEN_MASK 0x20UL 08650 #define _EBI_ROUTE_ALEPEN_DEFAULT 0x00000000UL 08651 #define EBI_ROUTE_ALEPEN_DEFAULT (_EBI_ROUTE_ALEPEN_DEFAULT << 5) 08652 #define EBI_ROUTE_ARDYPEN (0x1UL << 6) 08653 #define _EBI_ROUTE_ARDYPEN_SHIFT 6 08654 #define _EBI_ROUTE_ARDYPEN_MASK 0x40UL 08655 #define _EBI_ROUTE_ARDYPEN_DEFAULT 0x00000000UL 08656 #define EBI_ROUTE_ARDYPEN_DEFAULT (_EBI_ROUTE_ARDYPEN_DEFAULT << 6) 08662 /**************************************************************************/ 08667 /* Bit fields for GPIO P_CTRL */ 08668 #define _GPIO_P_CTRL_RESETVALUE 0x00000000UL 08669 #define _GPIO_P_CTRL_MASK 0x00000003UL 08670 #define _GPIO_P_CTRL_DRIVEMODE_SHIFT 0 08671 #define _GPIO_P_CTRL_DRIVEMODE_MASK 0x3UL 08672 #define _GPIO_P_CTRL_DRIVEMODE_DEFAULT 0x00000000UL 08673 #define _GPIO_P_CTRL_DRIVEMODE_STANDARD 0x00000000UL 08674 #define _GPIO_P_CTRL_DRIVEMODE_LOWEST 0x00000001UL 08675 #define _GPIO_P_CTRL_DRIVEMODE_HIGH 0x00000002UL 08676 #define _GPIO_P_CTRL_DRIVEMODE_LOW 0x00000003UL 08677 #define GPIO_P_CTRL_DRIVEMODE_DEFAULT (_GPIO_P_CTRL_DRIVEMODE_DEFAULT << 0) 08678 #define GPIO_P_CTRL_DRIVEMODE_STANDARD (_GPIO_P_CTRL_DRIVEMODE_STANDARD << 0) 08679 #define GPIO_P_CTRL_DRIVEMODE_LOWEST (_GPIO_P_CTRL_DRIVEMODE_LOWEST << 0) 08680 #define GPIO_P_CTRL_DRIVEMODE_HIGH (_GPIO_P_CTRL_DRIVEMODE_HIGH << 0) 08681 #define GPIO_P_CTRL_DRIVEMODE_LOW (_GPIO_P_CTRL_DRIVEMODE_LOW << 0) 08683 /* Bit fields for GPIO P_MODEL */ 08684 #define _GPIO_P_MODEL_RESETVALUE 0x00000000UL 08685 #define _GPIO_P_MODEL_MASK 0xFFFFFFFFUL 08686 #define _GPIO_P_MODEL_MODE0_SHIFT 0 08687 #define _GPIO_P_MODEL_MODE0_MASK 0xFUL 08688 #define _GPIO_P_MODEL_MODE0_DEFAULT 0x00000000UL 08689 #define _GPIO_P_MODEL_MODE0_DISABLED 0x00000000UL 08690 #define _GPIO_P_MODEL_MODE0_INPUT 0x00000001UL 08691 #define _GPIO_P_MODEL_MODE0_INPUTPULL 0x00000002UL 08692 #define _GPIO_P_MODEL_MODE0_INPUTPULLFILTER 0x00000003UL 08693 #define _GPIO_P_MODEL_MODE0_PUSHPULL 0x00000004UL 08694 #define _GPIO_P_MODEL_MODE0_PUSHPULLDRIVE 0x00000005UL 08695 #define _GPIO_P_MODEL_MODE0_WIREDOR 0x00000006UL 08696 #define _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN 0x00000007UL 08697 #define _GPIO_P_MODEL_MODE0_WIREDAND 0x00000008UL 08698 #define _GPIO_P_MODEL_MODE0_WIREDANDFILTER 0x00000009UL 08699 #define _GPIO_P_MODEL_MODE0_WIREDANDPULLUP 0x0000000AUL 08700 #define _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL 08701 #define _GPIO_P_MODEL_MODE0_WIREDANDDRIVE 0x0000000CUL 08702 #define _GPIO_P_MODEL_MODE0_WIREDANDDRIVEFILTER 0x0000000DUL 08703 #define _GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUP 0x0000000EUL 08704 #define _GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL 08705 #define GPIO_P_MODEL_MODE0_DEFAULT (_GPIO_P_MODEL_MODE0_DEFAULT << 0) 08706 #define GPIO_P_MODEL_MODE0_DISABLED (_GPIO_P_MODEL_MODE0_DISABLED << 0) 08707 #define GPIO_P_MODEL_MODE0_INPUT (_GPIO_P_MODEL_MODE0_INPUT << 0) 08708 #define GPIO_P_MODEL_MODE0_INPUTPULL (_GPIO_P_MODEL_MODE0_INPUTPULL << 0) 08709 #define GPIO_P_MODEL_MODE0_INPUTPULLFILTER (_GPIO_P_MODEL_MODE0_INPUTPULLFILTER << 0) 08710 #define GPIO_P_MODEL_MODE0_PUSHPULL (_GPIO_P_MODEL_MODE0_PUSHPULL << 0) 08711 #define GPIO_P_MODEL_MODE0_PUSHPULLDRIVE (_GPIO_P_MODEL_MODE0_PUSHPULLDRIVE << 0) 08712 #define GPIO_P_MODEL_MODE0_WIREDOR (_GPIO_P_MODEL_MODE0_WIREDOR << 0) 08713 #define GPIO_P_MODEL_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE0_WIREDORPULLDOWN << 0) 08714 #define GPIO_P_MODEL_MODE0_WIREDAND (_GPIO_P_MODEL_MODE0_WIREDAND << 0) 08715 #define GPIO_P_MODEL_MODE0_WIREDANDFILTER (_GPIO_P_MODEL_MODE0_WIREDANDFILTER << 0) 08716 #define GPIO_P_MODEL_MODE0_WIREDANDPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDPULLUP << 0) 08717 #define GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER << 0) 08718 #define GPIO_P_MODEL_MODE0_WIREDANDDRIVE (_GPIO_P_MODEL_MODE0_WIREDANDDRIVE << 0) 08719 #define GPIO_P_MODEL_MODE0_WIREDANDDRIVEFILTER (_GPIO_P_MODEL_MODE0_WIREDANDDRIVEFILTER << 0) 08720 #define GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUP << 0) 08721 #define GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUPFILTER << 0) 08722 #define _GPIO_P_MODEL_MODE1_SHIFT 4 08723 #define _GPIO_P_MODEL_MODE1_MASK 0xF0UL 08724 #define _GPIO_P_MODEL_MODE1_DEFAULT 0x00000000UL 08725 #define _GPIO_P_MODEL_MODE1_DISABLED 0x00000000UL 08726 #define _GPIO_P_MODEL_MODE1_INPUT 0x00000001UL 08727 #define _GPIO_P_MODEL_MODE1_INPUTPULL 0x00000002UL 08728 #define _GPIO_P_MODEL_MODE1_INPUTPULLFILTER 0x00000003UL 08729 #define _GPIO_P_MODEL_MODE1_PUSHPULL 0x00000004UL 08730 #define _GPIO_P_MODEL_MODE1_PUSHPULLDRIVE 0x00000005UL 08731 #define _GPIO_P_MODEL_MODE1_WIREDOR 0x00000006UL 08732 #define _GPIO_P_MODEL_MODE1_WIREDORPULLDOWN 0x00000007UL 08733 #define _GPIO_P_MODEL_MODE1_WIREDAND 0x00000008UL 08734 #define _GPIO_P_MODEL_MODE1_WIREDANDFILTER 0x00000009UL 08735 #define _GPIO_P_MODEL_MODE1_WIREDANDPULLUP 0x0000000AUL 08736 #define _GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER 0x0000000BUL 08737 #define _GPIO_P_MODEL_MODE1_WIREDANDDRIVE 0x0000000CUL 08738 #define _GPIO_P_MODEL_MODE1_WIREDANDDRIVEFILTER 0x0000000DUL 08739 #define _GPIO_P_MODEL_MODE1_WIREDANDDRIVEPULLUP 0x0000000EUL 08740 #define _GPIO_P_MODEL_MODE1_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL 08741 #define GPIO_P_MODEL_MODE1_DEFAULT (_GPIO_P_MODEL_MODE1_DEFAULT << 4) 08742 #define GPIO_P_MODEL_MODE1_DISABLED (_GPIO_P_MODEL_MODE1_DISABLED << 4) 08743 #define GPIO_P_MODEL_MODE1_INPUT (_GPIO_P_MODEL_MODE1_INPUT << 4) 08744 #define GPIO_P_MODEL_MODE1_INPUTPULL (_GPIO_P_MODEL_MODE1_INPUTPULL << 4) 08745 #define GPIO_P_MODEL_MODE1_INPUTPULLFILTER (_GPIO_P_MODEL_MODE1_INPUTPULLFILTER << 4) 08746 #define GPIO_P_MODEL_MODE1_PUSHPULL (_GPIO_P_MODEL_MODE1_PUSHPULL << 4) 08747 #define GPIO_P_MODEL_MODE1_PUSHPULLDRIVE (_GPIO_P_MODEL_MODE1_PUSHPULLDRIVE << 4) 08748 #define GPIO_P_MODEL_MODE1_WIREDOR (_GPIO_P_MODEL_MODE1_WIREDOR << 4) 08749 #define GPIO_P_MODEL_MODE1_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE1_WIREDORPULLDOWN << 4) 08750 #define GPIO_P_MODEL_MODE1_WIREDAND (_GPIO_P_MODEL_MODE1_WIREDAND << 4) 08751 #define GPIO_P_MODEL_MODE1_WIREDANDFILTER (_GPIO_P_MODEL_MODE1_WIREDANDFILTER << 4) 08752 #define GPIO_P_MODEL_MODE1_WIREDANDPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDPULLUP << 4) 08753 #define GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER << 4) 08754 #define GPIO_P_MODEL_MODE1_WIREDANDDRIVE (_GPIO_P_MODEL_MODE1_WIREDANDDRIVE << 4) 08755 #define GPIO_P_MODEL_MODE1_WIREDANDDRIVEFILTER (_GPIO_P_MODEL_MODE1_WIREDANDDRIVEFILTER << 4) 08756 #define GPIO_P_MODEL_MODE1_WIREDANDDRIVEPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDDRIVEPULLUP << 4) 08757 #define GPIO_P_MODEL_MODE1_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDDRIVEPULLUPFILTER << 4) 08758 #define _GPIO_P_MODEL_MODE2_SHIFT 8 08759 #define _GPIO_P_MODEL_MODE2_MASK 0xF00UL 08760 #define _GPIO_P_MODEL_MODE2_DEFAULT 0x00000000UL 08761 #define _GPIO_P_MODEL_MODE2_DISABLED 0x00000000UL 08762 #define _GPIO_P_MODEL_MODE2_INPUT 0x00000001UL 08763 #define _GPIO_P_MODEL_MODE2_INPUTPULL 0x00000002UL 08764 #define _GPIO_P_MODEL_MODE2_INPUTPULLFILTER 0x00000003UL 08765 #define _GPIO_P_MODEL_MODE2_PUSHPULL 0x00000004UL 08766 #define _GPIO_P_MODEL_MODE2_PUSHPULLDRIVE 0x00000005UL 08767 #define _GPIO_P_MODEL_MODE2_WIREDOR 0x00000006UL 08768 #define _GPIO_P_MODEL_MODE2_WIREDORPULLDOWN 0x00000007UL 08769 #define _GPIO_P_MODEL_MODE2_WIREDAND 0x00000008UL 08770 #define _GPIO_P_MODEL_MODE2_WIREDANDFILTER 0x00000009UL 08771 #define _GPIO_P_MODEL_MODE2_WIREDANDPULLUP 0x0000000AUL 08772 #define _GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER 0x0000000BUL 08773 #define _GPIO_P_MODEL_MODE2_WIREDANDDRIVE 0x0000000CUL 08774 #define _GPIO_P_MODEL_MODE2_WIREDANDDRIVEFILTER 0x0000000DUL 08775 #define _GPIO_P_MODEL_MODE2_WIREDANDDRIVEPULLUP 0x0000000EUL 08776 #define _GPIO_P_MODEL_MODE2_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL 08777 #define GPIO_P_MODEL_MODE2_DEFAULT (_GPIO_P_MODEL_MODE2_DEFAULT << 8) 08778 #define GPIO_P_MODEL_MODE2_DISABLED (_GPIO_P_MODEL_MODE2_DISABLED << 8) 08779 #define GPIO_P_MODEL_MODE2_INPUT (_GPIO_P_MODEL_MODE2_INPUT << 8) 08780 #define GPIO_P_MODEL_MODE2_INPUTPULL (_GPIO_P_MODEL_MODE2_INPUTPULL << 8) 08781 #define GPIO_P_MODEL_MODE2_INPUTPULLFILTER (_GPIO_P_MODEL_MODE2_INPUTPULLFILTER << 8) 08782 #define GPIO_P_MODEL_MODE2_PUSHPULL (_GPIO_P_MODEL_MODE2_PUSHPULL << 8) 08783 #define GPIO_P_MODEL_MODE2_PUSHPULLDRIVE (_GPIO_P_MODEL_MODE2_PUSHPULLDRIVE << 8) 08784 #define GPIO_P_MODEL_MODE2_WIREDOR (_GPIO_P_MODEL_MODE2_WIREDOR << 8) 08785 #define GPIO_P_MODEL_MODE2_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE2_WIREDORPULLDOWN << 8) 08786 #define GPIO_P_MODEL_MODE2_WIREDAND (_GPIO_P_MODEL_MODE2_WIREDAND << 8) 08787 #define GPIO_P_MODEL_MODE2_WIREDANDFILTER (_GPIO_P_MODEL_MODE2_WIREDANDFILTER << 8) 08788 #define GPIO_P_MODEL_MODE2_WIREDANDPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDPULLUP << 8) 08789 #define GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER << 8) 08790 #define GPIO_P_MODEL_MODE2_WIREDANDDRIVE (_GPIO_P_MODEL_MODE2_WIREDANDDRIVE << 8) 08791 #define GPIO_P_MODEL_MODE2_WIREDANDDRIVEFILTER (_GPIO_P_MODEL_MODE2_WIREDANDDRIVEFILTER << 8) 08792 #define GPIO_P_MODEL_MODE2_WIREDANDDRIVEPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDDRIVEPULLUP << 8) 08793 #define GPIO_P_MODEL_MODE2_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDDRIVEPULLUPFILTER << 8) 08794 #define _GPIO_P_MODEL_MODE3_SHIFT 12 08795 #define _GPIO_P_MODEL_MODE3_MASK 0xF000UL 08796 #define _GPIO_P_MODEL_MODE3_DEFAULT 0x00000000UL 08797 #define _GPIO_P_MODEL_MODE3_DISABLED 0x00000000UL 08798 #define _GPIO_P_MODEL_MODE3_INPUT 0x00000001UL 08799 #define _GPIO_P_MODEL_MODE3_INPUTPULL 0x00000002UL 08800 #define _GPIO_P_MODEL_MODE3_INPUTPULLFILTER 0x00000003UL 08801 #define _GPIO_P_MODEL_MODE3_PUSHPULL 0x00000004UL 08802 #define _GPIO_P_MODEL_MODE3_PUSHPULLDRIVE 0x00000005UL 08803 #define _GPIO_P_MODEL_MODE3_WIREDOR 0x00000006UL 08804 #define _GPIO_P_MODEL_MODE3_WIREDORPULLDOWN 0x00000007UL 08805 #define _GPIO_P_MODEL_MODE3_WIREDAND 0x00000008UL 08806 #define _GPIO_P_MODEL_MODE3_WIREDANDFILTER 0x00000009UL 08807 #define _GPIO_P_MODEL_MODE3_WIREDANDPULLUP 0x0000000AUL 08808 #define _GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER 0x0000000BUL 08809 #define _GPIO_P_MODEL_MODE3_WIREDANDDRIVE 0x0000000CUL 08810 #define _GPIO_P_MODEL_MODE3_WIREDANDDRIVEFILTER 0x0000000DUL 08811 #define _GPIO_P_MODEL_MODE3_WIREDANDDRIVEPULLUP 0x0000000EUL 08812 #define _GPIO_P_MODEL_MODE3_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL 08813 #define GPIO_P_MODEL_MODE3_DEFAULT (_GPIO_P_MODEL_MODE3_DEFAULT << 12) 08814 #define GPIO_P_MODEL_MODE3_DISABLED (_GPIO_P_MODEL_MODE3_DISABLED << 12) 08815 #define GPIO_P_MODEL_MODE3_INPUT (_GPIO_P_MODEL_MODE3_INPUT << 12) 08816 #define GPIO_P_MODEL_MODE3_INPUTPULL (_GPIO_P_MODEL_MODE3_INPUTPULL << 12) 08817 #define GPIO_P_MODEL_MODE3_INPUTPULLFILTER (_GPIO_P_MODEL_MODE3_INPUTPULLFILTER << 12) 08818 #define GPIO_P_MODEL_MODE3_PUSHPULL (_GPIO_P_MODEL_MODE3_PUSHPULL << 12) 08819 #define GPIO_P_MODEL_MODE3_PUSHPULLDRIVE (_GPIO_P_MODEL_MODE3_PUSHPULLDRIVE << 12) 08820 #define GPIO_P_MODEL_MODE3_WIREDOR (_GPIO_P_MODEL_MODE3_WIREDOR << 12) 08821 #define GPIO_P_MODEL_MODE3_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE3_WIREDORPULLDOWN << 12) 08822 #define GPIO_P_MODEL_MODE3_WIREDAND (_GPIO_P_MODEL_MODE3_WIREDAND << 12) 08823 #define GPIO_P_MODEL_MODE3_WIREDANDFILTER (_GPIO_P_MODEL_MODE3_WIREDANDFILTER << 12) 08824 #define GPIO_P_MODEL_MODE3_WIREDANDPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDPULLUP << 12) 08825 #define GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER << 12) 08826 #define GPIO_P_MODEL_MODE3_WIREDANDDRIVE (_GPIO_P_MODEL_MODE3_WIREDANDDRIVE << 12) 08827 #define GPIO_P_MODEL_MODE3_WIREDANDDRIVEFILTER (_GPIO_P_MODEL_MODE3_WIREDANDDRIVEFILTER << 12) 08828 #define GPIO_P_MODEL_MODE3_WIREDANDDRIVEPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDDRIVEPULLUP << 12) 08829 #define GPIO_P_MODEL_MODE3_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDDRIVEPULLUPFILTER << 12) 08830 #define _GPIO_P_MODEL_MODE4_SHIFT 16 08831 #define _GPIO_P_MODEL_MODE4_MASK 0xF0000UL 08832 #define _GPIO_P_MODEL_MODE4_DEFAULT 0x00000000UL 08833 #define _GPIO_P_MODEL_MODE4_DISABLED 0x00000000UL 08834 #define _GPIO_P_MODEL_MODE4_INPUT 0x00000001UL 08835 #define _GPIO_P_MODEL_MODE4_INPUTPULL 0x00000002UL 08836 #define _GPIO_P_MODEL_MODE4_INPUTPULLFILTER 0x00000003UL 08837 #define _GPIO_P_MODEL_MODE4_PUSHPULL 0x00000004UL 08838 #define _GPIO_P_MODEL_MODE4_PUSHPULLDRIVE 0x00000005UL 08839 #define _GPIO_P_MODEL_MODE4_WIREDOR 0x00000006UL 08840 #define _GPIO_P_MODEL_MODE4_WIREDORPULLDOWN 0x00000007UL 08841 #define _GPIO_P_MODEL_MODE4_WIREDAND 0x00000008UL 08842 #define _GPIO_P_MODEL_MODE4_WIREDANDFILTER 0x00000009UL 08843 #define _GPIO_P_MODEL_MODE4_WIREDANDPULLUP 0x0000000AUL 08844 #define _GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER 0x0000000BUL 08845 #define _GPIO_P_MODEL_MODE4_WIREDANDDRIVE 0x0000000CUL 08846 #define _GPIO_P_MODEL_MODE4_WIREDANDDRIVEFILTER 0x0000000DUL 08847 #define _GPIO_P_MODEL_MODE4_WIREDANDDRIVEPULLUP 0x0000000EUL 08848 #define _GPIO_P_MODEL_MODE4_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL 08849 #define GPIO_P_MODEL_MODE4_DEFAULT (_GPIO_P_MODEL_MODE4_DEFAULT << 16) 08850 #define GPIO_P_MODEL_MODE4_DISABLED (_GPIO_P_MODEL_MODE4_DISABLED << 16) 08851 #define GPIO_P_MODEL_MODE4_INPUT (_GPIO_P_MODEL_MODE4_INPUT << 16) 08852 #define GPIO_P_MODEL_MODE4_INPUTPULL (_GPIO_P_MODEL_MODE4_INPUTPULL << 16) 08853 #define GPIO_P_MODEL_MODE4_INPUTPULLFILTER (_GPIO_P_MODEL_MODE4_INPUTPULLFILTER << 16) 08854 #define GPIO_P_MODEL_MODE4_PUSHPULL (_GPIO_P_MODEL_MODE4_PUSHPULL << 16) 08855 #define GPIO_P_MODEL_MODE4_PUSHPULLDRIVE (_GPIO_P_MODEL_MODE4_PUSHPULLDRIVE << 16) 08856 #define GPIO_P_MODEL_MODE4_WIREDOR (_GPIO_P_MODEL_MODE4_WIREDOR << 16) 08857 #define GPIO_P_MODEL_MODE4_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE4_WIREDORPULLDOWN << 16) 08858 #define GPIO_P_MODEL_MODE4_WIREDAND (_GPIO_P_MODEL_MODE4_WIREDAND << 16) 08859 #define GPIO_P_MODEL_MODE4_WIREDANDFILTER (_GPIO_P_MODEL_MODE4_WIREDANDFILTER << 16) 08860 #define GPIO_P_MODEL_MODE4_WIREDANDPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDPULLUP << 16) 08861 #define GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER << 16) 08862 #define GPIO_P_MODEL_MODE4_WIREDANDDRIVE (_GPIO_P_MODEL_MODE4_WIREDANDDRIVE << 16) 08863 #define GPIO_P_MODEL_MODE4_WIREDANDDRIVEFILTER (_GPIO_P_MODEL_MODE4_WIREDANDDRIVEFILTER << 16) 08864 #define GPIO_P_MODEL_MODE4_WIREDANDDRIVEPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDDRIVEPULLUP << 16) 08865 #define GPIO_P_MODEL_MODE4_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDDRIVEPULLUPFILTER << 16) 08866 #define _GPIO_P_MODEL_MODE5_SHIFT 20 08867 #define _GPIO_P_MODEL_MODE5_MASK 0xF00000UL 08868 #define _GPIO_P_MODEL_MODE5_DEFAULT 0x00000000UL 08869 #define _GPIO_P_MODEL_MODE5_DISABLED 0x00000000UL 08870 #define _GPIO_P_MODEL_MODE5_INPUT 0x00000001UL 08871 #define _GPIO_P_MODEL_MODE5_INPUTPULL 0x00000002UL 08872 #define _GPIO_P_MODEL_MODE5_INPUTPULLFILTER 0x00000003UL 08873 #define _GPIO_P_MODEL_MODE5_PUSHPULL 0x00000004UL 08874 #define _GPIO_P_MODEL_MODE5_PUSHPULLDRIVE 0x00000005UL 08875 #define _GPIO_P_MODEL_MODE5_WIREDOR 0x00000006UL 08876 #define _GPIO_P_MODEL_MODE5_WIREDORPULLDOWN 0x00000007UL 08877 #define _GPIO_P_MODEL_MODE5_WIREDAND 0x00000008UL 08878 #define _GPIO_P_MODEL_MODE5_WIREDANDFILTER 0x00000009UL 08879 #define _GPIO_P_MODEL_MODE5_WIREDANDPULLUP 0x0000000AUL 08880 #define _GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER 0x0000000BUL 08881 #define _GPIO_P_MODEL_MODE5_WIREDANDDRIVE 0x0000000CUL 08882 #define _GPIO_P_MODEL_MODE5_WIREDANDDRIVEFILTER 0x0000000DUL 08883 #define _GPIO_P_MODEL_MODE5_WIREDANDDRIVEPULLUP 0x0000000EUL 08884 #define _GPIO_P_MODEL_MODE5_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL 08885 #define GPIO_P_MODEL_MODE5_DEFAULT (_GPIO_P_MODEL_MODE5_DEFAULT << 20) 08886 #define GPIO_P_MODEL_MODE5_DISABLED (_GPIO_P_MODEL_MODE5_DISABLED << 20) 08887 #define GPIO_P_MODEL_MODE5_INPUT (_GPIO_P_MODEL_MODE5_INPUT << 20) 08888 #define GPIO_P_MODEL_MODE5_INPUTPULL (_GPIO_P_MODEL_MODE5_INPUTPULL << 20) 08889 #define GPIO_P_MODEL_MODE5_INPUTPULLFILTER (_GPIO_P_MODEL_MODE5_INPUTPULLFILTER << 20) 08890 #define GPIO_P_MODEL_MODE5_PUSHPULL (_GPIO_P_MODEL_MODE5_PUSHPULL << 20) 08891 #define GPIO_P_MODEL_MODE5_PUSHPULLDRIVE (_GPIO_P_MODEL_MODE5_PUSHPULLDRIVE << 20) 08892 #define GPIO_P_MODEL_MODE5_WIREDOR (_GPIO_P_MODEL_MODE5_WIREDOR << 20) 08893 #define GPIO_P_MODEL_MODE5_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE5_WIREDORPULLDOWN << 20) 08894 #define GPIO_P_MODEL_MODE5_WIREDAND (_GPIO_P_MODEL_MODE5_WIREDAND << 20) 08895 #define GPIO_P_MODEL_MODE5_WIREDANDFILTER (_GPIO_P_MODEL_MODE5_WIREDANDFILTER << 20) 08896 #define GPIO_P_MODEL_MODE5_WIREDANDPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDPULLUP << 20) 08897 #define GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER << 20) 08898 #define GPIO_P_MODEL_MODE5_WIREDANDDRIVE (_GPIO_P_MODEL_MODE5_WIREDANDDRIVE << 20) 08899 #define GPIO_P_MODEL_MODE5_WIREDANDDRIVEFILTER (_GPIO_P_MODEL_MODE5_WIREDANDDRIVEFILTER << 20) 08900 #define GPIO_P_MODEL_MODE5_WIREDANDDRIVEPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDDRIVEPULLUP << 20) 08901 #define GPIO_P_MODEL_MODE5_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDDRIVEPULLUPFILTER << 20) 08902 #define _GPIO_P_MODEL_MODE6_SHIFT 24 08903 #define _GPIO_P_MODEL_MODE6_MASK 0xF000000UL 08904 #define _GPIO_P_MODEL_MODE6_DEFAULT 0x00000000UL 08905 #define _GPIO_P_MODEL_MODE6_DISABLED 0x00000000UL 08906 #define _GPIO_P_MODEL_MODE6_INPUT 0x00000001UL 08907 #define _GPIO_P_MODEL_MODE6_INPUTPULL 0x00000002UL 08908 #define _GPIO_P_MODEL_MODE6_INPUTPULLFILTER 0x00000003UL 08909 #define _GPIO_P_MODEL_MODE6_PUSHPULL 0x00000004UL 08910 #define _GPIO_P_MODEL_MODE6_PUSHPULLDRIVE 0x00000005UL 08911 #define _GPIO_P_MODEL_MODE6_WIREDOR 0x00000006UL 08912 #define _GPIO_P_MODEL_MODE6_WIREDORPULLDOWN 0x00000007UL 08913 #define _GPIO_P_MODEL_MODE6_WIREDAND 0x00000008UL 08914 #define _GPIO_P_MODEL_MODE6_WIREDANDFILTER 0x00000009UL 08915 #define _GPIO_P_MODEL_MODE6_WIREDANDPULLUP 0x0000000AUL 08916 #define _GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER 0x0000000BUL 08917 #define _GPIO_P_MODEL_MODE6_WIREDANDDRIVE 0x0000000CUL 08918 #define _GPIO_P_MODEL_MODE6_WIREDANDDRIVEFILTER 0x0000000DUL 08919 #define _GPIO_P_MODEL_MODE6_WIREDANDDRIVEPULLUP 0x0000000EUL 08920 #define _GPIO_P_MODEL_MODE6_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL 08921 #define GPIO_P_MODEL_MODE6_DEFAULT (_GPIO_P_MODEL_MODE6_DEFAULT << 24) 08922 #define GPIO_P_MODEL_MODE6_DISABLED (_GPIO_P_MODEL_MODE6_DISABLED << 24) 08923 #define GPIO_P_MODEL_MODE6_INPUT (_GPIO_P_MODEL_MODE6_INPUT << 24) 08924 #define GPIO_P_MODEL_MODE6_INPUTPULL (_GPIO_P_MODEL_MODE6_INPUTPULL << 24) 08925 #define GPIO_P_MODEL_MODE6_INPUTPULLFILTER (_GPIO_P_MODEL_MODE6_INPUTPULLFILTER << 24) 08926 #define GPIO_P_MODEL_MODE6_PUSHPULL (_GPIO_P_MODEL_MODE6_PUSHPULL << 24) 08927 #define GPIO_P_MODEL_MODE6_PUSHPULLDRIVE (_GPIO_P_MODEL_MODE6_PUSHPULLDRIVE << 24) 08928 #define GPIO_P_MODEL_MODE6_WIREDOR (_GPIO_P_MODEL_MODE6_WIREDOR << 24) 08929 #define GPIO_P_MODEL_MODE6_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE6_WIREDORPULLDOWN << 24) 08930 #define GPIO_P_MODEL_MODE6_WIREDAND (_GPIO_P_MODEL_MODE6_WIREDAND << 24) 08931 #define GPIO_P_MODEL_MODE6_WIREDANDFILTER (_GPIO_P_MODEL_MODE6_WIREDANDFILTER << 24) 08932 #define GPIO_P_MODEL_MODE6_WIREDANDPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDPULLUP << 24) 08933 #define GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER << 24) 08934 #define GPIO_P_MODEL_MODE6_WIREDANDDRIVE (_GPIO_P_MODEL_MODE6_WIREDANDDRIVE << 24) 08935 #define GPIO_P_MODEL_MODE6_WIREDANDDRIVEFILTER (_GPIO_P_MODEL_MODE6_WIREDANDDRIVEFILTER << 24) 08936 #define GPIO_P_MODEL_MODE6_WIREDANDDRIVEPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDDRIVEPULLUP << 24) 08937 #define GPIO_P_MODEL_MODE6_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDDRIVEPULLUPFILTER << 24) 08938 #define _GPIO_P_MODEL_MODE7_SHIFT 28 08939 #define _GPIO_P_MODEL_MODE7_MASK 0xF0000000UL 08940 #define _GPIO_P_MODEL_MODE7_DEFAULT 0x00000000UL 08941 #define _GPIO_P_MODEL_MODE7_DISABLED 0x00000000UL 08942 #define _GPIO_P_MODEL_MODE7_INPUT 0x00000001UL 08943 #define _GPIO_P_MODEL_MODE7_INPUTPULL 0x00000002UL 08944 #define _GPIO_P_MODEL_MODE7_INPUTPULLFILTER 0x00000003UL 08945 #define _GPIO_P_MODEL_MODE7_PUSHPULL 0x00000004UL 08946 #define _GPIO_P_MODEL_MODE7_PUSHPULLDRIVE 0x00000005UL 08947 #define _GPIO_P_MODEL_MODE7_WIREDOR 0x00000006UL 08948 #define _GPIO_P_MODEL_MODE7_WIREDORPULLDOWN 0x00000007UL 08949 #define _GPIO_P_MODEL_MODE7_WIREDAND 0x00000008UL 08950 #define _GPIO_P_MODEL_MODE7_WIREDANDFILTER 0x00000009UL 08951 #define _GPIO_P_MODEL_MODE7_WIREDANDPULLUP 0x0000000AUL 08952 #define _GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER 0x0000000BUL 08953 #define _GPIO_P_MODEL_MODE7_WIREDANDDRIVE 0x0000000CUL 08954 #define _GPIO_P_MODEL_MODE7_WIREDANDDRIVEFILTER 0x0000000DUL 08955 #define _GPIO_P_MODEL_MODE7_WIREDANDDRIVEPULLUP 0x0000000EUL 08956 #define _GPIO_P_MODEL_MODE7_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL 08957 #define GPIO_P_MODEL_MODE7_DEFAULT (_GPIO_P_MODEL_MODE7_DEFAULT << 28) 08958 #define GPIO_P_MODEL_MODE7_DISABLED (_GPIO_P_MODEL_MODE7_DISABLED << 28) 08959 #define GPIO_P_MODEL_MODE7_INPUT (_GPIO_P_MODEL_MODE7_INPUT << 28) 08960 #define GPIO_P_MODEL_MODE7_INPUTPULL (_GPIO_P_MODEL_MODE7_INPUTPULL << 28) 08961 #define GPIO_P_MODEL_MODE7_INPUTPULLFILTER (_GPIO_P_MODEL_MODE7_INPUTPULLFILTER << 28) 08962 #define GPIO_P_MODEL_MODE7_PUSHPULL (_GPIO_P_MODEL_MODE7_PUSHPULL << 28) 08963 #define GPIO_P_MODEL_MODE7_PUSHPULLDRIVE (_GPIO_P_MODEL_MODE7_PUSHPULLDRIVE << 28) 08964 #define GPIO_P_MODEL_MODE7_WIREDOR (_GPIO_P_MODEL_MODE7_WIREDOR << 28) 08965 #define GPIO_P_MODEL_MODE7_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE7_WIREDORPULLDOWN << 28) 08966 #define GPIO_P_MODEL_MODE7_WIREDAND (_GPIO_P_MODEL_MODE7_WIREDAND << 28) 08967 #define GPIO_P_MODEL_MODE7_WIREDANDFILTER (_GPIO_P_MODEL_MODE7_WIREDANDFILTER << 28) 08968 #define GPIO_P_MODEL_MODE7_WIREDANDPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDPULLUP << 28) 08969 #define GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER << 28) 08970 #define GPIO_P_MODEL_MODE7_WIREDANDDRIVE (_GPIO_P_MODEL_MODE7_WIREDANDDRIVE << 28) 08971 #define GPIO_P_MODEL_MODE7_WIREDANDDRIVEFILTER (_GPIO_P_MODEL_MODE7_WIREDANDDRIVEFILTER << 28) 08972 #define GPIO_P_MODEL_MODE7_WIREDANDDRIVEPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDDRIVEPULLUP << 28) 08973 #define GPIO_P_MODEL_MODE7_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDDRIVEPULLUPFILTER << 28) 08975 /* Bit fields for GPIO P_MODEH */ 08976 #define _GPIO_P_MODEH_RESETVALUE 0x00000000UL 08977 #define _GPIO_P_MODEH_MASK 0xFFFFFFFFUL 08978 #define _GPIO_P_MODEH_MODE8_SHIFT 0 08979 #define _GPIO_P_MODEH_MODE8_MASK 0xFUL 08980 #define _GPIO_P_MODEH_MODE8_DEFAULT 0x00000000UL 08981 #define _GPIO_P_MODEH_MODE8_DISABLED 0x00000000UL 08982 #define _GPIO_P_MODEH_MODE8_INPUT 0x00000001UL 08983 #define _GPIO_P_MODEH_MODE8_INPUTPULL 0x00000002UL 08984 #define _GPIO_P_MODEH_MODE8_INPUTPULLFILTER 0x00000003UL 08985 #define _GPIO_P_MODEH_MODE8_PUSHPULL 0x00000004UL 08986 #define _GPIO_P_MODEH_MODE8_PUSHPULLDRIVE 0x00000005UL 08987 #define _GPIO_P_MODEH_MODE8_WIREDOR 0x00000006UL 08988 #define _GPIO_P_MODEH_MODE8_WIREDORPULLDOWN 0x00000007UL 08989 #define _GPIO_P_MODEH_MODE8_WIREDAND 0x00000008UL 08990 #define _GPIO_P_MODEH_MODE8_WIREDANDFILTER 0x00000009UL 08991 #define _GPIO_P_MODEH_MODE8_WIREDANDPULLUP 0x0000000AUL 08992 #define _GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER 0x0000000BUL 08993 #define _GPIO_P_MODEH_MODE8_WIREDANDDRIVE 0x0000000CUL 08994 #define _GPIO_P_MODEH_MODE8_WIREDANDDRIVEFILTER 0x0000000DUL 08995 #define _GPIO_P_MODEH_MODE8_WIREDANDDRIVEPULLUP 0x0000000EUL 08996 #define _GPIO_P_MODEH_MODE8_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL 08997 #define GPIO_P_MODEH_MODE8_DEFAULT (_GPIO_P_MODEH_MODE8_DEFAULT << 0) 08998 #define GPIO_P_MODEH_MODE8_DISABLED (_GPIO_P_MODEH_MODE8_DISABLED << 0) 08999 #define GPIO_P_MODEH_MODE8_INPUT (_GPIO_P_MODEH_MODE8_INPUT << 0) 09000 #define GPIO_P_MODEH_MODE8_INPUTPULL (_GPIO_P_MODEH_MODE8_INPUTPULL << 0) 09001 #define GPIO_P_MODEH_MODE8_INPUTPULLFILTER (_GPIO_P_MODEH_MODE8_INPUTPULLFILTER << 0) 09002 #define GPIO_P_MODEH_MODE8_PUSHPULL (_GPIO_P_MODEH_MODE8_PUSHPULL << 0) 09003 #define GPIO_P_MODEH_MODE8_PUSHPULLDRIVE (_GPIO_P_MODEH_MODE8_PUSHPULLDRIVE << 0) 09004 #define GPIO_P_MODEH_MODE8_WIREDOR (_GPIO_P_MODEH_MODE8_WIREDOR << 0) 09005 #define GPIO_P_MODEH_MODE8_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE8_WIREDORPULLDOWN << 0) 09006 #define GPIO_P_MODEH_MODE8_WIREDAND (_GPIO_P_MODEH_MODE8_WIREDAND << 0) 09007 #define GPIO_P_MODEH_MODE8_WIREDANDFILTER (_GPIO_P_MODEH_MODE8_WIREDANDFILTER << 0) 09008 #define GPIO_P_MODEH_MODE8_WIREDANDPULLUP (_GPIO_P_MODEH_MODE8_WIREDANDPULLUP << 0) 09009 #define GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER << 0) 09010 #define GPIO_P_MODEH_MODE8_WIREDANDDRIVE (_GPIO_P_MODEH_MODE8_WIREDANDDRIVE << 0) 09011 #define GPIO_P_MODEH_MODE8_WIREDANDDRIVEFILTER (_GPIO_P_MODEH_MODE8_WIREDANDDRIVEFILTER << 0) 09012 #define GPIO_P_MODEH_MODE8_WIREDANDDRIVEPULLUP (_GPIO_P_MODEH_MODE8_WIREDANDDRIVEPULLUP << 0) 09013 #define GPIO_P_MODEH_MODE8_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEH_MODE8_WIREDANDDRIVEPULLUPFILTER << 0) 09014 #define _GPIO_P_MODEH_MODE9_SHIFT 4 09015 #define _GPIO_P_MODEH_MODE9_MASK 0xF0UL 09016 #define _GPIO_P_MODEH_MODE9_DEFAULT 0x00000000UL 09017 #define _GPIO_P_MODEH_MODE9_DISABLED 0x00000000UL 09018 #define _GPIO_P_MODEH_MODE9_INPUT 0x00000001UL 09019 #define _GPIO_P_MODEH_MODE9_INPUTPULL 0x00000002UL 09020 #define _GPIO_P_MODEH_MODE9_INPUTPULLFILTER 0x00000003UL 09021 #define _GPIO_P_MODEH_MODE9_PUSHPULL 0x00000004UL 09022 #define _GPIO_P_MODEH_MODE9_PUSHPULLDRIVE 0x00000005UL 09023 #define _GPIO_P_MODEH_MODE9_WIREDOR 0x00000006UL 09024 #define _GPIO_P_MODEH_MODE9_WIREDORPULLDOWN 0x00000007UL 09025 #define _GPIO_P_MODEH_MODE9_WIREDAND 0x00000008UL 09026 #define _GPIO_P_MODEH_MODE9_WIREDANDFILTER 0x00000009UL 09027 #define _GPIO_P_MODEH_MODE9_WIREDANDPULLUP 0x0000000AUL 09028 #define _GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER 0x0000000BUL 09029 #define _GPIO_P_MODEH_MODE9_WIREDANDDRIVE 0x0000000CUL 09030 #define _GPIO_P_MODEH_MODE9_WIREDANDDRIVEFILTER 0x0000000DUL 09031 #define _GPIO_P_MODEH_MODE9_WIREDANDDRIVEPULLUP 0x0000000EUL 09032 #define _GPIO_P_MODEH_MODE9_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL 09033 #define GPIO_P_MODEH_MODE9_DEFAULT (_GPIO_P_MODEH_MODE9_DEFAULT << 4) 09034 #define GPIO_P_MODEH_MODE9_DISABLED (_GPIO_P_MODEH_MODE9_DISABLED << 4) 09035 #define GPIO_P_MODEH_MODE9_INPUT (_GPIO_P_MODEH_MODE9_INPUT << 4) 09036 #define GPIO_P_MODEH_MODE9_INPUTPULL (_GPIO_P_MODEH_MODE9_INPUTPULL << 4) 09037 #define GPIO_P_MODEH_MODE9_INPUTPULLFILTER (_GPIO_P_MODEH_MODE9_INPUTPULLFILTER << 4) 09038 #define GPIO_P_MODEH_MODE9_PUSHPULL (_GPIO_P_MODEH_MODE9_PUSHPULL << 4) 09039 #define GPIO_P_MODEH_MODE9_PUSHPULLDRIVE (_GPIO_P_MODEH_MODE9_PUSHPULLDRIVE << 4) 09040 #define GPIO_P_MODEH_MODE9_WIREDOR (_GPIO_P_MODEH_MODE9_WIREDOR << 4) 09041 #define GPIO_P_MODEH_MODE9_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE9_WIREDORPULLDOWN << 4) 09042 #define GPIO_P_MODEH_MODE9_WIREDAND (_GPIO_P_MODEH_MODE9_WIREDAND << 4) 09043 #define GPIO_P_MODEH_MODE9_WIREDANDFILTER (_GPIO_P_MODEH_MODE9_WIREDANDFILTER << 4) 09044 #define GPIO_P_MODEH_MODE9_WIREDANDPULLUP (_GPIO_P_MODEH_MODE9_WIREDANDPULLUP << 4) 09045 #define GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER << 4) 09046 #define GPIO_P_MODEH_MODE9_WIREDANDDRIVE (_GPIO_P_MODEH_MODE9_WIREDANDDRIVE << 4) 09047 #define GPIO_P_MODEH_MODE9_WIREDANDDRIVEFILTER (_GPIO_P_MODEH_MODE9_WIREDANDDRIVEFILTER << 4) 09048 #define GPIO_P_MODEH_MODE9_WIREDANDDRIVEPULLUP (_GPIO_P_MODEH_MODE9_WIREDANDDRIVEPULLUP << 4) 09049 #define GPIO_P_MODEH_MODE9_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEH_MODE9_WIREDANDDRIVEPULLUPFILTER << 4) 09050 #define _GPIO_P_MODEH_MODE10_SHIFT 8 09051 #define _GPIO_P_MODEH_MODE10_MASK 0xF00UL 09052 #define _GPIO_P_MODEH_MODE10_DEFAULT 0x00000000UL 09053 #define _GPIO_P_MODEH_MODE10_DISABLED 0x00000000UL 09054 #define _GPIO_P_MODEH_MODE10_INPUT 0x00000001UL 09055 #define _GPIO_P_MODEH_MODE10_INPUTPULL 0x00000002UL 09056 #define _GPIO_P_MODEH_MODE10_INPUTPULLFILTER 0x00000003UL 09057 #define _GPIO_P_MODEH_MODE10_PUSHPULL 0x00000004UL 09058 #define _GPIO_P_MODEH_MODE10_PUSHPULLDRIVE 0x00000005UL 09059 #define _GPIO_P_MODEH_MODE10_WIREDOR 0x00000006UL 09060 #define _GPIO_P_MODEH_MODE10_WIREDORPULLDOWN 0x00000007UL 09061 #define _GPIO_P_MODEH_MODE10_WIREDAND 0x00000008UL 09062 #define _GPIO_P_MODEH_MODE10_WIREDANDFILTER 0x00000009UL 09063 #define _GPIO_P_MODEH_MODE10_WIREDANDPULLUP 0x0000000AUL 09064 #define _GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER 0x0000000BUL 09065 #define _GPIO_P_MODEH_MODE10_WIREDANDDRIVE 0x0000000CUL 09066 #define _GPIO_P_MODEH_MODE10_WIREDANDDRIVEFILTER 0x0000000DUL 09067 #define _GPIO_P_MODEH_MODE10_WIREDANDDRIVEPULLUP 0x0000000EUL 09068 #define _GPIO_P_MODEH_MODE10_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL 09069 #define GPIO_P_MODEH_MODE10_DEFAULT (_GPIO_P_MODEH_MODE10_DEFAULT << 8) 09070 #define GPIO_P_MODEH_MODE10_DISABLED (_GPIO_P_MODEH_MODE10_DISABLED << 8) 09071 #define GPIO_P_MODEH_MODE10_INPUT (_GPIO_P_MODEH_MODE10_INPUT << 8) 09072 #define GPIO_P_MODEH_MODE10_INPUTPULL (_GPIO_P_MODEH_MODE10_INPUTPULL << 8) 09073 #define GPIO_P_MODEH_MODE10_INPUTPULLFILTER (_GPIO_P_MODEH_MODE10_INPUTPULLFILTER << 8) 09074 #define GPIO_P_MODEH_MODE10_PUSHPULL (_GPIO_P_MODEH_MODE10_PUSHPULL << 8) 09075 #define GPIO_P_MODEH_MODE10_PUSHPULLDRIVE (_GPIO_P_MODEH_MODE10_PUSHPULLDRIVE << 8) 09076 #define GPIO_P_MODEH_MODE10_WIREDOR (_GPIO_P_MODEH_MODE10_WIREDOR << 8) 09077 #define GPIO_P_MODEH_MODE10_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE10_WIREDORPULLDOWN << 8) 09078 #define GPIO_P_MODEH_MODE10_WIREDAND (_GPIO_P_MODEH_MODE10_WIREDAND << 8) 09079 #define GPIO_P_MODEH_MODE10_WIREDANDFILTER (_GPIO_P_MODEH_MODE10_WIREDANDFILTER << 8) 09080 #define GPIO_P_MODEH_MODE10_WIREDANDPULLUP (_GPIO_P_MODEH_MODE10_WIREDANDPULLUP << 8) 09081 #define GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER << 8) 09082 #define GPIO_P_MODEH_MODE10_WIREDANDDRIVE (_GPIO_P_MODEH_MODE10_WIREDANDDRIVE << 8) 09083 #define GPIO_P_MODEH_MODE10_WIREDANDDRIVEFILTER (_GPIO_P_MODEH_MODE10_WIREDANDDRIVEFILTER << 8) 09084 #define GPIO_P_MODEH_MODE10_WIREDANDDRIVEPULLUP (_GPIO_P_MODEH_MODE10_WIREDANDDRIVEPULLUP << 8) 09085 #define GPIO_P_MODEH_MODE10_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEH_MODE10_WIREDANDDRIVEPULLUPFILTER << 8) 09086 #define _GPIO_P_MODEH_MODE11_SHIFT 12 09087 #define _GPIO_P_MODEH_MODE11_MASK 0xF000UL 09088 #define _GPIO_P_MODEH_MODE11_DEFAULT 0x00000000UL 09089 #define _GPIO_P_MODEH_MODE11_DISABLED 0x00000000UL 09090 #define _GPIO_P_MODEH_MODE11_INPUT 0x00000001UL 09091 #define _GPIO_P_MODEH_MODE11_INPUTPULL 0x00000002UL 09092 #define _GPIO_P_MODEH_MODE11_INPUTPULLFILTER 0x00000003UL 09093 #define _GPIO_P_MODEH_MODE11_PUSHPULL 0x00000004UL 09094 #define _GPIO_P_MODEH_MODE11_PUSHPULLDRIVE 0x00000005UL 09095 #define _GPIO_P_MODEH_MODE11_WIREDOR 0x00000006UL 09096 #define _GPIO_P_MODEH_MODE11_WIREDORPULLDOWN 0x00000007UL 09097 #define _GPIO_P_MODEH_MODE11_WIREDAND 0x00000008UL 09098 #define _GPIO_P_MODEH_MODE11_WIREDANDFILTER 0x00000009UL 09099 #define _GPIO_P_MODEH_MODE11_WIREDANDPULLUP 0x0000000AUL 09100 #define _GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER 0x0000000BUL 09101 #define _GPIO_P_MODEH_MODE11_WIREDANDDRIVE 0x0000000CUL 09102 #define _GPIO_P_MODEH_MODE11_WIREDANDDRIVEFILTER 0x0000000DUL 09103 #define _GPIO_P_MODEH_MODE11_WIREDANDDRIVEPULLUP 0x0000000EUL 09104 #define _GPIO_P_MODEH_MODE11_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL 09105 #define GPIO_P_MODEH_MODE11_DEFAULT (_GPIO_P_MODEH_MODE11_DEFAULT << 12) 09106 #define GPIO_P_MODEH_MODE11_DISABLED (_GPIO_P_MODEH_MODE11_DISABLED << 12) 09107 #define GPIO_P_MODEH_MODE11_INPUT (_GPIO_P_MODEH_MODE11_INPUT << 12) 09108 #define GPIO_P_MODEH_MODE11_INPUTPULL (_GPIO_P_MODEH_MODE11_INPUTPULL << 12) 09109 #define GPIO_P_MODEH_MODE11_INPUTPULLFILTER (_GPIO_P_MODEH_MODE11_INPUTPULLFILTER << 12) 09110 #define GPIO_P_MODEH_MODE11_PUSHPULL (_GPIO_P_MODEH_MODE11_PUSHPULL << 12) 09111 #define GPIO_P_MODEH_MODE11_PUSHPULLDRIVE (_GPIO_P_MODEH_MODE11_PUSHPULLDRIVE << 12) 09112 #define GPIO_P_MODEH_MODE11_WIREDOR (_GPIO_P_MODEH_MODE11_WIREDOR << 12) 09113 #define GPIO_P_MODEH_MODE11_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE11_WIREDORPULLDOWN << 12) 09114 #define GPIO_P_MODEH_MODE11_WIREDAND (_GPIO_P_MODEH_MODE11_WIREDAND << 12) 09115 #define GPIO_P_MODEH_MODE11_WIREDANDFILTER (_GPIO_P_MODEH_MODE11_WIREDANDFILTER << 12) 09116 #define GPIO_P_MODEH_MODE11_WIREDANDPULLUP (_GPIO_P_MODEH_MODE11_WIREDANDPULLUP << 12) 09117 #define GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER << 12) 09118 #define GPIO_P_MODEH_MODE11_WIREDANDDRIVE (_GPIO_P_MODEH_MODE11_WIREDANDDRIVE << 12) 09119 #define GPIO_P_MODEH_MODE11_WIREDANDDRIVEFILTER (_GPIO_P_MODEH_MODE11_WIREDANDDRIVEFILTER << 12) 09120 #define GPIO_P_MODEH_MODE11_WIREDANDDRIVEPULLUP (_GPIO_P_MODEH_MODE11_WIREDANDDRIVEPULLUP << 12) 09121 #define GPIO_P_MODEH_MODE11_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEH_MODE11_WIREDANDDRIVEPULLUPFILTER << 12) 09122 #define _GPIO_P_MODEH_MODE12_SHIFT 16 09123 #define _GPIO_P_MODEH_MODE12_MASK 0xF0000UL 09124 #define _GPIO_P_MODEH_MODE12_DEFAULT 0x00000000UL 09125 #define _GPIO_P_MODEH_MODE12_DISABLED 0x00000000UL 09126 #define _GPIO_P_MODEH_MODE12_INPUT 0x00000001UL 09127 #define _GPIO_P_MODEH_MODE12_INPUTPULL 0x00000002UL 09128 #define _GPIO_P_MODEH_MODE12_INPUTPULLFILTER 0x00000003UL 09129 #define _GPIO_P_MODEH_MODE12_PUSHPULL 0x00000004UL 09130 #define _GPIO_P_MODEH_MODE12_PUSHPULLDRIVE 0x00000005UL 09131 #define _GPIO_P_MODEH_MODE12_WIREDOR 0x00000006UL 09132 #define _GPIO_P_MODEH_MODE12_WIREDORPULLDOWN 0x00000007UL 09133 #define _GPIO_P_MODEH_MODE12_WIREDAND 0x00000008UL 09134 #define _GPIO_P_MODEH_MODE12_WIREDANDFILTER 0x00000009UL 09135 #define _GPIO_P_MODEH_MODE12_WIREDANDPULLUP 0x0000000AUL 09136 #define _GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER 0x0000000BUL 09137 #define _GPIO_P_MODEH_MODE12_WIREDANDDRIVE 0x0000000CUL 09138 #define _GPIO_P_MODEH_MODE12_WIREDANDDRIVEFILTER 0x0000000DUL 09139 #define _GPIO_P_MODEH_MODE12_WIREDANDDRIVEPULLUP 0x0000000EUL 09140 #define _GPIO_P_MODEH_MODE12_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL 09141 #define GPIO_P_MODEH_MODE12_DEFAULT (_GPIO_P_MODEH_MODE12_DEFAULT << 16) 09142 #define GPIO_P_MODEH_MODE12_DISABLED (_GPIO_P_MODEH_MODE12_DISABLED << 16) 09143 #define GPIO_P_MODEH_MODE12_INPUT (_GPIO_P_MODEH_MODE12_INPUT << 16) 09144 #define GPIO_P_MODEH_MODE12_INPUTPULL (_GPIO_P_MODEH_MODE12_INPUTPULL << 16) 09145 #define GPIO_P_MODEH_MODE12_INPUTPULLFILTER (_GPIO_P_MODEH_MODE12_INPUTPULLFILTER << 16) 09146 #define GPIO_P_MODEH_MODE12_PUSHPULL (_GPIO_P_MODEH_MODE12_PUSHPULL << 16) 09147 #define GPIO_P_MODEH_MODE12_PUSHPULLDRIVE (_GPIO_P_MODEH_MODE12_PUSHPULLDRIVE << 16) 09148 #define GPIO_P_MODEH_MODE12_WIREDOR (_GPIO_P_MODEH_MODE12_WIREDOR << 16) 09149 #define GPIO_P_MODEH_MODE12_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE12_WIREDORPULLDOWN << 16) 09150 #define GPIO_P_MODEH_MODE12_WIREDAND (_GPIO_P_MODEH_MODE12_WIREDAND << 16) 09151 #define GPIO_P_MODEH_MODE12_WIREDANDFILTER (_GPIO_P_MODEH_MODE12_WIREDANDFILTER << 16) 09152 #define GPIO_P_MODEH_MODE12_WIREDANDPULLUP (_GPIO_P_MODEH_MODE12_WIREDANDPULLUP << 16) 09153 #define GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER << 16) 09154 #define GPIO_P_MODEH_MODE12_WIREDANDDRIVE (_GPIO_P_MODEH_MODE12_WIREDANDDRIVE << 16) 09155 #define GPIO_P_MODEH_MODE12_WIREDANDDRIVEFILTER (_GPIO_P_MODEH_MODE12_WIREDANDDRIVEFILTER << 16) 09156 #define GPIO_P_MODEH_MODE12_WIREDANDDRIVEPULLUP (_GPIO_P_MODEH_MODE12_WIREDANDDRIVEPULLUP << 16) 09157 #define GPIO_P_MODEH_MODE12_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEH_MODE12_WIREDANDDRIVEPULLUPFILTER << 16) 09158 #define _GPIO_P_MODEH_MODE13_SHIFT 20 09159 #define _GPIO_P_MODEH_MODE13_MASK 0xF00000UL 09160 #define _GPIO_P_MODEH_MODE13_DEFAULT 0x00000000UL 09161 #define _GPIO_P_MODEH_MODE13_DISABLED 0x00000000UL 09162 #define _GPIO_P_MODEH_MODE13_INPUT 0x00000001UL 09163 #define _GPIO_P_MODEH_MODE13_INPUTPULL 0x00000002UL 09164 #define _GPIO_P_MODEH_MODE13_INPUTPULLFILTER 0x00000003UL 09165 #define _GPIO_P_MODEH_MODE13_PUSHPULL 0x00000004UL 09166 #define _GPIO_P_MODEH_MODE13_PUSHPULLDRIVE 0x00000005UL 09167 #define _GPIO_P_MODEH_MODE13_WIREDOR 0x00000006UL 09168 #define _GPIO_P_MODEH_MODE13_WIREDORPULLDOWN 0x00000007UL 09169 #define _GPIO_P_MODEH_MODE13_WIREDAND 0x00000008UL 09170 #define _GPIO_P_MODEH_MODE13_WIREDANDFILTER 0x00000009UL 09171 #define _GPIO_P_MODEH_MODE13_WIREDANDPULLUP 0x0000000AUL 09172 #define _GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER 0x0000000BUL 09173 #define _GPIO_P_MODEH_MODE13_WIREDANDDRIVE 0x0000000CUL 09174 #define _GPIO_P_MODEH_MODE13_WIREDANDDRIVEFILTER 0x0000000DUL 09175 #define _GPIO_P_MODEH_MODE13_WIREDANDDRIVEPULLUP 0x0000000EUL 09176 #define _GPIO_P_MODEH_MODE13_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL 09177 #define GPIO_P_MODEH_MODE13_DEFAULT (_GPIO_P_MODEH_MODE13_DEFAULT << 20) 09178 #define GPIO_P_MODEH_MODE13_DISABLED (_GPIO_P_MODEH_MODE13_DISABLED << 20) 09179 #define GPIO_P_MODEH_MODE13_INPUT (_GPIO_P_MODEH_MODE13_INPUT << 20) 09180 #define GPIO_P_MODEH_MODE13_INPUTPULL (_GPIO_P_MODEH_MODE13_INPUTPULL << 20) 09181 #define GPIO_P_MODEH_MODE13_INPUTPULLFILTER (_GPIO_P_MODEH_MODE13_INPUTPULLFILTER << 20) 09182 #define GPIO_P_MODEH_MODE13_PUSHPULL (_GPIO_P_MODEH_MODE13_PUSHPULL << 20) 09183 #define GPIO_P_MODEH_MODE13_PUSHPULLDRIVE (_GPIO_P_MODEH_MODE13_PUSHPULLDRIVE << 20) 09184 #define GPIO_P_MODEH_MODE13_WIREDOR (_GPIO_P_MODEH_MODE13_WIREDOR << 20) 09185 #define GPIO_P_MODEH_MODE13_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE13_WIREDORPULLDOWN << 20) 09186 #define GPIO_P_MODEH_MODE13_WIREDAND (_GPIO_P_MODEH_MODE13_WIREDAND << 20) 09187 #define GPIO_P_MODEH_MODE13_WIREDANDFILTER (_GPIO_P_MODEH_MODE13_WIREDANDFILTER << 20) 09188 #define GPIO_P_MODEH_MODE13_WIREDANDPULLUP (_GPIO_P_MODEH_MODE13_WIREDANDPULLUP << 20) 09189 #define GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER << 20) 09190 #define GPIO_P_MODEH_MODE13_WIREDANDDRIVE (_GPIO_P_MODEH_MODE13_WIREDANDDRIVE << 20) 09191 #define GPIO_P_MODEH_MODE13_WIREDANDDRIVEFILTER (_GPIO_P_MODEH_MODE13_WIREDANDDRIVEFILTER << 20) 09192 #define GPIO_P_MODEH_MODE13_WIREDANDDRIVEPULLUP (_GPIO_P_MODEH_MODE13_WIREDANDDRIVEPULLUP << 20) 09193 #define GPIO_P_MODEH_MODE13_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEH_MODE13_WIREDANDDRIVEPULLUPFILTER << 20) 09194 #define _GPIO_P_MODEH_MODE14_SHIFT 24 09195 #define _GPIO_P_MODEH_MODE14_MASK 0xF000000UL 09196 #define _GPIO_P_MODEH_MODE14_DEFAULT 0x00000000UL 09197 #define _GPIO_P_MODEH_MODE14_DISABLED 0x00000000UL 09198 #define _GPIO_P_MODEH_MODE14_INPUT 0x00000001UL 09199 #define _GPIO_P_MODEH_MODE14_INPUTPULL 0x00000002UL 09200 #define _GPIO_P_MODEH_MODE14_INPUTPULLFILTER 0x00000003UL 09201 #define _GPIO_P_MODEH_MODE14_PUSHPULL 0x00000004UL 09202 #define _GPIO_P_MODEH_MODE14_PUSHPULLDRIVE 0x00000005UL 09203 #define _GPIO_P_MODEH_MODE14_WIREDOR 0x00000006UL 09204 #define _GPIO_P_MODEH_MODE14_WIREDORPULLDOWN 0x00000007UL 09205 #define _GPIO_P_MODEH_MODE14_WIREDAND 0x00000008UL 09206 #define _GPIO_P_MODEH_MODE14_WIREDANDFILTER 0x00000009UL 09207 #define _GPIO_P_MODEH_MODE14_WIREDANDPULLUP 0x0000000AUL 09208 #define _GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER 0x0000000BUL 09209 #define _GPIO_P_MODEH_MODE14_WIREDANDDRIVE 0x0000000CUL 09210 #define _GPIO_P_MODEH_MODE14_WIREDANDDRIVEFILTER 0x0000000DUL 09211 #define _GPIO_P_MODEH_MODE14_WIREDANDDRIVEPULLUP 0x0000000EUL 09212 #define _GPIO_P_MODEH_MODE14_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL 09213 #define GPIO_P_MODEH_MODE14_DEFAULT (_GPIO_P_MODEH_MODE14_DEFAULT << 24) 09214 #define GPIO_P_MODEH_MODE14_DISABLED (_GPIO_P_MODEH_MODE14_DISABLED << 24) 09215 #define GPIO_P_MODEH_MODE14_INPUT (_GPIO_P_MODEH_MODE14_INPUT << 24) 09216 #define GPIO_P_MODEH_MODE14_INPUTPULL (_GPIO_P_MODEH_MODE14_INPUTPULL << 24) 09217 #define GPIO_P_MODEH_MODE14_INPUTPULLFILTER (_GPIO_P_MODEH_MODE14_INPUTPULLFILTER << 24) 09218 #define GPIO_P_MODEH_MODE14_PUSHPULL (_GPIO_P_MODEH_MODE14_PUSHPULL << 24) 09219 #define GPIO_P_MODEH_MODE14_PUSHPULLDRIVE (_GPIO_P_MODEH_MODE14_PUSHPULLDRIVE << 24) 09220 #define GPIO_P_MODEH_MODE14_WIREDOR (_GPIO_P_MODEH_MODE14_WIREDOR << 24) 09221 #define GPIO_P_MODEH_MODE14_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE14_WIREDORPULLDOWN << 24) 09222 #define GPIO_P_MODEH_MODE14_WIREDAND (_GPIO_P_MODEH_MODE14_WIREDAND << 24) 09223 #define GPIO_P_MODEH_MODE14_WIREDANDFILTER (_GPIO_P_MODEH_MODE14_WIREDANDFILTER << 24) 09224 #define GPIO_P_MODEH_MODE14_WIREDANDPULLUP (_GPIO_P_MODEH_MODE14_WIREDANDPULLUP << 24) 09225 #define GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER << 24) 09226 #define GPIO_P_MODEH_MODE14_WIREDANDDRIVE (_GPIO_P_MODEH_MODE14_WIREDANDDRIVE << 24) 09227 #define GPIO_P_MODEH_MODE14_WIREDANDDRIVEFILTER (_GPIO_P_MODEH_MODE14_WIREDANDDRIVEFILTER << 24) 09228 #define GPIO_P_MODEH_MODE14_WIREDANDDRIVEPULLUP (_GPIO_P_MODEH_MODE14_WIREDANDDRIVEPULLUP << 24) 09229 #define GPIO_P_MODEH_MODE14_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEH_MODE14_WIREDANDDRIVEPULLUPFILTER << 24) 09230 #define _GPIO_P_MODEH_MODE15_SHIFT 28 09231 #define _GPIO_P_MODEH_MODE15_MASK 0xF0000000UL 09232 #define _GPIO_P_MODEH_MODE15_DEFAULT 0x00000000UL 09233 #define _GPIO_P_MODEH_MODE15_DISABLED 0x00000000UL 09234 #define _GPIO_P_MODEH_MODE15_INPUT 0x00000001UL 09235 #define _GPIO_P_MODEH_MODE15_INPUTPULL 0x00000002UL 09236 #define _GPIO_P_MODEH_MODE15_INPUTPULLFILTER 0x00000003UL 09237 #define _GPIO_P_MODEH_MODE15_PUSHPULL 0x00000004UL 09238 #define _GPIO_P_MODEH_MODE15_PUSHPULLDRIVE 0x00000005UL 09239 #define _GPIO_P_MODEH_MODE15_WIREDOR 0x00000006UL 09240 #define _GPIO_P_MODEH_MODE15_WIREDORPULLDOWN 0x00000007UL 09241 #define _GPIO_P_MODEH_MODE15_WIREDAND 0x00000008UL 09242 #define _GPIO_P_MODEH_MODE15_WIREDANDFILTER 0x00000009UL 09243 #define _GPIO_P_MODEH_MODE15_WIREDANDPULLUP 0x0000000AUL 09244 #define _GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER 0x0000000BUL 09245 #define _GPIO_P_MODEH_MODE15_WIREDANDDRIVE 0x0000000CUL 09246 #define _GPIO_P_MODEH_MODE15_WIREDANDDRIVEFILTER 0x0000000DUL 09247 #define _GPIO_P_MODEH_MODE15_WIREDANDDRIVEPULLUP 0x0000000EUL 09248 #define _GPIO_P_MODEH_MODE15_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL 09249 #define GPIO_P_MODEH_MODE15_DEFAULT (_GPIO_P_MODEH_MODE15_DEFAULT << 28) 09250 #define GPIO_P_MODEH_MODE15_DISABLED (_GPIO_P_MODEH_MODE15_DISABLED << 28) 09251 #define GPIO_P_MODEH_MODE15_INPUT (_GPIO_P_MODEH_MODE15_INPUT << 28) 09252 #define GPIO_P_MODEH_MODE15_INPUTPULL (_GPIO_P_MODEH_MODE15_INPUTPULL << 28) 09253 #define GPIO_P_MODEH_MODE15_INPUTPULLFILTER (_GPIO_P_MODEH_MODE15_INPUTPULLFILTER << 28) 09254 #define GPIO_P_MODEH_MODE15_PUSHPULL (_GPIO_P_MODEH_MODE15_PUSHPULL << 28) 09255 #define GPIO_P_MODEH_MODE15_PUSHPULLDRIVE (_GPIO_P_MODEH_MODE15_PUSHPULLDRIVE << 28) 09256 #define GPIO_P_MODEH_MODE15_WIREDOR (_GPIO_P_MODEH_MODE15_WIREDOR << 28) 09257 #define GPIO_P_MODEH_MODE15_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE15_WIREDORPULLDOWN << 28) 09258 #define GPIO_P_MODEH_MODE15_WIREDAND (_GPIO_P_MODEH_MODE15_WIREDAND << 28) 09259 #define GPIO_P_MODEH_MODE15_WIREDANDFILTER (_GPIO_P_MODEH_MODE15_WIREDANDFILTER << 28) 09260 #define GPIO_P_MODEH_MODE15_WIREDANDPULLUP (_GPIO_P_MODEH_MODE15_WIREDANDPULLUP << 28) 09261 #define GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER << 28) 09262 #define GPIO_P_MODEH_MODE15_WIREDANDDRIVE (_GPIO_P_MODEH_MODE15_WIREDANDDRIVE << 28) 09263 #define GPIO_P_MODEH_MODE15_WIREDANDDRIVEFILTER (_GPIO_P_MODEH_MODE15_WIREDANDDRIVEFILTER << 28) 09264 #define GPIO_P_MODEH_MODE15_WIREDANDDRIVEPULLUP (_GPIO_P_MODEH_MODE15_WIREDANDDRIVEPULLUP << 28) 09265 #define GPIO_P_MODEH_MODE15_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEH_MODE15_WIREDANDDRIVEPULLUPFILTER << 28) 09267 /* Bit fields for GPIO P_DOUT */ 09268 #define _GPIO_P_DOUT_RESETVALUE 0x00000000UL 09269 #define _GPIO_P_DOUT_MASK 0x0000FFFFUL 09270 #define _GPIO_P_DOUT_DOUT_SHIFT 0 09271 #define _GPIO_P_DOUT_DOUT_MASK 0xFFFFUL 09272 #define _GPIO_P_DOUT_DOUT_DEFAULT 0x00000000UL 09273 #define GPIO_P_DOUT_DOUT_DEFAULT (_GPIO_P_DOUT_DOUT_DEFAULT << 0) 09275 /* Bit fields for GPIO P_DOUTSET */ 09276 #define _GPIO_P_DOUTSET_RESETVALUE 0x00000000UL 09277 #define _GPIO_P_DOUTSET_MASK 0x0000FFFFUL 09278 #define _GPIO_P_DOUTSET_DOUTSET_SHIFT 0 09279 #define _GPIO_P_DOUTSET_DOUTSET_MASK 0xFFFFUL 09280 #define _GPIO_P_DOUTSET_DOUTSET_DEFAULT 0x00000000UL 09281 #define GPIO_P_DOUTSET_DOUTSET_DEFAULT (_GPIO_P_DOUTSET_DOUTSET_DEFAULT << 0) 09283 /* Bit fields for GPIO P_DOUTCLR */ 09284 #define _GPIO_P_DOUTCLR_RESETVALUE 0x00000000UL 09285 #define _GPIO_P_DOUTCLR_MASK 0x0000FFFFUL 09286 #define _GPIO_P_DOUTCLR_DOUTCLR_SHIFT 0 09287 #define _GPIO_P_DOUTCLR_DOUTCLR_MASK 0xFFFFUL 09288 #define _GPIO_P_DOUTCLR_DOUTCLR_DEFAULT 0x00000000UL 09289 #define GPIO_P_DOUTCLR_DOUTCLR_DEFAULT (_GPIO_P_DOUTCLR_DOUTCLR_DEFAULT << 0) 09291 /* Bit fields for GPIO P_DOUTTGL */ 09292 #define _GPIO_P_DOUTTGL_RESETVALUE 0x00000000UL 09293 #define _GPIO_P_DOUTTGL_MASK 0x0000FFFFUL 09294 #define _GPIO_P_DOUTTGL_DOUTTGL_SHIFT 0 09295 #define _GPIO_P_DOUTTGL_DOUTTGL_MASK 0xFFFFUL 09296 #define _GPIO_P_DOUTTGL_DOUTTGL_DEFAULT 0x00000000UL 09297 #define GPIO_P_DOUTTGL_DOUTTGL_DEFAULT (_GPIO_P_DOUTTGL_DOUTTGL_DEFAULT << 0) 09299 /* Bit fields for GPIO P_DIN */ 09300 #define _GPIO_P_DIN_RESETVALUE 0x00000000UL 09301 #define _GPIO_P_DIN_MASK 0x0000FFFFUL 09302 #define _GPIO_P_DIN_DIN_SHIFT 0 09303 #define _GPIO_P_DIN_DIN_MASK 0xFFFFUL 09304 #define _GPIO_P_DIN_DIN_DEFAULT 0x00000000UL 09305 #define GPIO_P_DIN_DIN_DEFAULT (_GPIO_P_DIN_DIN_DEFAULT << 0) 09307 /* Bit fields for GPIO P_PINLOCKN */ 09308 #define _GPIO_P_PINLOCKN_RESETVALUE 0x0000FFFFUL 09309 #define _GPIO_P_PINLOCKN_MASK 0x0000FFFFUL 09310 #define _GPIO_P_PINLOCKN_PINLOCKN_SHIFT 0 09311 #define _GPIO_P_PINLOCKN_PINLOCKN_MASK 0xFFFFUL 09312 #define _GPIO_P_PINLOCKN_PINLOCKN_DEFAULT 0x0000FFFFUL 09313 #define GPIO_P_PINLOCKN_PINLOCKN_DEFAULT (_GPIO_P_PINLOCKN_PINLOCKN_DEFAULT << 0) 09315 /* Bit fields for GPIO EXTIPSELL */ 09316 #define _GPIO_EXTIPSELL_RESETVALUE 0x00000000UL 09317 #define _GPIO_EXTIPSELL_MASK 0x77777777UL 09318 #define _GPIO_EXTIPSELL_EXTIPSEL0_SHIFT 0 09319 #define _GPIO_EXTIPSELL_EXTIPSEL0_MASK 0x7UL 09320 #define _GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT 0x00000000UL 09321 #define _GPIO_EXTIPSELL_EXTIPSEL0_PORTA 0x00000000UL 09322 #define _GPIO_EXTIPSELL_EXTIPSEL0_PORTB 0x00000001UL 09323 #define _GPIO_EXTIPSELL_EXTIPSEL0_PORTC 0x00000002UL 09324 #define _GPIO_EXTIPSELL_EXTIPSEL0_PORTD 0x00000003UL 09325 #define _GPIO_EXTIPSELL_EXTIPSEL0_PORTE 0x00000004UL 09326 #define _GPIO_EXTIPSELL_EXTIPSEL0_PORTF 0x00000005UL 09327 #define GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT << 0) 09328 #define GPIO_EXTIPSELL_EXTIPSEL0_PORTA (_GPIO_EXTIPSELL_EXTIPSEL0_PORTA << 0) 09329 #define GPIO_EXTIPSELL_EXTIPSEL0_PORTB (_GPIO_EXTIPSELL_EXTIPSEL0_PORTB << 0) 09330 #define GPIO_EXTIPSELL_EXTIPSEL0_PORTC (_GPIO_EXTIPSELL_EXTIPSEL0_PORTC << 0) 09331 #define GPIO_EXTIPSELL_EXTIPSEL0_PORTD (_GPIO_EXTIPSELL_EXTIPSEL0_PORTD << 0) 09332 #define GPIO_EXTIPSELL_EXTIPSEL0_PORTE (_GPIO_EXTIPSELL_EXTIPSEL0_PORTE << 0) 09333 #define GPIO_EXTIPSELL_EXTIPSEL0_PORTF (_GPIO_EXTIPSELL_EXTIPSEL0_PORTF << 0) 09334 #define _GPIO_EXTIPSELL_EXTIPSEL1_SHIFT 4 09335 #define _GPIO_EXTIPSELL_EXTIPSEL1_MASK 0x70UL 09336 #define _GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT 0x00000000UL 09337 #define _GPIO_EXTIPSELL_EXTIPSEL1_PORTA 0x00000000UL 09338 #define _GPIO_EXTIPSELL_EXTIPSEL1_PORTB 0x00000001UL 09339 #define _GPIO_EXTIPSELL_EXTIPSEL1_PORTC 0x00000002UL 09340 #define _GPIO_EXTIPSELL_EXTIPSEL1_PORTD 0x00000003UL 09341 #define _GPIO_EXTIPSELL_EXTIPSEL1_PORTE 0x00000004UL 09342 #define _GPIO_EXTIPSELL_EXTIPSEL1_PORTF 0x00000005UL 09343 #define GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT << 4) 09344 #define GPIO_EXTIPSELL_EXTIPSEL1_PORTA (_GPIO_EXTIPSELL_EXTIPSEL1_PORTA << 4) 09345 #define GPIO_EXTIPSELL_EXTIPSEL1_PORTB (_GPIO_EXTIPSELL_EXTIPSEL1_PORTB << 4) 09346 #define GPIO_EXTIPSELL_EXTIPSEL1_PORTC (_GPIO_EXTIPSELL_EXTIPSEL1_PORTC << 4) 09347 #define GPIO_EXTIPSELL_EXTIPSEL1_PORTD (_GPIO_EXTIPSELL_EXTIPSEL1_PORTD << 4) 09348 #define GPIO_EXTIPSELL_EXTIPSEL1_PORTE (_GPIO_EXTIPSELL_EXTIPSEL1_PORTE << 4) 09349 #define GPIO_EXTIPSELL_EXTIPSEL1_PORTF (_GPIO_EXTIPSELL_EXTIPSEL1_PORTF << 4) 09350 #define _GPIO_EXTIPSELL_EXTIPSEL2_SHIFT 8 09351 #define _GPIO_EXTIPSELL_EXTIPSEL2_MASK 0x700UL 09352 #define _GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT 0x00000000UL 09353 #define _GPIO_EXTIPSELL_EXTIPSEL2_PORTA 0x00000000UL 09354 #define _GPIO_EXTIPSELL_EXTIPSEL2_PORTB 0x00000001UL 09355 #define _GPIO_EXTIPSELL_EXTIPSEL2_PORTC 0x00000002UL 09356 #define _GPIO_EXTIPSELL_EXTIPSEL2_PORTD 0x00000003UL 09357 #define _GPIO_EXTIPSELL_EXTIPSEL2_PORTE 0x00000004UL 09358 #define _GPIO_EXTIPSELL_EXTIPSEL2_PORTF 0x00000005UL 09359 #define GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT << 8) 09360 #define GPIO_EXTIPSELL_EXTIPSEL2_PORTA (_GPIO_EXTIPSELL_EXTIPSEL2_PORTA << 8) 09361 #define GPIO_EXTIPSELL_EXTIPSEL2_PORTB (_GPIO_EXTIPSELL_EXTIPSEL2_PORTB << 8) 09362 #define GPIO_EXTIPSELL_EXTIPSEL2_PORTC (_GPIO_EXTIPSELL_EXTIPSEL2_PORTC << 8) 09363 #define GPIO_EXTIPSELL_EXTIPSEL2_PORTD (_GPIO_EXTIPSELL_EXTIPSEL2_PORTD << 8) 09364 #define GPIO_EXTIPSELL_EXTIPSEL2_PORTE (_GPIO_EXTIPSELL_EXTIPSEL2_PORTE << 8) 09365 #define GPIO_EXTIPSELL_EXTIPSEL2_PORTF (_GPIO_EXTIPSELL_EXTIPSEL2_PORTF << 8) 09366 #define _GPIO_EXTIPSELL_EXTIPSEL3_SHIFT 12 09367 #define _GPIO_EXTIPSELL_EXTIPSEL3_MASK 0x7000UL 09368 #define _GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT 0x00000000UL 09369 #define _GPIO_EXTIPSELL_EXTIPSEL3_PORTA 0x00000000UL 09370 #define _GPIO_EXTIPSELL_EXTIPSEL3_PORTB 0x00000001UL 09371 #define _GPIO_EXTIPSELL_EXTIPSEL3_PORTC 0x00000002UL 09372 #define _GPIO_EXTIPSELL_EXTIPSEL3_PORTD 0x00000003UL 09373 #define _GPIO_EXTIPSELL_EXTIPSEL3_PORTE 0x00000004UL 09374 #define _GPIO_EXTIPSELL_EXTIPSEL3_PORTF 0x00000005UL 09375 #define GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT << 12) 09376 #define GPIO_EXTIPSELL_EXTIPSEL3_PORTA (_GPIO_EXTIPSELL_EXTIPSEL3_PORTA << 12) 09377 #define GPIO_EXTIPSELL_EXTIPSEL3_PORTB (_GPIO_EXTIPSELL_EXTIPSEL3_PORTB << 12) 09378 #define GPIO_EXTIPSELL_EXTIPSEL3_PORTC (_GPIO_EXTIPSELL_EXTIPSEL3_PORTC << 12) 09379 #define GPIO_EXTIPSELL_EXTIPSEL3_PORTD (_GPIO_EXTIPSELL_EXTIPSEL3_PORTD << 12) 09380 #define GPIO_EXTIPSELL_EXTIPSEL3_PORTE (_GPIO_EXTIPSELL_EXTIPSEL3_PORTE << 12) 09381 #define GPIO_EXTIPSELL_EXTIPSEL3_PORTF (_GPIO_EXTIPSELL_EXTIPSEL3_PORTF << 12) 09382 #define _GPIO_EXTIPSELL_EXTIPSEL4_SHIFT 16 09383 #define _GPIO_EXTIPSELL_EXTIPSEL4_MASK 0x70000UL 09384 #define _GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT 0x00000000UL 09385 #define _GPIO_EXTIPSELL_EXTIPSEL4_PORTA 0x00000000UL 09386 #define _GPIO_EXTIPSELL_EXTIPSEL4_PORTB 0x00000001UL 09387 #define _GPIO_EXTIPSELL_EXTIPSEL4_PORTC 0x00000002UL 09388 #define _GPIO_EXTIPSELL_EXTIPSEL4_PORTD 0x00000003UL 09389 #define _GPIO_EXTIPSELL_EXTIPSEL4_PORTE 0x00000004UL 09390 #define _GPIO_EXTIPSELL_EXTIPSEL4_PORTF 0x00000005UL 09391 #define GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT << 16) 09392 #define GPIO_EXTIPSELL_EXTIPSEL4_PORTA (_GPIO_EXTIPSELL_EXTIPSEL4_PORTA << 16) 09393 #define GPIO_EXTIPSELL_EXTIPSEL4_PORTB (_GPIO_EXTIPSELL_EXTIPSEL4_PORTB << 16) 09394 #define GPIO_EXTIPSELL_EXTIPSEL4_PORTC (_GPIO_EXTIPSELL_EXTIPSEL4_PORTC << 16) 09395 #define GPIO_EXTIPSELL_EXTIPSEL4_PORTD (_GPIO_EXTIPSELL_EXTIPSEL4_PORTD << 16) 09396 #define GPIO_EXTIPSELL_EXTIPSEL4_PORTE (_GPIO_EXTIPSELL_EXTIPSEL4_PORTE << 16) 09397 #define GPIO_EXTIPSELL_EXTIPSEL4_PORTF (_GPIO_EXTIPSELL_EXTIPSEL4_PORTF << 16) 09398 #define _GPIO_EXTIPSELL_EXTIPSEL5_SHIFT 20 09399 #define _GPIO_EXTIPSELL_EXTIPSEL5_MASK 0x700000UL 09400 #define _GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT 0x00000000UL 09401 #define _GPIO_EXTIPSELL_EXTIPSEL5_PORTA 0x00000000UL 09402 #define _GPIO_EXTIPSELL_EXTIPSEL5_PORTB 0x00000001UL 09403 #define _GPIO_EXTIPSELL_EXTIPSEL5_PORTC 0x00000002UL 09404 #define _GPIO_EXTIPSELL_EXTIPSEL5_PORTD 0x00000003UL 09405 #define _GPIO_EXTIPSELL_EXTIPSEL5_PORTE 0x00000004UL 09406 #define _GPIO_EXTIPSELL_EXTIPSEL5_PORTF 0x00000005UL 09407 #define GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT << 20) 09408 #define GPIO_EXTIPSELL_EXTIPSEL5_PORTA (_GPIO_EXTIPSELL_EXTIPSEL5_PORTA << 20) 09409 #define GPIO_EXTIPSELL_EXTIPSEL5_PORTB (_GPIO_EXTIPSELL_EXTIPSEL5_PORTB << 20) 09410 #define GPIO_EXTIPSELL_EXTIPSEL5_PORTC (_GPIO_EXTIPSELL_EXTIPSEL5_PORTC << 20) 09411 #define GPIO_EXTIPSELL_EXTIPSEL5_PORTD (_GPIO_EXTIPSELL_EXTIPSEL5_PORTD << 20) 09412 #define GPIO_EXTIPSELL_EXTIPSEL5_PORTE (_GPIO_EXTIPSELL_EXTIPSEL5_PORTE << 20) 09413 #define GPIO_EXTIPSELL_EXTIPSEL5_PORTF (_GPIO_EXTIPSELL_EXTIPSEL5_PORTF << 20) 09414 #define _GPIO_EXTIPSELL_EXTIPSEL6_SHIFT 24 09415 #define _GPIO_EXTIPSELL_EXTIPSEL6_MASK 0x7000000UL 09416 #define _GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT 0x00000000UL 09417 #define _GPIO_EXTIPSELL_EXTIPSEL6_PORTA 0x00000000UL 09418 #define _GPIO_EXTIPSELL_EXTIPSEL6_PORTB 0x00000001UL 09419 #define _GPIO_EXTIPSELL_EXTIPSEL6_PORTC 0x00000002UL 09420 #define _GPIO_EXTIPSELL_EXTIPSEL6_PORTD 0x00000003UL 09421 #define _GPIO_EXTIPSELL_EXTIPSEL6_PORTE 0x00000004UL 09422 #define _GPIO_EXTIPSELL_EXTIPSEL6_PORTF 0x00000005UL 09423 #define GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT << 24) 09424 #define GPIO_EXTIPSELL_EXTIPSEL6_PORTA (_GPIO_EXTIPSELL_EXTIPSEL6_PORTA << 24) 09425 #define GPIO_EXTIPSELL_EXTIPSEL6_PORTB (_GPIO_EXTIPSELL_EXTIPSEL6_PORTB << 24) 09426 #define GPIO_EXTIPSELL_EXTIPSEL6_PORTC (_GPIO_EXTIPSELL_EXTIPSEL6_PORTC << 24) 09427 #define GPIO_EXTIPSELL_EXTIPSEL6_PORTD (_GPIO_EXTIPSELL_EXTIPSEL6_PORTD << 24) 09428 #define GPIO_EXTIPSELL_EXTIPSEL6_PORTE (_GPIO_EXTIPSELL_EXTIPSEL6_PORTE << 24) 09429 #define GPIO_EXTIPSELL_EXTIPSEL6_PORTF (_GPIO_EXTIPSELL_EXTIPSEL6_PORTF << 24) 09430 #define _GPIO_EXTIPSELL_EXTIPSEL7_SHIFT 28 09431 #define _GPIO_EXTIPSELL_EXTIPSEL7_MASK 0x70000000UL 09432 #define _GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT 0x00000000UL 09433 #define _GPIO_EXTIPSELL_EXTIPSEL7_PORTA 0x00000000UL 09434 #define _GPIO_EXTIPSELL_EXTIPSEL7_PORTB 0x00000001UL 09435 #define _GPIO_EXTIPSELL_EXTIPSEL7_PORTC 0x00000002UL 09436 #define _GPIO_EXTIPSELL_EXTIPSEL7_PORTD 0x00000003UL 09437 #define _GPIO_EXTIPSELL_EXTIPSEL7_PORTE 0x00000004UL 09438 #define _GPIO_EXTIPSELL_EXTIPSEL7_PORTF 0x00000005UL 09439 #define GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT << 28) 09440 #define GPIO_EXTIPSELL_EXTIPSEL7_PORTA (_GPIO_EXTIPSELL_EXTIPSEL7_PORTA << 28) 09441 #define GPIO_EXTIPSELL_EXTIPSEL7_PORTB (_GPIO_EXTIPSELL_EXTIPSEL7_PORTB << 28) 09442 #define GPIO_EXTIPSELL_EXTIPSEL7_PORTC (_GPIO_EXTIPSELL_EXTIPSEL7_PORTC << 28) 09443 #define GPIO_EXTIPSELL_EXTIPSEL7_PORTD (_GPIO_EXTIPSELL_EXTIPSEL7_PORTD << 28) 09444 #define GPIO_EXTIPSELL_EXTIPSEL7_PORTE (_GPIO_EXTIPSELL_EXTIPSEL7_PORTE << 28) 09445 #define GPIO_EXTIPSELL_EXTIPSEL7_PORTF (_GPIO_EXTIPSELL_EXTIPSEL7_PORTF << 28) 09447 /* Bit fields for GPIO EXTIPSELH */ 09448 #define _GPIO_EXTIPSELH_RESETVALUE 0x00000000UL 09449 #define _GPIO_EXTIPSELH_MASK 0x77777777UL 09450 #define _GPIO_EXTIPSELH_EXTIPSEL8_SHIFT 0 09451 #define _GPIO_EXTIPSELH_EXTIPSEL8_MASK 0x7UL 09452 #define _GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT 0x00000000UL 09453 #define _GPIO_EXTIPSELH_EXTIPSEL8_PORTA 0x00000000UL 09454 #define _GPIO_EXTIPSELH_EXTIPSEL8_PORTB 0x00000001UL 09455 #define _GPIO_EXTIPSELH_EXTIPSEL8_PORTC 0x00000002UL 09456 #define _GPIO_EXTIPSELH_EXTIPSEL8_PORTD 0x00000003UL 09457 #define _GPIO_EXTIPSELH_EXTIPSEL8_PORTE 0x00000004UL 09458 #define _GPIO_EXTIPSELH_EXTIPSEL8_PORTF 0x00000005UL 09459 #define GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT << 0) 09460 #define GPIO_EXTIPSELH_EXTIPSEL8_PORTA (_GPIO_EXTIPSELH_EXTIPSEL8_PORTA << 0) 09461 #define GPIO_EXTIPSELH_EXTIPSEL8_PORTB (_GPIO_EXTIPSELH_EXTIPSEL8_PORTB << 0) 09462 #define GPIO_EXTIPSELH_EXTIPSEL8_PORTC (_GPIO_EXTIPSELH_EXTIPSEL8_PORTC << 0) 09463 #define GPIO_EXTIPSELH_EXTIPSEL8_PORTD (_GPIO_EXTIPSELH_EXTIPSEL8_PORTD << 0) 09464 #define GPIO_EXTIPSELH_EXTIPSEL8_PORTE (_GPIO_EXTIPSELH_EXTIPSEL8_PORTE << 0) 09465 #define GPIO_EXTIPSELH_EXTIPSEL8_PORTF (_GPIO_EXTIPSELH_EXTIPSEL8_PORTF << 0) 09466 #define _GPIO_EXTIPSELH_EXTIPSEL9_SHIFT 4 09467 #define _GPIO_EXTIPSELH_EXTIPSEL9_MASK 0x70UL 09468 #define _GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT 0x00000000UL 09469 #define _GPIO_EXTIPSELH_EXTIPSEL9_PORTA 0x00000000UL 09470 #define _GPIO_EXTIPSELH_EXTIPSEL9_PORTB 0x00000001UL 09471 #define _GPIO_EXTIPSELH_EXTIPSEL9_PORTC 0x00000002UL 09472 #define _GPIO_EXTIPSELH_EXTIPSEL9_PORTD 0x00000003UL 09473 #define _GPIO_EXTIPSELH_EXTIPSEL9_PORTE 0x00000004UL 09474 #define _GPIO_EXTIPSELH_EXTIPSEL9_PORTF 0x00000005UL 09475 #define GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT << 4) 09476 #define GPIO_EXTIPSELH_EXTIPSEL9_PORTA (_GPIO_EXTIPSELH_EXTIPSEL9_PORTA << 4) 09477 #define GPIO_EXTIPSELH_EXTIPSEL9_PORTB (_GPIO_EXTIPSELH_EXTIPSEL9_PORTB << 4) 09478 #define GPIO_EXTIPSELH_EXTIPSEL9_PORTC (_GPIO_EXTIPSELH_EXTIPSEL9_PORTC << 4) 09479 #define GPIO_EXTIPSELH_EXTIPSEL9_PORTD (_GPIO_EXTIPSELH_EXTIPSEL9_PORTD << 4) 09480 #define GPIO_EXTIPSELH_EXTIPSEL9_PORTE (_GPIO_EXTIPSELH_EXTIPSEL9_PORTE << 4) 09481 #define GPIO_EXTIPSELH_EXTIPSEL9_PORTF (_GPIO_EXTIPSELH_EXTIPSEL9_PORTF << 4) 09482 #define _GPIO_EXTIPSELH_EXTIPSEL10_SHIFT 8 09483 #define _GPIO_EXTIPSELH_EXTIPSEL10_MASK 0x700UL 09484 #define _GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT 0x00000000UL 09485 #define _GPIO_EXTIPSELH_EXTIPSEL10_PORTA 0x00000000UL 09486 #define _GPIO_EXTIPSELH_EXTIPSEL10_PORTB 0x00000001UL 09487 #define _GPIO_EXTIPSELH_EXTIPSEL10_PORTC 0x00000002UL 09488 #define _GPIO_EXTIPSELH_EXTIPSEL10_PORTD 0x00000003UL 09489 #define _GPIO_EXTIPSELH_EXTIPSEL10_PORTE 0x00000004UL 09490 #define _GPIO_EXTIPSELH_EXTIPSEL10_PORTF 0x00000005UL 09491 #define GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT << 8) 09492 #define GPIO_EXTIPSELH_EXTIPSEL10_PORTA (_GPIO_EXTIPSELH_EXTIPSEL10_PORTA << 8) 09493 #define GPIO_EXTIPSELH_EXTIPSEL10_PORTB (_GPIO_EXTIPSELH_EXTIPSEL10_PORTB << 8) 09494 #define GPIO_EXTIPSELH_EXTIPSEL10_PORTC (_GPIO_EXTIPSELH_EXTIPSEL10_PORTC << 8) 09495 #define GPIO_EXTIPSELH_EXTIPSEL10_PORTD (_GPIO_EXTIPSELH_EXTIPSEL10_PORTD << 8) 09496 #define GPIO_EXTIPSELH_EXTIPSEL10_PORTE (_GPIO_EXTIPSELH_EXTIPSEL10_PORTE << 8) 09497 #define GPIO_EXTIPSELH_EXTIPSEL10_PORTF (_GPIO_EXTIPSELH_EXTIPSEL10_PORTF << 8) 09498 #define _GPIO_EXTIPSELH_EXTIPSEL11_SHIFT 12 09499 #define _GPIO_EXTIPSELH_EXTIPSEL11_MASK 0x7000UL 09500 #define _GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT 0x00000000UL 09501 #define _GPIO_EXTIPSELH_EXTIPSEL11_PORTA 0x00000000UL 09502 #define _GPIO_EXTIPSELH_EXTIPSEL11_PORTB 0x00000001UL 09503 #define _GPIO_EXTIPSELH_EXTIPSEL11_PORTC 0x00000002UL 09504 #define _GPIO_EXTIPSELH_EXTIPSEL11_PORTD 0x00000003UL 09505 #define _GPIO_EXTIPSELH_EXTIPSEL11_PORTE 0x00000004UL 09506 #define _GPIO_EXTIPSELH_EXTIPSEL11_PORTF 0x00000005UL 09507 #define GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT << 12) 09508 #define GPIO_EXTIPSELH_EXTIPSEL11_PORTA (_GPIO_EXTIPSELH_EXTIPSEL11_PORTA << 12) 09509 #define GPIO_EXTIPSELH_EXTIPSEL11_PORTB (_GPIO_EXTIPSELH_EXTIPSEL11_PORTB << 12) 09510 #define GPIO_EXTIPSELH_EXTIPSEL11_PORTC (_GPIO_EXTIPSELH_EXTIPSEL11_PORTC << 12) 09511 #define GPIO_EXTIPSELH_EXTIPSEL11_PORTD (_GPIO_EXTIPSELH_EXTIPSEL11_PORTD << 12) 09512 #define GPIO_EXTIPSELH_EXTIPSEL11_PORTE (_GPIO_EXTIPSELH_EXTIPSEL11_PORTE << 12) 09513 #define GPIO_EXTIPSELH_EXTIPSEL11_PORTF (_GPIO_EXTIPSELH_EXTIPSEL11_PORTF << 12) 09514 #define _GPIO_EXTIPSELH_EXTIPSEL12_SHIFT 16 09515 #define _GPIO_EXTIPSELH_EXTIPSEL12_MASK 0x70000UL 09516 #define _GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT 0x00000000UL 09517 #define _GPIO_EXTIPSELH_EXTIPSEL12_PORTA 0x00000000UL 09518 #define _GPIO_EXTIPSELH_EXTIPSEL12_PORTB 0x00000001UL 09519 #define _GPIO_EXTIPSELH_EXTIPSEL12_PORTC 0x00000002UL 09520 #define _GPIO_EXTIPSELH_EXTIPSEL12_PORTD 0x00000003UL 09521 #define _GPIO_EXTIPSELH_EXTIPSEL12_PORTE 0x00000004UL 09522 #define _GPIO_EXTIPSELH_EXTIPSEL12_PORTF 0x00000005UL 09523 #define GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT << 16) 09524 #define GPIO_EXTIPSELH_EXTIPSEL12_PORTA (_GPIO_EXTIPSELH_EXTIPSEL12_PORTA << 16) 09525 #define GPIO_EXTIPSELH_EXTIPSEL12_PORTB (_GPIO_EXTIPSELH_EXTIPSEL12_PORTB << 16) 09526 #define GPIO_EXTIPSELH_EXTIPSEL12_PORTC (_GPIO_EXTIPSELH_EXTIPSEL12_PORTC << 16) 09527 #define GPIO_EXTIPSELH_EXTIPSEL12_PORTD (_GPIO_EXTIPSELH_EXTIPSEL12_PORTD << 16) 09528 #define GPIO_EXTIPSELH_EXTIPSEL12_PORTE (_GPIO_EXTIPSELH_EXTIPSEL12_PORTE << 16) 09529 #define GPIO_EXTIPSELH_EXTIPSEL12_PORTF (_GPIO_EXTIPSELH_EXTIPSEL12_PORTF << 16) 09530 #define _GPIO_EXTIPSELH_EXTIPSEL13_SHIFT 20 09531 #define _GPIO_EXTIPSELH_EXTIPSEL13_MASK 0x700000UL 09532 #define _GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT 0x00000000UL 09533 #define _GPIO_EXTIPSELH_EXTIPSEL13_PORTA 0x00000000UL 09534 #define _GPIO_EXTIPSELH_EXTIPSEL13_PORTB 0x00000001UL 09535 #define _GPIO_EXTIPSELH_EXTIPSEL13_PORTC 0x00000002UL 09536 #define _GPIO_EXTIPSELH_EXTIPSEL13_PORTD 0x00000003UL 09537 #define _GPIO_EXTIPSELH_EXTIPSEL13_PORTE 0x00000004UL 09538 #define _GPIO_EXTIPSELH_EXTIPSEL13_PORTF 0x00000005UL 09539 #define GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT << 20) 09540 #define GPIO_EXTIPSELH_EXTIPSEL13_PORTA (_GPIO_EXTIPSELH_EXTIPSEL13_PORTA << 20) 09541 #define GPIO_EXTIPSELH_EXTIPSEL13_PORTB (_GPIO_EXTIPSELH_EXTIPSEL13_PORTB << 20) 09542 #define GPIO_EXTIPSELH_EXTIPSEL13_PORTC (_GPIO_EXTIPSELH_EXTIPSEL13_PORTC << 20) 09543 #define GPIO_EXTIPSELH_EXTIPSEL13_PORTD (_GPIO_EXTIPSELH_EXTIPSEL13_PORTD << 20) 09544 #define GPIO_EXTIPSELH_EXTIPSEL13_PORTE (_GPIO_EXTIPSELH_EXTIPSEL13_PORTE << 20) 09545 #define GPIO_EXTIPSELH_EXTIPSEL13_PORTF (_GPIO_EXTIPSELH_EXTIPSEL13_PORTF << 20) 09546 #define _GPIO_EXTIPSELH_EXTIPSEL14_SHIFT 24 09547 #define _GPIO_EXTIPSELH_EXTIPSEL14_MASK 0x7000000UL 09548 #define _GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT 0x00000000UL 09549 #define _GPIO_EXTIPSELH_EXTIPSEL14_PORTA 0x00000000UL 09550 #define _GPIO_EXTIPSELH_EXTIPSEL14_PORTB 0x00000001UL 09551 #define _GPIO_EXTIPSELH_EXTIPSEL14_PORTC 0x00000002UL 09552 #define _GPIO_EXTIPSELH_EXTIPSEL14_PORTD 0x00000003UL 09553 #define _GPIO_EXTIPSELH_EXTIPSEL14_PORTE 0x00000004UL 09554 #define _GPIO_EXTIPSELH_EXTIPSEL14_PORTF 0x00000005UL 09555 #define GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT << 24) 09556 #define GPIO_EXTIPSELH_EXTIPSEL14_PORTA (_GPIO_EXTIPSELH_EXTIPSEL14_PORTA << 24) 09557 #define GPIO_EXTIPSELH_EXTIPSEL14_PORTB (_GPIO_EXTIPSELH_EXTIPSEL14_PORTB << 24) 09558 #define GPIO_EXTIPSELH_EXTIPSEL14_PORTC (_GPIO_EXTIPSELH_EXTIPSEL14_PORTC << 24) 09559 #define GPIO_EXTIPSELH_EXTIPSEL14_PORTD (_GPIO_EXTIPSELH_EXTIPSEL14_PORTD << 24) 09560 #define GPIO_EXTIPSELH_EXTIPSEL14_PORTE (_GPIO_EXTIPSELH_EXTIPSEL14_PORTE << 24) 09561 #define GPIO_EXTIPSELH_EXTIPSEL14_PORTF (_GPIO_EXTIPSELH_EXTIPSEL14_PORTF << 24) 09562 #define _GPIO_EXTIPSELH_EXTIPSEL15_SHIFT 28 09563 #define _GPIO_EXTIPSELH_EXTIPSEL15_MASK 0x70000000UL 09564 #define _GPIO_EXTIPSELH_EXTIPSEL15_DEFAULT 0x00000000UL 09565 #define _GPIO_EXTIPSELH_EXTIPSEL15_PORTA 0x00000000UL 09566 #define _GPIO_EXTIPSELH_EXTIPSEL15_PORTB 0x00000001UL 09567 #define _GPIO_EXTIPSELH_EXTIPSEL15_PORTC 0x00000002UL 09568 #define _GPIO_EXTIPSELH_EXTIPSEL15_PORTD 0x00000003UL 09569 #define _GPIO_EXTIPSELH_EXTIPSEL15_PORTE 0x00000004UL 09570 #define _GPIO_EXTIPSELH_EXTIPSEL15_PORTF 0x00000005UL 09571 #define GPIO_EXTIPSELH_EXTIPSEL15_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL15_DEFAULT << 28) 09572 #define GPIO_EXTIPSELH_EXTIPSEL15_PORTA (_GPIO_EXTIPSELH_EXTIPSEL15_PORTA << 28) 09573 #define GPIO_EXTIPSELH_EXTIPSEL15_PORTB (_GPIO_EXTIPSELH_EXTIPSEL15_PORTB << 28) 09574 #define GPIO_EXTIPSELH_EXTIPSEL15_PORTC (_GPIO_EXTIPSELH_EXTIPSEL15_PORTC << 28) 09575 #define GPIO_EXTIPSELH_EXTIPSEL15_PORTD (_GPIO_EXTIPSELH_EXTIPSEL15_PORTD << 28) 09576 #define GPIO_EXTIPSELH_EXTIPSEL15_PORTE (_GPIO_EXTIPSELH_EXTIPSEL15_PORTE << 28) 09577 #define GPIO_EXTIPSELH_EXTIPSEL15_PORTF (_GPIO_EXTIPSELH_EXTIPSEL15_PORTF << 28) 09579 /* Bit fields for GPIO EXTIRISE */ 09580 #define _GPIO_EXTIRISE_RESETVALUE 0x00000000UL 09581 #define _GPIO_EXTIRISE_MASK 0x0000FFFFUL 09582 #define _GPIO_EXTIRISE_EXTIRISE_SHIFT 0 09583 #define _GPIO_EXTIRISE_EXTIRISE_MASK 0xFFFFUL 09584 #define _GPIO_EXTIRISE_EXTIRISE_DEFAULT 0x00000000UL 09585 #define GPIO_EXTIRISE_EXTIRISE_DEFAULT (_GPIO_EXTIRISE_EXTIRISE_DEFAULT << 0) 09587 /* Bit fields for GPIO EXTIFALL */ 09588 #define _GPIO_EXTIFALL_RESETVALUE 0x00000000UL 09589 #define _GPIO_EXTIFALL_MASK 0x0000FFFFUL 09590 #define _GPIO_EXTIFALL_EXTIFALL_SHIFT 0 09591 #define _GPIO_EXTIFALL_EXTIFALL_MASK 0xFFFFUL 09592 #define _GPIO_EXTIFALL_EXTIFALL_DEFAULT 0x00000000UL 09593 #define GPIO_EXTIFALL_EXTIFALL_DEFAULT (_GPIO_EXTIFALL_EXTIFALL_DEFAULT << 0) 09595 /* Bit fields for GPIO IEN */ 09596 #define _GPIO_IEN_RESETVALUE 0x00000000UL 09597 #define _GPIO_IEN_MASK 0x0000FFFFUL 09598 #define _GPIO_IEN_EXT_SHIFT 0 09599 #define _GPIO_IEN_EXT_MASK 0xFFFFUL 09600 #define _GPIO_IEN_EXT_DEFAULT 0x00000000UL 09601 #define GPIO_IEN_EXT_DEFAULT (_GPIO_IEN_EXT_DEFAULT << 0) 09603 /* Bit fields for GPIO IF */ 09604 #define _GPIO_IF_RESETVALUE 0x00000000UL 09605 #define _GPIO_IF_MASK 0x0000FFFFUL 09606 #define _GPIO_IF_EXT_SHIFT 0 09607 #define _GPIO_IF_EXT_MASK 0xFFFFUL 09608 #define _GPIO_IF_EXT_DEFAULT 0x00000000UL 09609 #define GPIO_IF_EXT_DEFAULT (_GPIO_IF_EXT_DEFAULT << 0) 09611 /* Bit fields for GPIO IFS */ 09612 #define _GPIO_IFS_RESETVALUE 0x00000000UL 09613 #define _GPIO_IFS_MASK 0x0000FFFFUL 09614 #define _GPIO_IFS_EXT_SHIFT 0 09615 #define _GPIO_IFS_EXT_MASK 0xFFFFUL 09616 #define _GPIO_IFS_EXT_DEFAULT 0x00000000UL 09617 #define GPIO_IFS_EXT_DEFAULT (_GPIO_IFS_EXT_DEFAULT << 0) 09619 /* Bit fields for GPIO IFC */ 09620 #define _GPIO_IFC_RESETVALUE 0x00000000UL 09621 #define _GPIO_IFC_MASK 0x0000FFFFUL 09622 #define _GPIO_IFC_EXT_SHIFT 0 09623 #define _GPIO_IFC_EXT_MASK 0xFFFFUL 09624 #define _GPIO_IFC_EXT_DEFAULT 0x00000000UL 09625 #define GPIO_IFC_EXT_DEFAULT (_GPIO_IFC_EXT_DEFAULT << 0) 09627 /* Bit fields for GPIO ROUTE */ 09628 #define _GPIO_ROUTE_RESETVALUE 0x00000003UL 09629 #define _GPIO_ROUTE_MASK 0x00000307UL 09630 #define GPIO_ROUTE_SWCLKPEN (0x1UL << 0) 09631 #define _GPIO_ROUTE_SWCLKPEN_SHIFT 0 09632 #define _GPIO_ROUTE_SWCLKPEN_MASK 0x1UL 09633 #define _GPIO_ROUTE_SWCLKPEN_DEFAULT 0x00000001UL 09634 #define GPIO_ROUTE_SWCLKPEN_DEFAULT (_GPIO_ROUTE_SWCLKPEN_DEFAULT << 0) 09635 #define GPIO_ROUTE_SWDIOPEN (0x1UL << 1) 09636 #define _GPIO_ROUTE_SWDIOPEN_SHIFT 1 09637 #define _GPIO_ROUTE_SWDIOPEN_MASK 0x2UL 09638 #define _GPIO_ROUTE_SWDIOPEN_DEFAULT 0x00000001UL 09639 #define GPIO_ROUTE_SWDIOPEN_DEFAULT (_GPIO_ROUTE_SWDIOPEN_DEFAULT << 1) 09640 #define GPIO_ROUTE_SWOPEN (0x1UL << 2) 09641 #define _GPIO_ROUTE_SWOPEN_SHIFT 2 09642 #define _GPIO_ROUTE_SWOPEN_MASK 0x4UL 09643 #define _GPIO_ROUTE_SWOPEN_DEFAULT 0x00000000UL 09644 #define GPIO_ROUTE_SWOPEN_DEFAULT (_GPIO_ROUTE_SWOPEN_DEFAULT << 2) 09645 #define _GPIO_ROUTE_SWLOCATION_SHIFT 8 09646 #define _GPIO_ROUTE_SWLOCATION_MASK 0x300UL 09647 #define _GPIO_ROUTE_SWLOCATION_DEFAULT 0x00000000UL 09648 #define _GPIO_ROUTE_SWLOCATION_LOC0 0x00000000UL 09649 #define _GPIO_ROUTE_SWLOCATION_LOC1 0x00000001UL 09650 #define _GPIO_ROUTE_SWLOCATION_LOC2 0x00000002UL 09651 #define _GPIO_ROUTE_SWLOCATION_LOC3 0x00000003UL 09652 #define GPIO_ROUTE_SWLOCATION_DEFAULT (_GPIO_ROUTE_SWLOCATION_DEFAULT << 8) 09653 #define GPIO_ROUTE_SWLOCATION_LOC0 (_GPIO_ROUTE_SWLOCATION_LOC0 << 8) 09654 #define GPIO_ROUTE_SWLOCATION_LOC1 (_GPIO_ROUTE_SWLOCATION_LOC1 << 8) 09655 #define GPIO_ROUTE_SWLOCATION_LOC2 (_GPIO_ROUTE_SWLOCATION_LOC2 << 8) 09656 #define GPIO_ROUTE_SWLOCATION_LOC3 (_GPIO_ROUTE_SWLOCATION_LOC3 << 8) 09658 /* Bit fields for GPIO INSENSE */ 09659 #define _GPIO_INSENSE_RESETVALUE 0x00000003UL 09660 #define _GPIO_INSENSE_MASK 0x00000003UL 09661 #define GPIO_INSENSE_INT (0x1UL << 0) 09662 #define _GPIO_INSENSE_INT_SHIFT 0 09663 #define _GPIO_INSENSE_INT_MASK 0x1UL 09664 #define _GPIO_INSENSE_INT_DEFAULT 0x00000001UL 09665 #define GPIO_INSENSE_INT_DEFAULT (_GPIO_INSENSE_INT_DEFAULT << 0) 09666 #define GPIO_INSENSE_PRS (0x1UL << 1) 09667 #define _GPIO_INSENSE_PRS_SHIFT 1 09668 #define _GPIO_INSENSE_PRS_MASK 0x2UL 09669 #define _GPIO_INSENSE_PRS_DEFAULT 0x00000001UL 09670 #define GPIO_INSENSE_PRS_DEFAULT (_GPIO_INSENSE_PRS_DEFAULT << 1) 09672 /* Bit fields for GPIO LOCK */ 09673 #define _GPIO_LOCK_RESETVALUE 0x00000000UL 09674 #define _GPIO_LOCK_MASK 0x0000FFFFUL 09675 #define _GPIO_LOCK_LOCKKEY_SHIFT 0 09676 #define _GPIO_LOCK_LOCKKEY_MASK 0xFFFFUL 09677 #define _GPIO_LOCK_LOCKKEY_DEFAULT 0x00000000UL 09678 #define _GPIO_LOCK_LOCKKEY_LOCK 0x00000000UL 09679 #define _GPIO_LOCK_LOCKKEY_UNLOCKED 0x00000000UL 09680 #define _GPIO_LOCK_LOCKKEY_LOCKED 0x00000001UL 09681 #define _GPIO_LOCK_LOCKKEY_UNLOCK 0x0000A534UL 09682 #define GPIO_LOCK_LOCKKEY_DEFAULT (_GPIO_LOCK_LOCKKEY_DEFAULT << 0) 09683 #define GPIO_LOCK_LOCKKEY_LOCK (_GPIO_LOCK_LOCKKEY_LOCK << 0) 09684 #define GPIO_LOCK_LOCKKEY_UNLOCKED (_GPIO_LOCK_LOCKKEY_UNLOCKED << 0) 09685 #define GPIO_LOCK_LOCKKEY_LOCKED (_GPIO_LOCK_LOCKKEY_LOCKED << 0) 09686 #define GPIO_LOCK_LOCKKEY_UNLOCK (_GPIO_LOCK_LOCKKEY_UNLOCK << 0) 09692 /**************************************************************************/ 09697 /* Bit fields for PRS SWPULSE */ 09698 #define _PRS_SWPULSE_RESETVALUE 0x00000000UL 09699 #define _PRS_SWPULSE_MASK 0x000000FFUL 09700 #define PRS_SWPULSE_CH0PULSE (0x1UL << 0) 09701 #define _PRS_SWPULSE_CH0PULSE_SHIFT 0 09702 #define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL 09703 #define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL 09704 #define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) 09705 #define PRS_SWPULSE_CH1PULSE (0x1UL << 1) 09706 #define _PRS_SWPULSE_CH1PULSE_SHIFT 1 09707 #define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL 09708 #define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL 09709 #define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) 09710 #define PRS_SWPULSE_CH2PULSE (0x1UL << 2) 09711 #define _PRS_SWPULSE_CH2PULSE_SHIFT 2 09712 #define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL 09713 #define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL 09714 #define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) 09715 #define PRS_SWPULSE_CH3PULSE (0x1UL << 3) 09716 #define _PRS_SWPULSE_CH3PULSE_SHIFT 3 09717 #define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL 09718 #define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL 09719 #define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) 09720 #define PRS_SWPULSE_CH4PULSE (0x1UL << 4) 09721 #define _PRS_SWPULSE_CH4PULSE_SHIFT 4 09722 #define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL 09723 #define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL 09724 #define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) 09725 #define PRS_SWPULSE_CH5PULSE (0x1UL << 5) 09726 #define _PRS_SWPULSE_CH5PULSE_SHIFT 5 09727 #define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL 09728 #define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL 09729 #define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) 09730 #define PRS_SWPULSE_CH6PULSE (0x1UL << 6) 09731 #define _PRS_SWPULSE_CH6PULSE_SHIFT 6 09732 #define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL 09733 #define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL 09734 #define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) 09735 #define PRS_SWPULSE_CH7PULSE (0x1UL << 7) 09736 #define _PRS_SWPULSE_CH7PULSE_SHIFT 7 09737 #define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL 09738 #define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL 09739 #define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) 09741 /* Bit fields for PRS SWLEVEL */ 09742 #define _PRS_SWLEVEL_RESETVALUE 0x00000000UL 09743 #define _PRS_SWLEVEL_MASK 0x000000FFUL 09744 #define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) 09745 #define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 09746 #define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL 09747 #define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL 09748 #define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) 09749 #define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) 09750 #define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 09751 #define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL 09752 #define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL 09753 #define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) 09754 #define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) 09755 #define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 09756 #define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL 09757 #define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL 09758 #define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) 09759 #define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) 09760 #define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 09761 #define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL 09762 #define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL 09763 #define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) 09764 #define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) 09765 #define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 09766 #define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL 09767 #define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL 09768 #define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) 09769 #define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) 09770 #define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 09771 #define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL 09772 #define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL 09773 #define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) 09774 #define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) 09775 #define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 09776 #define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL 09777 #define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL 09778 #define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) 09779 #define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) 09780 #define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 09781 #define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL 09782 #define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL 09783 #define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) 09785 /* Bit fields for PRS CH_CTRL */ 09786 #define _PRS_CH_CTRL_RESETVALUE 0x00000000UL 09787 #define _PRS_CH_CTRL_MASK 0x033F0007UL 09788 #define _PRS_CH_CTRL_SIGSEL_SHIFT 0 09789 #define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL 09790 #define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL 09791 #define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL 09792 #define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL 09793 #define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL 09794 #define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL 09795 #define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL 09796 #define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL 09797 #define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL 09798 #define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL 09799 #define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL 09800 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL 09801 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL 09802 #define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL 09803 #define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL 09804 #define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL 09805 #define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL 09806 #define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL 09807 #define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL 09808 #define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL 09809 #define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL 09810 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL 09811 #define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL 09812 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL 09813 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL 09814 #define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL 09815 #define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL 09816 #define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL 09817 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL 09818 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL 09819 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL 09820 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL 09821 #define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL 09822 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL 09823 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL 09824 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL 09825 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL 09826 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL 09827 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL 09828 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL 09829 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL 09830 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL 09831 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL 09832 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL 09833 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL 09834 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL 09835 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL 09836 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL 09837 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL 09838 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL 09839 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL 09840 #define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) 09841 #define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) 09842 #define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) 09843 #define PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0) 09844 #define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) 09845 #define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) 09846 #define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) 09847 #define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) 09848 #define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) 09849 #define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) 09850 #define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) 09851 #define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) 09852 #define PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0) 09853 #define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) 09854 #define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) 09855 #define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) 09856 #define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) 09857 #define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) 09858 #define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) 09859 #define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) 09860 #define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) 09861 #define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) 09862 #define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) 09863 #define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) 09864 #define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) 09865 #define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) 09866 #define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) 09867 #define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) 09868 #define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) 09869 #define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) 09870 #define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) 09871 #define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) 09872 #define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) 09873 #define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) 09874 #define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) 09875 #define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) 09876 #define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) 09877 #define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) 09878 #define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) 09879 #define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) 09880 #define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) 09881 #define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) 09882 #define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) 09883 #define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) 09884 #define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) 09885 #define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) 09886 #define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) 09887 #define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) 09888 #define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) 09889 #define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) 09890 #define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 09891 #define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL 09892 #define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL 09893 #define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL 09894 #define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL 09895 #define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL 09896 #define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL 09897 #define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL 09898 #define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL 09899 #define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL 09900 #define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL 09901 #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL 09902 #define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL 09903 #define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL 09904 #define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL 09905 #define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000029UL 09906 #define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL 09907 #define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL 09908 #define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) 09909 #define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) 09910 #define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) 09911 #define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16) 09912 #define PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16) 09913 #define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) 09914 #define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) 09915 #define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) 09916 #define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16) 09917 #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) 09918 #define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) 09919 #define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) 09920 #define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) 09921 #define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 16) 09922 #define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) 09923 #define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) 09924 #define _PRS_CH_CTRL_EDSEL_SHIFT 24 09925 #define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL 09926 #define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL 09927 #define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL 09928 #define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL 09929 #define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL 09930 #define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL 09931 #define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) 09932 #define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) 09933 #define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) 09934 #define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) 09935 #define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) 09941 /**************************************************************************/ 09946 /* Bit fields for DMA STATUS */ 09947 #define _DMA_STATUS_RESETVALUE 0x10070000UL 09948 #define _DMA_STATUS_MASK 0xF01F00F1UL 09949 #define DMA_STATUS_EN (0x1UL << 0) 09950 #define _DMA_STATUS_EN_SHIFT 0 09951 #define _DMA_STATUS_EN_MASK 0x1UL 09952 #define _DMA_STATUS_EN_DEFAULT 0x00000000UL 09953 #define DMA_STATUS_EN_DEFAULT (_DMA_STATUS_EN_DEFAULT << 0) 09954 #define _DMA_STATUS_STATE_SHIFT 4 09955 #define _DMA_STATUS_STATE_MASK 0xF0UL 09956 #define _DMA_STATUS_STATE_DEFAULT 0x00000000UL 09957 #define _DMA_STATUS_STATE_IDLE 0x00000000UL 09958 #define _DMA_STATUS_STATE_RDCHCTRLDATA 0x00000001UL 09959 #define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL 09960 #define _DMA_STATUS_STATE_RDDSTENDPTR 0x00000003UL 09961 #define _DMA_STATUS_STATE_RDSRCDATA 0x00000004UL 09962 #define _DMA_STATUS_STATE_WRDSTDATA 0x00000005UL 09963 #define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL 09964 #define _DMA_STATUS_STATE_WRCHCTRLDATA 0x00000007UL 09965 #define _DMA_STATUS_STATE_STALLED 0x00000008UL 09966 #define _DMA_STATUS_STATE_DONE 0x00000009UL 09967 #define _DMA_STATUS_STATE_PERSCATTRANS 0x0000000AUL 09968 #define DMA_STATUS_STATE_DEFAULT (_DMA_STATUS_STATE_DEFAULT << 4) 09969 #define DMA_STATUS_STATE_IDLE (_DMA_STATUS_STATE_IDLE << 4) 09970 #define DMA_STATUS_STATE_RDCHCTRLDATA (_DMA_STATUS_STATE_RDCHCTRLDATA << 4) 09971 #define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) 09972 #define DMA_STATUS_STATE_RDDSTENDPTR (_DMA_STATUS_STATE_RDDSTENDPTR << 4) 09973 #define DMA_STATUS_STATE_RDSRCDATA (_DMA_STATUS_STATE_RDSRCDATA << 4) 09974 #define DMA_STATUS_STATE_WRDSTDATA (_DMA_STATUS_STATE_WRDSTDATA << 4) 09975 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) 09976 #define DMA_STATUS_STATE_WRCHCTRLDATA (_DMA_STATUS_STATE_WRCHCTRLDATA << 4) 09977 #define DMA_STATUS_STATE_STALLED (_DMA_STATUS_STATE_STALLED << 4) 09978 #define DMA_STATUS_STATE_DONE (_DMA_STATUS_STATE_DONE << 4) 09979 #define DMA_STATUS_STATE_PERSCATTRANS (_DMA_STATUS_STATE_PERSCATTRANS << 4) 09980 #define _DMA_STATUS_CHNUM_SHIFT 16 09981 #define _DMA_STATUS_CHNUM_MASK 0x1F0000UL 09982 #define _DMA_STATUS_CHNUM_DEFAULT 0x00000007UL 09983 #define DMA_STATUS_CHNUM_DEFAULT (_DMA_STATUS_CHNUM_DEFAULT << 16) 09985 /* Bit fields for DMA CONFIG */ 09986 #define _DMA_CONFIG_RESETVALUE 0x00000000UL 09987 #define _DMA_CONFIG_MASK 0x00000021UL 09988 #define DMA_CONFIG_EN (0x1UL << 0) 09989 #define _DMA_CONFIG_EN_SHIFT 0 09990 #define _DMA_CONFIG_EN_MASK 0x1UL 09991 #define _DMA_CONFIG_EN_DEFAULT 0x00000000UL 09992 #define DMA_CONFIG_EN_DEFAULT (_DMA_CONFIG_EN_DEFAULT << 0) 09993 #define DMA_CONFIG_CHPROT (0x1UL << 5) 09994 #define _DMA_CONFIG_CHPROT_SHIFT 5 09995 #define _DMA_CONFIG_CHPROT_MASK 0x20UL 09996 #define _DMA_CONFIG_CHPROT_DEFAULT 0x00000000UL 09997 #define DMA_CONFIG_CHPROT_DEFAULT (_DMA_CONFIG_CHPROT_DEFAULT << 5) 09999 /* Bit fields for DMA CTRLBASE */ 10000 #define _DMA_CTRLBASE_RESETVALUE 0x00000000UL 10001 #define _DMA_CTRLBASE_MASK 0xFFFFFFFFUL 10002 #define _DMA_CTRLBASE_CTRLBASE_SHIFT 0 10003 #define _DMA_CTRLBASE_CTRLBASE_MASK 0xFFFFFFFFUL 10004 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL 10005 #define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) 10007 /* Bit fields for DMA ALTCTRLBASE */ 10008 #define _DMA_ALTCTRLBASE_RESETVALUE 0x00000080UL 10009 #define _DMA_ALTCTRLBASE_MASK 0xFFFFFFFFUL 10010 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT 0 10011 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK 0xFFFFFFFFUL 10012 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT 0x00000080UL 10013 #define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0) 10015 /* Bit fields for DMA CHWAITSTATUS */ 10016 #define _DMA_CHWAITSTATUS_RESETVALUE 0x000000FFUL 10017 #define _DMA_CHWAITSTATUS_MASK 0x000000FFUL 10018 #define DMA_CHWAITSTATUS_CH0WAITSTATUS (0x1UL << 0) 10019 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT 0 10020 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK 0x1UL 10021 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT 0x00000001UL 10022 #define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0) 10023 #define DMA_CHWAITSTATUS_CH1WAITSTATUS (0x1UL << 1) 10024 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT 1 10025 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK 0x2UL 10026 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT 0x00000001UL 10027 #define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1) 10028 #define DMA_CHWAITSTATUS_CH2WAITSTATUS (0x1UL << 2) 10029 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT 2 10030 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK 0x4UL 10031 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT 0x00000001UL 10032 #define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2) 10033 #define DMA_CHWAITSTATUS_CH3WAITSTATUS (0x1UL << 3) 10034 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT 3 10035 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK 0x8UL 10036 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT 0x00000001UL 10037 #define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3) 10038 #define DMA_CHWAITSTATUS_CH4WAITSTATUS (0x1UL << 4) 10039 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT 4 10040 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK 0x10UL 10041 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT 0x00000001UL 10042 #define DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4) 10043 #define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) 10044 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT 5 10045 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK 0x20UL 10046 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT 0x00000001UL 10047 #define DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5) 10048 #define DMA_CHWAITSTATUS_CH6WAITSTATUS (0x1UL << 6) 10049 #define _DMA_CHWAITSTATUS_CH6WAITSTATUS_SHIFT 6 10050 #define _DMA_CHWAITSTATUS_CH6WAITSTATUS_MASK 0x40UL 10051 #define _DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT 0x00000001UL 10052 #define DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT << 6) 10053 #define DMA_CHWAITSTATUS_CH7WAITSTATUS (0x1UL << 7) 10054 #define _DMA_CHWAITSTATUS_CH7WAITSTATUS_SHIFT 7 10055 #define _DMA_CHWAITSTATUS_CH7WAITSTATUS_MASK 0x80UL 10056 #define _DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT 0x00000001UL 10057 #define DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT << 7) 10059 /* Bit fields for DMA CHSWREQ */ 10060 #define _DMA_CHSWREQ_RESETVALUE 0x00000000UL 10061 #define _DMA_CHSWREQ_MASK 0x000000FFUL 10062 #define DMA_CHSWREQ_CH0SWREQ (0x1UL << 0) 10063 #define _DMA_CHSWREQ_CH0SWREQ_SHIFT 0 10064 #define _DMA_CHSWREQ_CH0SWREQ_MASK 0x1UL 10065 #define _DMA_CHSWREQ_CH0SWREQ_DEFAULT 0x00000000UL 10066 #define DMA_CHSWREQ_CH0SWREQ_DEFAULT (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0) 10067 #define DMA_CHSWREQ_CH1SWREQ (0x1UL << 1) 10068 #define _DMA_CHSWREQ_CH1SWREQ_SHIFT 1 10069 #define _DMA_CHSWREQ_CH1SWREQ_MASK 0x2UL 10070 #define _DMA_CHSWREQ_CH1SWREQ_DEFAULT 0x00000000UL 10071 #define DMA_CHSWREQ_CH1SWREQ_DEFAULT (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1) 10072 #define DMA_CHSWREQ_CH2SWREQ (0x1UL << 2) 10073 #define _DMA_CHSWREQ_CH2SWREQ_SHIFT 2 10074 #define _DMA_CHSWREQ_CH2SWREQ_MASK 0x4UL 10075 #define _DMA_CHSWREQ_CH2SWREQ_DEFAULT 0x00000000UL 10076 #define DMA_CHSWREQ_CH2SWREQ_DEFAULT (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2) 10077 #define DMA_CHSWREQ_CH3SWREQ (0x1UL << 3) 10078 #define _DMA_CHSWREQ_CH3SWREQ_SHIFT 3 10079 #define _DMA_CHSWREQ_CH3SWREQ_MASK 0x8UL 10080 #define _DMA_CHSWREQ_CH3SWREQ_DEFAULT 0x00000000UL 10081 #define DMA_CHSWREQ_CH3SWREQ_DEFAULT (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3) 10082 #define DMA_CHSWREQ_CH4SWREQ (0x1UL << 4) 10083 #define _DMA_CHSWREQ_CH4SWREQ_SHIFT 4 10084 #define _DMA_CHSWREQ_CH4SWREQ_MASK 0x10UL 10085 #define _DMA_CHSWREQ_CH4SWREQ_DEFAULT 0x00000000UL 10086 #define DMA_CHSWREQ_CH4SWREQ_DEFAULT (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4) 10087 #define DMA_CHSWREQ_CH5SWREQ (0x1UL << 5) 10088 #define _DMA_CHSWREQ_CH5SWREQ_SHIFT 5 10089 #define _DMA_CHSWREQ_CH5SWREQ_MASK 0x20UL 10090 #define _DMA_CHSWREQ_CH5SWREQ_DEFAULT 0x00000000UL 10091 #define DMA_CHSWREQ_CH5SWREQ_DEFAULT (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5) 10092 #define DMA_CHSWREQ_CH6SWREQ (0x1UL << 6) 10093 #define _DMA_CHSWREQ_CH6SWREQ_SHIFT 6 10094 #define _DMA_CHSWREQ_CH6SWREQ_MASK 0x40UL 10095 #define _DMA_CHSWREQ_CH6SWREQ_DEFAULT 0x00000000UL 10096 #define DMA_CHSWREQ_CH6SWREQ_DEFAULT (_DMA_CHSWREQ_CH6SWREQ_DEFAULT << 6) 10097 #define DMA_CHSWREQ_CH7SWREQ (0x1UL << 7) 10098 #define _DMA_CHSWREQ_CH7SWREQ_SHIFT 7 10099 #define _DMA_CHSWREQ_CH7SWREQ_MASK 0x80UL 10100 #define _DMA_CHSWREQ_CH7SWREQ_DEFAULT 0x00000000UL 10101 #define DMA_CHSWREQ_CH7SWREQ_DEFAULT (_DMA_CHSWREQ_CH7SWREQ_DEFAULT << 7) 10103 /* Bit fields for DMA CHUSEBURSTS */ 10104 #define _DMA_CHUSEBURSTS_RESETVALUE 0x00000000UL 10105 #define _DMA_CHUSEBURSTS_MASK 0x000000FFUL 10106 #define DMA_CHUSEBURSTS_CH0USEBURSTS (0x1UL << 0) 10107 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT 0 10108 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK 0x1UL 10109 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT 0x00000000UL 10110 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST 0x00000000UL 10111 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY 0x00000001UL 10112 #define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0) 10113 #define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0) 10114 #define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0) 10115 #define DMA_CHUSEBURSTS_CH1USEBURSTS (0x1UL << 1) 10116 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT 1 10117 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK 0x2UL 10118 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT 0x00000000UL 10119 #define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1) 10120 #define DMA_CHUSEBURSTS_CH2USEBURSTS (0x1UL << 2) 10121 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT 2 10122 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK 0x4UL 10123 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT 0x00000000UL 10124 #define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2) 10125 #define DMA_CHUSEBURSTS_CH3USEBURSTS (0x1UL << 3) 10126 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT 3 10127 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK 0x8UL 10128 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT 0x00000000UL 10129 #define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3) 10130 #define DMA_CHUSEBURSTS_CH4USEBURSTS (0x1UL << 4) 10131 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT 4 10132 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_MASK 0x10UL 10133 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT 0x00000000UL 10134 #define DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4) 10135 #define DMA_CHUSEBURSTS_CH5USEBURSTS (0x1UL << 5) 10136 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT 5 10137 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_MASK 0x20UL 10138 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT 0x00000000UL 10139 #define DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5) 10140 #define DMA_CHUSEBURSTS_CH6USEBURSTS (0x1UL << 6) 10141 #define _DMA_CHUSEBURSTS_CH6USEBURSTS_SHIFT 6 10142 #define _DMA_CHUSEBURSTS_CH6USEBURSTS_MASK 0x40UL 10143 #define _DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT 0x00000000UL 10144 #define DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT << 6) 10145 #define DMA_CHUSEBURSTS_CH7USEBURSTS (0x1UL << 7) 10146 #define _DMA_CHUSEBURSTS_CH7USEBURSTS_SHIFT 7 10147 #define _DMA_CHUSEBURSTS_CH7USEBURSTS_MASK 0x80UL 10148 #define _DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT 0x00000000UL 10149 #define DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT << 7) 10151 /* Bit fields for DMA CHUSEBURSTC */ 10152 #define _DMA_CHUSEBURSTC_RESETVALUE 0x00000000UL 10153 #define _DMA_CHUSEBURSTC_MASK 0x000000FFUL 10154 #define DMA_CHUSEBURSTC_CH0USEBURSTC (0x1UL << 0) 10155 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT 0 10156 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK 0x1UL 10157 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT 0x00000000UL 10158 #define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0) 10159 #define DMA_CHUSEBURSTC_CH1USEBURSTC (0x1UL << 1) 10160 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT 1 10161 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK 0x2UL 10162 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT 0x00000000UL 10163 #define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1) 10164 #define DMA_CHUSEBURSTC_CH2USEBURSTC (0x1UL << 2) 10165 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT 2 10166 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK 0x4UL 10167 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT 0x00000000UL 10168 #define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2) 10169 #define DMA_CHUSEBURSTC_CH3USEBURSTC (0x1UL << 3) 10170 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT 3 10171 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK 0x8UL 10172 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT 0x00000000UL 10173 #define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3) 10174 #define DMA_CHUSEBURSTC_CH4USEBURSTC (0x1UL << 4) 10175 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT 4 10176 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_MASK 0x10UL 10177 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT 0x00000000UL 10178 #define DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4) 10179 #define DMA_CHUSEBURSTC_CH5USEBURSTC (0x1UL << 5) 10180 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT 5 10181 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_MASK 0x20UL 10182 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT 0x00000000UL 10183 #define DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5) 10184 #define DMA_CHUSEBURSTC_CH6USEBURSTC (0x1UL << 6) 10185 #define _DMA_CHUSEBURSTC_CH6USEBURSTC_SHIFT 6 10186 #define _DMA_CHUSEBURSTC_CH6USEBURSTC_MASK 0x40UL 10187 #define _DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT 0x00000000UL 10188 #define DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT << 6) 10189 #define DMA_CHUSEBURSTC_CH7USEBURSTC (0x1UL << 7) 10190 #define _DMA_CHUSEBURSTC_CH7USEBURSTC_SHIFT 7 10191 #define _DMA_CHUSEBURSTC_CH7USEBURSTC_MASK 0x80UL 10192 #define _DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT 0x00000000UL 10193 #define DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT << 7) 10195 /* Bit fields for DMA CHREQMASKS */ 10196 #define _DMA_CHREQMASKS_RESETVALUE 0x00000000UL 10197 #define _DMA_CHREQMASKS_MASK 0x000000FFUL 10198 #define DMA_CHREQMASKS_CH0REQMASKS (0x1UL << 0) 10199 #define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT 0 10200 #define _DMA_CHREQMASKS_CH0REQMASKS_MASK 0x1UL 10201 #define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT 0x00000000UL 10202 #define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0) 10203 #define DMA_CHREQMASKS_CH1REQMASKS (0x1UL << 1) 10204 #define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT 1 10205 #define _DMA_CHREQMASKS_CH1REQMASKS_MASK 0x2UL 10206 #define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT 0x00000000UL 10207 #define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1) 10208 #define DMA_CHREQMASKS_CH2REQMASKS (0x1UL << 2) 10209 #define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT 2 10210 #define _DMA_CHREQMASKS_CH2REQMASKS_MASK 0x4UL 10211 #define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT 0x00000000UL 10212 #define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2) 10213 #define DMA_CHREQMASKS_CH3REQMASKS (0x1UL << 3) 10214 #define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT 3 10215 #define _DMA_CHREQMASKS_CH3REQMASKS_MASK 0x8UL 10216 #define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT 0x00000000UL 10217 #define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3) 10218 #define DMA_CHREQMASKS_CH4REQMASKS (0x1UL << 4) 10219 #define _DMA_CHREQMASKS_CH4REQMASKS_SHIFT 4 10220 #define _DMA_CHREQMASKS_CH4REQMASKS_MASK 0x10UL 10221 #define _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT 0x00000000UL 10222 #define DMA_CHREQMASKS_CH4REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4) 10223 #define DMA_CHREQMASKS_CH5REQMASKS (0x1UL << 5) 10224 #define _DMA_CHREQMASKS_CH5REQMASKS_SHIFT 5 10225 #define _DMA_CHREQMASKS_CH5REQMASKS_MASK 0x20UL 10226 #define _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT 0x00000000UL 10227 #define DMA_CHREQMASKS_CH5REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5) 10228 #define DMA_CHREQMASKS_CH6REQMASKS (0x1UL << 6) 10229 #define _DMA_CHREQMASKS_CH6REQMASKS_SHIFT 6 10230 #define _DMA_CHREQMASKS_CH6REQMASKS_MASK 0x40UL 10231 #define _DMA_CHREQMASKS_CH6REQMASKS_DEFAULT 0x00000000UL 10232 #define DMA_CHREQMASKS_CH6REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH6REQMASKS_DEFAULT << 6) 10233 #define DMA_CHREQMASKS_CH7REQMASKS (0x1UL << 7) 10234 #define _DMA_CHREQMASKS_CH7REQMASKS_SHIFT 7 10235 #define _DMA_CHREQMASKS_CH7REQMASKS_MASK 0x80UL 10236 #define _DMA_CHREQMASKS_CH7REQMASKS_DEFAULT 0x00000000UL 10237 #define DMA_CHREQMASKS_CH7REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH7REQMASKS_DEFAULT << 7) 10239 /* Bit fields for DMA CHREQMASKC */ 10240 #define _DMA_CHREQMASKC_RESETVALUE 0x00000000UL 10241 #define _DMA_CHREQMASKC_MASK 0x000000FFUL 10242 #define DMA_CHREQMASKC_CH0REQMASKC (0x1UL << 0) 10243 #define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT 0 10244 #define _DMA_CHREQMASKC_CH0REQMASKC_MASK 0x1UL 10245 #define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT 0x00000000UL 10246 #define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0) 10247 #define DMA_CHREQMASKC_CH1REQMASKC (0x1UL << 1) 10248 #define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT 1 10249 #define _DMA_CHREQMASKC_CH1REQMASKC_MASK 0x2UL 10250 #define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT 0x00000000UL 10251 #define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1) 10252 #define DMA_CHREQMASKC_CH2REQMASKC (0x1UL << 2) 10253 #define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT 2 10254 #define _DMA_CHREQMASKC_CH2REQMASKC_MASK 0x4UL 10255 #define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT 0x00000000UL 10256 #define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2) 10257 #define DMA_CHREQMASKC_CH3REQMASKC (0x1UL << 3) 10258 #define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT 3 10259 #define _DMA_CHREQMASKC_CH3REQMASKC_MASK 0x8UL 10260 #define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT 0x00000000UL 10261 #define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3) 10262 #define DMA_CHREQMASKC_CH4REQMASKC (0x1UL << 4) 10263 #define _DMA_CHREQMASKC_CH4REQMASKC_SHIFT 4 10264 #define _DMA_CHREQMASKC_CH4REQMASKC_MASK 0x10UL 10265 #define _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT 0x00000000UL 10266 #define DMA_CHREQMASKC_CH4REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4) 10267 #define DMA_CHREQMASKC_CH5REQMASKC (0x1UL << 5) 10268 #define _DMA_CHREQMASKC_CH5REQMASKC_SHIFT 5 10269 #define _DMA_CHREQMASKC_CH5REQMASKC_MASK 0x20UL 10270 #define _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT 0x00000000UL 10271 #define DMA_CHREQMASKC_CH5REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5) 10272 #define DMA_CHREQMASKC_CH6REQMASKC (0x1UL << 6) 10273 #define _DMA_CHREQMASKC_CH6REQMASKC_SHIFT 6 10274 #define _DMA_CHREQMASKC_CH6REQMASKC_MASK 0x40UL 10275 #define _DMA_CHREQMASKC_CH6REQMASKC_DEFAULT 0x00000000UL 10276 #define DMA_CHREQMASKC_CH6REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH6REQMASKC_DEFAULT << 6) 10277 #define DMA_CHREQMASKC_CH7REQMASKC (0x1UL << 7) 10278 #define _DMA_CHREQMASKC_CH7REQMASKC_SHIFT 7 10279 #define _DMA_CHREQMASKC_CH7REQMASKC_MASK 0x80UL 10280 #define _DMA_CHREQMASKC_CH7REQMASKC_DEFAULT 0x00000000UL 10281 #define DMA_CHREQMASKC_CH7REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH7REQMASKC_DEFAULT << 7) 10283 /* Bit fields for DMA CHENS */ 10284 #define _DMA_CHENS_RESETVALUE 0x00000000UL 10285 #define _DMA_CHENS_MASK 0x000000FFUL 10286 #define DMA_CHENS_CH0ENS (0x1UL << 0) 10287 #define _DMA_CHENS_CH0ENS_SHIFT 0 10288 #define _DMA_CHENS_CH0ENS_MASK 0x1UL 10289 #define _DMA_CHENS_CH0ENS_DEFAULT 0x00000000UL 10290 #define DMA_CHENS_CH0ENS_DEFAULT (_DMA_CHENS_CH0ENS_DEFAULT << 0) 10291 #define DMA_CHENS_CH1ENS (0x1UL << 1) 10292 #define _DMA_CHENS_CH1ENS_SHIFT 1 10293 #define _DMA_CHENS_CH1ENS_MASK 0x2UL 10294 #define _DMA_CHENS_CH1ENS_DEFAULT 0x00000000UL 10295 #define DMA_CHENS_CH1ENS_DEFAULT (_DMA_CHENS_CH1ENS_DEFAULT << 1) 10296 #define DMA_CHENS_CH2ENS (0x1UL << 2) 10297 #define _DMA_CHENS_CH2ENS_SHIFT 2 10298 #define _DMA_CHENS_CH2ENS_MASK 0x4UL 10299 #define _DMA_CHENS_CH2ENS_DEFAULT 0x00000000UL 10300 #define DMA_CHENS_CH2ENS_DEFAULT (_DMA_CHENS_CH2ENS_DEFAULT << 2) 10301 #define DMA_CHENS_CH3ENS (0x1UL << 3) 10302 #define _DMA_CHENS_CH3ENS_SHIFT 3 10303 #define _DMA_CHENS_CH3ENS_MASK 0x8UL 10304 #define _DMA_CHENS_CH3ENS_DEFAULT 0x00000000UL 10305 #define DMA_CHENS_CH3ENS_DEFAULT (_DMA_CHENS_CH3ENS_DEFAULT << 3) 10306 #define DMA_CHENS_CH4ENS (0x1UL << 4) 10307 #define _DMA_CHENS_CH4ENS_SHIFT 4 10308 #define _DMA_CHENS_CH4ENS_MASK 0x10UL 10309 #define _DMA_CHENS_CH4ENS_DEFAULT 0x00000000UL 10310 #define DMA_CHENS_CH4ENS_DEFAULT (_DMA_CHENS_CH4ENS_DEFAULT << 4) 10311 #define DMA_CHENS_CH5ENS (0x1UL << 5) 10312 #define _DMA_CHENS_CH5ENS_SHIFT 5 10313 #define _DMA_CHENS_CH5ENS_MASK 0x20UL 10314 #define _DMA_CHENS_CH5ENS_DEFAULT 0x00000000UL 10315 #define DMA_CHENS_CH5ENS_DEFAULT (_DMA_CHENS_CH5ENS_DEFAULT << 5) 10316 #define DMA_CHENS_CH6ENS (0x1UL << 6) 10317 #define _DMA_CHENS_CH6ENS_SHIFT 6 10318 #define _DMA_CHENS_CH6ENS_MASK 0x40UL 10319 #define _DMA_CHENS_CH6ENS_DEFAULT 0x00000000UL 10320 #define DMA_CHENS_CH6ENS_DEFAULT (_DMA_CHENS_CH6ENS_DEFAULT << 6) 10321 #define DMA_CHENS_CH7ENS (0x1UL << 7) 10322 #define _DMA_CHENS_CH7ENS_SHIFT 7 10323 #define _DMA_CHENS_CH7ENS_MASK 0x80UL 10324 #define _DMA_CHENS_CH7ENS_DEFAULT 0x00000000UL 10325 #define DMA_CHENS_CH7ENS_DEFAULT (_DMA_CHENS_CH7ENS_DEFAULT << 7) 10327 /* Bit fields for DMA CHENC */ 10328 #define _DMA_CHENC_RESETVALUE 0x00000000UL 10329 #define _DMA_CHENC_MASK 0x000000FFUL 10330 #define DMA_CHENC_CH0ENC (0x1UL << 0) 10331 #define _DMA_CHENC_CH0ENC_SHIFT 0 10332 #define _DMA_CHENC_CH0ENC_MASK 0x1UL 10333 #define _DMA_CHENC_CH0ENC_DEFAULT 0x00000000UL 10334 #define DMA_CHENC_CH0ENC_DEFAULT (_DMA_CHENC_CH0ENC_DEFAULT << 0) 10335 #define DMA_CHENC_CH1ENC (0x1UL << 1) 10336 #define _DMA_CHENC_CH1ENC_SHIFT 1 10337 #define _DMA_CHENC_CH1ENC_MASK 0x2UL 10338 #define _DMA_CHENC_CH1ENC_DEFAULT 0x00000000UL 10339 #define DMA_CHENC_CH1ENC_DEFAULT (_DMA_CHENC_CH1ENC_DEFAULT << 1) 10340 #define DMA_CHENC_CH2ENC (0x1UL << 2) 10341 #define _DMA_CHENC_CH2ENC_SHIFT 2 10342 #define _DMA_CHENC_CH2ENC_MASK 0x4UL 10343 #define _DMA_CHENC_CH2ENC_DEFAULT 0x00000000UL 10344 #define DMA_CHENC_CH2ENC_DEFAULT (_DMA_CHENC_CH2ENC_DEFAULT << 2) 10345 #define DMA_CHENC_CH3ENC (0x1UL << 3) 10346 #define _DMA_CHENC_CH3ENC_SHIFT 3 10347 #define _DMA_CHENC_CH3ENC_MASK 0x8UL 10348 #define _DMA_CHENC_CH3ENC_DEFAULT 0x00000000UL 10349 #define DMA_CHENC_CH3ENC_DEFAULT (_DMA_CHENC_CH3ENC_DEFAULT << 3) 10350 #define DMA_CHENC_CH4ENC (0x1UL << 4) 10351 #define _DMA_CHENC_CH4ENC_SHIFT 4 10352 #define _DMA_CHENC_CH4ENC_MASK 0x10UL 10353 #define _DMA_CHENC_CH4ENC_DEFAULT 0x00000000UL 10354 #define DMA_CHENC_CH4ENC_DEFAULT (_DMA_CHENC_CH4ENC_DEFAULT << 4) 10355 #define DMA_CHENC_CH5ENC (0x1UL << 5) 10356 #define _DMA_CHENC_CH5ENC_SHIFT 5 10357 #define _DMA_CHENC_CH5ENC_MASK 0x20UL 10358 #define _DMA_CHENC_CH5ENC_DEFAULT 0x00000000UL 10359 #define DMA_CHENC_CH5ENC_DEFAULT (_DMA_CHENC_CH5ENC_DEFAULT << 5) 10360 #define DMA_CHENC_CH6ENC (0x1UL << 6) 10361 #define _DMA_CHENC_CH6ENC_SHIFT 6 10362 #define _DMA_CHENC_CH6ENC_MASK 0x40UL 10363 #define _DMA_CHENC_CH6ENC_DEFAULT 0x00000000UL 10364 #define DMA_CHENC_CH6ENC_DEFAULT (_DMA_CHENC_CH6ENC_DEFAULT << 6) 10365 #define DMA_CHENC_CH7ENC (0x1UL << 7) 10366 #define _DMA_CHENC_CH7ENC_SHIFT 7 10367 #define _DMA_CHENC_CH7ENC_MASK 0x80UL 10368 #define _DMA_CHENC_CH7ENC_DEFAULT 0x00000000UL 10369 #define DMA_CHENC_CH7ENC_DEFAULT (_DMA_CHENC_CH7ENC_DEFAULT << 7) 10371 /* Bit fields for DMA CHALTS */ 10372 #define _DMA_CHALTS_RESETVALUE 0x00000000UL 10373 #define _DMA_CHALTS_MASK 0x000000FFUL 10374 #define DMA_CHALTS_CH0ALTS (0x1UL << 0) 10375 #define _DMA_CHALTS_CH0ALTS_SHIFT 0 10376 #define _DMA_CHALTS_CH0ALTS_MASK 0x1UL 10377 #define _DMA_CHALTS_CH0ALTS_DEFAULT 0x00000000UL 10378 #define DMA_CHALTS_CH0ALTS_DEFAULT (_DMA_CHALTS_CH0ALTS_DEFAULT << 0) 10379 #define DMA_CHALTS_CH1ALTS (0x1UL << 1) 10380 #define _DMA_CHALTS_CH1ALTS_SHIFT 1 10381 #define _DMA_CHALTS_CH1ALTS_MASK 0x2UL 10382 #define _DMA_CHALTS_CH1ALTS_DEFAULT 0x00000000UL 10383 #define DMA_CHALTS_CH1ALTS_DEFAULT (_DMA_CHALTS_CH1ALTS_DEFAULT << 1) 10384 #define DMA_CHALTS_CH2ALTS (0x1UL << 2) 10385 #define _DMA_CHALTS_CH2ALTS_SHIFT 2 10386 #define _DMA_CHALTS_CH2ALTS_MASK 0x4UL 10387 #define _DMA_CHALTS_CH2ALTS_DEFAULT 0x00000000UL 10388 #define DMA_CHALTS_CH2ALTS_DEFAULT (_DMA_CHALTS_CH2ALTS_DEFAULT << 2) 10389 #define DMA_CHALTS_CH3ALTS (0x1UL << 3) 10390 #define _DMA_CHALTS_CH3ALTS_SHIFT 3 10391 #define _DMA_CHALTS_CH3ALTS_MASK 0x8UL 10392 #define _DMA_CHALTS_CH3ALTS_DEFAULT 0x00000000UL 10393 #define DMA_CHALTS_CH3ALTS_DEFAULT (_DMA_CHALTS_CH3ALTS_DEFAULT << 3) 10394 #define DMA_CHALTS_CH4ALTS (0x1UL << 4) 10395 #define _DMA_CHALTS_CH4ALTS_SHIFT 4 10396 #define _DMA_CHALTS_CH4ALTS_MASK 0x10UL 10397 #define _DMA_CHALTS_CH4ALTS_DEFAULT 0x00000000UL 10398 #define DMA_CHALTS_CH4ALTS_DEFAULT (_DMA_CHALTS_CH4ALTS_DEFAULT << 4) 10399 #define DMA_CHALTS_CH5ALTS (0x1UL << 5) 10400 #define _DMA_CHALTS_CH5ALTS_SHIFT 5 10401 #define _DMA_CHALTS_CH5ALTS_MASK 0x20UL 10402 #define _DMA_CHALTS_CH5ALTS_DEFAULT 0x00000000UL 10403 #define DMA_CHALTS_CH5ALTS_DEFAULT (_DMA_CHALTS_CH5ALTS_DEFAULT << 5) 10404 #define DMA_CHALTS_CH6ALTS (0x1UL << 6) 10405 #define _DMA_CHALTS_CH6ALTS_SHIFT 6 10406 #define _DMA_CHALTS_CH6ALTS_MASK 0x40UL 10407 #define _DMA_CHALTS_CH6ALTS_DEFAULT 0x00000000UL 10408 #define DMA_CHALTS_CH6ALTS_DEFAULT (_DMA_CHALTS_CH6ALTS_DEFAULT << 6) 10409 #define DMA_CHALTS_CH7ALTS (0x1UL << 7) 10410 #define _DMA_CHALTS_CH7ALTS_SHIFT 7 10411 #define _DMA_CHALTS_CH7ALTS_MASK 0x80UL 10412 #define _DMA_CHALTS_CH7ALTS_DEFAULT 0x00000000UL 10413 #define DMA_CHALTS_CH7ALTS_DEFAULT (_DMA_CHALTS_CH7ALTS_DEFAULT << 7) 10415 /* Bit fields for DMA CHALTC */ 10416 #define _DMA_CHALTC_RESETVALUE 0x00000000UL 10417 #define _DMA_CHALTC_MASK 0x000000FFUL 10418 #define DMA_CHALTC_CH0ALTC (0x1UL << 0) 10419 #define _DMA_CHALTC_CH0ALTC_SHIFT 0 10420 #define _DMA_CHALTC_CH0ALTC_MASK 0x1UL 10421 #define _DMA_CHALTC_CH0ALTC_DEFAULT 0x00000000UL 10422 #define DMA_CHALTC_CH0ALTC_DEFAULT (_DMA_CHALTC_CH0ALTC_DEFAULT << 0) 10423 #define DMA_CHALTC_CH1ALTC (0x1UL << 1) 10424 #define _DMA_CHALTC_CH1ALTC_SHIFT 1 10425 #define _DMA_CHALTC_CH1ALTC_MASK 0x2UL 10426 #define _DMA_CHALTC_CH1ALTC_DEFAULT 0x00000000UL 10427 #define DMA_CHALTC_CH1ALTC_DEFAULT (_DMA_CHALTC_CH1ALTC_DEFAULT << 1) 10428 #define DMA_CHALTC_CH2ALTC (0x1UL << 2) 10429 #define _DMA_CHALTC_CH2ALTC_SHIFT 2 10430 #define _DMA_CHALTC_CH2ALTC_MASK 0x4UL 10431 #define _DMA_CHALTC_CH2ALTC_DEFAULT 0x00000000UL 10432 #define DMA_CHALTC_CH2ALTC_DEFAULT (_DMA_CHALTC_CH2ALTC_DEFAULT << 2) 10433 #define DMA_CHALTC_CH3ALTC (0x1UL << 3) 10434 #define _DMA_CHALTC_CH3ALTC_SHIFT 3 10435 #define _DMA_CHALTC_CH3ALTC_MASK 0x8UL 10436 #define _DMA_CHALTC_CH3ALTC_DEFAULT 0x00000000UL 10437 #define DMA_CHALTC_CH3ALTC_DEFAULT (_DMA_CHALTC_CH3ALTC_DEFAULT << 3) 10438 #define DMA_CHALTC_CH4ALTC (0x1UL << 4) 10439 #define _DMA_CHALTC_CH4ALTC_SHIFT 4 10440 #define _DMA_CHALTC_CH4ALTC_MASK 0x10UL 10441 #define _DMA_CHALTC_CH4ALTC_DEFAULT 0x00000000UL 10442 #define DMA_CHALTC_CH4ALTC_DEFAULT (_DMA_CHALTC_CH4ALTC_DEFAULT << 4) 10443 #define DMA_CHALTC_CH5ALTC (0x1UL << 5) 10444 #define _DMA_CHALTC_CH5ALTC_SHIFT 5 10445 #define _DMA_CHALTC_CH5ALTC_MASK 0x20UL 10446 #define _DMA_CHALTC_CH5ALTC_DEFAULT 0x00000000UL 10447 #define DMA_CHALTC_CH5ALTC_DEFAULT (_DMA_CHALTC_CH5ALTC_DEFAULT << 5) 10448 #define DMA_CHALTC_CH6ALTC (0x1UL << 6) 10449 #define _DMA_CHALTC_CH6ALTC_SHIFT 6 10450 #define _DMA_CHALTC_CH6ALTC_MASK 0x40UL 10451 #define _DMA_CHALTC_CH6ALTC_DEFAULT 0x00000000UL 10452 #define DMA_CHALTC_CH6ALTC_DEFAULT (_DMA_CHALTC_CH6ALTC_DEFAULT << 6) 10453 #define DMA_CHALTC_CH7ALTC (0x1UL << 7) 10454 #define _DMA_CHALTC_CH7ALTC_SHIFT 7 10455 #define _DMA_CHALTC_CH7ALTC_MASK 0x80UL 10456 #define _DMA_CHALTC_CH7ALTC_DEFAULT 0x00000000UL 10457 #define DMA_CHALTC_CH7ALTC_DEFAULT (_DMA_CHALTC_CH7ALTC_DEFAULT << 7) 10459 /* Bit fields for DMA CHPRIS */ 10460 #define _DMA_CHPRIS_RESETVALUE 0x00000000UL 10461 #define _DMA_CHPRIS_MASK 0x000000FFUL 10462 #define DMA_CHPRIS_CH0PRIS (0x1UL << 0) 10463 #define _DMA_CHPRIS_CH0PRIS_SHIFT 0 10464 #define _DMA_CHPRIS_CH0PRIS_MASK 0x1UL 10465 #define _DMA_CHPRIS_CH0PRIS_DEFAULT 0x00000000UL 10466 #define DMA_CHPRIS_CH0PRIS_DEFAULT (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0) 10467 #define DMA_CHPRIS_CH1PRIS (0x1UL << 1) 10468 #define _DMA_CHPRIS_CH1PRIS_SHIFT 1 10469 #define _DMA_CHPRIS_CH1PRIS_MASK 0x2UL 10470 #define _DMA_CHPRIS_CH1PRIS_DEFAULT 0x00000000UL 10471 #define DMA_CHPRIS_CH1PRIS_DEFAULT (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1) 10472 #define DMA_CHPRIS_CH2PRIS (0x1UL << 2) 10473 #define _DMA_CHPRIS_CH2PRIS_SHIFT 2 10474 #define _DMA_CHPRIS_CH2PRIS_MASK 0x4UL 10475 #define _DMA_CHPRIS_CH2PRIS_DEFAULT 0x00000000UL 10476 #define DMA_CHPRIS_CH2PRIS_DEFAULT (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2) 10477 #define DMA_CHPRIS_CH3PRIS (0x1UL << 3) 10478 #define _DMA_CHPRIS_CH3PRIS_SHIFT 3 10479 #define _DMA_CHPRIS_CH3PRIS_MASK 0x8UL 10480 #define _DMA_CHPRIS_CH3PRIS_DEFAULT 0x00000000UL 10481 #define DMA_CHPRIS_CH3PRIS_DEFAULT (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3) 10482 #define DMA_CHPRIS_CH4PRIS (0x1UL << 4) 10483 #define _DMA_CHPRIS_CH4PRIS_SHIFT 4 10484 #define _DMA_CHPRIS_CH4PRIS_MASK 0x10UL 10485 #define _DMA_CHPRIS_CH4PRIS_DEFAULT 0x00000000UL 10486 #define DMA_CHPRIS_CH4PRIS_DEFAULT (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4) 10487 #define DMA_CHPRIS_CH5PRIS (0x1UL << 5) 10488 #define _DMA_CHPRIS_CH5PRIS_SHIFT 5 10489 #define _DMA_CHPRIS_CH5PRIS_MASK 0x20UL 10490 #define _DMA_CHPRIS_CH5PRIS_DEFAULT 0x00000000UL 10491 #define DMA_CHPRIS_CH5PRIS_DEFAULT (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5) 10492 #define DMA_CHPRIS_CH6PRIS (0x1UL << 6) 10493 #define _DMA_CHPRIS_CH6PRIS_SHIFT 6 10494 #define _DMA_CHPRIS_CH6PRIS_MASK 0x40UL 10495 #define _DMA_CHPRIS_CH6PRIS_DEFAULT 0x00000000UL 10496 #define DMA_CHPRIS_CH6PRIS_DEFAULT (_DMA_CHPRIS_CH6PRIS_DEFAULT << 6) 10497 #define DMA_CHPRIS_CH7PRIS (0x1UL << 7) 10498 #define _DMA_CHPRIS_CH7PRIS_SHIFT 7 10499 #define _DMA_CHPRIS_CH7PRIS_MASK 0x80UL 10500 #define _DMA_CHPRIS_CH7PRIS_DEFAULT 0x00000000UL 10501 #define DMA_CHPRIS_CH7PRIS_DEFAULT (_DMA_CHPRIS_CH7PRIS_DEFAULT << 7) 10503 /* Bit fields for DMA CHPRIC */ 10504 #define _DMA_CHPRIC_RESETVALUE 0x00000000UL 10505 #define _DMA_CHPRIC_MASK 0x000000FFUL 10506 #define DMA_CHPRIC_CH0PRIC (0x1UL << 0) 10507 #define _DMA_CHPRIC_CH0PRIC_SHIFT 0 10508 #define _DMA_CHPRIC_CH0PRIC_MASK 0x1UL 10509 #define _DMA_CHPRIC_CH0PRIC_DEFAULT 0x00000000UL 10510 #define DMA_CHPRIC_CH0PRIC_DEFAULT (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0) 10511 #define DMA_CHPRIC_CH1PRIC (0x1UL << 1) 10512 #define _DMA_CHPRIC_CH1PRIC_SHIFT 1 10513 #define _DMA_CHPRIC_CH1PRIC_MASK 0x2UL 10514 #define _DMA_CHPRIC_CH1PRIC_DEFAULT 0x00000000UL 10515 #define DMA_CHPRIC_CH1PRIC_DEFAULT (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1) 10516 #define DMA_CHPRIC_CH2PRIC (0x1UL << 2) 10517 #define _DMA_CHPRIC_CH2PRIC_SHIFT 2 10518 #define _DMA_CHPRIC_CH2PRIC_MASK 0x4UL 10519 #define _DMA_CHPRIC_CH2PRIC_DEFAULT 0x00000000UL 10520 #define DMA_CHPRIC_CH2PRIC_DEFAULT (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2) 10521 #define DMA_CHPRIC_CH3PRIC (0x1UL << 3) 10522 #define _DMA_CHPRIC_CH3PRIC_SHIFT 3 10523 #define _DMA_CHPRIC_CH3PRIC_MASK 0x8UL 10524 #define _DMA_CHPRIC_CH3PRIC_DEFAULT 0x00000000UL 10525 #define DMA_CHPRIC_CH3PRIC_DEFAULT (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3) 10526 #define DMA_CHPRIC_CH4PRIC (0x1UL << 4) 10527 #define _DMA_CHPRIC_CH4PRIC_SHIFT 4 10528 #define _DMA_CHPRIC_CH4PRIC_MASK 0x10UL 10529 #define _DMA_CHPRIC_CH4PRIC_DEFAULT 0x00000000UL 10530 #define DMA_CHPRIC_CH4PRIC_DEFAULT (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4) 10531 #define DMA_CHPRIC_CH5PRIC (0x1UL << 5) 10532 #define _DMA_CHPRIC_CH5PRIC_SHIFT 5 10533 #define _DMA_CHPRIC_CH5PRIC_MASK 0x20UL 10534 #define _DMA_CHPRIC_CH5PRIC_DEFAULT 0x00000000UL 10535 #define DMA_CHPRIC_CH5PRIC_DEFAULT (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5) 10536 #define DMA_CHPRIC_CH6PRIC (0x1UL << 6) 10537 #define _DMA_CHPRIC_CH6PRIC_SHIFT 6 10538 #define _DMA_CHPRIC_CH6PRIC_MASK 0x40UL 10539 #define _DMA_CHPRIC_CH6PRIC_DEFAULT 0x00000000UL 10540 #define DMA_CHPRIC_CH6PRIC_DEFAULT (_DMA_CHPRIC_CH6PRIC_DEFAULT << 6) 10541 #define DMA_CHPRIC_CH7PRIC (0x1UL << 7) 10542 #define _DMA_CHPRIC_CH7PRIC_SHIFT 7 10543 #define _DMA_CHPRIC_CH7PRIC_MASK 0x80UL 10544 #define _DMA_CHPRIC_CH7PRIC_DEFAULT 0x00000000UL 10545 #define DMA_CHPRIC_CH7PRIC_DEFAULT (_DMA_CHPRIC_CH7PRIC_DEFAULT << 7) 10547 /* Bit fields for DMA ERRORC */ 10548 #define _DMA_ERRORC_RESETVALUE 0x00000000UL 10549 #define _DMA_ERRORC_MASK 0x00000001UL 10550 #define DMA_ERRORC_ERRORC (0x1UL << 0) 10551 #define _DMA_ERRORC_ERRORC_SHIFT 0 10552 #define _DMA_ERRORC_ERRORC_MASK 0x1UL 10553 #define _DMA_ERRORC_ERRORC_DEFAULT 0x00000000UL 10554 #define DMA_ERRORC_ERRORC_DEFAULT (_DMA_ERRORC_ERRORC_DEFAULT << 0) 10556 /* Bit fields for DMA CHREQSTATUS */ 10557 #define _DMA_CHREQSTATUS_RESETVALUE 0x00000000UL 10558 #define _DMA_CHREQSTATUS_MASK 0x000000FFUL 10559 #define DMA_CHREQSTATUS_CH0REQSTATUS (0x1UL << 0) 10560 #define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT 0 10561 #define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK 0x1UL 10562 #define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT 0x00000000UL 10563 #define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0) 10564 #define DMA_CHREQSTATUS_CH1REQSTATUS (0x1UL << 1) 10565 #define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT 1 10566 #define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK 0x2UL 10567 #define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT 0x00000000UL 10568 #define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1) 10569 #define DMA_CHREQSTATUS_CH2REQSTATUS (0x1UL << 2) 10570 #define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT 2 10571 #define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK 0x4UL 10572 #define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT 0x00000000UL 10573 #define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2) 10574 #define DMA_CHREQSTATUS_CH3REQSTATUS (0x1UL << 3) 10575 #define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT 3 10576 #define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK 0x8UL 10577 #define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT 0x00000000UL 10578 #define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3) 10579 #define DMA_CHREQSTATUS_CH4REQSTATUS (0x1UL << 4) 10580 #define _DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT 4 10581 #define _DMA_CHREQSTATUS_CH4REQSTATUS_MASK 0x10UL 10582 #define _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT 0x00000000UL 10583 #define DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4) 10584 #define DMA_CHREQSTATUS_CH5REQSTATUS (0x1UL << 5) 10585 #define _DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT 5 10586 #define _DMA_CHREQSTATUS_CH5REQSTATUS_MASK 0x20UL 10587 #define _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT 0x00000000UL 10588 #define DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5) 10589 #define DMA_CHREQSTATUS_CH6REQSTATUS (0x1UL << 6) 10590 #define _DMA_CHREQSTATUS_CH6REQSTATUS_SHIFT 6 10591 #define _DMA_CHREQSTATUS_CH6REQSTATUS_MASK 0x40UL 10592 #define _DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT 0x00000000UL 10593 #define DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT << 6) 10594 #define DMA_CHREQSTATUS_CH7REQSTATUS (0x1UL << 7) 10595 #define _DMA_CHREQSTATUS_CH7REQSTATUS_SHIFT 7 10596 #define _DMA_CHREQSTATUS_CH7REQSTATUS_MASK 0x80UL 10597 #define _DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT 0x00000000UL 10598 #define DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT << 7) 10600 /* Bit fields for DMA CHSREQSTATUS */ 10601 #define _DMA_CHSREQSTATUS_RESETVALUE 0x00000000UL 10602 #define _DMA_CHSREQSTATUS_MASK 0x000000FFUL 10603 #define DMA_CHSREQSTATUS_CH0SREQSTATUS (0x1UL << 0) 10604 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT 0 10605 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK 0x1UL 10606 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT 0x00000000UL 10607 #define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0) 10608 #define DMA_CHSREQSTATUS_CH1SREQSTATUS (0x1UL << 1) 10609 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT 1 10610 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK 0x2UL 10611 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT 0x00000000UL 10612 #define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1) 10613 #define DMA_CHSREQSTATUS_CH2SREQSTATUS (0x1UL << 2) 10614 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT 2 10615 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK 0x4UL 10616 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT 0x00000000UL 10617 #define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2) 10618 #define DMA_CHSREQSTATUS_CH3SREQSTATUS (0x1UL << 3) 10619 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT 3 10620 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK 0x8UL 10621 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT 0x00000000UL 10622 #define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3) 10623 #define DMA_CHSREQSTATUS_CH4SREQSTATUS (0x1UL << 4) 10624 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT 4 10625 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK 0x10UL 10626 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT 0x00000000UL 10627 #define DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4) 10628 #define DMA_CHSREQSTATUS_CH5SREQSTATUS (0x1UL << 5) 10629 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT 5 10630 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK 0x20UL 10631 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT 0x00000000UL 10632 #define DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5) 10633 #define DMA_CHSREQSTATUS_CH6SREQSTATUS (0x1UL << 6) 10634 #define _DMA_CHSREQSTATUS_CH6SREQSTATUS_SHIFT 6 10635 #define _DMA_CHSREQSTATUS_CH6SREQSTATUS_MASK 0x40UL 10636 #define _DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT 0x00000000UL 10637 #define DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT << 6) 10638 #define DMA_CHSREQSTATUS_CH7SREQSTATUS (0x1UL << 7) 10639 #define _DMA_CHSREQSTATUS_CH7SREQSTATUS_SHIFT 7 10640 #define _DMA_CHSREQSTATUS_CH7SREQSTATUS_MASK 0x80UL 10641 #define _DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT 0x00000000UL 10642 #define DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT << 7) 10644 /* Bit fields for DMA IF */ 10645 #define _DMA_IF_RESETVALUE 0x00000000UL 10646 #define _DMA_IF_MASK 0x800000FFUL 10647 #define DMA_IF_CH0DONE (0x1UL << 0) 10648 #define _DMA_IF_CH0DONE_SHIFT 0 10649 #define _DMA_IF_CH0DONE_MASK 0x1UL 10650 #define _DMA_IF_CH0DONE_DEFAULT 0x00000000UL 10651 #define DMA_IF_CH0DONE_DEFAULT (_DMA_IF_CH0DONE_DEFAULT << 0) 10652 #define DMA_IF_CH1DONE (0x1UL << 1) 10653 #define _DMA_IF_CH1DONE_SHIFT 1 10654 #define _DMA_IF_CH1DONE_MASK 0x2UL 10655 #define _DMA_IF_CH1DONE_DEFAULT 0x00000000UL 10656 #define DMA_IF_CH1DONE_DEFAULT (_DMA_IF_CH1DONE_DEFAULT << 1) 10657 #define DMA_IF_CH2DONE (0x1UL << 2) 10658 #define _DMA_IF_CH2DONE_SHIFT 2 10659 #define _DMA_IF_CH2DONE_MASK 0x4UL 10660 #define _DMA_IF_CH2DONE_DEFAULT 0x00000000UL 10661 #define DMA_IF_CH2DONE_DEFAULT (_DMA_IF_CH2DONE_DEFAULT << 2) 10662 #define DMA_IF_CH3DONE (0x1UL << 3) 10663 #define _DMA_IF_CH3DONE_SHIFT 3 10664 #define _DMA_IF_CH3DONE_MASK 0x8UL 10665 #define _DMA_IF_CH3DONE_DEFAULT 0x00000000UL 10666 #define DMA_IF_CH3DONE_DEFAULT (_DMA_IF_CH3DONE_DEFAULT << 3) 10667 #define DMA_IF_CH4DONE (0x1UL << 4) 10668 #define _DMA_IF_CH4DONE_SHIFT 4 10669 #define _DMA_IF_CH4DONE_MASK 0x10UL 10670 #define _DMA_IF_CH4DONE_DEFAULT 0x00000000UL 10671 #define DMA_IF_CH4DONE_DEFAULT (_DMA_IF_CH4DONE_DEFAULT << 4) 10672 #define DMA_IF_CH5DONE (0x1UL << 5) 10673 #define _DMA_IF_CH5DONE_SHIFT 5 10674 #define _DMA_IF_CH5DONE_MASK 0x20UL 10675 #define _DMA_IF_CH5DONE_DEFAULT 0x00000000UL 10676 #define DMA_IF_CH5DONE_DEFAULT (_DMA_IF_CH5DONE_DEFAULT << 5) 10677 #define DMA_IF_CH6DONE (0x1UL << 6) 10678 #define _DMA_IF_CH6DONE_SHIFT 6 10679 #define _DMA_IF_CH6DONE_MASK 0x40UL 10680 #define _DMA_IF_CH6DONE_DEFAULT 0x00000000UL 10681 #define DMA_IF_CH6DONE_DEFAULT (_DMA_IF_CH6DONE_DEFAULT << 6) 10682 #define DMA_IF_CH7DONE (0x1UL << 7) 10683 #define _DMA_IF_CH7DONE_SHIFT 7 10684 #define _DMA_IF_CH7DONE_MASK 0x80UL 10685 #define _DMA_IF_CH7DONE_DEFAULT 0x00000000UL 10686 #define DMA_IF_CH7DONE_DEFAULT (_DMA_IF_CH7DONE_DEFAULT << 7) 10687 #define DMA_IF_ERR (0x1UL << 31) 10688 #define _DMA_IF_ERR_SHIFT 31 10689 #define _DMA_IF_ERR_MASK 0x80000000UL 10690 #define _DMA_IF_ERR_DEFAULT 0x00000000UL 10691 #define DMA_IF_ERR_DEFAULT (_DMA_IF_ERR_DEFAULT << 31) 10693 /* Bit fields for DMA IFS */ 10694 #define _DMA_IFS_RESETVALUE 0x00000000UL 10695 #define _DMA_IFS_MASK 0x800000FFUL 10696 #define DMA_IFS_CH0DONE (0x1UL << 0) 10697 #define _DMA_IFS_CH0DONE_SHIFT 0 10698 #define _DMA_IFS_CH0DONE_MASK 0x1UL 10699 #define _DMA_IFS_CH0DONE_DEFAULT 0x00000000UL 10700 #define DMA_IFS_CH0DONE_DEFAULT (_DMA_IFS_CH0DONE_DEFAULT << 0) 10701 #define DMA_IFS_CH1DONE (0x1UL << 1) 10702 #define _DMA_IFS_CH1DONE_SHIFT 1 10703 #define _DMA_IFS_CH1DONE_MASK 0x2UL 10704 #define _DMA_IFS_CH1DONE_DEFAULT 0x00000000UL 10705 #define DMA_IFS_CH1DONE_DEFAULT (_DMA_IFS_CH1DONE_DEFAULT << 1) 10706 #define DMA_IFS_CH2DONE (0x1UL << 2) 10707 #define _DMA_IFS_CH2DONE_SHIFT 2 10708 #define _DMA_IFS_CH2DONE_MASK 0x4UL 10709 #define _DMA_IFS_CH2DONE_DEFAULT 0x00000000UL 10710 #define DMA_IFS_CH2DONE_DEFAULT (_DMA_IFS_CH2DONE_DEFAULT << 2) 10711 #define DMA_IFS_CH3DONE (0x1UL << 3) 10712 #define _DMA_IFS_CH3DONE_SHIFT 3 10713 #define _DMA_IFS_CH3DONE_MASK 0x8UL 10714 #define _DMA_IFS_CH3DONE_DEFAULT 0x00000000UL 10715 #define DMA_IFS_CH3DONE_DEFAULT (_DMA_IFS_CH3DONE_DEFAULT << 3) 10716 #define DMA_IFS_CH4DONE (0x1UL << 4) 10717 #define _DMA_IFS_CH4DONE_SHIFT 4 10718 #define _DMA_IFS_CH4DONE_MASK 0x10UL 10719 #define _DMA_IFS_CH4DONE_DEFAULT 0x00000000UL 10720 #define DMA_IFS_CH4DONE_DEFAULT (_DMA_IFS_CH4DONE_DEFAULT << 4) 10721 #define DMA_IFS_CH5DONE (0x1UL << 5) 10722 #define _DMA_IFS_CH5DONE_SHIFT 5 10723 #define _DMA_IFS_CH5DONE_MASK 0x20UL 10724 #define _DMA_IFS_CH5DONE_DEFAULT 0x00000000UL 10725 #define DMA_IFS_CH5DONE_DEFAULT (_DMA_IFS_CH5DONE_DEFAULT << 5) 10726 #define DMA_IFS_CH6DONE (0x1UL << 6) 10727 #define _DMA_IFS_CH6DONE_SHIFT 6 10728 #define _DMA_IFS_CH6DONE_MASK 0x40UL 10729 #define _DMA_IFS_CH6DONE_DEFAULT 0x00000000UL 10730 #define DMA_IFS_CH6DONE_DEFAULT (_DMA_IFS_CH6DONE_DEFAULT << 6) 10731 #define DMA_IFS_CH7DONE (0x1UL << 7) 10732 #define _DMA_IFS_CH7DONE_SHIFT 7 10733 #define _DMA_IFS_CH7DONE_MASK 0x80UL 10734 #define _DMA_IFS_CH7DONE_DEFAULT 0x00000000UL 10735 #define DMA_IFS_CH7DONE_DEFAULT (_DMA_IFS_CH7DONE_DEFAULT << 7) 10736 #define DMA_IFS_ERR (0x1UL << 31) 10737 #define _DMA_IFS_ERR_SHIFT 31 10738 #define _DMA_IFS_ERR_MASK 0x80000000UL 10739 #define _DMA_IFS_ERR_DEFAULT 0x00000000UL 10740 #define DMA_IFS_ERR_DEFAULT (_DMA_IFS_ERR_DEFAULT << 31) 10742 /* Bit fields for DMA IFC */ 10743 #define _DMA_IFC_RESETVALUE 0x00000000UL 10744 #define _DMA_IFC_MASK 0x800000FFUL 10745 #define DMA_IFC_CH0DONE (0x1UL << 0) 10746 #define _DMA_IFC_CH0DONE_SHIFT 0 10747 #define _DMA_IFC_CH0DONE_MASK 0x1UL 10748 #define _DMA_IFC_CH0DONE_DEFAULT 0x00000000UL 10749 #define DMA_IFC_CH0DONE_DEFAULT (_DMA_IFC_CH0DONE_DEFAULT << 0) 10750 #define DMA_IFC_CH1DONE (0x1UL << 1) 10751 #define _DMA_IFC_CH1DONE_SHIFT 1 10752 #define _DMA_IFC_CH1DONE_MASK 0x2UL 10753 #define _DMA_IFC_CH1DONE_DEFAULT 0x00000000UL 10754 #define DMA_IFC_CH1DONE_DEFAULT (_DMA_IFC_CH1DONE_DEFAULT << 1) 10755 #define DMA_IFC_CH2DONE (0x1UL << 2) 10756 #define _DMA_IFC_CH2DONE_SHIFT 2 10757 #define _DMA_IFC_CH2DONE_MASK 0x4UL 10758 #define _DMA_IFC_CH2DONE_DEFAULT 0x00000000UL 10759 #define DMA_IFC_CH2DONE_DEFAULT (_DMA_IFC_CH2DONE_DEFAULT << 2) 10760 #define DMA_IFC_CH3DONE (0x1UL << 3) 10761 #define _DMA_IFC_CH3DONE_SHIFT 3 10762 #define _DMA_IFC_CH3DONE_MASK 0x8UL 10763 #define _DMA_IFC_CH3DONE_DEFAULT 0x00000000UL 10764 #define DMA_IFC_CH3DONE_DEFAULT (_DMA_IFC_CH3DONE_DEFAULT << 3) 10765 #define DMA_IFC_CH4DONE (0x1UL << 4) 10766 #define _DMA_IFC_CH4DONE_SHIFT 4 10767 #define _DMA_IFC_CH4DONE_MASK 0x10UL 10768 #define _DMA_IFC_CH4DONE_DEFAULT 0x00000000UL 10769 #define DMA_IFC_CH4DONE_DEFAULT (_DMA_IFC_CH4DONE_DEFAULT << 4) 10770 #define DMA_IFC_CH5DONE (0x1UL << 5) 10771 #define _DMA_IFC_CH5DONE_SHIFT 5 10772 #define _DMA_IFC_CH5DONE_MASK 0x20UL 10773 #define _DMA_IFC_CH5DONE_DEFAULT 0x00000000UL 10774 #define DMA_IFC_CH5DONE_DEFAULT (_DMA_IFC_CH5DONE_DEFAULT << 5) 10775 #define DMA_IFC_CH6DONE (0x1UL << 6) 10776 #define _DMA_IFC_CH6DONE_SHIFT 6 10777 #define _DMA_IFC_CH6DONE_MASK 0x40UL 10778 #define _DMA_IFC_CH6DONE_DEFAULT 0x00000000UL 10779 #define DMA_IFC_CH6DONE_DEFAULT (_DMA_IFC_CH6DONE_DEFAULT << 6) 10780 #define DMA_IFC_CH7DONE (0x1UL << 7) 10781 #define _DMA_IFC_CH7DONE_SHIFT 7 10782 #define _DMA_IFC_CH7DONE_MASK 0x80UL 10783 #define _DMA_IFC_CH7DONE_DEFAULT 0x00000000UL 10784 #define DMA_IFC_CH7DONE_DEFAULT (_DMA_IFC_CH7DONE_DEFAULT << 7) 10785 #define DMA_IFC_ERR (0x1UL << 31) 10786 #define _DMA_IFC_ERR_SHIFT 31 10787 #define _DMA_IFC_ERR_MASK 0x80000000UL 10788 #define _DMA_IFC_ERR_DEFAULT 0x00000000UL 10789 #define DMA_IFC_ERR_DEFAULT (_DMA_IFC_ERR_DEFAULT << 31) 10791 /* Bit fields for DMA IEN */ 10792 #define _DMA_IEN_RESETVALUE 0x00000000UL 10793 #define _DMA_IEN_MASK 0x800000FFUL 10794 #define DMA_IEN_CH0DONE (0x1UL << 0) 10795 #define _DMA_IEN_CH0DONE_SHIFT 0 10796 #define _DMA_IEN_CH0DONE_MASK 0x1UL 10797 #define _DMA_IEN_CH0DONE_DEFAULT 0x00000000UL 10798 #define DMA_IEN_CH0DONE_DEFAULT (_DMA_IEN_CH0DONE_DEFAULT << 0) 10799 #define DMA_IEN_CH1DONE (0x1UL << 1) 10800 #define _DMA_IEN_CH1DONE_SHIFT 1 10801 #define _DMA_IEN_CH1DONE_MASK 0x2UL 10802 #define _DMA_IEN_CH1DONE_DEFAULT 0x00000000UL 10803 #define DMA_IEN_CH1DONE_DEFAULT (_DMA_IEN_CH1DONE_DEFAULT << 1) 10804 #define DMA_IEN_CH2DONE (0x1UL << 2) 10805 #define _DMA_IEN_CH2DONE_SHIFT 2 10806 #define _DMA_IEN_CH2DONE_MASK 0x4UL 10807 #define _DMA_IEN_CH2DONE_DEFAULT 0x00000000UL 10808 #define DMA_IEN_CH2DONE_DEFAULT (_DMA_IEN_CH2DONE_DEFAULT << 2) 10809 #define DMA_IEN_CH3DONE (0x1UL << 3) 10810 #define _DMA_IEN_CH3DONE_SHIFT 3 10811 #define _DMA_IEN_CH3DONE_MASK 0x8UL 10812 #define _DMA_IEN_CH3DONE_DEFAULT 0x00000000UL 10813 #define DMA_IEN_CH3DONE_DEFAULT (_DMA_IEN_CH3DONE_DEFAULT << 3) 10814 #define DMA_IEN_CH4DONE (0x1UL << 4) 10815 #define _DMA_IEN_CH4DONE_SHIFT 4 10816 #define _DMA_IEN_CH4DONE_MASK 0x10UL 10817 #define _DMA_IEN_CH4DONE_DEFAULT 0x00000000UL 10818 #define DMA_IEN_CH4DONE_DEFAULT (_DMA_IEN_CH4DONE_DEFAULT << 4) 10819 #define DMA_IEN_CH5DONE (0x1UL << 5) 10820 #define _DMA_IEN_CH5DONE_SHIFT 5 10821 #define _DMA_IEN_CH5DONE_MASK 0x20UL 10822 #define _DMA_IEN_CH5DONE_DEFAULT 0x00000000UL 10823 #define DMA_IEN_CH5DONE_DEFAULT (_DMA_IEN_CH5DONE_DEFAULT << 5) 10824 #define DMA_IEN_CH6DONE (0x1UL << 6) 10825 #define _DMA_IEN_CH6DONE_SHIFT 6 10826 #define _DMA_IEN_CH6DONE_MASK 0x40UL 10827 #define _DMA_IEN_CH6DONE_DEFAULT 0x00000000UL 10828 #define DMA_IEN_CH6DONE_DEFAULT (_DMA_IEN_CH6DONE_DEFAULT << 6) 10829 #define DMA_IEN_CH7DONE (0x1UL << 7) 10830 #define _DMA_IEN_CH7DONE_SHIFT 7 10831 #define _DMA_IEN_CH7DONE_MASK 0x80UL 10832 #define _DMA_IEN_CH7DONE_DEFAULT 0x00000000UL 10833 #define DMA_IEN_CH7DONE_DEFAULT (_DMA_IEN_CH7DONE_DEFAULT << 7) 10834 #define DMA_IEN_ERR (0x1UL << 31) 10835 #define _DMA_IEN_ERR_SHIFT 31 10836 #define _DMA_IEN_ERR_MASK 0x80000000UL 10837 #define _DMA_IEN_ERR_DEFAULT 0x00000000UL 10838 #define DMA_IEN_ERR_DEFAULT (_DMA_IEN_ERR_DEFAULT << 31) 10840 /* Bit fields for DMA CH_CTRL */ 10841 #define _DMA_CH_CTRL_RESETVALUE 0x00000000UL 10842 #define _DMA_CH_CTRL_MASK 0x003F000FUL 10843 #define _DMA_CH_CTRL_SIGSEL_SHIFT 0 10844 #define _DMA_CH_CTRL_SIGSEL_MASK 0xFUL 10845 #define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL 10846 #define _DMA_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL 10847 #define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000000UL 10848 #define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000000UL 10849 #define _DMA_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000000UL 10850 #define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL 10851 #define _DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV 0x00000000UL 10852 #define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL 10853 #define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL 10854 #define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL 10855 #define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF 0x00000000UL 10856 #define _DMA_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000000UL 10857 #define _DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL 10858 #define _DMA_CH_CTRL_SIGSEL_AESDATAWR 0x00000000UL 10859 #define _DMA_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL 10860 #define _DMA_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL 10861 #define _DMA_CH_CTRL_SIGSEL_USART0TXBL 0x00000001UL 10862 #define _DMA_CH_CTRL_SIGSEL_USART1TXBL 0x00000001UL 10863 #define _DMA_CH_CTRL_SIGSEL_USART2TXBL 0x00000001UL 10864 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL 10865 #define _DMA_CH_CTRL_SIGSEL_LEUART1TXBL 0x00000001UL 10866 #define _DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL 10867 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL 10868 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL 10869 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC0 0x00000001UL 10870 #define _DMA_CH_CTRL_SIGSEL_UART0TXBL 0x00000001UL 10871 #define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR 0x00000001UL 10872 #define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY 0x00000002UL 10873 #define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 0x00000002UL 10874 #define _DMA_CH_CTRL_SIGSEL_USART2TXEMPTY 0x00000002UL 10875 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL 10876 #define _DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY 0x00000002UL 10877 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL 10878 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL 10879 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC1 0x00000002UL 10880 #define _DMA_CH_CTRL_SIGSEL_UART0TXEMPTY 0x00000002UL 10881 #define _DMA_CH_CTRL_SIGSEL_AESDATARD 0x00000002UL 10882 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL 10883 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL 10884 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC2 0x00000003UL 10885 #define _DMA_CH_CTRL_SIGSEL_AESKEYWR 0x00000003UL 10886 #define DMA_CH_CTRL_SIGSEL_ADC0SINGLE (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0) 10887 #define DMA_CH_CTRL_SIGSEL_DAC0CH0 (_DMA_CH_CTRL_SIGSEL_DAC0CH0 << 0) 10888 #define DMA_CH_CTRL_SIGSEL_USART0RXDATAV (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0) 10889 #define DMA_CH_CTRL_SIGSEL_USART1RXDATAV (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0) 10890 #define DMA_CH_CTRL_SIGSEL_USART2RXDATAV (_DMA_CH_CTRL_SIGSEL_USART2RXDATAV << 0) 10891 #define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0) 10892 #define DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV << 0) 10893 #define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0) 10894 #define DMA_CH_CTRL_SIGSEL_TIMER0UFOF (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0) 10895 #define DMA_CH_CTRL_SIGSEL_TIMER1UFOF (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0) 10896 #define DMA_CH_CTRL_SIGSEL_TIMER2UFOF (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0) 10897 #define DMA_CH_CTRL_SIGSEL_UART0RXDATAV (_DMA_CH_CTRL_SIGSEL_UART0RXDATAV << 0) 10898 #define DMA_CH_CTRL_SIGSEL_MSCWDATA (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0) 10899 #define DMA_CH_CTRL_SIGSEL_AESDATAWR (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0) 10900 #define DMA_CH_CTRL_SIGSEL_ADC0SCAN (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0) 10901 #define DMA_CH_CTRL_SIGSEL_DAC0CH1 (_DMA_CH_CTRL_SIGSEL_DAC0CH1 << 0) 10902 #define DMA_CH_CTRL_SIGSEL_USART0TXBL (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0) 10903 #define DMA_CH_CTRL_SIGSEL_USART1TXBL (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0) 10904 #define DMA_CH_CTRL_SIGSEL_USART2TXBL (_DMA_CH_CTRL_SIGSEL_USART2TXBL << 0) 10905 #define DMA_CH_CTRL_SIGSEL_LEUART0TXBL (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0) 10906 #define DMA_CH_CTRL_SIGSEL_LEUART1TXBL (_DMA_CH_CTRL_SIGSEL_LEUART1TXBL << 0) 10907 #define DMA_CH_CTRL_SIGSEL_I2C0TXBL (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0) 10908 #define DMA_CH_CTRL_SIGSEL_TIMER0CC0 (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0) 10909 #define DMA_CH_CTRL_SIGSEL_TIMER1CC0 (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0) 10910 #define DMA_CH_CTRL_SIGSEL_TIMER2CC0 (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0) 10911 #define DMA_CH_CTRL_SIGSEL_UART0TXBL (_DMA_CH_CTRL_SIGSEL_UART0TXBL << 0) 10912 #define DMA_CH_CTRL_SIGSEL_AESXORDATAWR (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0) 10913 #define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0) 10914 #define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0) 10915 #define DMA_CH_CTRL_SIGSEL_USART2TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART2TXEMPTY << 0) 10916 #define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0) 10917 #define DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY << 0) 10918 #define DMA_CH_CTRL_SIGSEL_TIMER0CC1 (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0) 10919 #define DMA_CH_CTRL_SIGSEL_TIMER1CC1 (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0) 10920 #define DMA_CH_CTRL_SIGSEL_TIMER2CC1 (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0) 10921 #define DMA_CH_CTRL_SIGSEL_UART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_UART0TXEMPTY << 0) 10922 #define DMA_CH_CTRL_SIGSEL_AESDATARD (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0) 10923 #define DMA_CH_CTRL_SIGSEL_TIMER0CC2 (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0) 10924 #define DMA_CH_CTRL_SIGSEL_TIMER1CC2 (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0) 10925 #define DMA_CH_CTRL_SIGSEL_TIMER2CC2 (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0) 10926 #define DMA_CH_CTRL_SIGSEL_AESKEYWR (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0) 10927 #define _DMA_CH_CTRL_SOURCESEL_SHIFT 16 10928 #define _DMA_CH_CTRL_SOURCESEL_MASK 0x3F0000UL 10929 #define _DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL 10930 #define _DMA_CH_CTRL_SOURCESEL_ADC0 0x00000008UL 10931 #define _DMA_CH_CTRL_SOURCESEL_DAC0 0x0000000AUL 10932 #define _DMA_CH_CTRL_SOURCESEL_USART0 0x0000000CUL 10933 #define _DMA_CH_CTRL_SOURCESEL_USART1 0x0000000DUL 10934 #define _DMA_CH_CTRL_SOURCESEL_USART2 0x0000000EUL 10935 #define _DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL 10936 #define _DMA_CH_CTRL_SOURCESEL_LEUART1 0x00000011UL 10937 #define _DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL 10938 #define _DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL 10939 #define _DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL 10940 #define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL 10941 #define _DMA_CH_CTRL_SOURCESEL_UART0 0x0000002CUL 10942 #define _DMA_CH_CTRL_SOURCESEL_MSC 0x00000030UL 10943 #define _DMA_CH_CTRL_SOURCESEL_AES 0x00000031UL 10944 #define DMA_CH_CTRL_SOURCESEL_NONE (_DMA_CH_CTRL_SOURCESEL_NONE << 16) 10945 #define DMA_CH_CTRL_SOURCESEL_ADC0 (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16) 10946 #define DMA_CH_CTRL_SOURCESEL_DAC0 (_DMA_CH_CTRL_SOURCESEL_DAC0 << 16) 10947 #define DMA_CH_CTRL_SOURCESEL_USART0 (_DMA_CH_CTRL_SOURCESEL_USART0 << 16) 10948 #define DMA_CH_CTRL_SOURCESEL_USART1 (_DMA_CH_CTRL_SOURCESEL_USART1 << 16) 10949 #define DMA_CH_CTRL_SOURCESEL_USART2 (_DMA_CH_CTRL_SOURCESEL_USART2 << 16) 10950 #define DMA_CH_CTRL_SOURCESEL_LEUART0 (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16) 10951 #define DMA_CH_CTRL_SOURCESEL_LEUART1 (_DMA_CH_CTRL_SOURCESEL_LEUART1 << 16) 10952 #define DMA_CH_CTRL_SOURCESEL_I2C0 (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16) 10953 #define DMA_CH_CTRL_SOURCESEL_TIMER0 (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16) 10954 #define DMA_CH_CTRL_SOURCESEL_TIMER1 (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16) 10955 #define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) 10956 #define DMA_CH_CTRL_SOURCESEL_UART0 (_DMA_CH_CTRL_SOURCESEL_UART0 << 16) 10957 #define DMA_CH_CTRL_SOURCESEL_MSC (_DMA_CH_CTRL_SOURCESEL_MSC << 16) 10958 #define DMA_CH_CTRL_SOURCESEL_AES (_DMA_CH_CTRL_SOURCESEL_AES << 16) 10964 /**************************************************************************/ 10969 /* Bit fields for VCMP CTRL */ 10970 #define _VCMP_CTRL_RESETVALUE 0x47000000UL 10971 #define _VCMP_CTRL_MASK 0x4F030715UL 10972 #define VCMP_CTRL_EN (0x1UL << 0) 10973 #define _VCMP_CTRL_EN_SHIFT 0 10974 #define _VCMP_CTRL_EN_MASK 0x1UL 10975 #define _VCMP_CTRL_EN_DEFAULT 0x00000000UL 10976 #define VCMP_CTRL_EN_DEFAULT (_VCMP_CTRL_EN_DEFAULT << 0) 10977 #define VCMP_CTRL_INACTVAL (0x1UL << 2) 10978 #define _VCMP_CTRL_INACTVAL_SHIFT 2 10979 #define _VCMP_CTRL_INACTVAL_MASK 0x4UL 10980 #define _VCMP_CTRL_INACTVAL_DEFAULT 0x00000000UL 10981 #define VCMP_CTRL_INACTVAL_DEFAULT (_VCMP_CTRL_INACTVAL_DEFAULT << 2) 10982 #define VCMP_CTRL_HYSTEN (0x1UL << 4) 10983 #define _VCMP_CTRL_HYSTEN_SHIFT 4 10984 #define _VCMP_CTRL_HYSTEN_MASK 0x10UL 10985 #define _VCMP_CTRL_HYSTEN_DEFAULT 0x00000000UL 10986 #define VCMP_CTRL_HYSTEN_DEFAULT (_VCMP_CTRL_HYSTEN_DEFAULT << 4) 10987 #define _VCMP_CTRL_WARMTIME_SHIFT 8 10988 #define _VCMP_CTRL_WARMTIME_MASK 0x700UL 10989 #define _VCMP_CTRL_WARMTIME_DEFAULT 0x00000000UL 10990 #define _VCMP_CTRL_WARMTIME_4CYCLES 0x00000000UL 10991 #define _VCMP_CTRL_WARMTIME_8CYCLES 0x00000001UL 10992 #define _VCMP_CTRL_WARMTIME_16CYCLES 0x00000002UL 10993 #define _VCMP_CTRL_WARMTIME_32CYCLES 0x00000003UL 10994 #define _VCMP_CTRL_WARMTIME_64CYCLES 0x00000004UL 10995 #define _VCMP_CTRL_WARMTIME_128CYCLES 0x00000005UL 10996 #define _VCMP_CTRL_WARMTIME_256CYCLES 0x00000006UL 10997 #define _VCMP_CTRL_WARMTIME_512CYCLES 0x00000007UL 10998 #define VCMP_CTRL_WARMTIME_DEFAULT (_VCMP_CTRL_WARMTIME_DEFAULT << 8) 10999 #define VCMP_CTRL_WARMTIME_4CYCLES (_VCMP_CTRL_WARMTIME_4CYCLES << 8) 11000 #define VCMP_CTRL_WARMTIME_8CYCLES (_VCMP_CTRL_WARMTIME_8CYCLES << 8) 11001 #define VCMP_CTRL_WARMTIME_16CYCLES (_VCMP_CTRL_WARMTIME_16CYCLES << 8) 11002 #define VCMP_CTRL_WARMTIME_32CYCLES (_VCMP_CTRL_WARMTIME_32CYCLES << 8) 11003 #define VCMP_CTRL_WARMTIME_64CYCLES (_VCMP_CTRL_WARMTIME_64CYCLES << 8) 11004 #define VCMP_CTRL_WARMTIME_128CYCLES (_VCMP_CTRL_WARMTIME_128CYCLES << 8) 11005 #define VCMP_CTRL_WARMTIME_256CYCLES (_VCMP_CTRL_WARMTIME_256CYCLES << 8) 11006 #define VCMP_CTRL_WARMTIME_512CYCLES (_VCMP_CTRL_WARMTIME_512CYCLES << 8) 11007 #define VCMP_CTRL_IRISE (0x1UL << 16) 11008 #define _VCMP_CTRL_IRISE_SHIFT 16 11009 #define _VCMP_CTRL_IRISE_MASK 0x10000UL 11010 #define _VCMP_CTRL_IRISE_DEFAULT 0x00000000UL 11011 #define VCMP_CTRL_IRISE_DEFAULT (_VCMP_CTRL_IRISE_DEFAULT << 16) 11012 #define VCMP_CTRL_IFALL (0x1UL << 17) 11013 #define _VCMP_CTRL_IFALL_SHIFT 17 11014 #define _VCMP_CTRL_IFALL_MASK 0x20000UL 11015 #define _VCMP_CTRL_IFALL_DEFAULT 0x00000000UL 11016 #define VCMP_CTRL_IFALL_DEFAULT (_VCMP_CTRL_IFALL_DEFAULT << 17) 11017 #define _VCMP_CTRL_BIASPROG_SHIFT 24 11018 #define _VCMP_CTRL_BIASPROG_MASK 0xF000000UL 11019 #define _VCMP_CTRL_BIASPROG_DEFAULT 0x00000007UL 11020 #define VCMP_CTRL_BIASPROG_DEFAULT (_VCMP_CTRL_BIASPROG_DEFAULT << 24) 11021 #define VCMP_CTRL_HALFBIAS (0x1UL << 30) 11022 #define _VCMP_CTRL_HALFBIAS_SHIFT 30 11023 #define _VCMP_CTRL_HALFBIAS_MASK 0x40000000UL 11024 #define _VCMP_CTRL_HALFBIAS_DEFAULT 0x00000001UL 11025 #define VCMP_CTRL_HALFBIAS_DEFAULT (_VCMP_CTRL_HALFBIAS_DEFAULT << 30) 11027 /* Bit fields for VCMP INPUTSEL */ 11028 #define _VCMP_INPUTSEL_RESETVALUE 0x00000000UL 11029 #define _VCMP_INPUTSEL_MASK 0x0000013FUL 11030 #define _VCMP_INPUTSEL_TRIGLEVEL_SHIFT 0 11031 #define _VCMP_INPUTSEL_TRIGLEVEL_MASK 0x3FUL 11032 #define _VCMP_INPUTSEL_TRIGLEVEL_DEFAULT 0x00000000UL 11033 #define VCMP_INPUTSEL_TRIGLEVEL_DEFAULT (_VCMP_INPUTSEL_TRIGLEVEL_DEFAULT << 0) 11034 #define VCMP_INPUTSEL_LPREF (0x1UL << 8) 11035 #define _VCMP_INPUTSEL_LPREF_SHIFT 8 11036 #define _VCMP_INPUTSEL_LPREF_MASK 0x100UL 11037 #define _VCMP_INPUTSEL_LPREF_DEFAULT 0x00000000UL 11038 #define VCMP_INPUTSEL_LPREF_DEFAULT (_VCMP_INPUTSEL_LPREF_DEFAULT << 8) 11040 /* Bit fields for VCMP STATUS */ 11041 #define _VCMP_STATUS_RESETVALUE 0x00000000UL 11042 #define _VCMP_STATUS_MASK 0x00000003UL 11043 #define VCMP_STATUS_VCMPACT (0x1UL << 0) 11044 #define _VCMP_STATUS_VCMPACT_SHIFT 0 11045 #define _VCMP_STATUS_VCMPACT_MASK 0x1UL 11046 #define _VCMP_STATUS_VCMPACT_DEFAULT 0x00000000UL 11047 #define VCMP_STATUS_VCMPACT_DEFAULT (_VCMP_STATUS_VCMPACT_DEFAULT << 0) 11048 #define VCMP_STATUS_VCMPOUT (0x1UL << 1) 11049 #define _VCMP_STATUS_VCMPOUT_SHIFT 1 11050 #define _VCMP_STATUS_VCMPOUT_MASK 0x2UL 11051 #define _VCMP_STATUS_VCMPOUT_DEFAULT 0x00000000UL 11052 #define VCMP_STATUS_VCMPOUT_DEFAULT (_VCMP_STATUS_VCMPOUT_DEFAULT << 1) 11054 /* Bit fields for VCMP IEN */ 11055 #define _VCMP_IEN_RESETVALUE 0x00000000UL 11056 #define _VCMP_IEN_MASK 0x00000003UL 11057 #define VCMP_IEN_EDGE (0x1UL << 0) 11058 #define _VCMP_IEN_EDGE_SHIFT 0 11059 #define _VCMP_IEN_EDGE_MASK 0x1UL 11060 #define _VCMP_IEN_EDGE_DEFAULT 0x00000000UL 11061 #define VCMP_IEN_EDGE_DEFAULT (_VCMP_IEN_EDGE_DEFAULT << 0) 11062 #define VCMP_IEN_WARMUP (0x1UL << 1) 11063 #define _VCMP_IEN_WARMUP_SHIFT 1 11064 #define _VCMP_IEN_WARMUP_MASK 0x2UL 11065 #define _VCMP_IEN_WARMUP_DEFAULT 0x00000000UL 11066 #define VCMP_IEN_WARMUP_DEFAULT (_VCMP_IEN_WARMUP_DEFAULT << 1) 11068 /* Bit fields for VCMP IF */ 11069 #define _VCMP_IF_RESETVALUE 0x00000000UL 11070 #define _VCMP_IF_MASK 0x00000003UL 11071 #define VCMP_IF_EDGE (0x1UL << 0) 11072 #define _VCMP_IF_EDGE_SHIFT 0 11073 #define _VCMP_IF_EDGE_MASK 0x1UL 11074 #define _VCMP_IF_EDGE_DEFAULT 0x00000000UL 11075 #define VCMP_IF_EDGE_DEFAULT (_VCMP_IF_EDGE_DEFAULT << 0) 11076 #define VCMP_IF_WARMUP (0x1UL << 1) 11077 #define _VCMP_IF_WARMUP_SHIFT 1 11078 #define _VCMP_IF_WARMUP_MASK 0x2UL 11079 #define _VCMP_IF_WARMUP_DEFAULT 0x00000000UL 11080 #define VCMP_IF_WARMUP_DEFAULT (_VCMP_IF_WARMUP_DEFAULT << 1) 11082 /* Bit fields for VCMP IFS */ 11083 #define _VCMP_IFS_RESETVALUE 0x00000000UL 11084 #define _VCMP_IFS_MASK 0x00000003UL 11085 #define VCMP_IFS_EDGE (0x1UL << 0) 11086 #define _VCMP_IFS_EDGE_SHIFT 0 11087 #define _VCMP_IFS_EDGE_MASK 0x1UL 11088 #define _VCMP_IFS_EDGE_DEFAULT 0x00000000UL 11089 #define VCMP_IFS_EDGE_DEFAULT (_VCMP_IFS_EDGE_DEFAULT << 0) 11090 #define VCMP_IFS_WARMUP (0x1UL << 1) 11091 #define _VCMP_IFS_WARMUP_SHIFT 1 11092 #define _VCMP_IFS_WARMUP_MASK 0x2UL 11093 #define _VCMP_IFS_WARMUP_DEFAULT 0x00000000UL 11094 #define VCMP_IFS_WARMUP_DEFAULT (_VCMP_IFS_WARMUP_DEFAULT << 1) 11096 /* Bit fields for VCMP IFC */ 11097 #define _VCMP_IFC_RESETVALUE 0x00000000UL 11098 #define _VCMP_IFC_MASK 0x00000003UL 11099 #define VCMP_IFC_EDGE (0x1UL << 0) 11100 #define _VCMP_IFC_EDGE_SHIFT 0 11101 #define _VCMP_IFC_EDGE_MASK 0x1UL 11102 #define _VCMP_IFC_EDGE_DEFAULT 0x00000000UL 11103 #define VCMP_IFC_EDGE_DEFAULT (_VCMP_IFC_EDGE_DEFAULT << 0) 11104 #define VCMP_IFC_WARMUP (0x1UL << 1) 11105 #define _VCMP_IFC_WARMUP_SHIFT 1 11106 #define _VCMP_IFC_WARMUP_MASK 0x2UL 11107 #define _VCMP_IFC_WARMUP_DEFAULT 0x00000000UL 11108 #define VCMP_IFC_WARMUP_DEFAULT (_VCMP_IFC_WARMUP_DEFAULT << 1) 11114 /**************************************************************************/ 11119 /* Bit fields for LCD CTRL */ 11120 #define _LCD_CTRL_RESETVALUE 0x00000000UL 11121 #define _LCD_CTRL_MASK 0x00000007UL 11122 #define LCD_CTRL_EN (0x1UL << 0) 11123 #define _LCD_CTRL_EN_SHIFT 0 11124 #define _LCD_CTRL_EN_MASK 0x1UL 11125 #define _LCD_CTRL_EN_DEFAULT 0x00000000UL 11126 #define LCD_CTRL_EN_DEFAULT (_LCD_CTRL_EN_DEFAULT << 0) 11127 #define _LCD_CTRL_UDCTRL_SHIFT 1 11128 #define _LCD_CTRL_UDCTRL_MASK 0x6UL 11129 #define _LCD_CTRL_UDCTRL_DEFAULT 0x00000000UL 11130 #define _LCD_CTRL_UDCTRL_REGULAR 0x00000000UL 11131 #define _LCD_CTRL_UDCTRL_FCEVENT 0x00000001UL 11132 #define _LCD_CTRL_UDCTRL_FRAMESTART 0x00000002UL 11133 #define LCD_CTRL_UDCTRL_DEFAULT (_LCD_CTRL_UDCTRL_DEFAULT << 1) 11134 #define LCD_CTRL_UDCTRL_REGULAR (_LCD_CTRL_UDCTRL_REGULAR << 1) 11135 #define LCD_CTRL_UDCTRL_FCEVENT (_LCD_CTRL_UDCTRL_FCEVENT << 1) 11136 #define LCD_CTRL_UDCTRL_FRAMESTART (_LCD_CTRL_UDCTRL_FRAMESTART << 1) 11138 /* Bit fields for LCD DISPCTRL */ 11139 #define _LCD_DISPCTRL_RESETVALUE 0x000C1F00UL 11140 #define _LCD_DISPCTRL_MASK 0x001D9F1FUL 11141 #define _LCD_DISPCTRL_MUX_SHIFT 0 11142 #define _LCD_DISPCTRL_MUX_MASK 0x3UL 11143 #define _LCD_DISPCTRL_MUX_DEFAULT 0x00000000UL 11144 #define _LCD_DISPCTRL_MUX_STATIC 0x00000000UL 11145 #define _LCD_DISPCTRL_MUX_DUPLEX 0x00000001UL 11146 #define _LCD_DISPCTRL_MUX_TRIPLEX 0x00000002UL 11147 #define _LCD_DISPCTRL_MUX_QUADRUPLEX 0x00000003UL 11148 #define LCD_DISPCTRL_MUX_DEFAULT (_LCD_DISPCTRL_MUX_DEFAULT << 0) 11149 #define LCD_DISPCTRL_MUX_STATIC (_LCD_DISPCTRL_MUX_STATIC << 0) 11150 #define LCD_DISPCTRL_MUX_DUPLEX (_LCD_DISPCTRL_MUX_DUPLEX << 0) 11151 #define LCD_DISPCTRL_MUX_TRIPLEX (_LCD_DISPCTRL_MUX_TRIPLEX << 0) 11152 #define LCD_DISPCTRL_MUX_QUADRUPLEX (_LCD_DISPCTRL_MUX_QUADRUPLEX << 0) 11153 #define _LCD_DISPCTRL_BIAS_SHIFT 2 11154 #define _LCD_DISPCTRL_BIAS_MASK 0xCUL 11155 #define _LCD_DISPCTRL_BIAS_DEFAULT 0x00000000UL 11156 #define _LCD_DISPCTRL_BIAS_STATIC 0x00000000UL 11157 #define _LCD_DISPCTRL_BIAS_ONEHALF 0x00000001UL 11158 #define _LCD_DISPCTRL_BIAS_ONETHIRD 0x00000002UL 11159 #define LCD_DISPCTRL_BIAS_DEFAULT (_LCD_DISPCTRL_BIAS_DEFAULT << 2) 11160 #define LCD_DISPCTRL_BIAS_STATIC (_LCD_DISPCTRL_BIAS_STATIC << 2) 11161 #define LCD_DISPCTRL_BIAS_ONEHALF (_LCD_DISPCTRL_BIAS_ONEHALF << 2) 11162 #define LCD_DISPCTRL_BIAS_ONETHIRD (_LCD_DISPCTRL_BIAS_ONETHIRD << 2) 11163 #define LCD_DISPCTRL_WAVE (0x1UL << 4) 11164 #define _LCD_DISPCTRL_WAVE_SHIFT 4 11165 #define _LCD_DISPCTRL_WAVE_MASK 0x10UL 11166 #define _LCD_DISPCTRL_WAVE_DEFAULT 0x00000000UL 11167 #define _LCD_DISPCTRL_WAVE_LOWPOWER 0x00000000UL 11168 #define _LCD_DISPCTRL_WAVE_NORMAL 0x00000001UL 11169 #define LCD_DISPCTRL_WAVE_DEFAULT (_LCD_DISPCTRL_WAVE_DEFAULT << 4) 11170 #define LCD_DISPCTRL_WAVE_LOWPOWER (_LCD_DISPCTRL_WAVE_LOWPOWER << 4) 11171 #define LCD_DISPCTRL_WAVE_NORMAL (_LCD_DISPCTRL_WAVE_NORMAL << 4) 11172 #define _LCD_DISPCTRL_CONLEV_SHIFT 8 11173 #define _LCD_DISPCTRL_CONLEV_MASK 0x1F00UL 11174 #define _LCD_DISPCTRL_CONLEV_MIN 0x00000000UL 11175 #define _LCD_DISPCTRL_CONLEV_DEFAULT 0x0000001FUL 11176 #define _LCD_DISPCTRL_CONLEV_MAX 0x0000001FUL 11177 #define LCD_DISPCTRL_CONLEV_MIN (_LCD_DISPCTRL_CONLEV_MIN << 8) 11178 #define LCD_DISPCTRL_CONLEV_DEFAULT (_LCD_DISPCTRL_CONLEV_DEFAULT << 8) 11179 #define LCD_DISPCTRL_CONLEV_MAX (_LCD_DISPCTRL_CONLEV_MAX << 8) 11180 #define LCD_DISPCTRL_CONCONF (0x1UL << 15) 11181 #define _LCD_DISPCTRL_CONCONF_SHIFT 15 11182 #define _LCD_DISPCTRL_CONCONF_MASK 0x8000UL 11183 #define _LCD_DISPCTRL_CONCONF_DEFAULT 0x00000000UL 11184 #define _LCD_DISPCTRL_CONCONF_VLCD 0x00000000UL 11185 #define _LCD_DISPCTRL_CONCONF_GND 0x00000001UL 11186 #define LCD_DISPCTRL_CONCONF_DEFAULT (_LCD_DISPCTRL_CONCONF_DEFAULT << 15) 11187 #define LCD_DISPCTRL_CONCONF_VLCD (_LCD_DISPCTRL_CONCONF_VLCD << 15) 11188 #define LCD_DISPCTRL_CONCONF_GND (_LCD_DISPCTRL_CONCONF_GND << 15) 11189 #define LCD_DISPCTRL_VLCDSEL (0x1UL << 16) 11190 #define _LCD_DISPCTRL_VLCDSEL_SHIFT 16 11191 #define _LCD_DISPCTRL_VLCDSEL_MASK 0x10000UL 11192 #define _LCD_DISPCTRL_VLCDSEL_DEFAULT 0x00000000UL 11193 #define _LCD_DISPCTRL_VLCDSEL_VDD 0x00000000UL 11194 #define _LCD_DISPCTRL_VLCDSEL_VEXTBOOST 0x00000001UL 11195 #define LCD_DISPCTRL_VLCDSEL_DEFAULT (_LCD_DISPCTRL_VLCDSEL_DEFAULT << 16) 11196 #define LCD_DISPCTRL_VLCDSEL_VDD (_LCD_DISPCTRL_VLCDSEL_VDD << 16) 11197 #define LCD_DISPCTRL_VLCDSEL_VEXTBOOST (_LCD_DISPCTRL_VLCDSEL_VEXTBOOST << 16) 11198 #define _LCD_DISPCTRL_VBLEV_SHIFT 18 11199 #define _LCD_DISPCTRL_VBLEV_MASK 0x1C0000UL 11200 #define _LCD_DISPCTRL_VBLEV_LEVEL0 0x00000000UL 11201 #define _LCD_DISPCTRL_VBLEV_LEVEL1 0x00000001UL 11202 #define _LCD_DISPCTRL_VBLEV_LEVEL2 0x00000002UL 11203 #define _LCD_DISPCTRL_VBLEV_DEFAULT 0x00000003UL 11204 #define _LCD_DISPCTRL_VBLEV_LEVEL3 0x00000003UL 11205 #define _LCD_DISPCTRL_VBLEV_LEVEL4 0x00000004UL 11206 #define _LCD_DISPCTRL_VBLEV_LEVEL5 0x00000005UL 11207 #define _LCD_DISPCTRL_VBLEV_LEVEL6 0x00000006UL 11208 #define _LCD_DISPCTRL_VBLEV_LEVEL7 0x00000007UL 11209 #define LCD_DISPCTRL_VBLEV_LEVEL0 (_LCD_DISPCTRL_VBLEV_LEVEL0 << 18) 11210 #define LCD_DISPCTRL_VBLEV_LEVEL1 (_LCD_DISPCTRL_VBLEV_LEVEL1 << 18) 11211 #define LCD_DISPCTRL_VBLEV_LEVEL2 (_LCD_DISPCTRL_VBLEV_LEVEL2 << 18) 11212 #define LCD_DISPCTRL_VBLEV_DEFAULT (_LCD_DISPCTRL_VBLEV_DEFAULT << 18) 11213 #define LCD_DISPCTRL_VBLEV_LEVEL3 (_LCD_DISPCTRL_VBLEV_LEVEL3 << 18) 11214 #define LCD_DISPCTRL_VBLEV_LEVEL4 (_LCD_DISPCTRL_VBLEV_LEVEL4 << 18) 11215 #define LCD_DISPCTRL_VBLEV_LEVEL5 (_LCD_DISPCTRL_VBLEV_LEVEL5 << 18) 11216 #define LCD_DISPCTRL_VBLEV_LEVEL6 (_LCD_DISPCTRL_VBLEV_LEVEL6 << 18) 11217 #define LCD_DISPCTRL_VBLEV_LEVEL7 (_LCD_DISPCTRL_VBLEV_LEVEL7 << 18) 11219 /* Bit fields for LCD SEGEN */ 11220 #define _LCD_SEGEN_RESETVALUE 0x00000000UL 11221 #define _LCD_SEGEN_MASK 0x000003FFUL 11222 #define _LCD_SEGEN_SEGEN_SHIFT 0 11223 #define _LCD_SEGEN_SEGEN_MASK 0x3FFUL 11224 #define _LCD_SEGEN_SEGEN_DEFAULT 0x00000000UL 11225 #define LCD_SEGEN_SEGEN_DEFAULT (_LCD_SEGEN_SEGEN_DEFAULT << 0) 11227 /* Bit fields for LCD BACTRL */ 11228 #define _LCD_BACTRL_RESETVALUE 0x00000000UL 11229 #define _LCD_BACTRL_MASK 0x00FF01FFUL 11230 #define LCD_BACTRL_BLINKEN (0x1UL << 0) 11231 #define _LCD_BACTRL_BLINKEN_SHIFT 0 11232 #define _LCD_BACTRL_BLINKEN_MASK 0x1UL 11233 #define _LCD_BACTRL_BLINKEN_DEFAULT 0x00000000UL 11234 #define LCD_BACTRL_BLINKEN_DEFAULT (_LCD_BACTRL_BLINKEN_DEFAULT << 0) 11235 #define LCD_BACTRL_BLANK (0x1UL << 1) 11236 #define _LCD_BACTRL_BLANK_SHIFT 1 11237 #define _LCD_BACTRL_BLANK_MASK 0x2UL 11238 #define _LCD_BACTRL_BLANK_DEFAULT 0x00000000UL 11239 #define LCD_BACTRL_BLANK_DEFAULT (_LCD_BACTRL_BLANK_DEFAULT << 1) 11240 #define LCD_BACTRL_AEN (0x1UL << 2) 11241 #define _LCD_BACTRL_AEN_SHIFT 2 11242 #define _LCD_BACTRL_AEN_MASK 0x4UL 11243 #define _LCD_BACTRL_AEN_DEFAULT 0x00000000UL 11244 #define LCD_BACTRL_AEN_DEFAULT (_LCD_BACTRL_AEN_DEFAULT << 2) 11245 #define _LCD_BACTRL_AREGASC_SHIFT 3 11246 #define _LCD_BACTRL_AREGASC_MASK 0x18UL 11247 #define _LCD_BACTRL_AREGASC_DEFAULT 0x00000000UL 11248 #define _LCD_BACTRL_AREGASC_NOSHIFT 0x00000000UL 11249 #define _LCD_BACTRL_AREGASC_SHIFTLEFT 0x00000001UL 11250 #define _LCD_BACTRL_AREGASC_SHIFTRIGHT 0x00000002UL 11251 #define LCD_BACTRL_AREGASC_DEFAULT (_LCD_BACTRL_AREGASC_DEFAULT << 3) 11252 #define LCD_BACTRL_AREGASC_NOSHIFT (_LCD_BACTRL_AREGASC_NOSHIFT << 3) 11253 #define LCD_BACTRL_AREGASC_SHIFTLEFT (_LCD_BACTRL_AREGASC_SHIFTLEFT << 3) 11254 #define LCD_BACTRL_AREGASC_SHIFTRIGHT (_LCD_BACTRL_AREGASC_SHIFTRIGHT << 3) 11255 #define _LCD_BACTRL_AREGBSC_SHIFT 5 11256 #define _LCD_BACTRL_AREGBSC_MASK 0x60UL 11257 #define _LCD_BACTRL_AREGBSC_DEFAULT 0x00000000UL 11258 #define _LCD_BACTRL_AREGBSC_NOSHIFT 0x00000000UL 11259 #define _LCD_BACTRL_AREGBSC_SHIFTLEFT 0x00000001UL 11260 #define _LCD_BACTRL_AREGBSC_SHIFTRIGHT 0x00000002UL 11261 #define LCD_BACTRL_AREGBSC_DEFAULT (_LCD_BACTRL_AREGBSC_DEFAULT << 5) 11262 #define LCD_BACTRL_AREGBSC_NOSHIFT (_LCD_BACTRL_AREGBSC_NOSHIFT << 5) 11263 #define LCD_BACTRL_AREGBSC_SHIFTLEFT (_LCD_BACTRL_AREGBSC_SHIFTLEFT << 5) 11264 #define LCD_BACTRL_AREGBSC_SHIFTRIGHT (_LCD_BACTRL_AREGBSC_SHIFTRIGHT << 5) 11265 #define LCD_BACTRL_ALOGSEL (0x1UL << 7) 11266 #define _LCD_BACTRL_ALOGSEL_SHIFT 7 11267 #define _LCD_BACTRL_ALOGSEL_MASK 0x80UL 11268 #define _LCD_BACTRL_ALOGSEL_DEFAULT 0x00000000UL 11269 #define _LCD_BACTRL_ALOGSEL_AND 0x00000000UL 11270 #define _LCD_BACTRL_ALOGSEL_OR 0x00000001UL 11271 #define LCD_BACTRL_ALOGSEL_DEFAULT (_LCD_BACTRL_ALOGSEL_DEFAULT << 7) 11272 #define LCD_BACTRL_ALOGSEL_AND (_LCD_BACTRL_ALOGSEL_AND << 7) 11273 #define LCD_BACTRL_ALOGSEL_OR (_LCD_BACTRL_ALOGSEL_OR << 7) 11274 #define LCD_BACTRL_FCEN (0x1UL << 8) 11275 #define _LCD_BACTRL_FCEN_SHIFT 8 11276 #define _LCD_BACTRL_FCEN_MASK 0x100UL 11277 #define _LCD_BACTRL_FCEN_DEFAULT 0x00000000UL 11278 #define LCD_BACTRL_FCEN_DEFAULT (_LCD_BACTRL_FCEN_DEFAULT << 8) 11279 #define _LCD_BACTRL_FCPRESC_SHIFT 16 11280 #define _LCD_BACTRL_FCPRESC_MASK 0x30000UL 11281 #define _LCD_BACTRL_FCPRESC_DEFAULT 0x00000000UL 11282 #define _LCD_BACTRL_FCPRESC_DIV1 0x00000000UL 11283 #define _LCD_BACTRL_FCPRESC_DIV2 0x00000001UL 11284 #define _LCD_BACTRL_FCPRESC_DIV4 0x00000002UL 11285 #define _LCD_BACTRL_FCPRESC_DIV8 0x00000003UL 11286 #define LCD_BACTRL_FCPRESC_DEFAULT (_LCD_BACTRL_FCPRESC_DEFAULT << 16) 11287 #define LCD_BACTRL_FCPRESC_DIV1 (_LCD_BACTRL_FCPRESC_DIV1 << 16) 11288 #define LCD_BACTRL_FCPRESC_DIV2 (_LCD_BACTRL_FCPRESC_DIV2 << 16) 11289 #define LCD_BACTRL_FCPRESC_DIV4 (_LCD_BACTRL_FCPRESC_DIV4 << 16) 11290 #define LCD_BACTRL_FCPRESC_DIV8 (_LCD_BACTRL_FCPRESC_DIV8 << 16) 11291 #define _LCD_BACTRL_FCTOP_SHIFT 18 11292 #define _LCD_BACTRL_FCTOP_MASK 0xFC0000UL 11293 #define _LCD_BACTRL_FCTOP_DEFAULT 0x00000000UL 11294 #define LCD_BACTRL_FCTOP_DEFAULT (_LCD_BACTRL_FCTOP_DEFAULT << 18) 11296 /* Bit fields for LCD STATUS */ 11297 #define _LCD_STATUS_RESETVALUE 0x00000000UL 11298 #define _LCD_STATUS_MASK 0x0000010FUL 11299 #define _LCD_STATUS_ASTATE_SHIFT 0 11300 #define _LCD_STATUS_ASTATE_MASK 0xFUL 11301 #define _LCD_STATUS_ASTATE_DEFAULT 0x00000000UL 11302 #define LCD_STATUS_ASTATE_DEFAULT (_LCD_STATUS_ASTATE_DEFAULT << 0) 11303 #define LCD_STATUS_BLINK (0x1UL << 8) 11304 #define _LCD_STATUS_BLINK_SHIFT 8 11305 #define _LCD_STATUS_BLINK_MASK 0x100UL 11306 #define _LCD_STATUS_BLINK_DEFAULT 0x00000000UL 11307 #define LCD_STATUS_BLINK_DEFAULT (_LCD_STATUS_BLINK_DEFAULT << 8) 11309 /* Bit fields for LCD AREGA */ 11310 #define _LCD_AREGA_RESETVALUE 0x00000000UL 11311 #define _LCD_AREGA_MASK 0x000000FFUL 11312 #define _LCD_AREGA_AREGA_SHIFT 0 11313 #define _LCD_AREGA_AREGA_MASK 0xFFUL 11314 #define _LCD_AREGA_AREGA_DEFAULT 0x00000000UL 11315 #define LCD_AREGA_AREGA_DEFAULT (_LCD_AREGA_AREGA_DEFAULT << 0) 11317 /* Bit fields for LCD AREGB */ 11318 #define _LCD_AREGB_RESETVALUE 0x00000000UL 11319 #define _LCD_AREGB_MASK 0x000000FFUL 11320 #define _LCD_AREGB_AREGB_SHIFT 0 11321 #define _LCD_AREGB_AREGB_MASK 0xFFUL 11322 #define _LCD_AREGB_AREGB_DEFAULT 0x00000000UL 11323 #define LCD_AREGB_AREGB_DEFAULT (_LCD_AREGB_AREGB_DEFAULT << 0) 11325 /* Bit fields for LCD IF */ 11326 #define _LCD_IF_RESETVALUE 0x00000000UL 11327 #define _LCD_IF_MASK 0x00000001UL 11328 #define LCD_IF_FC (0x1UL << 0) 11329 #define _LCD_IF_FC_SHIFT 0 11330 #define _LCD_IF_FC_MASK 0x1UL 11331 #define _LCD_IF_FC_DEFAULT 0x00000000UL 11332 #define LCD_IF_FC_DEFAULT (_LCD_IF_FC_DEFAULT << 0) 11334 /* Bit fields for LCD IFS */ 11335 #define _LCD_IFS_RESETVALUE 0x00000000UL 11336 #define _LCD_IFS_MASK 0x00000001UL 11337 #define LCD_IFS_FC (0x1UL << 0) 11338 #define _LCD_IFS_FC_SHIFT 0 11339 #define _LCD_IFS_FC_MASK 0x1UL 11340 #define _LCD_IFS_FC_DEFAULT 0x00000000UL 11341 #define LCD_IFS_FC_DEFAULT (_LCD_IFS_FC_DEFAULT << 0) 11343 /* Bit fields for LCD IFC */ 11344 #define _LCD_IFC_RESETVALUE 0x00000000UL 11345 #define _LCD_IFC_MASK 0x00000001UL 11346 #define LCD_IFC_FC (0x1UL << 0) 11347 #define _LCD_IFC_FC_SHIFT 0 11348 #define _LCD_IFC_FC_MASK 0x1UL 11349 #define _LCD_IFC_FC_DEFAULT 0x00000000UL 11350 #define LCD_IFC_FC_DEFAULT (_LCD_IFC_FC_DEFAULT << 0) 11352 /* Bit fields for LCD IEN */ 11353 #define _LCD_IEN_RESETVALUE 0x00000000UL 11354 #define _LCD_IEN_MASK 0x00000001UL 11355 #define LCD_IEN_FC (0x1UL << 0) 11356 #define _LCD_IEN_FC_SHIFT 0 11357 #define _LCD_IEN_FC_MASK 0x1UL 11358 #define _LCD_IEN_FC_DEFAULT 0x00000000UL 11359 #define LCD_IEN_FC_DEFAULT (_LCD_IEN_FC_DEFAULT << 0) 11361 /* Bit fields for LCD SEGD0L */ 11362 #define _LCD_SEGD0L_RESETVALUE 0x00000000UL 11363 #define _LCD_SEGD0L_MASK 0xFFFFFFFFUL 11364 #define _LCD_SEGD0L_SEGD0L_SHIFT 0 11365 #define _LCD_SEGD0L_SEGD0L_MASK 0xFFFFFFFFUL 11366 #define _LCD_SEGD0L_SEGD0L_DEFAULT 0x00000000UL 11367 #define LCD_SEGD0L_SEGD0L_DEFAULT (_LCD_SEGD0L_SEGD0L_DEFAULT << 0) 11369 /* Bit fields for LCD SEGD1L */ 11370 #define _LCD_SEGD1L_RESETVALUE 0x00000000UL 11371 #define _LCD_SEGD1L_MASK 0xFFFFFFFFUL 11372 #define _LCD_SEGD1L_SEGD1L_SHIFT 0 11373 #define _LCD_SEGD1L_SEGD1L_MASK 0xFFFFFFFFUL 11374 #define _LCD_SEGD1L_SEGD1L_DEFAULT 0x00000000UL 11375 #define LCD_SEGD1L_SEGD1L_DEFAULT (_LCD_SEGD1L_SEGD1L_DEFAULT << 0) 11377 /* Bit fields for LCD SEGD2L */ 11378 #define _LCD_SEGD2L_RESETVALUE 0x00000000UL 11379 #define _LCD_SEGD2L_MASK 0xFFFFFFFFUL 11380 #define _LCD_SEGD2L_SEGD2L_SHIFT 0 11381 #define _LCD_SEGD2L_SEGD2L_MASK 0xFFFFFFFFUL 11382 #define _LCD_SEGD2L_SEGD2L_DEFAULT 0x00000000UL 11383 #define LCD_SEGD2L_SEGD2L_DEFAULT (_LCD_SEGD2L_SEGD2L_DEFAULT << 0) 11385 /* Bit fields for LCD SEGD3L */ 11386 #define _LCD_SEGD3L_RESETVALUE 0x00000000UL 11387 #define _LCD_SEGD3L_MASK 0xFFFFFFFFUL 11388 #define _LCD_SEGD3L_SEGD3L_SHIFT 0 11389 #define _LCD_SEGD3L_SEGD3L_MASK 0xFFFFFFFFUL 11390 #define _LCD_SEGD3L_SEGD3L_DEFAULT 0x00000000UL 11391 #define LCD_SEGD3L_SEGD3L_DEFAULT (_LCD_SEGD3L_SEGD3L_DEFAULT << 0) 11393 /* Bit fields for LCD SEGD0H */ 11394 #define _LCD_SEGD0H_RESETVALUE 0x00000000UL 11395 #define _LCD_SEGD0H_MASK 0x000000FFUL 11396 #define _LCD_SEGD0H_SEGD0H_SHIFT 0 11397 #define _LCD_SEGD0H_SEGD0H_MASK 0xFFUL 11398 #define _LCD_SEGD0H_SEGD0H_DEFAULT 0x00000000UL 11399 #define LCD_SEGD0H_SEGD0H_DEFAULT (_LCD_SEGD0H_SEGD0H_DEFAULT << 0) 11401 /* Bit fields for LCD SEGD1H */ 11402 #define _LCD_SEGD1H_RESETVALUE 0x00000000UL 11403 #define _LCD_SEGD1H_MASK 0x000000FFUL 11404 #define _LCD_SEGD1H_SEGD1H_SHIFT 0 11405 #define _LCD_SEGD1H_SEGD1H_MASK 0xFFUL 11406 #define _LCD_SEGD1H_SEGD1H_DEFAULT 0x00000000UL 11407 #define LCD_SEGD1H_SEGD1H_DEFAULT (_LCD_SEGD1H_SEGD1H_DEFAULT << 0) 11409 /* Bit fields for LCD SEGD2H */ 11410 #define _LCD_SEGD2H_RESETVALUE 0x00000000UL 11411 #define _LCD_SEGD2H_MASK 0x000000FFUL 11412 #define _LCD_SEGD2H_SEGD2H_SHIFT 0 11413 #define _LCD_SEGD2H_SEGD2H_MASK 0xFFUL 11414 #define _LCD_SEGD2H_SEGD2H_DEFAULT 0x00000000UL 11415 #define LCD_SEGD2H_SEGD2H_DEFAULT (_LCD_SEGD2H_SEGD2H_DEFAULT << 0) 11417 /* Bit fields for LCD SEGD3H */ 11418 #define _LCD_SEGD3H_RESETVALUE 0x00000000UL 11419 #define _LCD_SEGD3H_MASK 0x000000FFUL 11420 #define _LCD_SEGD3H_SEGD3H_SHIFT 0 11421 #define _LCD_SEGD3H_SEGD3H_MASK 0xFFUL 11422 #define _LCD_SEGD3H_SEGD3H_DEFAULT 0x00000000UL 11423 #define LCD_SEGD3H_SEGD3H_DEFAULT (_LCD_SEGD3H_SEGD3H_DEFAULT << 0) 11425 /* Bit fields for LCD FREEZE */ 11426 #define _LCD_FREEZE_RESETVALUE 0x00000000UL 11427 #define _LCD_FREEZE_MASK 0x00000001UL 11428 #define LCD_FREEZE_REGFREEZE (0x1UL << 0) 11429 #define _LCD_FREEZE_REGFREEZE_SHIFT 0 11430 #define _LCD_FREEZE_REGFREEZE_MASK 0x1UL 11431 #define _LCD_FREEZE_REGFREEZE_DEFAULT 0x00000000UL 11432 #define _LCD_FREEZE_REGFREEZE_UPDATE 0x00000000UL 11433 #define _LCD_FREEZE_REGFREEZE_FREEZE 0x00000001UL 11434 #define LCD_FREEZE_REGFREEZE_DEFAULT (_LCD_FREEZE_REGFREEZE_DEFAULT << 0) 11435 #define LCD_FREEZE_REGFREEZE_UPDATE (_LCD_FREEZE_REGFREEZE_UPDATE << 0) 11436 #define LCD_FREEZE_REGFREEZE_FREEZE (_LCD_FREEZE_REGFREEZE_FREEZE << 0) 11438 /* Bit fields for LCD SYNCBUSY */ 11439 #define _LCD_SYNCBUSY_RESETVALUE 0x00000000UL 11440 #define _LCD_SYNCBUSY_MASK 0x00000FFFUL 11441 #define LCD_SYNCBUSY_CTRL (0x1UL << 0) 11442 #define _LCD_SYNCBUSY_CTRL_SHIFT 0 11443 #define _LCD_SYNCBUSY_CTRL_MASK 0x1UL 11444 #define _LCD_SYNCBUSY_CTRL_DEFAULT 0x00000000UL 11445 #define LCD_SYNCBUSY_CTRL_DEFAULT (_LCD_SYNCBUSY_CTRL_DEFAULT << 0) 11446 #define LCD_SYNCBUSY_BACTRL (0x1UL << 1) 11447 #define _LCD_SYNCBUSY_BACTRL_SHIFT 1 11448 #define _LCD_SYNCBUSY_BACTRL_MASK 0x2UL 11449 #define _LCD_SYNCBUSY_BACTRL_DEFAULT 0x00000000UL 11450 #define LCD_SYNCBUSY_BACTRL_DEFAULT (_LCD_SYNCBUSY_BACTRL_DEFAULT << 1) 11451 #define LCD_SYNCBUSY_AREGA (0x1UL << 2) 11452 #define _LCD_SYNCBUSY_AREGA_SHIFT 2 11453 #define _LCD_SYNCBUSY_AREGA_MASK 0x4UL 11454 #define _LCD_SYNCBUSY_AREGA_DEFAULT 0x00000000UL 11455 #define LCD_SYNCBUSY_AREGA_DEFAULT (_LCD_SYNCBUSY_AREGA_DEFAULT << 2) 11456 #define LCD_SYNCBUSY_AREGB (0x1UL << 3) 11457 #define _LCD_SYNCBUSY_AREGB_SHIFT 3 11458 #define _LCD_SYNCBUSY_AREGB_MASK 0x8UL 11459 #define _LCD_SYNCBUSY_AREGB_DEFAULT 0x00000000UL 11460 #define LCD_SYNCBUSY_AREGB_DEFAULT (_LCD_SYNCBUSY_AREGB_DEFAULT << 3) 11461 #define LCD_SYNCBUSY_SEGD0L (0x1UL << 4) 11462 #define _LCD_SYNCBUSY_SEGD0L_SHIFT 4 11463 #define _LCD_SYNCBUSY_SEGD0L_MASK 0x10UL 11464 #define _LCD_SYNCBUSY_SEGD0L_DEFAULT 0x00000000UL 11465 #define LCD_SYNCBUSY_SEGD0L_DEFAULT (_LCD_SYNCBUSY_SEGD0L_DEFAULT << 4) 11466 #define LCD_SYNCBUSY_SEGD1L (0x1UL << 5) 11467 #define _LCD_SYNCBUSY_SEGD1L_SHIFT 5 11468 #define _LCD_SYNCBUSY_SEGD1L_MASK 0x20UL 11469 #define _LCD_SYNCBUSY_SEGD1L_DEFAULT 0x00000000UL 11470 #define LCD_SYNCBUSY_SEGD1L_DEFAULT (_LCD_SYNCBUSY_SEGD1L_DEFAULT << 5) 11471 #define LCD_SYNCBUSY_SEGD2L (0x1UL << 6) 11472 #define _LCD_SYNCBUSY_SEGD2L_SHIFT 6 11473 #define _LCD_SYNCBUSY_SEGD2L_MASK 0x40UL 11474 #define _LCD_SYNCBUSY_SEGD2L_DEFAULT 0x00000000UL 11475 #define LCD_SYNCBUSY_SEGD2L_DEFAULT (_LCD_SYNCBUSY_SEGD2L_DEFAULT << 6) 11476 #define LCD_SYNCBUSY_SEGD3L (0x1UL << 7) 11477 #define _LCD_SYNCBUSY_SEGD3L_SHIFT 7 11478 #define _LCD_SYNCBUSY_SEGD3L_MASK 0x80UL 11479 #define _LCD_SYNCBUSY_SEGD3L_DEFAULT 0x00000000UL 11480 #define LCD_SYNCBUSY_SEGD3L_DEFAULT (_LCD_SYNCBUSY_SEGD3L_DEFAULT << 7) 11481 #define LCD_SYNCBUSY_SEGD0H (0x1UL << 8) 11482 #define _LCD_SYNCBUSY_SEGD0H_SHIFT 8 11483 #define _LCD_SYNCBUSY_SEGD0H_MASK 0x100UL 11484 #define _LCD_SYNCBUSY_SEGD0H_DEFAULT 0x00000000UL 11485 #define LCD_SYNCBUSY_SEGD0H_DEFAULT (_LCD_SYNCBUSY_SEGD0H_DEFAULT << 8) 11486 #define LCD_SYNCBUSY_SEGD1H (0x1UL << 9) 11487 #define _LCD_SYNCBUSY_SEGD1H_SHIFT 9 11488 #define _LCD_SYNCBUSY_SEGD1H_MASK 0x200UL 11489 #define _LCD_SYNCBUSY_SEGD1H_DEFAULT 0x00000000UL 11490 #define LCD_SYNCBUSY_SEGD1H_DEFAULT (_LCD_SYNCBUSY_SEGD1H_DEFAULT << 9) 11491 #define LCD_SYNCBUSY_SEGD2H (0x1UL << 10) 11492 #define _LCD_SYNCBUSY_SEGD2H_SHIFT 10 11493 #define _LCD_SYNCBUSY_SEGD2H_MASK 0x400UL 11494 #define _LCD_SYNCBUSY_SEGD2H_DEFAULT 0x00000000UL 11495 #define LCD_SYNCBUSY_SEGD2H_DEFAULT (_LCD_SYNCBUSY_SEGD2H_DEFAULT << 10) 11496 #define LCD_SYNCBUSY_SEGD3H (0x1UL << 11) 11497 #define _LCD_SYNCBUSY_SEGD3H_SHIFT 11 11498 #define _LCD_SYNCBUSY_SEGD3H_MASK 0x800UL 11499 #define _LCD_SYNCBUSY_SEGD3H_DEFAULT 0x00000000UL 11500 #define LCD_SYNCBUSY_SEGD3H_DEFAULT (_LCD_SYNCBUSY_SEGD3H_DEFAULT << 11) 11506 /**************************************************************************/ 11511 /* Bit fields for RTC CTRL */ 11512 #define _RTC_CTRL_RESETVALUE 0x00000000UL 11513 #define _RTC_CTRL_MASK 0x00000007UL 11514 #define RTC_CTRL_EN (0x1UL << 0) 11515 #define _RTC_CTRL_EN_SHIFT 0 11516 #define _RTC_CTRL_EN_MASK 0x1UL 11517 #define _RTC_CTRL_EN_DEFAULT 0x00000000UL 11518 #define RTC_CTRL_EN_DEFAULT (_RTC_CTRL_EN_DEFAULT << 0) 11519 #define RTC_CTRL_DEBUGRUN (0x1UL << 1) 11520 #define _RTC_CTRL_DEBUGRUN_SHIFT 1 11521 #define _RTC_CTRL_DEBUGRUN_MASK 0x2UL 11522 #define _RTC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL 11523 #define RTC_CTRL_DEBUGRUN_DEFAULT (_RTC_CTRL_DEBUGRUN_DEFAULT << 1) 11524 #define RTC_CTRL_COMP0TOP (0x1UL << 2) 11525 #define _RTC_CTRL_COMP0TOP_SHIFT 2 11526 #define _RTC_CTRL_COMP0TOP_MASK 0x4UL 11527 #define _RTC_CTRL_COMP0TOP_DEFAULT 0x00000000UL 11528 #define _RTC_CTRL_COMP0TOP_DISABLE 0x00000000UL 11529 #define _RTC_CTRL_COMP0TOP_ENABLE 0x00000001UL 11530 #define RTC_CTRL_COMP0TOP_DEFAULT (_RTC_CTRL_COMP0TOP_DEFAULT << 2) 11531 #define RTC_CTRL_COMP0TOP_DISABLE (_RTC_CTRL_COMP0TOP_DISABLE << 2) 11532 #define RTC_CTRL_COMP0TOP_ENABLE (_RTC_CTRL_COMP0TOP_ENABLE << 2) 11534 /* Bit fields for RTC CNT */ 11535 #define _RTC_CNT_RESETVALUE 0x00000000UL 11536 #define _RTC_CNT_MASK 0x00FFFFFFUL 11537 #define _RTC_CNT_CNT_SHIFT 0 11538 #define _RTC_CNT_CNT_MASK 0xFFFFFFUL 11539 #define _RTC_CNT_CNT_DEFAULT 0x00000000UL 11540 #define RTC_CNT_CNT_DEFAULT (_RTC_CNT_CNT_DEFAULT << 0) 11542 /* Bit fields for RTC COMP0 */ 11543 #define _RTC_COMP0_RESETVALUE 0x00000000UL 11544 #define _RTC_COMP0_MASK 0x00FFFFFFUL 11545 #define _RTC_COMP0_COMP0_SHIFT 0 11546 #define _RTC_COMP0_COMP0_MASK 0xFFFFFFUL 11547 #define _RTC_COMP0_COMP0_DEFAULT 0x00000000UL 11548 #define RTC_COMP0_COMP0_DEFAULT (_RTC_COMP0_COMP0_DEFAULT << 0) 11550 /* Bit fields for RTC COMP1 */ 11551 #define _RTC_COMP1_RESETVALUE 0x00000000UL 11552 #define _RTC_COMP1_MASK 0x00FFFFFFUL 11553 #define _RTC_COMP1_COMP1_SHIFT 0 11554 #define _RTC_COMP1_COMP1_MASK 0xFFFFFFUL 11555 #define _RTC_COMP1_COMP1_DEFAULT 0x00000000UL 11556 #define RTC_COMP1_COMP1_DEFAULT (_RTC_COMP1_COMP1_DEFAULT << 0) 11558 /* Bit fields for RTC IF */ 11559 #define _RTC_IF_RESETVALUE 0x00000000UL 11560 #define _RTC_IF_MASK 0x00000007UL 11561 #define RTC_IF_OF (0x1UL << 0) 11562 #define _RTC_IF_OF_SHIFT 0 11563 #define _RTC_IF_OF_MASK 0x1UL 11564 #define _RTC_IF_OF_DEFAULT 0x00000000UL 11565 #define RTC_IF_OF_DEFAULT (_RTC_IF_OF_DEFAULT << 0) 11566 #define RTC_IF_COMP0 (0x1UL << 1) 11567 #define _RTC_IF_COMP0_SHIFT 1 11568 #define _RTC_IF_COMP0_MASK 0x2UL 11569 #define _RTC_IF_COMP0_DEFAULT 0x00000000UL 11570 #define RTC_IF_COMP0_DEFAULT (_RTC_IF_COMP0_DEFAULT << 1) 11571 #define RTC_IF_COMP1 (0x1UL << 2) 11572 #define _RTC_IF_COMP1_SHIFT 2 11573 #define _RTC_IF_COMP1_MASK 0x4UL 11574 #define _RTC_IF_COMP1_DEFAULT 0x00000000UL 11575 #define RTC_IF_COMP1_DEFAULT (_RTC_IF_COMP1_DEFAULT << 2) 11577 /* Bit fields for RTC IFS */ 11578 #define _RTC_IFS_RESETVALUE 0x00000000UL 11579 #define _RTC_IFS_MASK 0x00000007UL 11580 #define RTC_IFS_OF (0x1UL << 0) 11581 #define _RTC_IFS_OF_SHIFT 0 11582 #define _RTC_IFS_OF_MASK 0x1UL 11583 #define _RTC_IFS_OF_DEFAULT 0x00000000UL 11584 #define RTC_IFS_OF_DEFAULT (_RTC_IFS_OF_DEFAULT << 0) 11585 #define RTC_IFS_COMP0 (0x1UL << 1) 11586 #define _RTC_IFS_COMP0_SHIFT 1 11587 #define _RTC_IFS_COMP0_MASK 0x2UL 11588 #define _RTC_IFS_COMP0_DEFAULT 0x00000000UL 11589 #define RTC_IFS_COMP0_DEFAULT (_RTC_IFS_COMP0_DEFAULT << 1) 11590 #define RTC_IFS_COMP1 (0x1UL << 2) 11591 #define _RTC_IFS_COMP1_SHIFT 2 11592 #define _RTC_IFS_COMP1_MASK 0x4UL 11593 #define _RTC_IFS_COMP1_DEFAULT 0x00000000UL 11594 #define RTC_IFS_COMP1_DEFAULT (_RTC_IFS_COMP1_DEFAULT << 2) 11596 /* Bit fields for RTC IFC */ 11597 #define _RTC_IFC_RESETVALUE 0x00000000UL 11598 #define _RTC_IFC_MASK 0x00000007UL 11599 #define RTC_IFC_OF (0x1UL << 0) 11600 #define _RTC_IFC_OF_SHIFT 0 11601 #define _RTC_IFC_OF_MASK 0x1UL 11602 #define _RTC_IFC_OF_DEFAULT 0x00000000UL 11603 #define RTC_IFC_OF_DEFAULT (_RTC_IFC_OF_DEFAULT << 0) 11604 #define RTC_IFC_COMP0 (0x1UL << 1) 11605 #define _RTC_IFC_COMP0_SHIFT 1 11606 #define _RTC_IFC_COMP0_MASK 0x2UL 11607 #define _RTC_IFC_COMP0_DEFAULT 0x00000000UL 11608 #define RTC_IFC_COMP0_DEFAULT (_RTC_IFC_COMP0_DEFAULT << 1) 11609 #define RTC_IFC_COMP1 (0x1UL << 2) 11610 #define _RTC_IFC_COMP1_SHIFT 2 11611 #define _RTC_IFC_COMP1_MASK 0x4UL 11612 #define _RTC_IFC_COMP1_DEFAULT 0x00000000UL 11613 #define RTC_IFC_COMP1_DEFAULT (_RTC_IFC_COMP1_DEFAULT << 2) 11615 /* Bit fields for RTC IEN */ 11616 #define _RTC_IEN_RESETVALUE 0x00000000UL 11617 #define _RTC_IEN_MASK 0x00000007UL 11618 #define RTC_IEN_OF (0x1UL << 0) 11619 #define _RTC_IEN_OF_SHIFT 0 11620 #define _RTC_IEN_OF_MASK 0x1UL 11621 #define _RTC_IEN_OF_DEFAULT 0x00000000UL 11622 #define RTC_IEN_OF_DEFAULT (_RTC_IEN_OF_DEFAULT << 0) 11623 #define RTC_IEN_COMP0 (0x1UL << 1) 11624 #define _RTC_IEN_COMP0_SHIFT 1 11625 #define _RTC_IEN_COMP0_MASK 0x2UL 11626 #define _RTC_IEN_COMP0_DEFAULT 0x00000000UL 11627 #define RTC_IEN_COMP0_DEFAULT (_RTC_IEN_COMP0_DEFAULT << 1) 11628 #define RTC_IEN_COMP1 (0x1UL << 2) 11629 #define _RTC_IEN_COMP1_SHIFT 2 11630 #define _RTC_IEN_COMP1_MASK 0x4UL 11631 #define _RTC_IEN_COMP1_DEFAULT 0x00000000UL 11632 #define RTC_IEN_COMP1_DEFAULT (_RTC_IEN_COMP1_DEFAULT << 2) 11634 /* Bit fields for RTC FREEZE */ 11635 #define _RTC_FREEZE_RESETVALUE 0x00000000UL 11636 #define _RTC_FREEZE_MASK 0x00000001UL 11637 #define RTC_FREEZE_REGFREEZE (0x1UL << 0) 11638 #define _RTC_FREEZE_REGFREEZE_SHIFT 0 11639 #define _RTC_FREEZE_REGFREEZE_MASK 0x1UL 11640 #define _RTC_FREEZE_REGFREEZE_DEFAULT 0x00000000UL 11641 #define _RTC_FREEZE_REGFREEZE_UPDATE 0x00000000UL 11642 #define _RTC_FREEZE_REGFREEZE_FREEZE 0x00000001UL 11643 #define RTC_FREEZE_REGFREEZE_DEFAULT (_RTC_FREEZE_REGFREEZE_DEFAULT << 0) 11644 #define RTC_FREEZE_REGFREEZE_UPDATE (_RTC_FREEZE_REGFREEZE_UPDATE << 0) 11645 #define RTC_FREEZE_REGFREEZE_FREEZE (_RTC_FREEZE_REGFREEZE_FREEZE << 0) 11647 /* Bit fields for RTC SYNCBUSY */ 11648 #define _RTC_SYNCBUSY_RESETVALUE 0x00000000UL 11649 #define _RTC_SYNCBUSY_MASK 0x00000007UL 11650 #define RTC_SYNCBUSY_CTRL (0x1UL << 0) 11651 #define _RTC_SYNCBUSY_CTRL_SHIFT 0 11652 #define _RTC_SYNCBUSY_CTRL_MASK 0x1UL 11653 #define _RTC_SYNCBUSY_CTRL_DEFAULT 0x00000000UL 11654 #define RTC_SYNCBUSY_CTRL_DEFAULT (_RTC_SYNCBUSY_CTRL_DEFAULT << 0) 11655 #define RTC_SYNCBUSY_COMP0 (0x1UL << 1) 11656 #define _RTC_SYNCBUSY_COMP0_SHIFT 1 11657 #define _RTC_SYNCBUSY_COMP0_MASK 0x2UL 11658 #define _RTC_SYNCBUSY_COMP0_DEFAULT 0x00000000UL 11659 #define RTC_SYNCBUSY_COMP0_DEFAULT (_RTC_SYNCBUSY_COMP0_DEFAULT << 1) 11660 #define RTC_SYNCBUSY_COMP1 (0x1UL << 2) 11661 #define _RTC_SYNCBUSY_COMP1_SHIFT 2 11662 #define _RTC_SYNCBUSY_COMP1_MASK 0x4UL 11663 #define _RTC_SYNCBUSY_COMP1_DEFAULT 0x00000000UL 11664 #define RTC_SYNCBUSY_COMP1_DEFAULT (_RTC_SYNCBUSY_COMP1_DEFAULT << 2) 11670 /**************************************************************************/ 11675 /* Bit fields for WDOG CTRL */ 11676 #define _WDOG_CTRL_RESETVALUE 0x00000F00UL 11677 #define _WDOG_CTRL_MASK 0x00003F7FUL 11678 #define WDOG_CTRL_EN (0x1UL << 0) 11679 #define _WDOG_CTRL_EN_SHIFT 0 11680 #define _WDOG_CTRL_EN_MASK 0x1UL 11681 #define _WDOG_CTRL_EN_DEFAULT 0x00000000UL 11682 #define WDOG_CTRL_EN_DEFAULT (_WDOG_CTRL_EN_DEFAULT << 0) 11683 #define WDOG_CTRL_DEBUGRUN (0x1UL << 1) 11684 #define _WDOG_CTRL_DEBUGRUN_SHIFT 1 11685 #define _WDOG_CTRL_DEBUGRUN_MASK 0x2UL 11686 #define _WDOG_CTRL_DEBUGRUN_DEFAULT 0x00000000UL 11687 #define WDOG_CTRL_DEBUGRUN_DEFAULT (_WDOG_CTRL_DEBUGRUN_DEFAULT << 1) 11688 #define WDOG_CTRL_EM2RUN (0x1UL << 2) 11689 #define _WDOG_CTRL_EM2RUN_SHIFT 2 11690 #define _WDOG_CTRL_EM2RUN_MASK 0x4UL 11691 #define _WDOG_CTRL_EM2RUN_DEFAULT 0x00000000UL 11692 #define WDOG_CTRL_EM2RUN_DEFAULT (_WDOG_CTRL_EM2RUN_DEFAULT << 2) 11693 #define WDOG_CTRL_EM3RUN (0x1UL << 3) 11694 #define _WDOG_CTRL_EM3RUN_SHIFT 3 11695 #define _WDOG_CTRL_EM3RUN_MASK 0x8UL 11696 #define _WDOG_CTRL_EM3RUN_DEFAULT 0x00000000UL 11697 #define WDOG_CTRL_EM3RUN_DEFAULT (_WDOG_CTRL_EM3RUN_DEFAULT << 3) 11698 #define WDOG_CTRL_LOCK (0x1UL << 4) 11699 #define _WDOG_CTRL_LOCK_SHIFT 4 11700 #define _WDOG_CTRL_LOCK_MASK 0x10UL 11701 #define _WDOG_CTRL_LOCK_DEFAULT 0x00000000UL 11702 #define WDOG_CTRL_LOCK_DEFAULT (_WDOG_CTRL_LOCK_DEFAULT << 4) 11703 #define WDOG_CTRL_EM4BLOCK (0x1UL << 5) 11704 #define _WDOG_CTRL_EM4BLOCK_SHIFT 5 11705 #define _WDOG_CTRL_EM4BLOCK_MASK 0x20UL 11706 #define _WDOG_CTRL_EM4BLOCK_DEFAULT 0x00000000UL 11707 #define WDOG_CTRL_EM4BLOCK_DEFAULT (_WDOG_CTRL_EM4BLOCK_DEFAULT << 5) 11708 #define WDOG_CTRL_SWOSCBLOCK (0x1UL << 6) 11709 #define _WDOG_CTRL_SWOSCBLOCK_SHIFT 6 11710 #define _WDOG_CTRL_SWOSCBLOCK_MASK 0x40UL 11711 #define _WDOG_CTRL_SWOSCBLOCK_DEFAULT 0x00000000UL 11712 #define WDOG_CTRL_SWOSCBLOCK_DEFAULT (_WDOG_CTRL_SWOSCBLOCK_DEFAULT << 6) 11713 #define _WDOG_CTRL_PERSEL_SHIFT 8 11714 #define _WDOG_CTRL_PERSEL_MASK 0xF00UL 11715 #define _WDOG_CTRL_PERSEL_DEFAULT 0x0000000FUL 11716 #define WDOG_CTRL_PERSEL_DEFAULT (_WDOG_CTRL_PERSEL_DEFAULT << 8) 11717 #define _WDOG_CTRL_CLKSEL_SHIFT 12 11718 #define _WDOG_CTRL_CLKSEL_MASK 0x3000UL 11719 #define _WDOG_CTRL_CLKSEL_DEFAULT 0x00000000UL 11720 #define _WDOG_CTRL_CLKSEL_ULFRCO 0x00000000UL 11721 #define _WDOG_CTRL_CLKSEL_LFRCO 0x00000001UL 11722 #define _WDOG_CTRL_CLKSEL_LFXO 0x00000002UL 11723 #define WDOG_CTRL_CLKSEL_DEFAULT (_WDOG_CTRL_CLKSEL_DEFAULT << 12) 11724 #define WDOG_CTRL_CLKSEL_ULFRCO (_WDOG_CTRL_CLKSEL_ULFRCO << 12) 11725 #define WDOG_CTRL_CLKSEL_LFRCO (_WDOG_CTRL_CLKSEL_LFRCO << 12) 11726 #define WDOG_CTRL_CLKSEL_LFXO (_WDOG_CTRL_CLKSEL_LFXO << 12) 11728 /* Bit fields for WDOG CMD */ 11729 #define _WDOG_CMD_RESETVALUE 0x00000000UL 11730 #define _WDOG_CMD_MASK 0x00000001UL 11731 #define WDOG_CMD_CLEAR (0x1UL << 0) 11732 #define _WDOG_CMD_CLEAR_SHIFT 0 11733 #define _WDOG_CMD_CLEAR_MASK 0x1UL 11734 #define _WDOG_CMD_CLEAR_DEFAULT 0x00000000UL 11735 #define _WDOG_CMD_CLEAR_UNCHANGED 0x00000000UL 11736 #define _WDOG_CMD_CLEAR_CLEARED 0x00000001UL 11737 #define WDOG_CMD_CLEAR_DEFAULT (_WDOG_CMD_CLEAR_DEFAULT << 0) 11738 #define WDOG_CMD_CLEAR_UNCHANGED (_WDOG_CMD_CLEAR_UNCHANGED << 0) 11739 #define WDOG_CMD_CLEAR_CLEARED (_WDOG_CMD_CLEAR_CLEARED << 0) 11741 /* Bit fields for WDOG SYNCBUSY */ 11742 #define _WDOG_SYNCBUSY_RESETVALUE 0x00000000UL 11743 #define _WDOG_SYNCBUSY_MASK 0x00000003UL 11744 #define WDOG_SYNCBUSY_CTRL (0x1UL << 0) 11745 #define _WDOG_SYNCBUSY_CTRL_SHIFT 0 11746 #define _WDOG_SYNCBUSY_CTRL_MASK 0x1UL 11747 #define _WDOG_SYNCBUSY_CTRL_DEFAULT 0x00000000UL 11748 #define WDOG_SYNCBUSY_CTRL_DEFAULT (_WDOG_SYNCBUSY_CTRL_DEFAULT << 0) 11749 #define WDOG_SYNCBUSY_CMD (0x1UL << 1) 11750 #define _WDOG_SYNCBUSY_CMD_SHIFT 1 11751 #define _WDOG_SYNCBUSY_CMD_MASK 0x2UL 11752 #define _WDOG_SYNCBUSY_CMD_DEFAULT 0x00000000UL 11753 #define WDOG_SYNCBUSY_CMD_DEFAULT (_WDOG_SYNCBUSY_CMD_DEFAULT << 1) 11759 /**************************************************************************/ 11763 /* Bit fields for EFM32G890F128_DEVINFO */ 11764 #define _DEVINFO_CAL_CRC_MASK 0x0000FFFFUL 11765 #define _DEVINFO_CAL_CRC_SHIFT 0 11766 #define _DEVINFO_CAL_TEMP_MASK 0x00FF0000UL 11767 #define _DEVINFO_CAL_TEMP_SHIFT 16 11768 #define _DEVINFO_ADC0CAL0_1V25_GAIN_MASK 0x00007F00UL 11769 #define _DEVINFO_ADC0CAL0_1V25_GAIN_SHIFT 8 11770 #define _DEVINFO_ADC0CAL0_1V25_OFFSET_MASK 0x0000007FUL 11771 #define _DEVINFO_ADC0CAL0_1V25_OFFSET_SHIFT 0 11772 #define _DEVINFO_ADC0CAL0_2V5_GAIN_MASK 0x7F000000UL 11773 #define _DEVINFO_ADC0CAL0_2V5_GAIN_SHIFT 24 11774 #define _DEVINFO_ADC0CAL0_2V5_OFFSET_MASK 0x007F0000UL 11775 #define _DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT 16 11776 #define _DEVINFO_ADC0CAL1_VDD_GAIN_MASK 0x00007F00UL 11777 #define _DEVINFO_ADC0CAL1_VDD_GAIN_SHIFT 8 11778 #define _DEVINFO_ADC0CAL1_VDD_OFFSET_MASK 0x0000007FUL 11779 #define _DEVINFO_ADC0CAL1_VDD_OFFSET_SHIFT 0 11780 #define _DEVINFO_ADC0CAL1_5VDIFF_GAIN_MASK 0x7F000000UL 11781 #define _DEVINFO_ADC0CAL1_5VDIFF_GAIN_SHIFT 24 11782 #define _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_MASK 0x007F0000UL 11783 #define _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT 16 11784 #define _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_MASK 0x0000007FUL 11785 #define _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT 0 11786 #define _DEVINFO_ADC0CAL2_TEMP1V25_MASK 0xFFF00000UL 11787 #define _DEVINFO_ADC0CAL2_TEMP1V25_SHIFT 20 11788 #define _DEVINFO_DAC0CAL0_1V25_GAIN_MASK 0x007F0000UL 11789 #define _DEVINFO_DAC0CAL0_1V25_GAIN_SHIFT 16 11790 #define _DEVINFO_DAC0CAL0_1V25_CH1_OFFSET_MASK 0x00003F00UL 11791 #define _DEVINFO_DAC0CAL0_1V25_CH1_OFFSET_SHIFT 8 11792 #define _DEVINFO_DAC0CAL0_1V25_CH0_OFFSET_MASK 0x0000003FUL 11793 #define _DEVINFO_DAC0CAL0_1V25_CH0_OFFSET_SHIFT 0 11794 #define _DEVINFO_DAC0CAL1_2V5_GAIN_MASK 0x007F0000UL 11795 #define _DEVINFO_DAC0CAL1_2V5_GAIN_SHIFT 16 11796 #define _DEVINFO_DAC0CAL1_2V5_CH1_OFFSET_MASK 0x00003F00UL 11797 #define _DEVINFO_DAC0CAL1_2V5_CH1_OFFSET_SHIFT 8 11798 #define _DEVINFO_DAC0CAL1_2V5_CH0_OFFSET_MASK 0x0000003FUL 11799 #define _DEVINFO_DAC0CAL1_2V5_CH0_OFFSET_SHIFT 0 11800 #define _DEVINFO_DAC0CAL2_VDD_GAIN_MASK 0x007F0000UL 11801 #define _DEVINFO_DAC0CAL2_VDD_GAIN_SHIFT 16 11802 #define _DEVINFO_DAC0CAL2_VDD_CH1_OFFSET_MASK 0x00003F00UL 11803 #define _DEVINFO_DAC0CAL2_VDD_CH1_OFFSET_SHIFT 8 11804 #define _DEVINFO_DAC0CAL2_VDD_CH0_OFFSET_MASK 0x0000003FUL 11805 #define _DEVINFO_DAC0CAL2_VDD_CH0_OFFSET_SHIFT 0 11806 #define _DEVINFO_HFRCOCAL0_BAND1_MASK 0x000000FFUL 11807 #define _DEVINFO_HFRCOCAL0_BAND1_SHIFT 0 11808 #define _DEVINFO_HFRCOCAL0_BAND7_MASK 0x0000FF00UL 11809 #define _DEVINFO_HFRCOCAL0_BAND7_SHIFT 8 11810 #define _DEVINFO_HFRCOCAL0_BAND11_MASK 0x00FF0000UL 11811 #define _DEVINFO_HFRCOCAL0_BAND11_SHIFT 16 11812 #define _DEVINFO_HFRCOCAL0_BAND14_MASK 0xFF000000UL 11813 #define _DEVINFO_HFRCOCAL0_BAND14_SHIFT 24 11814 #define _DEVINFO_HFRCOCAL1_BAND21_MASK 0x000000FFUL 11815 #define _DEVINFO_HFRCOCAL1_BAND21_SHIFT 0 11816 #define _DEVINFO_HFRCOCAL1_BAND28_MASK 0x0000FF00UL 11817 #define _DEVINFO_HFRCOCAL1_BAND28_SHIFT 8 11818 #define _DEVINFO_UNIQUEL_MASK 0xFFFFFFFFUL 11819 #define _DEVINFO_UNIQUEL_SHIFT 0 11820 #define _DEVINFO_UNIQUEH_MASK 0xFFFFFFFFUL 11821 #define _DEVINFO_UNIQUEH_SHIFT 0 11822 #define _DEVINFO_MSIZE_SRAM_MASK 0xFFFF0000UL 11823 #define _DEVINFO_MSIZE_SRAM_SHIFT 16 11824 #define _DEVINFO_MSIZE_FLASH_MASK 0x0000FFFFUL 11825 #define _DEVINFO_MSIZE_FLASH_SHIFT 0 11826 #define _DEVINFO_PART_PROD_REV_MASK 0xFF000000UL 11827 #define _DEVINFO_PART_PROD_REV_SHIFT 24 11828 #define _DEVINFO_PART_DEVICE_FAMILY_MASK 0x00FF0000UL 11829 #define _DEVINFO_PART_DEVICE_FAMILY_SHIFT 16 11830 #define _DEVINFO_PART_DEVICE_NUMBER_MASK 0x0000FFFFUL 11831 #define _DEVINFO_PART_DEVICE_NUMBER_SHIFT 0 11837 /**************************************************************************/ 11841 /* Bit fields for EFM32G890F128_ROMTABLE */ 11842 #define _ROMTABLE_PID0_FAMILYLSB_MASK 0x000000C0UL 11843 #define _ROMTABLE_PID0_FAMILYLSB_SHIFT 6 11844 #define _ROMTABLE_PID0_REVMAJOR_MASK 0x0000003FUL 11845 #define _ROMTABLE_PID0_REVMAJOR_SHIFT 0 11846 #define _ROMTABLE_PID1_FAMILYMSB_MASK 0x0000000FUL 11847 #define _ROMTABLE_PID1_FAMILYMSB_SHIFT 0 11848 #define _ROMTABLE_PID2_REVMINORMSB_MASK 0x000000F0UL 11849 #define _ROMTABLE_PID2_REVMINORMSB_SHIFT 4 11850 #define _ROMTABLE_PID3_REVMINORLSB_MASK 0x000000F0UL 11851 #define _ROMTABLE_PID3_REVMINORLSB_SHIFT 4 11857 /****************************************************************************** 11858 * Unlock codes 11859 *****************************************************************************/ 11860 /**************************************************************************/ 11864 #define MSC_UNLOCK_CODE 0x1B71 11868 /**************************************************************************/ 11872 #define EMU_UNLOCK_CODE 0xADE8 11876 /**************************************************************************/ 11880 #define CMU_UNLOCK_CODE 0x580E 11884 /**************************************************************************/ 11888 #define GPIO_UNLOCK_CODE 0xA534 11892 /**************************************************************************/ 11896 #define TIMER_UNLOCK_CODE 0xCE80 11901 /**************************************************************************/ 11906 /**************************************************************************/ 11912 #define AFCHAN_MAX 79 11913 #define AFCHANLOC_MAX 4 11914 11915 #define AFACHAN_MAX 37 11916 11918 #define AF_CMU_CLK0 0 11919 #define AF_CMU_CLK1 1 11920 #define AF_EBI_AD00 2 11921 #define AF_EBI_AD01 3 11922 #define AF_EBI_AD02 4 11923 #define AF_EBI_AD03 5 11924 #define AF_EBI_AD04 6 11925 #define AF_EBI_AD05 7 11926 #define AF_EBI_AD06 8 11927 #define AF_EBI_AD07 9 11928 #define AF_EBI_AD08 10 11929 #define AF_EBI_AD09 11 11930 #define AF_EBI_AD10 12 11931 #define AF_EBI_AD11 13 11932 #define AF_EBI_AD12 14 11933 #define AF_EBI_AD13 15 11934 #define AF_EBI_AD14 16 11935 #define AF_EBI_AD15 17 11936 #define AF_EBI_CS0 18 11937 #define AF_EBI_CS1 19 11938 #define AF_EBI_CS2 20 11939 #define AF_EBI_CS3 21 11940 #define AF_EBI_WEn 22 11941 #define AF_EBI_REn 23 11942 #define AF_EBI_ARDY 24 11943 #define AF_EBI_ALE 25 11944 #define AF_TIMER0_CC0 26 11945 #define AF_TIMER0_CC1 27 11946 #define AF_TIMER0_CC2 28 11947 #define AF_TIMER0_CDTI0 29 11948 #define AF_TIMER0_CDTI1 30 11949 #define AF_TIMER0_CDTI2 31 11950 #define AF_TIMER1_CC0 32 11951 #define AF_TIMER1_CC1 33 11952 #define AF_TIMER1_CC2 34 11953 #define AF_TIMER1_CDTI0 35 11954 #define AF_TIMER1_CDTI1 36 11955 #define AF_TIMER1_CDTI2 37 11956 #define AF_TIMER2_CC0 38 11957 #define AF_TIMER2_CC1 39 11958 #define AF_TIMER2_CC2 40 11959 #define AF_TIMER2_CDTI0 41 11960 #define AF_TIMER2_CDTI1 42 11961 #define AF_TIMER2_CDTI2 43 11962 #define AF_USART0_TX 44 11963 #define AF_USART0_RX 45 11964 #define AF_USART0_CLK 46 11965 #define AF_USART0_CS 47 11966 #define AF_USART1_TX 48 11967 #define AF_USART1_RX 49 11968 #define AF_USART1_CLK 50 11969 #define AF_USART1_CS 51 11970 #define AF_USART2_TX 52 11971 #define AF_USART2_RX 53 11972 #define AF_USART2_CLK 54 11973 #define AF_USART2_CS 55 11974 #define AF_UART0_TX 56 11975 #define AF_UART0_RX 57 11976 #define AF_UART0_CLK 58 11977 #define AF_UART0_CS 59 11978 #define AF_LEUART0_TX 60 11979 #define AF_LEUART0_RX 61 11980 #define AF_LEUART1_TX 62 11981 #define AF_LEUART1_RX 63 11982 #define AF_LETIMER0_OUT0 64 11983 #define AF_LETIMER0_OUT1 65 11984 #define AF_PCNT0_S0IN 66 11985 #define AF_PCNT0_S1IN 67 11986 #define AF_PCNT1_S0IN 68 11987 #define AF_PCNT1_S1IN 69 11988 #define AF_PCNT2_S0IN 70 11989 #define AF_PCNT2_S1IN 71 11990 #define AF_I2C0_SDA 72 11991 #define AF_I2C0_SCL 73 11992 #define AF_ACMP0_OUT 74 11993 #define AF_ACMP1_OUT 75 11994 #define AF_DBG_SWO 76 11995 #define AF_DBG_SWDIO 77 11996 #define AF_DBG_SWCLK 78 11997 11999 #define AFA_MSC_TM0 0 12000 #define AFA_MSC_TM1 1 12001 #define AFA_MSC_TM2 2 12002 #define AFA_ADC0_CH0 3 12003 #define AFA_ADC0_CH1 4 12004 #define AFA_ADC0_CH2 5 12005 #define AFA_ADC0_CH3 6 12006 #define AFA_ADC0_CH4 7 12007 #define AFA_ADC0_CH5 8 12008 #define AFA_ADC0_CH6 9 12009 #define AFA_ADC0_CH7 10 12010 #define AFA_ADC0_VCM 11 12011 #define AFA_DAC0_OUT0 12 12012 #define AFA_DAC0_OUT1 13 12013 #define AFA_ACMP0_CH0 14 12014 #define AFA_ACMP0_CH1 15 12015 #define AFA_ACMP0_CH2 16 12016 #define AFA_ACMP0_CH3 17 12017 #define AFA_ACMP0_CH4 18 12018 #define AFA_ACMP0_CH5 19 12019 #define AFA_ACMP0_CH6 20 12020 #define AFA_ACMP0_CH7 21 12021 #define AFA_ACMP1_CH0 22 12022 #define AFA_ACMP1_CH1 23 12023 #define AFA_ACMP1_CH2 24 12024 #define AFA_ACMP1_CH3 25 12025 #define AFA_ACMP1_CH4 26 12026 #define AFA_ACMP1_CH5 27 12027 #define AFA_ACMP1_CH6 28 12028 #define AFA_ACMP1_CH7 29 12029 #define AFA_LCD_BCAP_P 30 12030 #define AFA_LCD_BCAP_N 31 12031 #define AFA_LCD_BEXT 32 12032 #define AFA_HFXTAL_P 33 12033 #define AFA_HFXTAL_N 34 12034 #define AFA_LFXTAL_P 35 12035 #define AFA_LFXTAL_N 36 12036 12038 #define AF_TIMER_CC0(i) ((i) == 0 ? AF_TIMER0_CC0 : (i) == 1 ? AF_TIMER1_CC0 : (i) == 2 ? AF_TIMER2_CC0 : -1) 12039 #define AF_UART_CLK(i) ((i) == 0 ? AF_UART0_CLK : -1) 12040 #define AF_I2C_SDA(i) ((i) == 0 ? AF_I2C0_SDA : -1) 12041 #define AF_TIMER_CC1(i) ((i) == 0 ? AF_TIMER0_CC1 : (i) == 1 ? AF_TIMER1_CC1 : (i) == 2 ? AF_TIMER2_CC1 : -1) 12042 #define AF_USART_CS(i) ((i) == 0 ? AF_USART0_CS : (i) == 1 ? AF_USART1_CS : (i) == 2 ? AF_USART2_CS : -1) 12043 #define AF_I2C_SCL(i) ((i) == 0 ? AF_I2C0_SCL : -1) 12044 #define AF_TIMER_CC2(i) ((i) == 0 ? AF_TIMER0_CC2 : (i) == 1 ? AF_TIMER1_CC2 : (i) == 2 ? AF_TIMER2_CC2 : -1) 12045 #define AF_TIMER_CDTI1(i) ((i) == 0 ? AF_TIMER0_CDTI1 : (i) == 1 ? AF_TIMER1_CDTI1 : (i) == 2 ? AF_TIMER2_CDTI1 : -1) 12046 #define AF_TIMER_CDTI0(i) ((i) == 0 ? AF_TIMER0_CDTI0 : (i) == 1 ? AF_TIMER1_CDTI0 : (i) == 2 ? AF_TIMER2_CDTI0 : -1) 12047 #define AF_USART_CLK(i) ((i) == 0 ? AF_USART0_CLK : (i) == 1 ? AF_USART1_CLK : (i) == 2 ? AF_USART2_CLK : -1) 12048 #define AF_UART_RX(i) ((i) == 0 ? AF_UART0_RX : -1) 12049 #define AF_UART_TX(i) ((i) == 0 ? AF_UART0_TX : -1) 12050 #define AF_LETIMER_OUT1(i) ((i) == 0 ? AF_LETIMER0_OUT1 : -1) 12051 #define AF_LEUART_RX(i) ((i) == 0 ? AF_LEUART0_RX : (i) == 1 ? AF_LEUART1_RX : -1) 12052 #define AF_PCNT_S1IN(i) ((i) == 0 ? AF_PCNT0_S1IN : (i) == 1 ? AF_PCNT1_S1IN : (i) == 2 ? AF_PCNT2_S1IN : -1) 12053 #define AF_TIMER_CDTI2(i) ((i) == 0 ? AF_TIMER0_CDTI2 : (i) == 1 ? AF_TIMER1_CDTI2 : (i) == 2 ? AF_TIMER2_CDTI2 : -1) 12054 #define AF_LEUART_TX(i) ((i) == 0 ? AF_LEUART0_TX : (i) == 1 ? AF_LEUART1_TX : -1) 12055 #define AF_USART_TX(i) ((i) == 0 ? AF_USART0_TX : (i) == 1 ? AF_USART1_TX : (i) == 2 ? AF_USART2_TX : -1) 12056 #define AF_LETIMER_OUT0(i) ((i) == 0 ? AF_LETIMER0_OUT0 : -1) 12057 #define AF_ACMP_OUT(i) ((i) == 0 ? AF_ACMP0_OUT : (i) == 1 ? AF_ACMP1_OUT : -1) 12058 #define AF_USART_RX(i) ((i) == 0 ? AF_USART0_RX : (i) == 1 ? AF_USART1_RX : (i) == 2 ? AF_USART2_RX : -1) 12059 #define AF_UART_CS(i) ((i) == 0 ? AF_UART0_CS : -1) 12060 #define AF_PCNT_S0IN(i) ((i) == 0 ? AF_PCNT0_S0IN : (i) == 1 ? AF_PCNT1_S0IN : (i) == 2 ? AF_PCNT2_S0IN : -1) 12061 #define AFA_DAC_OUT1(i) ((i) == 0 ? AFA_DAC0_OUT1 : -1) 12062 #define AFA_DAC_OUT0(i) ((i) == 0 ? AFA_DAC0_OUT0 : -1) 12063 #define AFA_ADC_CH7(i) ((i) == 0 ? AFA_ADC0_CH7 : -1) 12064 #define AFA_ADC_VCM(i) ((i) == 0 ? AFA_ADC0_VCM : -1) 12065 #define AFA_ACMP_CH1(i) ((i) == 0 ? AFA_ACMP0_CH1 : (i) == 1 ? AFA_ACMP1_CH1 : -1) 12066 #define AFA_ADC_CH0(i) ((i) == 0 ? AFA_ADC0_CH0 : -1) 12067 #define AFA_ACMP_CH0(i) ((i) == 0 ? AFA_ACMP0_CH0 : (i) == 1 ? AFA_ACMP1_CH0 : -1) 12068 #define AFA_ACMP_CH3(i) ((i) == 0 ? AFA_ACMP0_CH3 : (i) == 1 ? AFA_ACMP1_CH3 : -1) 12069 #define AFA_ADC_CH1(i) ((i) == 0 ? AFA_ADC0_CH1 : -1) 12070 #define AFA_ACMP_CH2(i) ((i) == 0 ? AFA_ACMP0_CH2 : (i) == 1 ? AFA_ACMP1_CH2 : -1) 12071 #define AFA_ADC_CH2(i) ((i) == 0 ? AFA_ADC0_CH2 : -1) 12072 #define AFA_ADC_CH3(i) ((i) == 0 ? AFA_ADC0_CH3 : -1) 12073 #define AFA_ADC_CH4(i) ((i) == 0 ? AFA_ADC0_CH4 : -1) 12074 #define AFA_ADC_CH5(i) ((i) == 0 ? AFA_ADC0_CH5 : -1) 12075 #define AFA_ADC_CH6(i) ((i) == 0 ? AFA_ADC0_CH6 : -1) 12076 #define AFA_ACMP_CH5(i) ((i) == 0 ? AFA_ACMP0_CH5 : (i) == 1 ? AFA_ACMP1_CH5 : -1) 12077 #define AFA_ACMP_CH4(i) ((i) == 0 ? AFA_ACMP0_CH4 : (i) == 1 ? AFA_ACMP1_CH4 : -1) 12078 #define AFA_ACMP_CH7(i) ((i) == 0 ? AFA_ACMP0_CH7 : (i) == 1 ? AFA_ACMP1_CH7 : -1) 12079 #define AFA_ACMP_CH6(i) ((i) == 0 ? AFA_ACMP0_CH6 : (i) == 1 ? AFA_ACMP1_CH6 : -1) 12080 12085 /**************************************************************************/ 12091 #define AF_CMU_CLK0_PORT(f) ((f) == 0 ? 0 : (f) == 1 ? 2 : -1) 12092 #define AF_CMU_CLK1_PORT(f) ((f) == 0 ? 0 : (f) == 1 ? 3 : -1) 12093 #define AF_EBI_AD00_PORT(f) ((f) == 0 ? 4 : -1) 12094 #define AF_EBI_AD01_PORT(f) ((f) == 0 ? 4 : -1) 12095 #define AF_EBI_AD02_PORT(f) ((f) == 0 ? 4 : -1) 12096 #define AF_EBI_AD03_PORT(f) ((f) == 0 ? 4 : -1) 12097 #define AF_EBI_AD04_PORT(f) ((f) == 0 ? 4 : -1) 12098 #define AF_EBI_AD05_PORT(f) ((f) == 0 ? 4 : -1) 12099 #define AF_EBI_AD06_PORT(f) ((f) == 0 ? 4 : -1) 12100 #define AF_EBI_AD07_PORT(f) ((f) == 0 ? 4 : -1) 12101 #define AF_EBI_AD08_PORT(f) ((f) == 0 ? 0 : -1) 12102 #define AF_EBI_AD09_PORT(f) ((f) == 0 ? 0 : -1) 12103 #define AF_EBI_AD10_PORT(f) ((f) == 0 ? 0 : -1) 12104 #define AF_EBI_AD11_PORT(f) ((f) == 0 ? 0 : -1) 12105 #define AF_EBI_AD12_PORT(f) ((f) == 0 ? 0 : -1) 12106 #define AF_EBI_AD13_PORT(f) ((f) == 0 ? 0 : -1) 12107 #define AF_EBI_AD14_PORT(f) ((f) == 0 ? 0 : -1) 12108 #define AF_EBI_AD15_PORT(f) ((f) == 0 ? 0 : -1) 12109 #define AF_EBI_CS0_PORT(f) ((f) == 0 ? 3 : -1) 12110 #define AF_EBI_CS1_PORT(f) ((f) == 0 ? 3 : -1) 12111 #define AF_EBI_CS2_PORT(f) ((f) == 0 ? 3 : -1) 12112 #define AF_EBI_CS3_PORT(f) ((f) == 0 ? 3 : -1) 12113 #define AF_EBI_WEn_PORT(f) ((f) == 0 ? 5 : -1) 12114 #define AF_EBI_REn_PORT(f) ((f) == 0 ? 5 : -1) 12115 #define AF_EBI_ARDY_PORT(f) ((f) == 0 ? 5 : -1) 12116 #define AF_EBI_ALE_PORT(f) ((f) == 0 ? 5 : -1) 12117 #define AF_TIMER0_CC0_PORT(f) ((f) == 0 ? 0 : (f) == 1 ? 0 : (f) == 2 ? 5 : (f) == 3 ? 3 : -1) 12118 #define AF_TIMER0_CC1_PORT(f) ((f) == 0 ? 0 : (f) == 1 ? 0 : (f) == 2 ? 5 : (f) == 3 ? 3 : -1) 12119 #define AF_TIMER0_CC2_PORT(f) ((f) == 0 ? 0 : (f) == 1 ? 0 : (f) == 2 ? 5 : (f) == 3 ? 3 : -1) 12120 #define AF_TIMER0_CDTI0_PORT(f) ((f) == 0 ? 0 : (f) == 1 ? 2 : (f) == 2 ? 5 : (f) == 3 ? 2 : -1) 12121 #define AF_TIMER0_CDTI1_PORT(f) ((f) == 0 ? 0 : (f) == 1 ? 2 : (f) == 2 ? 5 : (f) == 3 ? 2 : -1) 12122 #define AF_TIMER0_CDTI2_PORT(f) ((f) == 0 ? 0 : (f) == 1 ? 2 : (f) == 2 ? 5 : (f) == 3 ? 2 : -1) 12123 #define AF_TIMER1_CC0_PORT(f) ((f) == 0 ? 2 : (f) == 1 ? 4 : (f) == 2 ? 1 : -1) 12124 #define AF_TIMER1_CC1_PORT(f) ((f) == 0 ? 2 : (f) == 1 ? 4 : (f) == 2 ? 1 : -1) 12125 #define AF_TIMER1_CC2_PORT(f) ((f) == 0 ? 2 : (f) == 1 ? 4 : (f) == 2 ? 1 : -1) 12126 #define AF_TIMER1_CDTI0_PORT(f) (-1) 12127 #define AF_TIMER1_CDTI1_PORT(f) (-1) 12128 #define AF_TIMER1_CDTI2_PORT(f) (-1) 12129 #define AF_TIMER2_CC0_PORT(f) ((f) == 0 ? 0 : (f) == 1 ? 0 : (f) == 2 ? 2 : -1) 12130 #define AF_TIMER2_CC1_PORT(f) ((f) == 0 ? 0 : (f) == 1 ? 0 : (f) == 2 ? 2 : -1) 12131 #define AF_TIMER2_CC2_PORT(f) ((f) == 0 ? 0 : (f) == 1 ? 0 : (f) == 2 ? 2 : -1) 12132 #define AF_TIMER2_CDTI0_PORT(f) (-1) 12133 #define AF_TIMER2_CDTI1_PORT(f) (-1) 12134 #define AF_TIMER2_CDTI2_PORT(f) (-1) 12135 #define AF_USART0_TX_PORT(f) ((f) == 0 ? 4 : (f) == 1 ? 4 : (f) == 2 ? 2 : -1) 12136 #define AF_USART0_RX_PORT(f) ((f) == 0 ? 4 : (f) == 1 ? 4 : (f) == 2 ? 2 : -1) 12137 #define AF_USART0_CLK_PORT(f) ((f) == 0 ? 4 : (f) == 1 ? 4 : (f) == 2 ? 2 : -1) 12138 #define AF_USART0_CS_PORT(f) ((f) == 0 ? 4 : (f) == 1 ? 4 : (f) == 2 ? 2 : -1) 12139 #define AF_USART1_TX_PORT(f) ((f) == 0 ? 2 : (f) == 1 ? 3 : -1) 12140 #define AF_USART1_RX_PORT(f) ((f) == 0 ? 2 : (f) == 1 ? 3 : -1) 12141 #define AF_USART1_CLK_PORT(f) ((f) == 0 ? 1 : (f) == 1 ? 3 : -1) 12142 #define AF_USART1_CS_PORT(f) ((f) == 0 ? 1 : (f) == 1 ? 3 : -1) 12143 #define AF_USART2_TX_PORT(f) ((f) == 0 ? 2 : (f) == 1 ? 1 : -1) 12144 #define AF_USART2_RX_PORT(f) ((f) == 0 ? 2 : (f) == 1 ? 1 : -1) 12145 #define AF_USART2_CLK_PORT(f) ((f) == 0 ? 2 : (f) == 1 ? 1 : -1) 12146 #define AF_USART2_CS_PORT(f) ((f) == 0 ? 2 : (f) == 1 ? 1 : -1) 12147 #define AF_UART0_TX_PORT(f) ((f) == 0 ? 5 : (f) == 1 ? 4 : (f) == 2 ? 0 : (f) == 3 ? 2 : -1) 12148 #define AF_UART0_RX_PORT(f) ((f) == 0 ? 5 : (f) == 1 ? 4 : (f) == 2 ? 0 : (f) == 3 ? 2 : -1) 12149 #define AF_UART0_CLK_PORT(f) (-1) 12150 #define AF_UART0_CS_PORT(f) (-1) 12151 #define AF_LEUART0_TX_PORT(f) ((f) == 0 ? 3 : (f) == 1 ? 1 : (f) == 2 ? 4 : -1) 12152 #define AF_LEUART0_RX_PORT(f) ((f) == 0 ? 3 : (f) == 1 ? 1 : (f) == 2 ? 4 : -1) 12153 #define AF_LEUART1_TX_PORT(f) ((f) == 0 ? 2 : (f) == 1 ? 0 : -1) 12154 #define AF_LEUART1_RX_PORT(f) ((f) == 0 ? 2 : (f) == 1 ? 0 : -1) 12155 #define AF_LETIMER0_OUT0_PORT(f) ((f) == 0 ? 3 : (f) == 1 ? 1 : (f) == 2 ? 5 : (f) == 3 ? 2 : -1) 12156 #define AF_LETIMER0_OUT1_PORT(f) ((f) == 0 ? 3 : (f) == 1 ? 1 : (f) == 2 ? 5 : (f) == 3 ? 2 : -1) 12157 #define AF_PCNT0_S0IN_PORT(f) ((f) == 0 ? 2 : (f) == 1 ? 4 : (f) == 2 ? 2 : -1) 12158 #define AF_PCNT0_S1IN_PORT(f) ((f) == 0 ? 2 : (f) == 1 ? 4 : (f) == 2 ? 2 : -1) 12159 #define AF_PCNT1_S0IN_PORT(f) ((f) == 0 ? 2 : (f) == 1 ? 1 : -1) 12160 #define AF_PCNT1_S1IN_PORT(f) ((f) == 0 ? 2 : (f) == 1 ? 1 : -1) 12161 #define AF_PCNT2_S0IN_PORT(f) ((f) == 0 ? 3 : (f) == 1 ? 4 : -1) 12162 #define AF_PCNT2_S1IN_PORT(f) ((f) == 0 ? 3 : (f) == 1 ? 4 : -1) 12163 #define AF_I2C0_SDA_PORT(f) ((f) == 0 ? 0 : (f) == 1 ? 3 : (f) == 2 ? 2 : (f) == 3 ? 3 : -1) 12164 #define AF_I2C0_SCL_PORT(f) ((f) == 0 ? 0 : (f) == 1 ? 3 : (f) == 2 ? 2 : (f) == 3 ? 3 : -1) 12165 #define AF_ACMP0_OUT_PORT(f) ((f) == 0 ? 4 : (f) == 1 ? 4 : -1) 12166 #define AF_ACMP1_OUT_PORT(f) ((f) == 0 ? 5 : (f) == 1 ? 4 : -1) 12167 #define AF_DBG_SWO_PORT(f) ((f) == 0 ? 5 : (f) == 1 ? 2 : -1) 12168 #define AF_DBG_SWDIO_PORT(f) ((f) == 0 ? 5 : (f) == 1 ? 5 : -1) 12169 #define AF_DBG_SWCLK_PORT(f) ((f) == 0 ? 5 : (f) == 1 ? 5 : -1) 12170 12175 /**************************************************************************/ 12181 #define AF_CMU_CLK0_PIN(f) ((f) == 0 ? 2 : (f) == 1 ? 12 : -1) 12182 #define AF_CMU_CLK1_PIN(f) ((f) == 0 ? 1 : (f) == 1 ? 8 : -1) 12183 #define AF_EBI_AD00_PIN(f) ((f) == 0 ? 8 : -1) 12184 #define AF_EBI_AD01_PIN(f) ((f) == 0 ? 9 : -1) 12185 #define AF_EBI_AD02_PIN(f) ((f) == 0 ? 10 : -1) 12186 #define AF_EBI_AD03_PIN(f) ((f) == 0 ? 11 : -1) 12187 #define AF_EBI_AD04_PIN(f) ((f) == 0 ? 12 : -1) 12188 #define AF_EBI_AD05_PIN(f) ((f) == 0 ? 13 : -1) 12189 #define AF_EBI_AD06_PIN(f) ((f) == 0 ? 14 : -1) 12190 #define AF_EBI_AD07_PIN(f) ((f) == 0 ? 15 : -1) 12191 #define AF_EBI_AD08_PIN(f) ((f) == 0 ? 15 : -1) 12192 #define AF_EBI_AD09_PIN(f) ((f) == 0 ? 0 : -1) 12193 #define AF_EBI_AD10_PIN(f) ((f) == 0 ? 1 : -1) 12194 #define AF_EBI_AD11_PIN(f) ((f) == 0 ? 2 : -1) 12195 #define AF_EBI_AD12_PIN(f) ((f) == 0 ? 3 : -1) 12196 #define AF_EBI_AD13_PIN(f) ((f) == 0 ? 4 : -1) 12197 #define AF_EBI_AD14_PIN(f) ((f) == 0 ? 5 : -1) 12198 #define AF_EBI_AD15_PIN(f) ((f) == 0 ? 6 : -1) 12199 #define AF_EBI_CS0_PIN(f) ((f) == 0 ? 9 : -1) 12200 #define AF_EBI_CS1_PIN(f) ((f) == 0 ? 10 : -1) 12201 #define AF_EBI_CS2_PIN(f) ((f) == 0 ? 11 : -1) 12202 #define AF_EBI_CS3_PIN(f) ((f) == 0 ? 12 : -1) 12203 #define AF_EBI_WEn_PIN(f) ((f) == 0 ? 4 : -1) 12204 #define AF_EBI_REn_PIN(f) ((f) == 0 ? 5 : -1) 12205 #define AF_EBI_ARDY_PIN(f) ((f) == 0 ? 2 : -1) 12206 #define AF_EBI_ALE_PIN(f) ((f) == 0 ? 3 : -1) 12207 #define AF_TIMER0_CC0_PIN(f) ((f) == 0 ? 0 : (f) == 1 ? 0 : (f) == 2 ? 6 : (f) == 3 ? 1 : -1) 12208 #define AF_TIMER0_CC1_PIN(f) ((f) == 0 ? 1 : (f) == 1 ? 1 : (f) == 2 ? 7 : (f) == 3 ? 2 : -1) 12209 #define AF_TIMER0_CC2_PIN(f) ((f) == 0 ? 2 : (f) == 1 ? 2 : (f) == 2 ? 8 : (f) == 3 ? 3 : -1) 12210 #define AF_TIMER0_CDTI0_PIN(f) ((f) == 0 ? 3 : (f) == 1 ? 13 : (f) == 2 ? 3 : (f) == 3 ? 13 : -1) 12211 #define AF_TIMER0_CDTI1_PIN(f) ((f) == 0 ? 4 : (f) == 1 ? 14 : (f) == 2 ? 4 : (f) == 3 ? 14 : -1) 12212 #define AF_TIMER0_CDTI2_PIN(f) ((f) == 0 ? 5 : (f) == 1 ? 15 : (f) == 2 ? 5 : (f) == 3 ? 15 : -1) 12213 #define AF_TIMER1_CC0_PIN(f) ((f) == 0 ? 13 : (f) == 1 ? 10 : (f) == 2 ? 0 : -1) 12214 #define AF_TIMER1_CC1_PIN(f) ((f) == 0 ? 14 : (f) == 1 ? 11 : (f) == 2 ? 1 : -1) 12215 #define AF_TIMER1_CC2_PIN(f) ((f) == 0 ? 15 : (f) == 1 ? 12 : (f) == 2 ? 2 : -1) 12216 #define AF_TIMER1_CDTI0_PIN(f) (-1) 12217 #define AF_TIMER1_CDTI1_PIN(f) (-1) 12218 #define AF_TIMER1_CDTI2_PIN(f) (-1) 12219 #define AF_TIMER2_CC0_PIN(f) ((f) == 0 ? 8 : (f) == 1 ? 12 : (f) == 2 ? 8 : -1) 12220 #define AF_TIMER2_CC1_PIN(f) ((f) == 0 ? 9 : (f) == 1 ? 13 : (f) == 2 ? 9 : -1) 12221 #define AF_TIMER2_CC2_PIN(f) ((f) == 0 ? 10 : (f) == 1 ? 14 : (f) == 2 ? 10 : -1) 12222 #define AF_TIMER2_CDTI0_PIN(f) (-1) 12223 #define AF_TIMER2_CDTI1_PIN(f) (-1) 12224 #define AF_TIMER2_CDTI2_PIN(f) (-1) 12225 #define AF_USART0_TX_PIN(f) ((f) == 0 ? 10 : (f) == 1 ? 7 : (f) == 2 ? 11 : -1) 12226 #define AF_USART0_RX_PIN(f) ((f) == 0 ? 11 : (f) == 1 ? 6 : (f) == 2 ? 10 : -1) 12227 #define AF_USART0_CLK_PIN(f) ((f) == 0 ? 12 : (f) == 1 ? 5 : (f) == 2 ? 9 : -1) 12228 #define AF_USART0_CS_PIN(f) ((f) == 0 ? 13 : (f) == 1 ? 4 : (f) == 2 ? 8 : -1) 12229 #define AF_USART1_TX_PIN(f) ((f) == 0 ? 0 : (f) == 1 ? 0 : -1) 12230 #define AF_USART1_RX_PIN(f) ((f) == 0 ? 1 : (f) == 1 ? 1 : -1) 12231 #define AF_USART1_CLK_PIN(f) ((f) == 0 ? 7 : (f) == 1 ? 2 : -1) 12232 #define AF_USART1_CS_PIN(f) ((f) == 0 ? 8 : (f) == 1 ? 3 : -1) 12233 #define AF_USART2_TX_PIN(f) ((f) == 0 ? 2 : (f) == 1 ? 3 : -1) 12234 #define AF_USART2_RX_PIN(f) ((f) == 0 ? 3 : (f) == 1 ? 4 : -1) 12235 #define AF_USART2_CLK_PIN(f) ((f) == 0 ? 4 : (f) == 1 ? 5 : -1) 12236 #define AF_USART2_CS_PIN(f) ((f) == 0 ? 5 : (f) == 1 ? 6 : -1) 12237 #define AF_UART0_TX_PIN(f) ((f) == 0 ? 6 : (f) == 1 ? 0 : (f) == 2 ? 3 : (f) == 3 ? 14 : -1) 12238 #define AF_UART0_RX_PIN(f) ((f) == 0 ? 7 : (f) == 1 ? 1 : (f) == 2 ? 4 : (f) == 3 ? 15 : -1) 12239 #define AF_UART0_CLK_PIN(f) (-1) 12240 #define AF_UART0_CS_PIN(f) (-1) 12241 #define AF_LEUART0_TX_PIN(f) ((f) == 0 ? 4 : (f) == 1 ? 13 : (f) == 2 ? 14 : -1) 12242 #define AF_LEUART0_RX_PIN(f) ((f) == 0 ? 5 : (f) == 1 ? 14 : (f) == 2 ? 15 : -1) 12243 #define AF_LEUART1_TX_PIN(f) ((f) == 0 ? 6 : (f) == 1 ? 5 : -1) 12244 #define AF_LEUART1_RX_PIN(f) ((f) == 0 ? 7 : (f) == 1 ? 6 : -1) 12245 #define AF_LETIMER0_OUT0_PIN(f) ((f) == 0 ? 6 : (f) == 1 ? 11 : (f) == 2 ? 0 : (f) == 3 ? 4 : -1) 12246 #define AF_LETIMER0_OUT1_PIN(f) ((f) == 0 ? 7 : (f) == 1 ? 12 : (f) == 2 ? 1 : (f) == 3 ? 5 : -1) 12247 #define AF_PCNT0_S0IN_PIN(f) ((f) == 0 ? 13 : (f) == 1 ? 0 : (f) == 2 ? 0 : -1) 12248 #define AF_PCNT0_S1IN_PIN(f) ((f) == 0 ? 14 : (f) == 1 ? 1 : (f) == 2 ? 1 : -1) 12249 #define AF_PCNT1_S0IN_PIN(f) ((f) == 0 ? 4 : (f) == 1 ? 3 : -1) 12250 #define AF_PCNT1_S1IN_PIN(f) ((f) == 0 ? 5 : (f) == 1 ? 4 : -1) 12251 #define AF_PCNT2_S0IN_PIN(f) ((f) == 0 ? 0 : (f) == 1 ? 8 : -1) 12252 #define AF_PCNT2_S1IN_PIN(f) ((f) == 0 ? 1 : (f) == 1 ? 9 : -1) 12253 #define AF_I2C0_SDA_PIN(f) ((f) == 0 ? 0 : (f) == 1 ? 6 : (f) == 2 ? 6 : (f) == 3 ? 14 : -1) 12254 #define AF_I2C0_SCL_PIN(f) ((f) == 0 ? 1 : (f) == 1 ? 7 : (f) == 2 ? 7 : (f) == 3 ? 15 : -1) 12255 #define AF_ACMP0_OUT_PIN(f) ((f) == 0 ? 13 : (f) == 1 ? 2 : -1) 12256 #define AF_ACMP1_OUT_PIN(f) ((f) == 0 ? 2 : (f) == 1 ? 3 : -1) 12257 #define AF_DBG_SWO_PIN(f) ((f) == 0 ? 2 : (f) == 1 ? 15 : -1) 12258 #define AF_DBG_SWDIO_PIN(f) ((f) == 0 ? 1 : (f) == 1 ? 1 : -1) 12259 #define AF_DBG_SWCLK_PIN(f) ((f) == 0 ? 0 : (f) == 1 ? 0 : -1) 12260 12266 #define AF_PORT(c, f) ( \ 12267 (c) == 0 ? AF_CMU_CLK0_PORT((f)) : \ 12268 (c) == 1 ? AF_CMU_CLK1_PORT((f)) : \ 12269 (c) == 2 ? AF_EBI_AD00_PORT((f)) : \ 12270 (c) == 3 ? AF_EBI_AD01_PORT((f)) : \ 12271 (c) == 4 ? AF_EBI_AD02_PORT((f)) : \ 12272 (c) == 5 ? AF_EBI_AD03_PORT((f)) : \ 12273 (c) == 6 ? AF_EBI_AD04_PORT((f)) : \ 12274 (c) == 7 ? AF_EBI_AD05_PORT((f)) : \ 12275 (c) == 8 ? AF_EBI_AD06_PORT((f)) : \ 12276 (c) == 9 ? AF_EBI_AD07_PORT((f)) : \ 12277 (c) == 10 ? AF_EBI_AD08_PORT((f)) : \ 12278 (c) == 11 ? AF_EBI_AD09_PORT((f)) : \ 12279 (c) == 12 ? AF_EBI_AD10_PORT((f)) : \ 12280 (c) == 13 ? AF_EBI_AD11_PORT((f)) : \ 12281 (c) == 14 ? AF_EBI_AD12_PORT((f)) : \ 12282 (c) == 15 ? AF_EBI_AD13_PORT((f)) : \ 12283 (c) == 16 ? AF_EBI_AD14_PORT((f)) : \ 12284 (c) == 17 ? AF_EBI_AD15_PORT((f)) : \ 12285 (c) == 18 ? AF_EBI_CS0_PORT((f)) : \ 12286 (c) == 19 ? AF_EBI_CS1_PORT((f)) : \ 12287 (c) == 20 ? AF_EBI_CS2_PORT((f)) : \ 12288 (c) == 21 ? AF_EBI_CS3_PORT((f)) : \ 12289 (c) == 22 ? AF_EBI_WEn_PORT((f)) : \ 12290 (c) == 23 ? AF_EBI_REn_PORT((f)) : \ 12291 (c) == 24 ? AF_EBI_ARDY_PORT((f)) : \ 12292 (c) == 25 ? AF_EBI_ALE_PORT((f)) : \ 12293 (c) == 26 ? AF_TIMER0_CC0_PORT((f)) : \ 12294 (c) == 27 ? AF_TIMER0_CC1_PORT((f)) : \ 12295 (c) == 28 ? AF_TIMER0_CC2_PORT((f)) : \ 12296 (c) == 29 ? AF_TIMER0_CDTI0_PORT((f)) : \ 12297 (c) == 30 ? AF_TIMER0_CDTI1_PORT((f)) : \ 12298 (c) == 31 ? AF_TIMER0_CDTI2_PORT((f)) : \ 12299 (c) == 32 ? AF_TIMER1_CC0_PORT((f)) : \ 12300 (c) == 33 ? AF_TIMER1_CC1_PORT((f)) : \ 12301 (c) == 34 ? AF_TIMER1_CC2_PORT((f)) : \ 12302 (c) == 35 ? AF_TIMER1_CDTI0_PORT((f)) : \ 12303 (c) == 36 ? AF_TIMER1_CDTI1_PORT((f)) : \ 12304 (c) == 37 ? AF_TIMER1_CDTI2_PORT((f)) : \ 12305 (c) == 38 ? AF_TIMER2_CC0_PORT((f)) : \ 12306 (c) == 39 ? AF_TIMER2_CC1_PORT((f)) : \ 12307 (c) == 40 ? AF_TIMER2_CC2_PORT((f)) : \ 12308 (c) == 41 ? AF_TIMER2_CDTI0_PORT((f)) : \ 12309 (c) == 42 ? AF_TIMER2_CDTI1_PORT((f)) : \ 12310 (c) == 43 ? AF_TIMER2_CDTI2_PORT((f)) : \ 12311 (c) == 44 ? AF_USART0_TX_PORT((f)) : \ 12312 (c) == 45 ? AF_USART0_RX_PORT((f)) : \ 12313 (c) == 46 ? AF_USART0_CLK_PORT((f)) : \ 12314 (c) == 47 ? AF_USART0_CS_PORT((f)) : \ 12315 (c) == 48 ? AF_USART1_TX_PORT((f)) : \ 12316 (c) == 49 ? AF_USART1_RX_PORT((f)) : \ 12317 (c) == 50 ? AF_USART1_CLK_PORT((f)) : \ 12318 (c) == 51 ? AF_USART1_CS_PORT((f)) : \ 12319 (c) == 52 ? AF_USART2_TX_PORT((f)) : \ 12320 (c) == 53 ? AF_USART2_RX_PORT((f)) : \ 12321 (c) == 54 ? AF_USART2_CLK_PORT((f)) : \ 12322 (c) == 55 ? AF_USART2_CS_PORT((f)) : \ 12323 (c) == 56 ? AF_UART0_TX_PORT((f)) : \ 12324 (c) == 57 ? AF_UART0_RX_PORT((f)) : \ 12325 (c) == 58 ? AF_UART0_CLK_PORT((f)) : \ 12326 (c) == 59 ? AF_UART0_CS_PORT((f)) : \ 12327 (c) == 60 ? AF_LEUART0_TX_PORT((f)) : \ 12328 (c) == 61 ? AF_LEUART0_RX_PORT((f)) : \ 12329 (c) == 62 ? AF_LEUART1_TX_PORT((f)) : \ 12330 (c) == 63 ? AF_LEUART1_RX_PORT((f)) : \ 12331 (c) == 64 ? AF_LETIMER0_OUT0_PORT((f)) : \ 12332 (c) == 65 ? AF_LETIMER0_OUT1_PORT((f)) : \ 12333 (c) == 66 ? AF_PCNT0_S0IN_PORT((f)) : \ 12334 (c) == 67 ? AF_PCNT0_S1IN_PORT((f)) : \ 12335 (c) == 68 ? AF_PCNT1_S0IN_PORT((f)) : \ 12336 (c) == 69 ? AF_PCNT1_S1IN_PORT((f)) : \ 12337 (c) == 70 ? AF_PCNT2_S0IN_PORT((f)) : \ 12338 (c) == 71 ? AF_PCNT2_S1IN_PORT((f)) : \ 12339 (c) == 72 ? AF_I2C0_SDA_PORT((f)) : \ 12340 (c) == 73 ? AF_I2C0_SCL_PORT((f)) : \ 12341 (c) == 74 ? AF_ACMP0_OUT_PORT((f)) : \ 12342 (c) == 75 ? AF_ACMP1_OUT_PORT((f)) : \ 12343 (c) == 76 ? AF_DBG_SWO_PORT((f)) : \ 12344 (c) == 77 ? AF_DBG_SWDIO_PORT((f)) : \ 12345 (c) == 78 ? AF_DBG_SWCLK_PORT((f)) : \ 12346 -1) 12347 12348 #define AF_PIN(c, f) ( \ 12349 (c) == 0 ? AF_CMU_CLK0_PIN((f)) : \ 12350 (c) == 1 ? AF_CMU_CLK1_PIN((f)) : \ 12351 (c) == 2 ? AF_EBI_AD00_PIN((f)) : \ 12352 (c) == 3 ? AF_EBI_AD01_PIN((f)) : \ 12353 (c) == 4 ? AF_EBI_AD02_PIN((f)) : \ 12354 (c) == 5 ? AF_EBI_AD03_PIN((f)) : \ 12355 (c) == 6 ? AF_EBI_AD04_PIN((f)) : \ 12356 (c) == 7 ? AF_EBI_AD05_PIN((f)) : \ 12357 (c) == 8 ? AF_EBI_AD06_PIN((f)) : \ 12358 (c) == 9 ? AF_EBI_AD07_PIN((f)) : \ 12359 (c) == 10 ? AF_EBI_AD08_PIN((f)) : \ 12360 (c) == 11 ? AF_EBI_AD09_PIN((f)) : \ 12361 (c) == 12 ? AF_EBI_AD10_PIN((f)) : \ 12362 (c) == 13 ? AF_EBI_AD11_PIN((f)) : \ 12363 (c) == 14 ? AF_EBI_AD12_PIN((f)) : \ 12364 (c) == 15 ? AF_EBI_AD13_PIN((f)) : \ 12365 (c) == 16 ? AF_EBI_AD14_PIN((f)) : \ 12366 (c) == 17 ? AF_EBI_AD15_PIN((f)) : \ 12367 (c) == 18 ? AF_EBI_CS0_PIN((f)) : \ 12368 (c) == 19 ? AF_EBI_CS1_PIN((f)) : \ 12369 (c) == 20 ? AF_EBI_CS2_PIN((f)) : \ 12370 (c) == 21 ? AF_EBI_CS3_PIN((f)) : \ 12371 (c) == 22 ? AF_EBI_WEn_PIN((f)) : \ 12372 (c) == 23 ? AF_EBI_REn_PIN((f)) : \ 12373 (c) == 24 ? AF_EBI_ARDY_PIN((f)) : \ 12374 (c) == 25 ? AF_EBI_ALE_PIN((f)) : \ 12375 (c) == 26 ? AF_TIMER0_CC0_PIN((f)) : \ 12376 (c) == 27 ? AF_TIMER0_CC1_PIN((f)) : \ 12377 (c) == 28 ? AF_TIMER0_CC2_PIN((f)) : \ 12378 (c) == 29 ? AF_TIMER0_CDTI0_PIN((f)) : \ 12379 (c) == 30 ? AF_TIMER0_CDTI1_PIN((f)) : \ 12380 (c) == 31 ? AF_TIMER0_CDTI2_PIN((f)) : \ 12381 (c) == 32 ? AF_TIMER1_CC0_PIN((f)) : \ 12382 (c) == 33 ? AF_TIMER1_CC1_PIN((f)) : \ 12383 (c) == 34 ? AF_TIMER1_CC2_PIN((f)) : \ 12384 (c) == 35 ? AF_TIMER1_CDTI0_PIN((f)) : \ 12385 (c) == 36 ? AF_TIMER1_CDTI1_PIN((f)) : \ 12386 (c) == 37 ? AF_TIMER1_CDTI2_PIN((f)) : \ 12387 (c) == 38 ? AF_TIMER2_CC0_PIN((f)) : \ 12388 (c) == 39 ? AF_TIMER2_CC1_PIN((f)) : \ 12389 (c) == 40 ? AF_TIMER2_CC2_PIN((f)) : \ 12390 (c) == 41 ? AF_TIMER2_CDTI0_PIN((f)) : \ 12391 (c) == 42 ? AF_TIMER2_CDTI1_PIN((f)) : \ 12392 (c) == 43 ? AF_TIMER2_CDTI2_PIN((f)) : \ 12393 (c) == 44 ? AF_USART0_TX_PIN((f)) : \ 12394 (c) == 45 ? AF_USART0_RX_PIN((f)) : \ 12395 (c) == 46 ? AF_USART0_CLK_PIN((f)) : \ 12396 (c) == 47 ? AF_USART0_CS_PIN((f)) : \ 12397 (c) == 48 ? AF_USART1_TX_PIN((f)) : \ 12398 (c) == 49 ? AF_USART1_RX_PIN((f)) : \ 12399 (c) == 50 ? AF_USART1_CLK_PIN((f)) : \ 12400 (c) == 51 ? AF_USART1_CS_PIN((f)) : \ 12401 (c) == 52 ? AF_USART2_TX_PIN((f)) : \ 12402 (c) == 53 ? AF_USART2_RX_PIN((f)) : \ 12403 (c) == 54 ? AF_USART2_CLK_PIN((f)) : \ 12404 (c) == 55 ? AF_USART2_CS_PIN((f)) : \ 12405 (c) == 56 ? AF_UART0_TX_PIN((f)) : \ 12406 (c) == 57 ? AF_UART0_RX_PIN((f)) : \ 12407 (c) == 58 ? AF_UART0_CLK_PIN((f)) : \ 12408 (c) == 59 ? AF_UART0_CS_PIN((f)) : \ 12409 (c) == 60 ? AF_LEUART0_TX_PIN((f)) : \ 12410 (c) == 61 ? AF_LEUART0_RX_PIN((f)) : \ 12411 (c) == 62 ? AF_LEUART1_TX_PIN((f)) : \ 12412 (c) == 63 ? AF_LEUART1_RX_PIN((f)) : \ 12413 (c) == 64 ? AF_LETIMER0_OUT0_PIN((f)) : \ 12414 (c) == 65 ? AF_LETIMER0_OUT1_PIN((f)) : \ 12415 (c) == 66 ? AF_PCNT0_S0IN_PIN((f)) : \ 12416 (c) == 67 ? AF_PCNT0_S1IN_PIN((f)) : \ 12417 (c) == 68 ? AF_PCNT1_S0IN_PIN((f)) : \ 12418 (c) == 69 ? AF_PCNT1_S1IN_PIN((f)) : \ 12419 (c) == 70 ? AF_PCNT2_S0IN_PIN((f)) : \ 12420 (c) == 71 ? AF_PCNT2_S1IN_PIN((f)) : \ 12421 (c) == 72 ? AF_I2C0_SDA_PIN((f)) : \ 12422 (c) == 73 ? AF_I2C0_SCL_PIN((f)) : \ 12423 (c) == 74 ? AF_ACMP0_OUT_PIN((f)) : \ 12424 (c) == 75 ? AF_ACMP1_OUT_PIN((f)) : \ 12425 (c) == 76 ? AF_DBG_SWO_PIN((f)) : \ 12426 (c) == 77 ? AF_DBG_SWDIO_PIN((f)) : \ 12427 (c) == 78 ? AF_DBG_SWCLK_PIN((f)) : \ 12428 -1) 12429 12431 #define AF_COUNT(c) ( \ 12432 (c) == 0 ? 2 : \ 12433 (c) == 1 ? 2 : \ 12434 (c) == 2 ? 1 : \ 12435 (c) == 3 ? 1 : \ 12436 (c) == 4 ? 1 : \ 12437 (c) == 5 ? 1 : \ 12438 (c) == 6 ? 1 : \ 12439 (c) == 7 ? 1 : \ 12440 (c) == 8 ? 1 : \ 12441 (c) == 9 ? 1 : \ 12442 (c) == 10 ? 1 : \ 12443 (c) == 11 ? 1 : \ 12444 (c) == 12 ? 1 : \ 12445 (c) == 13 ? 1 : \ 12446 (c) == 14 ? 1 : \ 12447 (c) == 15 ? 1 : \ 12448 (c) == 16 ? 1 : \ 12449 (c) == 17 ? 1 : \ 12450 (c) == 18 ? 1 : \ 12451 (c) == 19 ? 1 : \ 12452 (c) == 20 ? 1 : \ 12453 (c) == 21 ? 1 : \ 12454 (c) == 22 ? 1 : \ 12455 (c) == 23 ? 1 : \ 12456 (c) == 24 ? 1 : \ 12457 (c) == 25 ? 1 : \ 12458 (c) == 26 ? 4 : \ 12459 (c) == 27 ? 4 : \ 12460 (c) == 28 ? 4 : \ 12461 (c) == 29 ? 4 : \ 12462 (c) == 30 ? 4 : \ 12463 (c) == 31 ? 4 : \ 12464 (c) == 32 ? 3 : \ 12465 (c) == 33 ? 3 : \ 12466 (c) == 34 ? 3 : \ 12467 (c) == 35 ? 0 : \ 12468 (c) == 36 ? 0 : \ 12469 (c) == 37 ? 0 : \ 12470 (c) == 38 ? 3 : \ 12471 (c) == 39 ? 3 : \ 12472 (c) == 40 ? 3 : \ 12473 (c) == 41 ? 0 : \ 12474 (c) == 42 ? 0 : \ 12475 (c) == 43 ? 0 : \ 12476 (c) == 44 ? 3 : \ 12477 (c) == 45 ? 3 : \ 12478 (c) == 46 ? 3 : \ 12479 (c) == 47 ? 3 : \ 12480 (c) == 48 ? 2 : \ 12481 (c) == 49 ? 2 : \ 12482 (c) == 50 ? 2 : \ 12483 (c) == 51 ? 2 : \ 12484 (c) == 52 ? 2 : \ 12485 (c) == 53 ? 2 : \ 12486 (c) == 54 ? 2 : \ 12487 (c) == 55 ? 2 : \ 12488 (c) == 56 ? 4 : \ 12489 (c) == 57 ? 4 : \ 12490 (c) == 58 ? 0 : \ 12491 (c) == 59 ? 0 : \ 12492 (c) == 60 ? 3 : \ 12493 (c) == 61 ? 3 : \ 12494 (c) == 62 ? 2 : \ 12495 (c) == 63 ? 2 : \ 12496 (c) == 64 ? 4 : \ 12497 (c) == 65 ? 4 : \ 12498 (c) == 66 ? 3 : \ 12499 (c) == 67 ? 3 : \ 12500 (c) == 68 ? 2 : \ 12501 (c) == 69 ? 2 : \ 12502 (c) == 70 ? 2 : \ 12503 (c) == 71 ? 2 : \ 12504 (c) == 72 ? 4 : \ 12505 (c) == 73 ? 4 : \ 12506 (c) == 74 ? 2 : \ 12507 (c) == 75 ? 2 : \ 12508 (c) == 76 ? 2 : \ 12509 (c) == 77 ? 2 : \ 12510 (c) == 78 ? 2 : \ 12511 -1) 12512 12513 #endif 12514 12536 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ 12537 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK)); 12538
1.7.3