EFM32G890F128

Collaboration diagram for EFM32G890F128:

Modules
	EFM32G890F128 Core
	EFM32G890F128 Part
	EFM32G890F128 Peripheral TypeDefs
	EFM32G890F128 Bit Fields
Defines
#define	SET_BIT_FIELD(REG, MASK, VALUE, OFFSET)   REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
	Set the value of a bit field within a register.
Typedefs
typedef enum IRQn	IRQn_Type
Enumerations
enum	IRQn {   NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11,   UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2,   SysTick_IRQn = -1, DMA_IRQn = 0, GPIO_EVEN_IRQn = 1, TIMER0_IRQn = 2,   USART0_RX_IRQn = 3, USART0_TX_IRQn = 4, ACMP0_IRQn = 5, ADC0_IRQn = 6,   DAC0_IRQn = 7, I2C0_IRQn = 8, GPIO_ODD_IRQn = 9, TIMER1_IRQn = 10,   TIMER2_IRQn = 11, USART1_RX_IRQn = 12, USART1_TX_IRQn = 13, USART2_RX_IRQn = 14,   USART2_TX_IRQn = 15, UART0_RX_IRQn = 16, UART0_TX_IRQn = 17, LEUART0_IRQn = 18,   LEUART1_IRQn = 19, LETIMER0_IRQn = 20, PCNT0_IRQn = 21, PCNT1_IRQn = 22,   PCNT2_IRQn = 23, RTC_IRQn = 24, CMU_IRQn = 25, VCMP_IRQn = 26,   LCD_IRQn = 27, MSC_IRQn = 28, AES_IRQn = 29 }

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Define Documentation

#define SET_BIT_FIELD	(		REG,
			MASK,
			VALUE,
			OFFSET
	)		REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));

Set the value of a bit field within a register.

Parameters:

REG	The register to update
MASK	The mask for the bit field to update
VALUE	The value to write to the bit field
OFFSET	The number of bits that the field is offset within the register. 0 (zero) means LSB.

Definition at line 12536 of file efm32g890f128.h.

---

Typedef Documentation

typedef enum IRQn IRQn_Type

Interrupt Number Definition

---

Enumeration Type Documentation

enum IRQn

Interrupt Number Definition

Enumerator:

NonMaskableInt_IRQn	2 Non Maskable Interrupt
HardFault_IRQn	3 Cortex-M3 Hard Fault Interrupt
MemoryManagement_IRQn	4 Cortex-M3 Memory Management Interrupt
BusFault_IRQn	5 Cortex-M3 Bus Fault Interrupt
UsageFault_IRQn	6 Cortex-M3 Usage Fault Interrupt
SVCall_IRQn	11 Cortex-M3 SV Call Interrupt
DebugMonitor_IRQn	12 Cortex-M3 Debug Monitor Interrupt
PendSV_IRQn	14 Cortex-M3 Pend SV Interrupt
SysTick_IRQn	15 Cortex-M3 System Tick Interrupt
DMA_IRQn	DMA Interrupt
GPIO_EVEN_IRQn	GPIO_EVEN Interrupt
TIMER0_IRQn	TIMER0 Interrupt
USART0_RX_IRQn	USART0_RX Interrupt
USART0_TX_IRQn	USART0_TX Interrupt
ACMP0_IRQn	ACMP0 Interrupt
ADC0_IRQn	ADC0 Interrupt
DAC0_IRQn	DAC0 Interrupt
I2C0_IRQn	I2C0 Interrupt
GPIO_ODD_IRQn	GPIO_ODD Interrupt
TIMER1_IRQn	TIMER1 Interrupt
TIMER2_IRQn	TIMER2 Interrupt
USART1_RX_IRQn	USART1_RX Interrupt
USART1_TX_IRQn	USART1_TX Interrupt
USART2_RX_IRQn	USART2_RX Interrupt
USART2_TX_IRQn	USART2_TX Interrupt
UART0_RX_IRQn	UART0_RX Interrupt
UART0_TX_IRQn	UART0_TX Interrupt
LEUART0_IRQn	LEUART0 Interrupt
LEUART1_IRQn	LEUART1 Interrupt
LETIMER0_IRQn	LETIMER0 Interrupt
PCNT0_IRQn	PCNT0 Interrupt
PCNT1_IRQn	PCNT1 Interrupt
PCNT2_IRQn	PCNT2 Interrupt
RTC_IRQn	RTC Interrupt
CMU_IRQn	CMU Interrupt
VCMP_IRQn	VCMP Interrupt
LCD_IRQn	LCD Interrupt
MSC_IRQn	MSC Interrupt
AES_IRQn	AES Interrupt

Definition at line 43 of file efm32g890f128.h.

{
/******  Cortex-M3 Processor Exceptions Numbers *******************************************/
  NonMaskableInt_IRQn   = -14,              
  HardFault_IRQn        = -13,              
  MemoryManagement_IRQn = -12,              
  BusFault_IRQn         = -11,              
  UsageFault_IRQn       = -10,              
  SVCall_IRQn           = -5,               
  DebugMonitor_IRQn     = -4,               
  PendSV_IRQn           = -2,               
  SysTick_IRQn          = -1,               
/******  EFM32G Peripheral Interrupt Numbers **********************************************/
  DMA_IRQn              = 0,                
  GPIO_EVEN_IRQn        = 1,                
  TIMER0_IRQn           = 2,                
  USART0_RX_IRQn        = 3,                
  USART0_TX_IRQn        = 4,                
  ACMP0_IRQn            = 5,                
  ADC0_IRQn             = 6,                
  DAC0_IRQn             = 7,                
  I2C0_IRQn             = 8,                
  GPIO_ODD_IRQn         = 9,                
  TIMER1_IRQn           = 10,               
  TIMER2_IRQn           = 11,               
  USART1_RX_IRQn        = 12,               
  USART1_TX_IRQn        = 13,               
  USART2_RX_IRQn        = 14,               
  USART2_TX_IRQn        = 15,               
  UART0_RX_IRQn         = 16,               
  UART0_TX_IRQn         = 17,               
  LEUART0_IRQn          = 18,               
  LEUART1_IRQn          = 19,               
  LETIMER0_IRQn         = 20,               
  PCNT0_IRQn            = 21,               
  PCNT1_IRQn            = 22,               
  PCNT2_IRQn            = 23,               
  RTC_IRQn              = 24,               
  CMU_IRQn              = 25,               
  VCMP_IRQn             = 26,               
  LCD_IRQn              = 27,               
  MSC_IRQn              = 28,               
  AES_IRQn              = 29,               
} IRQn_Type;