EFM32G890F128 DMA

DMA_TypeDef. More...

Collaboration diagram for EFM32G890F128 DMA:

Data Structures
struct	DMA_TypeDef
struct	DMA_DESCRIPTOR_TypeDef
	DMA channel control data structure (descriptor) for PL230 controller. More...
Defines
#define	DMAREQ_ADC0_SINGLE   ((8 << 16) + 0)
#define	DMAREQ_ADC0_SCAN   ((8 << 16) + 1)
#define	DMAREQ_DAC0_CH0   ((10 << 16) + 0)
#define	DMAREQ_DAC0_CH1   ((10 << 16) + 1)
#define	DMAREQ_USART0_RXDATAV   ((12 << 16) + 0)
#define	DMAREQ_USART0_TXBL   ((12 << 16) + 1)
#define	DMAREQ_USART0_TXEMPTY   ((12 << 16) + 2)
#define	DMAREQ_USART1_RXDATAV   ((13 << 16) + 0)
#define	DMAREQ_USART1_TXBL   ((13 << 16) + 1)
#define	DMAREQ_USART1_TXEMPTY   ((13 << 16) + 2)
#define	DMAREQ_USART2_RXDATAV   ((14 << 16) + 0)
#define	DMAREQ_USART2_TXBL   ((14 << 16) + 1)
#define	DMAREQ_USART2_TXEMPTY   ((14 << 16) + 2)
#define	DMAREQ_LEUART0_RXDATAV   ((16 << 16) + 0)
#define	DMAREQ_LEUART0_TXBL   ((16 << 16) + 1)
#define	DMAREQ_LEUART0_TXEMPTY   ((16 << 16) + 2)
#define	DMAREQ_LEUART1_RXDATAV   ((17 << 16) + 0)
#define	DMAREQ_LEUART1_TXBL   ((17 << 16) + 1)
#define	DMAREQ_LEUART1_TXEMPTY   ((17 << 16) + 2)
#define	DMAREQ_I2C0_RXDATAV   ((20 << 16) + 0)
#define	DMAREQ_I2C0_TXBL   ((20 << 16) + 1)
#define	DMAREQ_TIMER0_UFOF   ((24 << 16) + 0)
#define	DMAREQ_TIMER0_CC0   ((24 << 16) + 1)
#define	DMAREQ_TIMER0_CC1   ((24 << 16) + 2)
#define	DMAREQ_TIMER0_CC2   ((24 << 16) + 3)
#define	DMAREQ_TIMER1_UFOF   ((25 << 16) + 0)
#define	DMAREQ_TIMER1_CC0   ((25 << 16) + 1)
#define	DMAREQ_TIMER1_CC1   ((25 << 16) + 2)
#define	DMAREQ_TIMER1_CC2   ((25 << 16) + 3)
#define	DMAREQ_TIMER2_UFOF   ((26 << 16) + 0)
#define	DMAREQ_TIMER2_CC0   ((26 << 16) + 1)
#define	DMAREQ_TIMER2_CC1   ((26 << 16) + 2)
#define	DMAREQ_TIMER2_CC2   ((26 << 16) + 3)
#define	DMAREQ_UART0_RXDATAV   ((44 << 16) + 0)
#define	DMAREQ_UART0_TXBL   ((44 << 16) + 1)
#define	DMAREQ_UART0_TXEMPTY   ((44 << 16) + 2)
#define	DMAREQ_MSC_WDATA   ((48 << 16) + 0)
#define	DMAREQ_AES_DATAWR   ((49 << 16) + 0)
#define	DMAREQ_AES_XORDATAWR   ((49 << 16) + 1)
#define	DMAREQ_AES_DATARD   ((49 << 16) + 2)
#define	DMAREQ_AES_KEYWR   ((49 << 16) + 3)
#define	_DMA_CTRL_DST_INC_MASK   0xC0000000UL
#define	_DMA_CTRL_DST_INC_SHIFT   30
#define	_DMA_CTRL_DST_INC_BYTE   0x00
#define	_DMA_CTRL_DST_INC_HALFWORD   0x01
#define	_DMA_CTRL_DST_INC_WORD   0x02
#define	_DMA_CTRL_DST_INC_NONE   0x03
#define	DMA_CTRL_DST_INC_BYTE   0x00000000UL
#define	DMA_CTRL_DST_INC_HALFWORD   0x40000000UL
#define	DMA_CTRL_DST_INC_WORD   0x80000000UL
#define	DMA_CTRL_DST_INC_NONE   0xC0000000UL
#define	_DMA_CTRL_DST_SIZE_MASK   0x30000000UL
#define	_DMA_CTRL_DST_SIZE_SHIFT   28
#define	_DMA_CTRL_DST_SIZE_BYTE   0x00
#define	_DMA_CTRL_DST_SIZE_HALFWORD   0x01
#define	_DMA_CTRL_DST_SIZE_WORD   0x02
#define	_DMA_CTRL_DST_SIZE_RSVD   0x03
#define	DMA_CTRL_DST_SIZE_BYTE   0x00000000UL
#define	DMA_CTRL_DST_SIZE_HALFWORD   0x10000000UL
#define	DMA_CTRL_DST_SIZE_WORD   0x20000000UL
#define	DMA_CTRL_DST_SIZE_RSVD   0x30000000UL
#define	_DMA_CTRL_SRC_INC_MASK   0x0C000000UL
#define	_DMA_CTRL_SRC_INC_SHIFT   26
#define	_DMA_CTRL_SRC_INC_BYTE   0x00
#define	_DMA_CTRL_SRC_INC_HALFWORD   0x01
#define	_DMA_CTRL_SRC_INC_WORD   0x02
#define	_DMA_CTRL_SRC_INC_NONE   0x03
#define	DMA_CTRL_SRC_INC_BYTE   0x00000000UL
#define	DMA_CTRL_SRC_INC_HALFWORD   0x04000000UL
#define	DMA_CTRL_SRC_INC_WORD   0x08000000UL
#define	DMA_CTRL_SRC_INC_NONE   0x0C000000UL
#define	_DMA_CTRL_SRC_SIZE_MASK   0x03000000UL
#define	_DMA_CTRL_SRC_SIZE_SHIFT   24
#define	_DMA_CTRL_SRC_SIZE_BYTE   0x00
#define	_DMA_CTRL_SRC_SIZE_HALFWORD   0x01
#define	_DMA_CTRL_SRC_SIZE_WORD   0x02
#define	_DMA_CTRL_SRC_SIZE_RSVD   0x03
#define	DMA_CTRL_SRC_SIZE_BYTE   0x00000000UL
#define	DMA_CTRL_SRC_SIZE_HALFWORD   0x01000000UL
#define	DMA_CTRL_SRC_SIZE_WORD   0x02000000UL
#define	DMA_CTRL_SRC_SIZE_RSVD   0x03000000UL
#define	_DMA_CTRL_DST_PROT_CTRL_MASK   0x00E00000UL
#define	_DMA_CTRL_DST_PROT_CTRL_SHIFT   21
#define	DMA_CTRL_DST_PROT_PRIVILEGED   0x00200000UL
#define	DMA_CTRL_DST_PROT_NON_PRIVILEGED   0x00000000UL
#define	_DMA_CTRL_SRC_PROT_CTRL_MASK   0x001C0000UL
#define	_DMA_CTRL_SRC_PROT_CTRL_SHIFT   18
#define	DMA_CTRL_SRC_PROT_PRIVILEGED   0x00040000UL
#define	DMA_CTRL_SRC_PROT_NON_PRIVILEGED   0x00000000UL
#define	_DMA_CTRL_PROT_NON_PRIVILEGED   0x00
#define	_DMA_CTRL_PROT_PRIVILEGED   0x01
#define	_DMA_CTRL_R_POWER_MASK   0x0003C000UL
#define	_DMA_CTRL_R_POWER_SHIFT   14
#define	_DMA_CTRL_R_POWER_1   0x00
#define	_DMA_CTRL_R_POWER_2   0x01
#define	_DMA_CTRL_R_POWER_4   0x02
#define	_DMA_CTRL_R_POWER_8   0x03
#define	_DMA_CTRL_R_POWER_16   0x04
#define	_DMA_CTRL_R_POWER_32   0x05
#define	_DMA_CTRL_R_POWER_64   0x06
#define	_DMA_CTRL_R_POWER_128   0x07
#define	_DMA_CTRL_R_POWER_256   0x08
#define	_DMA_CTRL_R_POWER_512   0x09
#define	_DMA_CTRL_R_POWER_1024   0x0a
#define	DMA_CTRL_R_POWER_1   0x00000000UL
#define	DMA_CTRL_R_POWER_2   0x00004000UL
#define	DMA_CTRL_R_POWER_4   0x00008000UL
#define	DMA_CTRL_R_POWER_8   0x0000c000UL
#define	DMA_CTRL_R_POWER_16   0x00010000UL
#define	DMA_CTRL_R_POWER_32   0x00014000UL
#define	DMA_CTRL_R_POWER_64   0x00018000UL
#define	DMA_CTRL_R_POWER_128   0x0001c000UL
#define	DMA_CTRL_R_POWER_256   0x00020000UL
#define	DMA_CTRL_R_POWER_512   0x00024000UL
#define	DMA_CTRL_R_POWER_1024   0x00028000UL
#define	_DMA_CTRL_N_MINUS_1_MASK   0x00003FF0UL
#define	_DMA_CTRL_N_MINUS_1_SHIFT   4
#define	_DMA_CTRL_NEXT_USEBURST_MASK   0x00000008UL
#define	_DMA_CTRL_NEXT_USEBURST_SHIFT   3
#define	_DMA_CTRL_CYCLE_CTRL_MASK   0x00000007UL
#define	_DMA_CTRL_CYCLE_CTRL_SHIFT   0
#define	_DMA_CTRL_CYCLE_CTRL_INVALID   0x00
#define	_DMA_CTRL_CYCLE_CTRL_BASIC   0x01
#define	_DMA_CTRL_CYCLE_CTRL_AUTO   0x02
#define	_DMA_CTRL_CYCLE_CTRL_PINGPONG   0x03
#define	_DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER   0x04
#define	_DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER_ALT   0x05
#define	_DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER   0x06
#define	_DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT   0x07
#define	DMA_CTRL_CYCLE_CTRL_INVALID   0x00000000UL
#define	DMA_CTRL_CYCLE_CTRL_BASIC   0x00000001UL
#define	DMA_CTRL_CYCLE_CTRL_AUTO   0x00000002UL
#define	DMA_CTRL_CYCLE_CTRL_PINGPONG   0x00000003UL
#define	DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER   0x000000004UL
#define	DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER_ALT   0x000000005UL
#define	DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER   0x000000006UL
#define	DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT   0x000000007UL
#define	_DMA_STATUS_RESETVALUE   0x10070000UL
#define	_DMA_STATUS_MASK   0xF01F00F1UL
#define	DMA_STATUS_EN   (0x1UL << 0)
#define	_DMA_STATUS_EN_SHIFT   0
#define	_DMA_STATUS_EN_MASK   0x1UL
#define	_DMA_STATUS_EN_DEFAULT   0x00000000UL
#define	DMA_STATUS_EN_DEFAULT   (_DMA_STATUS_EN_DEFAULT << 0)
#define	_DMA_STATUS_STATE_SHIFT   4
#define	_DMA_STATUS_STATE_MASK   0xF0UL
#define	_DMA_STATUS_STATE_DEFAULT   0x00000000UL
#define	_DMA_STATUS_STATE_IDLE   0x00000000UL
#define	_DMA_STATUS_STATE_RDCHCTRLDATA   0x00000001UL
#define	_DMA_STATUS_STATE_RDSRCENDPTR   0x00000002UL
#define	_DMA_STATUS_STATE_RDDSTENDPTR   0x00000003UL
#define	_DMA_STATUS_STATE_RDSRCDATA   0x00000004UL
#define	_DMA_STATUS_STATE_WRDSTDATA   0x00000005UL
#define	_DMA_STATUS_STATE_WAITREQCLR   0x00000006UL
#define	_DMA_STATUS_STATE_WRCHCTRLDATA   0x00000007UL
#define	_DMA_STATUS_STATE_STALLED   0x00000008UL
#define	_DMA_STATUS_STATE_DONE   0x00000009UL
#define	_DMA_STATUS_STATE_PERSCATTRANS   0x0000000AUL
#define	DMA_STATUS_STATE_DEFAULT   (_DMA_STATUS_STATE_DEFAULT << 4)
#define	DMA_STATUS_STATE_IDLE   (_DMA_STATUS_STATE_IDLE << 4)
#define	DMA_STATUS_STATE_RDCHCTRLDATA   (_DMA_STATUS_STATE_RDCHCTRLDATA << 4)
#define	DMA_STATUS_STATE_RDSRCENDPTR   (_DMA_STATUS_STATE_RDSRCENDPTR << 4)
#define	DMA_STATUS_STATE_RDDSTENDPTR   (_DMA_STATUS_STATE_RDDSTENDPTR << 4)
#define	DMA_STATUS_STATE_RDSRCDATA   (_DMA_STATUS_STATE_RDSRCDATA << 4)
#define	DMA_STATUS_STATE_WRDSTDATA   (_DMA_STATUS_STATE_WRDSTDATA << 4)
#define	DMA_STATUS_STATE_WAITREQCLR   (_DMA_STATUS_STATE_WAITREQCLR << 4)
#define	DMA_STATUS_STATE_WRCHCTRLDATA   (_DMA_STATUS_STATE_WRCHCTRLDATA << 4)
#define	DMA_STATUS_STATE_STALLED   (_DMA_STATUS_STATE_STALLED << 4)
#define	DMA_STATUS_STATE_DONE   (_DMA_STATUS_STATE_DONE << 4)
#define	DMA_STATUS_STATE_PERSCATTRANS   (_DMA_STATUS_STATE_PERSCATTRANS << 4)
#define	_DMA_STATUS_CHNUM_SHIFT   16
#define	_DMA_STATUS_CHNUM_MASK   0x1F0000UL
#define	_DMA_STATUS_CHNUM_DEFAULT   0x00000007UL
#define	DMA_STATUS_CHNUM_DEFAULT   (_DMA_STATUS_CHNUM_DEFAULT << 16)
#define	_DMA_CONFIG_RESETVALUE   0x00000000UL
#define	_DMA_CONFIG_MASK   0x00000021UL
#define	DMA_CONFIG_EN   (0x1UL << 0)
#define	_DMA_CONFIG_EN_SHIFT   0
#define	_DMA_CONFIG_EN_MASK   0x1UL
#define	_DMA_CONFIG_EN_DEFAULT   0x00000000UL
#define	DMA_CONFIG_EN_DEFAULT   (_DMA_CONFIG_EN_DEFAULT << 0)
#define	DMA_CONFIG_CHPROT   (0x1UL << 5)
#define	_DMA_CONFIG_CHPROT_SHIFT   5
#define	_DMA_CONFIG_CHPROT_MASK   0x20UL
#define	_DMA_CONFIG_CHPROT_DEFAULT   0x00000000UL
#define	DMA_CONFIG_CHPROT_DEFAULT   (_DMA_CONFIG_CHPROT_DEFAULT << 5)
#define	_DMA_CTRLBASE_RESETVALUE   0x00000000UL
#define	_DMA_CTRLBASE_MASK   0xFFFFFFFFUL
#define	_DMA_CTRLBASE_CTRLBASE_SHIFT   0
#define	_DMA_CTRLBASE_CTRLBASE_MASK   0xFFFFFFFFUL
#define	_DMA_CTRLBASE_CTRLBASE_DEFAULT   0x00000000UL
#define	DMA_CTRLBASE_CTRLBASE_DEFAULT   (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0)
#define	_DMA_ALTCTRLBASE_RESETVALUE   0x00000080UL
#define	_DMA_ALTCTRLBASE_MASK   0xFFFFFFFFUL
#define	_DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT   0
#define	_DMA_ALTCTRLBASE_ALTCTRLBASE_MASK   0xFFFFFFFFUL
#define	_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT   0x00000080UL
#define	DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT   (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0)
#define	_DMA_CHWAITSTATUS_RESETVALUE   0x000000FFUL
#define	_DMA_CHWAITSTATUS_MASK   0x000000FFUL
#define	DMA_CHWAITSTATUS_CH0WAITSTATUS   (0x1UL << 0)
#define	_DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT   0
#define	_DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK   0x1UL
#define	_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT   0x00000001UL
#define	DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0)
#define	DMA_CHWAITSTATUS_CH1WAITSTATUS   (0x1UL << 1)
#define	_DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT   1
#define	_DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK   0x2UL
#define	_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT   0x00000001UL
#define	DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1)
#define	DMA_CHWAITSTATUS_CH2WAITSTATUS   (0x1UL << 2)
#define	_DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT   2
#define	_DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK   0x4UL
#define	_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT   0x00000001UL
#define	DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2)
#define	DMA_CHWAITSTATUS_CH3WAITSTATUS   (0x1UL << 3)
#define	_DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT   3
#define	_DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK   0x8UL
#define	_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT   0x00000001UL
#define	DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3)
#define	DMA_CHWAITSTATUS_CH4WAITSTATUS   (0x1UL << 4)
#define	_DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT   4
#define	_DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK   0x10UL
#define	_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT   0x00000001UL
#define	DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4)
#define	DMA_CHWAITSTATUS_CH5WAITSTATUS   (0x1UL << 5)
#define	_DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT   5
#define	_DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK   0x20UL
#define	_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT   0x00000001UL
#define	DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5)
#define	DMA_CHWAITSTATUS_CH6WAITSTATUS   (0x1UL << 6)
#define	_DMA_CHWAITSTATUS_CH6WAITSTATUS_SHIFT   6
#define	_DMA_CHWAITSTATUS_CH6WAITSTATUS_MASK   0x40UL
#define	_DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT   0x00000001UL
#define	DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT << 6)
#define	DMA_CHWAITSTATUS_CH7WAITSTATUS   (0x1UL << 7)
#define	_DMA_CHWAITSTATUS_CH7WAITSTATUS_SHIFT   7
#define	_DMA_CHWAITSTATUS_CH7WAITSTATUS_MASK   0x80UL
#define	_DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT   0x00000001UL
#define	DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT << 7)
#define	_DMA_CHSWREQ_RESETVALUE   0x00000000UL
#define	_DMA_CHSWREQ_MASK   0x000000FFUL
#define	DMA_CHSWREQ_CH0SWREQ   (0x1UL << 0)
#define	_DMA_CHSWREQ_CH0SWREQ_SHIFT   0
#define	_DMA_CHSWREQ_CH0SWREQ_MASK   0x1UL
#define	_DMA_CHSWREQ_CH0SWREQ_DEFAULT   0x00000000UL
#define	DMA_CHSWREQ_CH0SWREQ_DEFAULT   (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0)
#define	DMA_CHSWREQ_CH1SWREQ   (0x1UL << 1)
#define	_DMA_CHSWREQ_CH1SWREQ_SHIFT   1
#define	_DMA_CHSWREQ_CH1SWREQ_MASK   0x2UL
#define	_DMA_CHSWREQ_CH1SWREQ_DEFAULT   0x00000000UL
#define	DMA_CHSWREQ_CH1SWREQ_DEFAULT   (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1)
#define	DMA_CHSWREQ_CH2SWREQ   (0x1UL << 2)
#define	_DMA_CHSWREQ_CH2SWREQ_SHIFT   2
#define	_DMA_CHSWREQ_CH2SWREQ_MASK   0x4UL
#define	_DMA_CHSWREQ_CH2SWREQ_DEFAULT   0x00000000UL
#define	DMA_CHSWREQ_CH2SWREQ_DEFAULT   (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2)
#define	DMA_CHSWREQ_CH3SWREQ   (0x1UL << 3)
#define	_DMA_CHSWREQ_CH3SWREQ_SHIFT   3
#define	_DMA_CHSWREQ_CH3SWREQ_MASK   0x8UL
#define	_DMA_CHSWREQ_CH3SWREQ_DEFAULT   0x00000000UL
#define	DMA_CHSWREQ_CH3SWREQ_DEFAULT   (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3)
#define	DMA_CHSWREQ_CH4SWREQ   (0x1UL << 4)
#define	_DMA_CHSWREQ_CH4SWREQ_SHIFT   4
#define	_DMA_CHSWREQ_CH4SWREQ_MASK   0x10UL
#define	_DMA_CHSWREQ_CH4SWREQ_DEFAULT   0x00000000UL
#define	DMA_CHSWREQ_CH4SWREQ_DEFAULT   (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4)
#define	DMA_CHSWREQ_CH5SWREQ   (0x1UL << 5)
#define	_DMA_CHSWREQ_CH5SWREQ_SHIFT   5
#define	_DMA_CHSWREQ_CH5SWREQ_MASK   0x20UL
#define	_DMA_CHSWREQ_CH5SWREQ_DEFAULT   0x00000000UL
#define	DMA_CHSWREQ_CH5SWREQ_DEFAULT   (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5)
#define	DMA_CHSWREQ_CH6SWREQ   (0x1UL << 6)
#define	_DMA_CHSWREQ_CH6SWREQ_SHIFT   6
#define	_DMA_CHSWREQ_CH6SWREQ_MASK   0x40UL
#define	_DMA_CHSWREQ_CH6SWREQ_DEFAULT   0x00000000UL
#define	DMA_CHSWREQ_CH6SWREQ_DEFAULT   (_DMA_CHSWREQ_CH6SWREQ_DEFAULT << 6)
#define	DMA_CHSWREQ_CH7SWREQ   (0x1UL << 7)
#define	_DMA_CHSWREQ_CH7SWREQ_SHIFT   7
#define	_DMA_CHSWREQ_CH7SWREQ_MASK   0x80UL
#define	_DMA_CHSWREQ_CH7SWREQ_DEFAULT   0x00000000UL
#define	DMA_CHSWREQ_CH7SWREQ_DEFAULT   (_DMA_CHSWREQ_CH7SWREQ_DEFAULT << 7)
#define	_DMA_CHUSEBURSTS_RESETVALUE   0x00000000UL
#define	_DMA_CHUSEBURSTS_MASK   0x000000FFUL
#define	DMA_CHUSEBURSTS_CH0USEBURSTS   (0x1UL << 0)
#define	_DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT   0
#define	_DMA_CHUSEBURSTS_CH0USEBURSTS_MASK   0x1UL
#define	_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT   0x00000000UL
#define	_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST   0x00000000UL
#define	_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY   0x00000001UL
#define	DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0)
#define	DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST   (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0)
#define	DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY   (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0)
#define	DMA_CHUSEBURSTS_CH1USEBURSTS   (0x1UL << 1)
#define	_DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT   1
#define	_DMA_CHUSEBURSTS_CH1USEBURSTS_MASK   0x2UL
#define	_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT   0x00000000UL
#define	DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1)
#define	DMA_CHUSEBURSTS_CH2USEBURSTS   (0x1UL << 2)
#define	_DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT   2
#define	_DMA_CHUSEBURSTS_CH2USEBURSTS_MASK   0x4UL
#define	_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT   0x00000000UL
#define	DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2)
#define	DMA_CHUSEBURSTS_CH3USEBURSTS   (0x1UL << 3)
#define	_DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT   3
#define	_DMA_CHUSEBURSTS_CH3USEBURSTS_MASK   0x8UL
#define	_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT   0x00000000UL
#define	DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3)
#define	DMA_CHUSEBURSTS_CH4USEBURSTS   (0x1UL << 4)
#define	_DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT   4
#define	_DMA_CHUSEBURSTS_CH4USEBURSTS_MASK   0x10UL
#define	_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT   0x00000000UL
#define	DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4)
#define	DMA_CHUSEBURSTS_CH5USEBURSTS   (0x1UL << 5)
#define	_DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT   5
#define	_DMA_CHUSEBURSTS_CH5USEBURSTS_MASK   0x20UL
#define	_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT   0x00000000UL
#define	DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5)
#define	DMA_CHUSEBURSTS_CH6USEBURSTS   (0x1UL << 6)
#define	_DMA_CHUSEBURSTS_CH6USEBURSTS_SHIFT   6
#define	_DMA_CHUSEBURSTS_CH6USEBURSTS_MASK   0x40UL
#define	_DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT   0x00000000UL
#define	DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT << 6)
#define	DMA_CHUSEBURSTS_CH7USEBURSTS   (0x1UL << 7)
#define	_DMA_CHUSEBURSTS_CH7USEBURSTS_SHIFT   7
#define	_DMA_CHUSEBURSTS_CH7USEBURSTS_MASK   0x80UL
#define	_DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT   0x00000000UL
#define	DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT << 7)
#define	_DMA_CHUSEBURSTC_RESETVALUE   0x00000000UL
#define	_DMA_CHUSEBURSTC_MASK   0x000000FFUL
#define	DMA_CHUSEBURSTC_CH0USEBURSTC   (0x1UL << 0)
#define	_DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT   0
#define	_DMA_CHUSEBURSTC_CH0USEBURSTC_MASK   0x1UL
#define	_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT   0x00000000UL
#define	DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0)
#define	DMA_CHUSEBURSTC_CH1USEBURSTC   (0x1UL << 1)
#define	_DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT   1
#define	_DMA_CHUSEBURSTC_CH1USEBURSTC_MASK   0x2UL
#define	_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT   0x00000000UL
#define	DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1)
#define	DMA_CHUSEBURSTC_CH2USEBURSTC   (0x1UL << 2)
#define	_DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT   2
#define	_DMA_CHUSEBURSTC_CH2USEBURSTC_MASK   0x4UL
#define	_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT   0x00000000UL
#define	DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2)
#define	DMA_CHUSEBURSTC_CH3USEBURSTC   (0x1UL << 3)
#define	_DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT   3
#define	_DMA_CHUSEBURSTC_CH3USEBURSTC_MASK   0x8UL
#define	_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT   0x00000000UL
#define	DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3)
#define	DMA_CHUSEBURSTC_CH4USEBURSTC   (0x1UL << 4)
#define	_DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT   4
#define	_DMA_CHUSEBURSTC_CH4USEBURSTC_MASK   0x10UL
#define	_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT   0x00000000UL
#define	DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4)
#define	DMA_CHUSEBURSTC_CH5USEBURSTC   (0x1UL << 5)
#define	_DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT   5
#define	_DMA_CHUSEBURSTC_CH5USEBURSTC_MASK   0x20UL
#define	_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT   0x00000000UL
#define	DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5)
#define	DMA_CHUSEBURSTC_CH6USEBURSTC   (0x1UL << 6)
#define	_DMA_CHUSEBURSTC_CH6USEBURSTC_SHIFT   6
#define	_DMA_CHUSEBURSTC_CH6USEBURSTC_MASK   0x40UL
#define	_DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT   0x00000000UL
#define	DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT << 6)
#define	DMA_CHUSEBURSTC_CH7USEBURSTC   (0x1UL << 7)
#define	_DMA_CHUSEBURSTC_CH7USEBURSTC_SHIFT   7
#define	_DMA_CHUSEBURSTC_CH7USEBURSTC_MASK   0x80UL
#define	_DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT   0x00000000UL
#define	DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT << 7)
#define	_DMA_CHREQMASKS_RESETVALUE   0x00000000UL
#define	_DMA_CHREQMASKS_MASK   0x000000FFUL
#define	DMA_CHREQMASKS_CH0REQMASKS   (0x1UL << 0)
#define	_DMA_CHREQMASKS_CH0REQMASKS_SHIFT   0
#define	_DMA_CHREQMASKS_CH0REQMASKS_MASK   0x1UL
#define	_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT   0x00000000UL
#define	DMA_CHREQMASKS_CH0REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0)
#define	DMA_CHREQMASKS_CH1REQMASKS   (0x1UL << 1)
#define	_DMA_CHREQMASKS_CH1REQMASKS_SHIFT   1
#define	_DMA_CHREQMASKS_CH1REQMASKS_MASK   0x2UL
#define	_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT   0x00000000UL
#define	DMA_CHREQMASKS_CH1REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1)
#define	DMA_CHREQMASKS_CH2REQMASKS   (0x1UL << 2)
#define	_DMA_CHREQMASKS_CH2REQMASKS_SHIFT   2
#define	_DMA_CHREQMASKS_CH2REQMASKS_MASK   0x4UL
#define	_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT   0x00000000UL
#define	DMA_CHREQMASKS_CH2REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2)
#define	DMA_CHREQMASKS_CH3REQMASKS   (0x1UL << 3)
#define	_DMA_CHREQMASKS_CH3REQMASKS_SHIFT   3
#define	_DMA_CHREQMASKS_CH3REQMASKS_MASK   0x8UL
#define	_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT   0x00000000UL
#define	DMA_CHREQMASKS_CH3REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3)
#define	DMA_CHREQMASKS_CH4REQMASKS   (0x1UL << 4)
#define	_DMA_CHREQMASKS_CH4REQMASKS_SHIFT   4
#define	_DMA_CHREQMASKS_CH4REQMASKS_MASK   0x10UL
#define	_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT   0x00000000UL
#define	DMA_CHREQMASKS_CH4REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4)
#define	DMA_CHREQMASKS_CH5REQMASKS   (0x1UL << 5)
#define	_DMA_CHREQMASKS_CH5REQMASKS_SHIFT   5
#define	_DMA_CHREQMASKS_CH5REQMASKS_MASK   0x20UL
#define	_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT   0x00000000UL
#define	DMA_CHREQMASKS_CH5REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5)
#define	DMA_CHREQMASKS_CH6REQMASKS   (0x1UL << 6)
#define	_DMA_CHREQMASKS_CH6REQMASKS_SHIFT   6
#define	_DMA_CHREQMASKS_CH6REQMASKS_MASK   0x40UL
#define	_DMA_CHREQMASKS_CH6REQMASKS_DEFAULT   0x00000000UL
#define	DMA_CHREQMASKS_CH6REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH6REQMASKS_DEFAULT << 6)
#define	DMA_CHREQMASKS_CH7REQMASKS   (0x1UL << 7)
#define	_DMA_CHREQMASKS_CH7REQMASKS_SHIFT   7
#define	_DMA_CHREQMASKS_CH7REQMASKS_MASK   0x80UL
#define	_DMA_CHREQMASKS_CH7REQMASKS_DEFAULT   0x00000000UL
#define	DMA_CHREQMASKS_CH7REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH7REQMASKS_DEFAULT << 7)
#define	_DMA_CHREQMASKC_RESETVALUE   0x00000000UL
#define	_DMA_CHREQMASKC_MASK   0x000000FFUL
#define	DMA_CHREQMASKC_CH0REQMASKC   (0x1UL << 0)
#define	_DMA_CHREQMASKC_CH0REQMASKC_SHIFT   0
#define	_DMA_CHREQMASKC_CH0REQMASKC_MASK   0x1UL
#define	_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT   0x00000000UL
#define	DMA_CHREQMASKC_CH0REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0)
#define	DMA_CHREQMASKC_CH1REQMASKC   (0x1UL << 1)
#define	_DMA_CHREQMASKC_CH1REQMASKC_SHIFT   1
#define	_DMA_CHREQMASKC_CH1REQMASKC_MASK   0x2UL
#define	_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT   0x00000000UL
#define	DMA_CHREQMASKC_CH1REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1)
#define	DMA_CHREQMASKC_CH2REQMASKC   (0x1UL << 2)
#define	_DMA_CHREQMASKC_CH2REQMASKC_SHIFT   2
#define	_DMA_CHREQMASKC_CH2REQMASKC_MASK   0x4UL
#define	_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT   0x00000000UL
#define	DMA_CHREQMASKC_CH2REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2)
#define	DMA_CHREQMASKC_CH3REQMASKC   (0x1UL << 3)
#define	_DMA_CHREQMASKC_CH3REQMASKC_SHIFT   3
#define	_DMA_CHREQMASKC_CH3REQMASKC_MASK   0x8UL
#define	_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT   0x00000000UL
#define	DMA_CHREQMASKC_CH3REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3)
#define	DMA_CHREQMASKC_CH4REQMASKC   (0x1UL << 4)
#define	_DMA_CHREQMASKC_CH4REQMASKC_SHIFT   4
#define	_DMA_CHREQMASKC_CH4REQMASKC_MASK   0x10UL
#define	_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT   0x00000000UL
#define	DMA_CHREQMASKC_CH4REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4)
#define	DMA_CHREQMASKC_CH5REQMASKC   (0x1UL << 5)
#define	_DMA_CHREQMASKC_CH5REQMASKC_SHIFT   5
#define	_DMA_CHREQMASKC_CH5REQMASKC_MASK   0x20UL
#define	_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT   0x00000000UL
#define	DMA_CHREQMASKC_CH5REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5)
#define	DMA_CHREQMASKC_CH6REQMASKC   (0x1UL << 6)
#define	_DMA_CHREQMASKC_CH6REQMASKC_SHIFT   6
#define	_DMA_CHREQMASKC_CH6REQMASKC_MASK   0x40UL
#define	_DMA_CHREQMASKC_CH6REQMASKC_DEFAULT   0x00000000UL
#define	DMA_CHREQMASKC_CH6REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH6REQMASKC_DEFAULT << 6)
#define	DMA_CHREQMASKC_CH7REQMASKC   (0x1UL << 7)
#define	_DMA_CHREQMASKC_CH7REQMASKC_SHIFT   7
#define	_DMA_CHREQMASKC_CH7REQMASKC_MASK   0x80UL
#define	_DMA_CHREQMASKC_CH7REQMASKC_DEFAULT   0x00000000UL
#define	DMA_CHREQMASKC_CH7REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH7REQMASKC_DEFAULT << 7)
#define	_DMA_CHENS_RESETVALUE   0x00000000UL
#define	_DMA_CHENS_MASK   0x000000FFUL
#define	DMA_CHENS_CH0ENS   (0x1UL << 0)
#define	_DMA_CHENS_CH0ENS_SHIFT   0
#define	_DMA_CHENS_CH0ENS_MASK   0x1UL
#define	_DMA_CHENS_CH0ENS_DEFAULT   0x00000000UL
#define	DMA_CHENS_CH0ENS_DEFAULT   (_DMA_CHENS_CH0ENS_DEFAULT << 0)
#define	DMA_CHENS_CH1ENS   (0x1UL << 1)
#define	_DMA_CHENS_CH1ENS_SHIFT   1
#define	_DMA_CHENS_CH1ENS_MASK   0x2UL
#define	_DMA_CHENS_CH1ENS_DEFAULT   0x00000000UL
#define	DMA_CHENS_CH1ENS_DEFAULT   (_DMA_CHENS_CH1ENS_DEFAULT << 1)
#define	DMA_CHENS_CH2ENS   (0x1UL << 2)
#define	_DMA_CHENS_CH2ENS_SHIFT   2
#define	_DMA_CHENS_CH2ENS_MASK   0x4UL
#define	_DMA_CHENS_CH2ENS_DEFAULT   0x00000000UL
#define	DMA_CHENS_CH2ENS_DEFAULT   (_DMA_CHENS_CH2ENS_DEFAULT << 2)
#define	DMA_CHENS_CH3ENS   (0x1UL << 3)
#define	_DMA_CHENS_CH3ENS_SHIFT   3
#define	_DMA_CHENS_CH3ENS_MASK   0x8UL
#define	_DMA_CHENS_CH3ENS_DEFAULT   0x00000000UL
#define	DMA_CHENS_CH3ENS_DEFAULT   (_DMA_CHENS_CH3ENS_DEFAULT << 3)
#define	DMA_CHENS_CH4ENS   (0x1UL << 4)
#define	_DMA_CHENS_CH4ENS_SHIFT   4
#define	_DMA_CHENS_CH4ENS_MASK   0x10UL
#define	_DMA_CHENS_CH4ENS_DEFAULT   0x00000000UL
#define	DMA_CHENS_CH4ENS_DEFAULT   (_DMA_CHENS_CH4ENS_DEFAULT << 4)
#define	DMA_CHENS_CH5ENS   (0x1UL << 5)
#define	_DMA_CHENS_CH5ENS_SHIFT   5
#define	_DMA_CHENS_CH5ENS_MASK   0x20UL
#define	_DMA_CHENS_CH5ENS_DEFAULT   0x00000000UL
#define	DMA_CHENS_CH5ENS_DEFAULT   (_DMA_CHENS_CH5ENS_DEFAULT << 5)
#define	DMA_CHENS_CH6ENS   (0x1UL << 6)
#define	_DMA_CHENS_CH6ENS_SHIFT   6
#define	_DMA_CHENS_CH6ENS_MASK   0x40UL
#define	_DMA_CHENS_CH6ENS_DEFAULT   0x00000000UL
#define	DMA_CHENS_CH6ENS_DEFAULT   (_DMA_CHENS_CH6ENS_DEFAULT << 6)
#define	DMA_CHENS_CH7ENS   (0x1UL << 7)
#define	_DMA_CHENS_CH7ENS_SHIFT   7
#define	_DMA_CHENS_CH7ENS_MASK   0x80UL
#define	_DMA_CHENS_CH7ENS_DEFAULT   0x00000000UL
#define	DMA_CHENS_CH7ENS_DEFAULT   (_DMA_CHENS_CH7ENS_DEFAULT << 7)
#define	_DMA_CHENC_RESETVALUE   0x00000000UL
#define	_DMA_CHENC_MASK   0x000000FFUL
#define	DMA_CHENC_CH0ENC   (0x1UL << 0)
#define	_DMA_CHENC_CH0ENC_SHIFT   0
#define	_DMA_CHENC_CH0ENC_MASK   0x1UL
#define	_DMA_CHENC_CH0ENC_DEFAULT   0x00000000UL
#define	DMA_CHENC_CH0ENC_DEFAULT   (_DMA_CHENC_CH0ENC_DEFAULT << 0)
#define	DMA_CHENC_CH1ENC   (0x1UL << 1)
#define	_DMA_CHENC_CH1ENC_SHIFT   1
#define	_DMA_CHENC_CH1ENC_MASK   0x2UL
#define	_DMA_CHENC_CH1ENC_DEFAULT   0x00000000UL
#define	DMA_CHENC_CH1ENC_DEFAULT   (_DMA_CHENC_CH1ENC_DEFAULT << 1)
#define	DMA_CHENC_CH2ENC   (0x1UL << 2)
#define	_DMA_CHENC_CH2ENC_SHIFT   2
#define	_DMA_CHENC_CH2ENC_MASK   0x4UL
#define	_DMA_CHENC_CH2ENC_DEFAULT   0x00000000UL
#define	DMA_CHENC_CH2ENC_DEFAULT   (_DMA_CHENC_CH2ENC_DEFAULT << 2)
#define	DMA_CHENC_CH3ENC   (0x1UL << 3)
#define	_DMA_CHENC_CH3ENC_SHIFT   3
#define	_DMA_CHENC_CH3ENC_MASK   0x8UL
#define	_DMA_CHENC_CH3ENC_DEFAULT   0x00000000UL
#define	DMA_CHENC_CH3ENC_DEFAULT   (_DMA_CHENC_CH3ENC_DEFAULT << 3)
#define	DMA_CHENC_CH4ENC   (0x1UL << 4)
#define	_DMA_CHENC_CH4ENC_SHIFT   4
#define	_DMA_CHENC_CH4ENC_MASK   0x10UL
#define	_DMA_CHENC_CH4ENC_DEFAULT   0x00000000UL
#define	DMA_CHENC_CH4ENC_DEFAULT   (_DMA_CHENC_CH4ENC_DEFAULT << 4)
#define	DMA_CHENC_CH5ENC   (0x1UL << 5)
#define	_DMA_CHENC_CH5ENC_SHIFT   5
#define	_DMA_CHENC_CH5ENC_MASK   0x20UL
#define	_DMA_CHENC_CH5ENC_DEFAULT   0x00000000UL
#define	DMA_CHENC_CH5ENC_DEFAULT   (_DMA_CHENC_CH5ENC_DEFAULT << 5)
#define	DMA_CHENC_CH6ENC   (0x1UL << 6)
#define	_DMA_CHENC_CH6ENC_SHIFT   6
#define	_DMA_CHENC_CH6ENC_MASK   0x40UL
#define	_DMA_CHENC_CH6ENC_DEFAULT   0x00000000UL
#define	DMA_CHENC_CH6ENC_DEFAULT   (_DMA_CHENC_CH6ENC_DEFAULT << 6)
#define	DMA_CHENC_CH7ENC   (0x1UL << 7)
#define	_DMA_CHENC_CH7ENC_SHIFT   7
#define	_DMA_CHENC_CH7ENC_MASK   0x80UL
#define	_DMA_CHENC_CH7ENC_DEFAULT   0x00000000UL
#define	DMA_CHENC_CH7ENC_DEFAULT   (_DMA_CHENC_CH7ENC_DEFAULT << 7)
#define	_DMA_CHALTS_RESETVALUE   0x00000000UL
#define	_DMA_CHALTS_MASK   0x000000FFUL
#define	DMA_CHALTS_CH0ALTS   (0x1UL << 0)
#define	_DMA_CHALTS_CH0ALTS_SHIFT   0
#define	_DMA_CHALTS_CH0ALTS_MASK   0x1UL
#define	_DMA_CHALTS_CH0ALTS_DEFAULT   0x00000000UL
#define	DMA_CHALTS_CH0ALTS_DEFAULT   (_DMA_CHALTS_CH0ALTS_DEFAULT << 0)
#define	DMA_CHALTS_CH1ALTS   (0x1UL << 1)
#define	_DMA_CHALTS_CH1ALTS_SHIFT   1
#define	_DMA_CHALTS_CH1ALTS_MASK   0x2UL
#define	_DMA_CHALTS_CH1ALTS_DEFAULT   0x00000000UL
#define	DMA_CHALTS_CH1ALTS_DEFAULT   (_DMA_CHALTS_CH1ALTS_DEFAULT << 1)
#define	DMA_CHALTS_CH2ALTS   (0x1UL << 2)
#define	_DMA_CHALTS_CH2ALTS_SHIFT   2
#define	_DMA_CHALTS_CH2ALTS_MASK   0x4UL
#define	_DMA_CHALTS_CH2ALTS_DEFAULT   0x00000000UL
#define	DMA_CHALTS_CH2ALTS_DEFAULT   (_DMA_CHALTS_CH2ALTS_DEFAULT << 2)
#define	DMA_CHALTS_CH3ALTS   (0x1UL << 3)
#define	_DMA_CHALTS_CH3ALTS_SHIFT   3
#define	_DMA_CHALTS_CH3ALTS_MASK   0x8UL
#define	_DMA_CHALTS_CH3ALTS_DEFAULT   0x00000000UL
#define	DMA_CHALTS_CH3ALTS_DEFAULT   (_DMA_CHALTS_CH3ALTS_DEFAULT << 3)
#define	DMA_CHALTS_CH4ALTS   (0x1UL << 4)
#define	_DMA_CHALTS_CH4ALTS_SHIFT   4
#define	_DMA_CHALTS_CH4ALTS_MASK   0x10UL
#define	_DMA_CHALTS_CH4ALTS_DEFAULT   0x00000000UL
#define	DMA_CHALTS_CH4ALTS_DEFAULT   (_DMA_CHALTS_CH4ALTS_DEFAULT << 4)
#define	DMA_CHALTS_CH5ALTS   (0x1UL << 5)
#define	_DMA_CHALTS_CH5ALTS_SHIFT   5
#define	_DMA_CHALTS_CH5ALTS_MASK   0x20UL
#define	_DMA_CHALTS_CH5ALTS_DEFAULT   0x00000000UL
#define	DMA_CHALTS_CH5ALTS_DEFAULT   (_DMA_CHALTS_CH5ALTS_DEFAULT << 5)
#define	DMA_CHALTS_CH6ALTS   (0x1UL << 6)
#define	_DMA_CHALTS_CH6ALTS_SHIFT   6
#define	_DMA_CHALTS_CH6ALTS_MASK   0x40UL
#define	_DMA_CHALTS_CH6ALTS_DEFAULT   0x00000000UL
#define	DMA_CHALTS_CH6ALTS_DEFAULT   (_DMA_CHALTS_CH6ALTS_DEFAULT << 6)
#define	DMA_CHALTS_CH7ALTS   (0x1UL << 7)
#define	_DMA_CHALTS_CH7ALTS_SHIFT   7
#define	_DMA_CHALTS_CH7ALTS_MASK   0x80UL
#define	_DMA_CHALTS_CH7ALTS_DEFAULT   0x00000000UL
#define	DMA_CHALTS_CH7ALTS_DEFAULT   (_DMA_CHALTS_CH7ALTS_DEFAULT << 7)
#define	_DMA_CHALTC_RESETVALUE   0x00000000UL
#define	_DMA_CHALTC_MASK   0x000000FFUL
#define	DMA_CHALTC_CH0ALTC   (0x1UL << 0)
#define	_DMA_CHALTC_CH0ALTC_SHIFT   0
#define	_DMA_CHALTC_CH0ALTC_MASK   0x1UL
#define	_DMA_CHALTC_CH0ALTC_DEFAULT   0x00000000UL
#define	DMA_CHALTC_CH0ALTC_DEFAULT   (_DMA_CHALTC_CH0ALTC_DEFAULT << 0)
#define	DMA_CHALTC_CH1ALTC   (0x1UL << 1)
#define	_DMA_CHALTC_CH1ALTC_SHIFT   1
#define	_DMA_CHALTC_CH1ALTC_MASK   0x2UL
#define	_DMA_CHALTC_CH1ALTC_DEFAULT   0x00000000UL
#define	DMA_CHALTC_CH1ALTC_DEFAULT   (_DMA_CHALTC_CH1ALTC_DEFAULT << 1)
#define	DMA_CHALTC_CH2ALTC   (0x1UL << 2)
#define	_DMA_CHALTC_CH2ALTC_SHIFT   2
#define	_DMA_CHALTC_CH2ALTC_MASK   0x4UL
#define	_DMA_CHALTC_CH2ALTC_DEFAULT   0x00000000UL
#define	DMA_CHALTC_CH2ALTC_DEFAULT   (_DMA_CHALTC_CH2ALTC_DEFAULT << 2)
#define	DMA_CHALTC_CH3ALTC   (0x1UL << 3)
#define	_DMA_CHALTC_CH3ALTC_SHIFT   3
#define	_DMA_CHALTC_CH3ALTC_MASK   0x8UL
#define	_DMA_CHALTC_CH3ALTC_DEFAULT   0x00000000UL
#define	DMA_CHALTC_CH3ALTC_DEFAULT   (_DMA_CHALTC_CH3ALTC_DEFAULT << 3)
#define	DMA_CHALTC_CH4ALTC   (0x1UL << 4)
#define	_DMA_CHALTC_CH4ALTC_SHIFT   4
#define	_DMA_CHALTC_CH4ALTC_MASK   0x10UL
#define	_DMA_CHALTC_CH4ALTC_DEFAULT   0x00000000UL
#define	DMA_CHALTC_CH4ALTC_DEFAULT   (_DMA_CHALTC_CH4ALTC_DEFAULT << 4)
#define	DMA_CHALTC_CH5ALTC   (0x1UL << 5)
#define	_DMA_CHALTC_CH5ALTC_SHIFT   5
#define	_DMA_CHALTC_CH5ALTC_MASK   0x20UL
#define	_DMA_CHALTC_CH5ALTC_DEFAULT   0x00000000UL
#define	DMA_CHALTC_CH5ALTC_DEFAULT   (_DMA_CHALTC_CH5ALTC_DEFAULT << 5)
#define	DMA_CHALTC_CH6ALTC   (0x1UL << 6)
#define	_DMA_CHALTC_CH6ALTC_SHIFT   6
#define	_DMA_CHALTC_CH6ALTC_MASK   0x40UL
#define	_DMA_CHALTC_CH6ALTC_DEFAULT   0x00000000UL
#define	DMA_CHALTC_CH6ALTC_DEFAULT   (_DMA_CHALTC_CH6ALTC_DEFAULT << 6)
#define	DMA_CHALTC_CH7ALTC   (0x1UL << 7)
#define	_DMA_CHALTC_CH7ALTC_SHIFT   7
#define	_DMA_CHALTC_CH7ALTC_MASK   0x80UL
#define	_DMA_CHALTC_CH7ALTC_DEFAULT   0x00000000UL
#define	DMA_CHALTC_CH7ALTC_DEFAULT   (_DMA_CHALTC_CH7ALTC_DEFAULT << 7)
#define	_DMA_CHPRIS_RESETVALUE   0x00000000UL
#define	_DMA_CHPRIS_MASK   0x000000FFUL
#define	DMA_CHPRIS_CH0PRIS   (0x1UL << 0)
#define	_DMA_CHPRIS_CH0PRIS_SHIFT   0
#define	_DMA_CHPRIS_CH0PRIS_MASK   0x1UL
#define	_DMA_CHPRIS_CH0PRIS_DEFAULT   0x00000000UL
#define	DMA_CHPRIS_CH0PRIS_DEFAULT   (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0)
#define	DMA_CHPRIS_CH1PRIS   (0x1UL << 1)
#define	_DMA_CHPRIS_CH1PRIS_SHIFT   1
#define	_DMA_CHPRIS_CH1PRIS_MASK   0x2UL
#define	_DMA_CHPRIS_CH1PRIS_DEFAULT   0x00000000UL
#define	DMA_CHPRIS_CH1PRIS_DEFAULT   (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1)
#define	DMA_CHPRIS_CH2PRIS   (0x1UL << 2)
#define	_DMA_CHPRIS_CH2PRIS_SHIFT   2
#define	_DMA_CHPRIS_CH2PRIS_MASK   0x4UL
#define	_DMA_CHPRIS_CH2PRIS_DEFAULT   0x00000000UL
#define	DMA_CHPRIS_CH2PRIS_DEFAULT   (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2)
#define	DMA_CHPRIS_CH3PRIS   (0x1UL << 3)
#define	_DMA_CHPRIS_CH3PRIS_SHIFT   3
#define	_DMA_CHPRIS_CH3PRIS_MASK   0x8UL
#define	_DMA_CHPRIS_CH3PRIS_DEFAULT   0x00000000UL
#define	DMA_CHPRIS_CH3PRIS_DEFAULT   (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3)
#define	DMA_CHPRIS_CH4PRIS   (0x1UL << 4)
#define	_DMA_CHPRIS_CH4PRIS_SHIFT   4
#define	_DMA_CHPRIS_CH4PRIS_MASK   0x10UL
#define	_DMA_CHPRIS_CH4PRIS_DEFAULT   0x00000000UL
#define	DMA_CHPRIS_CH4PRIS_DEFAULT   (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4)
#define	DMA_CHPRIS_CH5PRIS   (0x1UL << 5)
#define	_DMA_CHPRIS_CH5PRIS_SHIFT   5
#define	_DMA_CHPRIS_CH5PRIS_MASK   0x20UL
#define	_DMA_CHPRIS_CH5PRIS_DEFAULT   0x00000000UL
#define	DMA_CHPRIS_CH5PRIS_DEFAULT   (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5)
#define	DMA_CHPRIS_CH6PRIS   (0x1UL << 6)
#define	_DMA_CHPRIS_CH6PRIS_SHIFT   6
#define	_DMA_CHPRIS_CH6PRIS_MASK   0x40UL
#define	_DMA_CHPRIS_CH6PRIS_DEFAULT   0x00000000UL
#define	DMA_CHPRIS_CH6PRIS_DEFAULT   (_DMA_CHPRIS_CH6PRIS_DEFAULT << 6)
#define	DMA_CHPRIS_CH7PRIS   (0x1UL << 7)
#define	_DMA_CHPRIS_CH7PRIS_SHIFT   7
#define	_DMA_CHPRIS_CH7PRIS_MASK   0x80UL
#define	_DMA_CHPRIS_CH7PRIS_DEFAULT   0x00000000UL
#define	DMA_CHPRIS_CH7PRIS_DEFAULT   (_DMA_CHPRIS_CH7PRIS_DEFAULT << 7)
#define	_DMA_CHPRIC_RESETVALUE   0x00000000UL
#define	_DMA_CHPRIC_MASK   0x000000FFUL
#define	DMA_CHPRIC_CH0PRIC   (0x1UL << 0)
#define	_DMA_CHPRIC_CH0PRIC_SHIFT   0
#define	_DMA_CHPRIC_CH0PRIC_MASK   0x1UL
#define	_DMA_CHPRIC_CH0PRIC_DEFAULT   0x00000000UL
#define	DMA_CHPRIC_CH0PRIC_DEFAULT   (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0)
#define	DMA_CHPRIC_CH1PRIC   (0x1UL << 1)
#define	_DMA_CHPRIC_CH1PRIC_SHIFT   1
#define	_DMA_CHPRIC_CH1PRIC_MASK   0x2UL
#define	_DMA_CHPRIC_CH1PRIC_DEFAULT   0x00000000UL
#define	DMA_CHPRIC_CH1PRIC_DEFAULT   (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1)
#define	DMA_CHPRIC_CH2PRIC   (0x1UL << 2)
#define	_DMA_CHPRIC_CH2PRIC_SHIFT   2
#define	_DMA_CHPRIC_CH2PRIC_MASK   0x4UL
#define	_DMA_CHPRIC_CH2PRIC_DEFAULT   0x00000000UL
#define	DMA_CHPRIC_CH2PRIC_DEFAULT   (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2)
#define	DMA_CHPRIC_CH3PRIC   (0x1UL << 3)
#define	_DMA_CHPRIC_CH3PRIC_SHIFT   3
#define	_DMA_CHPRIC_CH3PRIC_MASK   0x8UL
#define	_DMA_CHPRIC_CH3PRIC_DEFAULT   0x00000000UL
#define	DMA_CHPRIC_CH3PRIC_DEFAULT   (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3)
#define	DMA_CHPRIC_CH4PRIC   (0x1UL << 4)
#define	_DMA_CHPRIC_CH4PRIC_SHIFT   4
#define	_DMA_CHPRIC_CH4PRIC_MASK   0x10UL
#define	_DMA_CHPRIC_CH4PRIC_DEFAULT   0x00000000UL
#define	DMA_CHPRIC_CH4PRIC_DEFAULT   (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4)
#define	DMA_CHPRIC_CH5PRIC   (0x1UL << 5)
#define	_DMA_CHPRIC_CH5PRIC_SHIFT   5
#define	_DMA_CHPRIC_CH5PRIC_MASK   0x20UL
#define	_DMA_CHPRIC_CH5PRIC_DEFAULT   0x00000000UL
#define	DMA_CHPRIC_CH5PRIC_DEFAULT   (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5)
#define	DMA_CHPRIC_CH6PRIC   (0x1UL << 6)
#define	_DMA_CHPRIC_CH6PRIC_SHIFT   6
#define	_DMA_CHPRIC_CH6PRIC_MASK   0x40UL
#define	_DMA_CHPRIC_CH6PRIC_DEFAULT   0x00000000UL
#define	DMA_CHPRIC_CH6PRIC_DEFAULT   (_DMA_CHPRIC_CH6PRIC_DEFAULT << 6)
#define	DMA_CHPRIC_CH7PRIC   (0x1UL << 7)
#define	_DMA_CHPRIC_CH7PRIC_SHIFT   7
#define	_DMA_CHPRIC_CH7PRIC_MASK   0x80UL
#define	_DMA_CHPRIC_CH7PRIC_DEFAULT   0x00000000UL
#define	DMA_CHPRIC_CH7PRIC_DEFAULT   (_DMA_CHPRIC_CH7PRIC_DEFAULT << 7)
#define	_DMA_ERRORC_RESETVALUE   0x00000000UL
#define	_DMA_ERRORC_MASK   0x00000001UL
#define	DMA_ERRORC_ERRORC   (0x1UL << 0)
#define	_DMA_ERRORC_ERRORC_SHIFT   0
#define	_DMA_ERRORC_ERRORC_MASK   0x1UL
#define	_DMA_ERRORC_ERRORC_DEFAULT   0x00000000UL
#define	DMA_ERRORC_ERRORC_DEFAULT   (_DMA_ERRORC_ERRORC_DEFAULT << 0)
#define	_DMA_CHREQSTATUS_RESETVALUE   0x00000000UL
#define	_DMA_CHREQSTATUS_MASK   0x000000FFUL
#define	DMA_CHREQSTATUS_CH0REQSTATUS   (0x1UL << 0)
#define	_DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT   0
#define	_DMA_CHREQSTATUS_CH0REQSTATUS_MASK   0x1UL
#define	_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT   0x00000000UL
#define	DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0)
#define	DMA_CHREQSTATUS_CH1REQSTATUS   (0x1UL << 1)
#define	_DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT   1
#define	_DMA_CHREQSTATUS_CH1REQSTATUS_MASK   0x2UL
#define	_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT   0x00000000UL
#define	DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1)
#define	DMA_CHREQSTATUS_CH2REQSTATUS   (0x1UL << 2)
#define	_DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT   2
#define	_DMA_CHREQSTATUS_CH2REQSTATUS_MASK   0x4UL
#define	_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT   0x00000000UL
#define	DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2)
#define	DMA_CHREQSTATUS_CH3REQSTATUS   (0x1UL << 3)
#define	_DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT   3
#define	_DMA_CHREQSTATUS_CH3REQSTATUS_MASK   0x8UL
#define	_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT   0x00000000UL
#define	DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3)
#define	DMA_CHREQSTATUS_CH4REQSTATUS   (0x1UL << 4)
#define	_DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT   4
#define	_DMA_CHREQSTATUS_CH4REQSTATUS_MASK   0x10UL
#define	_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT   0x00000000UL
#define	DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4)
#define	DMA_CHREQSTATUS_CH5REQSTATUS   (0x1UL << 5)
#define	_DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT   5
#define	_DMA_CHREQSTATUS_CH5REQSTATUS_MASK   0x20UL
#define	_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT   0x00000000UL
#define	DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5)
#define	DMA_CHREQSTATUS_CH6REQSTATUS   (0x1UL << 6)
#define	_DMA_CHREQSTATUS_CH6REQSTATUS_SHIFT   6
#define	_DMA_CHREQSTATUS_CH6REQSTATUS_MASK   0x40UL
#define	_DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT   0x00000000UL
#define	DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT << 6)
#define	DMA_CHREQSTATUS_CH7REQSTATUS   (0x1UL << 7)
#define	_DMA_CHREQSTATUS_CH7REQSTATUS_SHIFT   7
#define	_DMA_CHREQSTATUS_CH7REQSTATUS_MASK   0x80UL
#define	_DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT   0x00000000UL
#define	DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT << 7)
#define	_DMA_CHSREQSTATUS_RESETVALUE   0x00000000UL
#define	_DMA_CHSREQSTATUS_MASK   0x000000FFUL
#define	DMA_CHSREQSTATUS_CH0SREQSTATUS   (0x1UL << 0)
#define	_DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT   0
#define	_DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK   0x1UL
#define	_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT   0x00000000UL
#define	DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0)
#define	DMA_CHSREQSTATUS_CH1SREQSTATUS   (0x1UL << 1)
#define	_DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT   1
#define	_DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK   0x2UL
#define	_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT   0x00000000UL
#define	DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1)
#define	DMA_CHSREQSTATUS_CH2SREQSTATUS   (0x1UL << 2)
#define	_DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT   2
#define	_DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK   0x4UL
#define	_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT   0x00000000UL
#define	DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2)
#define	DMA_CHSREQSTATUS_CH3SREQSTATUS   (0x1UL << 3)
#define	_DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT   3
#define	_DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK   0x8UL
#define	_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT   0x00000000UL
#define	DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3)
#define	DMA_CHSREQSTATUS_CH4SREQSTATUS   (0x1UL << 4)
#define	_DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT   4
#define	_DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK   0x10UL
#define	_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT   0x00000000UL
#define	DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4)
#define	DMA_CHSREQSTATUS_CH5SREQSTATUS   (0x1UL << 5)
#define	_DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT   5
#define	_DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK   0x20UL
#define	_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT   0x00000000UL
#define	DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5)
#define	DMA_CHSREQSTATUS_CH6SREQSTATUS   (0x1UL << 6)
#define	_DMA_CHSREQSTATUS_CH6SREQSTATUS_SHIFT   6
#define	_DMA_CHSREQSTATUS_CH6SREQSTATUS_MASK   0x40UL
#define	_DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT   0x00000000UL
#define	DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT << 6)
#define	DMA_CHSREQSTATUS_CH7SREQSTATUS   (0x1UL << 7)
#define	_DMA_CHSREQSTATUS_CH7SREQSTATUS_SHIFT   7
#define	_DMA_CHSREQSTATUS_CH7SREQSTATUS_MASK   0x80UL
#define	_DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT   0x00000000UL
#define	DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT << 7)
#define	_DMA_IF_RESETVALUE   0x00000000UL
#define	_DMA_IF_MASK   0x800000FFUL
#define	DMA_IF_CH0DONE   (0x1UL << 0)
#define	_DMA_IF_CH0DONE_SHIFT   0
#define	_DMA_IF_CH0DONE_MASK   0x1UL
#define	_DMA_IF_CH0DONE_DEFAULT   0x00000000UL
#define	DMA_IF_CH0DONE_DEFAULT   (_DMA_IF_CH0DONE_DEFAULT << 0)
#define	DMA_IF_CH1DONE   (0x1UL << 1)
#define	_DMA_IF_CH1DONE_SHIFT   1
#define	_DMA_IF_CH1DONE_MASK   0x2UL
#define	_DMA_IF_CH1DONE_DEFAULT   0x00000000UL
#define	DMA_IF_CH1DONE_DEFAULT   (_DMA_IF_CH1DONE_DEFAULT << 1)
#define	DMA_IF_CH2DONE   (0x1UL << 2)
#define	_DMA_IF_CH2DONE_SHIFT   2
#define	_DMA_IF_CH2DONE_MASK   0x4UL
#define	_DMA_IF_CH2DONE_DEFAULT   0x00000000UL
#define	DMA_IF_CH2DONE_DEFAULT   (_DMA_IF_CH2DONE_DEFAULT << 2)
#define	DMA_IF_CH3DONE   (0x1UL << 3)
#define	_DMA_IF_CH3DONE_SHIFT   3
#define	_DMA_IF_CH3DONE_MASK   0x8UL
#define	_DMA_IF_CH3DONE_DEFAULT   0x00000000UL
#define	DMA_IF_CH3DONE_DEFAULT   (_DMA_IF_CH3DONE_DEFAULT << 3)
#define	DMA_IF_CH4DONE   (0x1UL << 4)
#define	_DMA_IF_CH4DONE_SHIFT   4
#define	_DMA_IF_CH4DONE_MASK   0x10UL
#define	_DMA_IF_CH4DONE_DEFAULT   0x00000000UL
#define	DMA_IF_CH4DONE_DEFAULT   (_DMA_IF_CH4DONE_DEFAULT << 4)
#define	DMA_IF_CH5DONE   (0x1UL << 5)
#define	_DMA_IF_CH5DONE_SHIFT   5
#define	_DMA_IF_CH5DONE_MASK   0x20UL
#define	_DMA_IF_CH5DONE_DEFAULT   0x00000000UL
#define	DMA_IF_CH5DONE_DEFAULT   (_DMA_IF_CH5DONE_DEFAULT << 5)
#define	DMA_IF_CH6DONE   (0x1UL << 6)
#define	_DMA_IF_CH6DONE_SHIFT   6
#define	_DMA_IF_CH6DONE_MASK   0x40UL
#define	_DMA_IF_CH6DONE_DEFAULT   0x00000000UL
#define	DMA_IF_CH6DONE_DEFAULT   (_DMA_IF_CH6DONE_DEFAULT << 6)
#define	DMA_IF_CH7DONE   (0x1UL << 7)
#define	_DMA_IF_CH7DONE_SHIFT   7
#define	_DMA_IF_CH7DONE_MASK   0x80UL
#define	_DMA_IF_CH7DONE_DEFAULT   0x00000000UL
#define	DMA_IF_CH7DONE_DEFAULT   (_DMA_IF_CH7DONE_DEFAULT << 7)
#define	DMA_IF_ERR   (0x1UL << 31)
#define	_DMA_IF_ERR_SHIFT   31
#define	_DMA_IF_ERR_MASK   0x80000000UL
#define	_DMA_IF_ERR_DEFAULT   0x00000000UL
#define	DMA_IF_ERR_DEFAULT   (_DMA_IF_ERR_DEFAULT << 31)
#define	_DMA_IFS_RESETVALUE   0x00000000UL
#define	_DMA_IFS_MASK   0x800000FFUL
#define	DMA_IFS_CH0DONE   (0x1UL << 0)
#define	_DMA_IFS_CH0DONE_SHIFT   0
#define	_DMA_IFS_CH0DONE_MASK   0x1UL
#define	_DMA_IFS_CH0DONE_DEFAULT   0x00000000UL
#define	DMA_IFS_CH0DONE_DEFAULT   (_DMA_IFS_CH0DONE_DEFAULT << 0)
#define	DMA_IFS_CH1DONE   (0x1UL << 1)
#define	_DMA_IFS_CH1DONE_SHIFT   1
#define	_DMA_IFS_CH1DONE_MASK   0x2UL
#define	_DMA_IFS_CH1DONE_DEFAULT   0x00000000UL
#define	DMA_IFS_CH1DONE_DEFAULT   (_DMA_IFS_CH1DONE_DEFAULT << 1)
#define	DMA_IFS_CH2DONE   (0x1UL << 2)
#define	_DMA_IFS_CH2DONE_SHIFT   2
#define	_DMA_IFS_CH2DONE_MASK   0x4UL
#define	_DMA_IFS_CH2DONE_DEFAULT   0x00000000UL
#define	DMA_IFS_CH2DONE_DEFAULT   (_DMA_IFS_CH2DONE_DEFAULT << 2)
#define	DMA_IFS_CH3DONE   (0x1UL << 3)
#define	_DMA_IFS_CH3DONE_SHIFT   3
#define	_DMA_IFS_CH3DONE_MASK   0x8UL
#define	_DMA_IFS_CH3DONE_DEFAULT   0x00000000UL
#define	DMA_IFS_CH3DONE_DEFAULT   (_DMA_IFS_CH3DONE_DEFAULT << 3)
#define	DMA_IFS_CH4DONE   (0x1UL << 4)
#define	_DMA_IFS_CH4DONE_SHIFT   4
#define	_DMA_IFS_CH4DONE_MASK   0x10UL
#define	_DMA_IFS_CH4DONE_DEFAULT   0x00000000UL
#define	DMA_IFS_CH4DONE_DEFAULT   (_DMA_IFS_CH4DONE_DEFAULT << 4)
#define	DMA_IFS_CH5DONE   (0x1UL << 5)
#define	_DMA_IFS_CH5DONE_SHIFT   5
#define	_DMA_IFS_CH5DONE_MASK   0x20UL
#define	_DMA_IFS_CH5DONE_DEFAULT   0x00000000UL
#define	DMA_IFS_CH5DONE_DEFAULT   (_DMA_IFS_CH5DONE_DEFAULT << 5)
#define	DMA_IFS_CH6DONE   (0x1UL << 6)
#define	_DMA_IFS_CH6DONE_SHIFT   6
#define	_DMA_IFS_CH6DONE_MASK   0x40UL
#define	_DMA_IFS_CH6DONE_DEFAULT   0x00000000UL
#define	DMA_IFS_CH6DONE_DEFAULT   (_DMA_IFS_CH6DONE_DEFAULT << 6)
#define	DMA_IFS_CH7DONE   (0x1UL << 7)
#define	_DMA_IFS_CH7DONE_SHIFT   7
#define	_DMA_IFS_CH7DONE_MASK   0x80UL
#define	_DMA_IFS_CH7DONE_DEFAULT   0x00000000UL
#define	DMA_IFS_CH7DONE_DEFAULT   (_DMA_IFS_CH7DONE_DEFAULT << 7)
#define	DMA_IFS_ERR   (0x1UL << 31)
#define	_DMA_IFS_ERR_SHIFT   31
#define	_DMA_IFS_ERR_MASK   0x80000000UL
#define	_DMA_IFS_ERR_DEFAULT   0x00000000UL
#define	DMA_IFS_ERR_DEFAULT   (_DMA_IFS_ERR_DEFAULT << 31)
#define	_DMA_IFC_RESETVALUE   0x00000000UL
#define	_DMA_IFC_MASK   0x800000FFUL
#define	DMA_IFC_CH0DONE   (0x1UL << 0)
#define	_DMA_IFC_CH0DONE_SHIFT   0
#define	_DMA_IFC_CH0DONE_MASK   0x1UL
#define	_DMA_IFC_CH0DONE_DEFAULT   0x00000000UL
#define	DMA_IFC_CH0DONE_DEFAULT   (_DMA_IFC_CH0DONE_DEFAULT << 0)
#define	DMA_IFC_CH1DONE   (0x1UL << 1)
#define	_DMA_IFC_CH1DONE_SHIFT   1
#define	_DMA_IFC_CH1DONE_MASK   0x2UL
#define	_DMA_IFC_CH1DONE_DEFAULT   0x00000000UL
#define	DMA_IFC_CH1DONE_DEFAULT   (_DMA_IFC_CH1DONE_DEFAULT << 1)
#define	DMA_IFC_CH2DONE   (0x1UL << 2)
#define	_DMA_IFC_CH2DONE_SHIFT   2
#define	_DMA_IFC_CH2DONE_MASK   0x4UL
#define	_DMA_IFC_CH2DONE_DEFAULT   0x00000000UL
#define	DMA_IFC_CH2DONE_DEFAULT   (_DMA_IFC_CH2DONE_DEFAULT << 2)
#define	DMA_IFC_CH3DONE   (0x1UL << 3)
#define	_DMA_IFC_CH3DONE_SHIFT   3
#define	_DMA_IFC_CH3DONE_MASK   0x8UL
#define	_DMA_IFC_CH3DONE_DEFAULT   0x00000000UL
#define	DMA_IFC_CH3DONE_DEFAULT   (_DMA_IFC_CH3DONE_DEFAULT << 3)
#define	DMA_IFC_CH4DONE   (0x1UL << 4)
#define	_DMA_IFC_CH4DONE_SHIFT   4
#define	_DMA_IFC_CH4DONE_MASK   0x10UL
#define	_DMA_IFC_CH4DONE_DEFAULT   0x00000000UL
#define	DMA_IFC_CH4DONE_DEFAULT   (_DMA_IFC_CH4DONE_DEFAULT << 4)
#define	DMA_IFC_CH5DONE   (0x1UL << 5)
#define	_DMA_IFC_CH5DONE_SHIFT   5
#define	_DMA_IFC_CH5DONE_MASK   0x20UL
#define	_DMA_IFC_CH5DONE_DEFAULT   0x00000000UL
#define	DMA_IFC_CH5DONE_DEFAULT   (_DMA_IFC_CH5DONE_DEFAULT << 5)
#define	DMA_IFC_CH6DONE   (0x1UL << 6)
#define	_DMA_IFC_CH6DONE_SHIFT   6
#define	_DMA_IFC_CH6DONE_MASK   0x40UL
#define	_DMA_IFC_CH6DONE_DEFAULT   0x00000000UL
#define	DMA_IFC_CH6DONE_DEFAULT   (_DMA_IFC_CH6DONE_DEFAULT << 6)
#define	DMA_IFC_CH7DONE   (0x1UL << 7)
#define	_DMA_IFC_CH7DONE_SHIFT   7
#define	_DMA_IFC_CH7DONE_MASK   0x80UL
#define	_DMA_IFC_CH7DONE_DEFAULT   0x00000000UL
#define	DMA_IFC_CH7DONE_DEFAULT   (_DMA_IFC_CH7DONE_DEFAULT << 7)
#define	DMA_IFC_ERR   (0x1UL << 31)
#define	_DMA_IFC_ERR_SHIFT   31
#define	_DMA_IFC_ERR_MASK   0x80000000UL
#define	_DMA_IFC_ERR_DEFAULT   0x00000000UL
#define	DMA_IFC_ERR_DEFAULT   (_DMA_IFC_ERR_DEFAULT << 31)
#define	_DMA_IEN_RESETVALUE   0x00000000UL
#define	_DMA_IEN_MASK   0x800000FFUL
#define	DMA_IEN_CH0DONE   (0x1UL << 0)
#define	_DMA_IEN_CH0DONE_SHIFT   0
#define	_DMA_IEN_CH0DONE_MASK   0x1UL
#define	_DMA_IEN_CH0DONE_DEFAULT   0x00000000UL
#define	DMA_IEN_CH0DONE_DEFAULT   (_DMA_IEN_CH0DONE_DEFAULT << 0)
#define	DMA_IEN_CH1DONE   (0x1UL << 1)
#define	_DMA_IEN_CH1DONE_SHIFT   1
#define	_DMA_IEN_CH1DONE_MASK   0x2UL
#define	_DMA_IEN_CH1DONE_DEFAULT   0x00000000UL
#define	DMA_IEN_CH1DONE_DEFAULT   (_DMA_IEN_CH1DONE_DEFAULT << 1)
#define	DMA_IEN_CH2DONE   (0x1UL << 2)
#define	_DMA_IEN_CH2DONE_SHIFT   2
#define	_DMA_IEN_CH2DONE_MASK   0x4UL
#define	_DMA_IEN_CH2DONE_DEFAULT   0x00000000UL
#define	DMA_IEN_CH2DONE_DEFAULT   (_DMA_IEN_CH2DONE_DEFAULT << 2)
#define	DMA_IEN_CH3DONE   (0x1UL << 3)
#define	_DMA_IEN_CH3DONE_SHIFT   3
#define	_DMA_IEN_CH3DONE_MASK   0x8UL
#define	_DMA_IEN_CH3DONE_DEFAULT   0x00000000UL
#define	DMA_IEN_CH3DONE_DEFAULT   (_DMA_IEN_CH3DONE_DEFAULT << 3)
#define	DMA_IEN_CH4DONE   (0x1UL << 4)
#define	_DMA_IEN_CH4DONE_SHIFT   4
#define	_DMA_IEN_CH4DONE_MASK   0x10UL
#define	_DMA_IEN_CH4DONE_DEFAULT   0x00000000UL
#define	DMA_IEN_CH4DONE_DEFAULT   (_DMA_IEN_CH4DONE_DEFAULT << 4)
#define	DMA_IEN_CH5DONE   (0x1UL << 5)
#define	_DMA_IEN_CH5DONE_SHIFT   5
#define	_DMA_IEN_CH5DONE_MASK   0x20UL
#define	_DMA_IEN_CH5DONE_DEFAULT   0x00000000UL
#define	DMA_IEN_CH5DONE_DEFAULT   (_DMA_IEN_CH5DONE_DEFAULT << 5)
#define	DMA_IEN_CH6DONE   (0x1UL << 6)
#define	_DMA_IEN_CH6DONE_SHIFT   6
#define	_DMA_IEN_CH6DONE_MASK   0x40UL
#define	_DMA_IEN_CH6DONE_DEFAULT   0x00000000UL
#define	DMA_IEN_CH6DONE_DEFAULT   (_DMA_IEN_CH6DONE_DEFAULT << 6)
#define	DMA_IEN_CH7DONE   (0x1UL << 7)
#define	_DMA_IEN_CH7DONE_SHIFT   7
#define	_DMA_IEN_CH7DONE_MASK   0x80UL
#define	_DMA_IEN_CH7DONE_DEFAULT   0x00000000UL
#define	DMA_IEN_CH7DONE_DEFAULT   (_DMA_IEN_CH7DONE_DEFAULT << 7)
#define	DMA_IEN_ERR   (0x1UL << 31)
#define	_DMA_IEN_ERR_SHIFT   31
#define	_DMA_IEN_ERR_MASK   0x80000000UL
#define	_DMA_IEN_ERR_DEFAULT   0x00000000UL
#define	DMA_IEN_ERR_DEFAULT   (_DMA_IEN_ERR_DEFAULT << 31)
#define	_DMA_CH_CTRL_RESETVALUE   0x00000000UL
#define	_DMA_CH_CTRL_MASK   0x003F000FUL
#define	_DMA_CH_CTRL_SIGSEL_SHIFT   0
#define	_DMA_CH_CTRL_SIGSEL_MASK   0xFUL
#define	_DMA_CH_CTRL_SIGSEL_ADC0SINGLE   0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_DAC0CH0   0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_USART0RXDATAV   0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_USART1RXDATAV   0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_USART2RXDATAV   0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV   0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV   0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV   0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_TIMER0UFOF   0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_TIMER1UFOF   0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_TIMER2UFOF   0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_UART0RXDATAV   0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_MSCWDATA   0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_AESDATAWR   0x00000000UL
#define	_DMA_CH_CTRL_SIGSEL_ADC0SCAN   0x00000001UL
#define	_DMA_CH_CTRL_SIGSEL_DAC0CH1   0x00000001UL
#define	_DMA_CH_CTRL_SIGSEL_USART0TXBL   0x00000001UL
#define	_DMA_CH_CTRL_SIGSEL_USART1TXBL   0x00000001UL
#define	_DMA_CH_CTRL_SIGSEL_USART2TXBL   0x00000001UL
#define	_DMA_CH_CTRL_SIGSEL_LEUART0TXBL   0x00000001UL
#define	_DMA_CH_CTRL_SIGSEL_LEUART1TXBL   0x00000001UL
#define	_DMA_CH_CTRL_SIGSEL_I2C0TXBL   0x00000001UL
#define	_DMA_CH_CTRL_SIGSEL_TIMER0CC0   0x00000001UL
#define	_DMA_CH_CTRL_SIGSEL_TIMER1CC0   0x00000001UL
#define	_DMA_CH_CTRL_SIGSEL_TIMER2CC0   0x00000001UL
#define	_DMA_CH_CTRL_SIGSEL_UART0TXBL   0x00000001UL
#define	_DMA_CH_CTRL_SIGSEL_AESXORDATAWR   0x00000001UL
#define	_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY   0x00000002UL
#define	_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY   0x00000002UL
#define	_DMA_CH_CTRL_SIGSEL_USART2TXEMPTY   0x00000002UL
#define	_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY   0x00000002UL
#define	_DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY   0x00000002UL
#define	_DMA_CH_CTRL_SIGSEL_TIMER0CC1   0x00000002UL
#define	_DMA_CH_CTRL_SIGSEL_TIMER1CC1   0x00000002UL
#define	_DMA_CH_CTRL_SIGSEL_TIMER2CC1   0x00000002UL
#define	_DMA_CH_CTRL_SIGSEL_UART0TXEMPTY   0x00000002UL
#define	_DMA_CH_CTRL_SIGSEL_AESDATARD   0x00000002UL
#define	_DMA_CH_CTRL_SIGSEL_TIMER0CC2   0x00000003UL
#define	_DMA_CH_CTRL_SIGSEL_TIMER1CC2   0x00000003UL
#define	_DMA_CH_CTRL_SIGSEL_TIMER2CC2   0x00000003UL
#define	_DMA_CH_CTRL_SIGSEL_AESKEYWR   0x00000003UL
#define	DMA_CH_CTRL_SIGSEL_ADC0SINGLE   (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0)
#define	DMA_CH_CTRL_SIGSEL_DAC0CH0   (_DMA_CH_CTRL_SIGSEL_DAC0CH0 << 0)
#define	DMA_CH_CTRL_SIGSEL_USART0RXDATAV   (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0)
#define	DMA_CH_CTRL_SIGSEL_USART1RXDATAV   (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0)
#define	DMA_CH_CTRL_SIGSEL_USART2RXDATAV   (_DMA_CH_CTRL_SIGSEL_USART2RXDATAV << 0)
#define	DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV   (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0)
#define	DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV   (_DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV << 0)
#define	DMA_CH_CTRL_SIGSEL_I2C0RXDATAV   (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0)
#define	DMA_CH_CTRL_SIGSEL_TIMER0UFOF   (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0)
#define	DMA_CH_CTRL_SIGSEL_TIMER1UFOF   (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0)
#define	DMA_CH_CTRL_SIGSEL_TIMER2UFOF   (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0)
#define	DMA_CH_CTRL_SIGSEL_UART0RXDATAV   (_DMA_CH_CTRL_SIGSEL_UART0RXDATAV << 0)
#define	DMA_CH_CTRL_SIGSEL_MSCWDATA   (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0)
#define	DMA_CH_CTRL_SIGSEL_AESDATAWR   (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0)
#define	DMA_CH_CTRL_SIGSEL_ADC0SCAN   (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0)
#define	DMA_CH_CTRL_SIGSEL_DAC0CH1   (_DMA_CH_CTRL_SIGSEL_DAC0CH1 << 0)
#define	DMA_CH_CTRL_SIGSEL_USART0TXBL   (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0)
#define	DMA_CH_CTRL_SIGSEL_USART1TXBL   (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0)
#define	DMA_CH_CTRL_SIGSEL_USART2TXBL   (_DMA_CH_CTRL_SIGSEL_USART2TXBL << 0)
#define	DMA_CH_CTRL_SIGSEL_LEUART0TXBL   (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0)
#define	DMA_CH_CTRL_SIGSEL_LEUART1TXBL   (_DMA_CH_CTRL_SIGSEL_LEUART1TXBL << 0)
#define	DMA_CH_CTRL_SIGSEL_I2C0TXBL   (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0)
#define	DMA_CH_CTRL_SIGSEL_TIMER0CC0   (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0)
#define	DMA_CH_CTRL_SIGSEL_TIMER1CC0   (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0)
#define	DMA_CH_CTRL_SIGSEL_TIMER2CC0   (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0)
#define	DMA_CH_CTRL_SIGSEL_UART0TXBL   (_DMA_CH_CTRL_SIGSEL_UART0TXBL << 0)
#define	DMA_CH_CTRL_SIGSEL_AESXORDATAWR   (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0)
#define	DMA_CH_CTRL_SIGSEL_USART0TXEMPTY   (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0)
#define	DMA_CH_CTRL_SIGSEL_USART1TXEMPTY   (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0)
#define	DMA_CH_CTRL_SIGSEL_USART2TXEMPTY   (_DMA_CH_CTRL_SIGSEL_USART2TXEMPTY << 0)
#define	DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY   (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0)
#define	DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY   (_DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY << 0)
#define	DMA_CH_CTRL_SIGSEL_TIMER0CC1   (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0)
#define	DMA_CH_CTRL_SIGSEL_TIMER1CC1   (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0)
#define	DMA_CH_CTRL_SIGSEL_TIMER2CC1   (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0)
#define	DMA_CH_CTRL_SIGSEL_UART0TXEMPTY   (_DMA_CH_CTRL_SIGSEL_UART0TXEMPTY << 0)
#define	DMA_CH_CTRL_SIGSEL_AESDATARD   (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0)
#define	DMA_CH_CTRL_SIGSEL_TIMER0CC2   (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0)
#define	DMA_CH_CTRL_SIGSEL_TIMER1CC2   (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0)
#define	DMA_CH_CTRL_SIGSEL_TIMER2CC2   (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0)
#define	DMA_CH_CTRL_SIGSEL_AESKEYWR   (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0)
#define	_DMA_CH_CTRL_SOURCESEL_SHIFT   16
#define	_DMA_CH_CTRL_SOURCESEL_MASK   0x3F0000UL
#define	_DMA_CH_CTRL_SOURCESEL_NONE   0x00000000UL
#define	_DMA_CH_CTRL_SOURCESEL_ADC0   0x00000008UL
#define	_DMA_CH_CTRL_SOURCESEL_DAC0   0x0000000AUL
#define	_DMA_CH_CTRL_SOURCESEL_USART0   0x0000000CUL
#define	_DMA_CH_CTRL_SOURCESEL_USART1   0x0000000DUL
#define	_DMA_CH_CTRL_SOURCESEL_USART2   0x0000000EUL
#define	_DMA_CH_CTRL_SOURCESEL_LEUART0   0x00000010UL
#define	_DMA_CH_CTRL_SOURCESEL_LEUART1   0x00000011UL
#define	_DMA_CH_CTRL_SOURCESEL_I2C0   0x00000014UL
#define	_DMA_CH_CTRL_SOURCESEL_TIMER0   0x00000018UL
#define	_DMA_CH_CTRL_SOURCESEL_TIMER1   0x00000019UL
#define	_DMA_CH_CTRL_SOURCESEL_TIMER2   0x0000001AUL
#define	_DMA_CH_CTRL_SOURCESEL_UART0   0x0000002CUL
#define	_DMA_CH_CTRL_SOURCESEL_MSC   0x00000030UL
#define	_DMA_CH_CTRL_SOURCESEL_AES   0x00000031UL
#define	DMA_CH_CTRL_SOURCESEL_NONE   (_DMA_CH_CTRL_SOURCESEL_NONE << 16)
#define	DMA_CH_CTRL_SOURCESEL_ADC0   (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16)
#define	DMA_CH_CTRL_SOURCESEL_DAC0   (_DMA_CH_CTRL_SOURCESEL_DAC0 << 16)
#define	DMA_CH_CTRL_SOURCESEL_USART0   (_DMA_CH_CTRL_SOURCESEL_USART0 << 16)
#define	DMA_CH_CTRL_SOURCESEL_USART1   (_DMA_CH_CTRL_SOURCESEL_USART1 << 16)
#define	DMA_CH_CTRL_SOURCESEL_USART2   (_DMA_CH_CTRL_SOURCESEL_USART2 << 16)
#define	DMA_CH_CTRL_SOURCESEL_LEUART0   (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16)
#define	DMA_CH_CTRL_SOURCESEL_LEUART1   (_DMA_CH_CTRL_SOURCESEL_LEUART1 << 16)
#define	DMA_CH_CTRL_SOURCESEL_I2C0   (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16)
#define	DMA_CH_CTRL_SOURCESEL_TIMER0   (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16)
#define	DMA_CH_CTRL_SOURCESEL_TIMER1   (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16)
#define	DMA_CH_CTRL_SOURCESEL_TIMER2   (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16)
#define	DMA_CH_CTRL_SOURCESEL_UART0   (_DMA_CH_CTRL_SOURCESEL_UART0 << 16)
#define	DMA_CH_CTRL_SOURCESEL_MSC   (_DMA_CH_CTRL_SOURCESEL_MSC << 16)
#define	DMA_CH_CTRL_SOURCESEL_AES   (_DMA_CH_CTRL_SOURCESEL_AES << 16)

---

Detailed Description

DMA_TypeDef.

---

Define Documentation

#define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT   0x00000080UL

Mode DEFAULT for DMA_ALTCTRLBASE

Definition at line 10012 of file efm32g890f128.h.

#define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK   0xFFFFFFFFUL

Bit mask for DMA_ALTCTRLBASE

Definition at line 10011 of file efm32g890f128.h.

#define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT   0

Shift value for DMA_ALTCTRLBASE

Definition at line 10010 of file efm32g890f128.h.

#define _DMA_ALTCTRLBASE_MASK   0xFFFFFFFFUL

Mask for DMA_ALTCTRLBASE

Definition at line 10009 of file efm32g890f128.h.

#define _DMA_ALTCTRLBASE_RESETVALUE   0x00000080UL

Default value for DMA_ALTCTRLBASE

Definition at line 10008 of file efm32g890f128.h.

#define _DMA_CH_CTRL_MASK   0x003F000FUL

Mask for DMA_CH_CTRL

Definition at line 10842 of file efm32g890f128.h.

#define _DMA_CH_CTRL_RESETVALUE   0x00000000UL

Default value for DMA_CH_CTRL

Definition at line 10841 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_ADC0SCAN   0x00000001UL

Mode ADC0SCAN for DMA_CH_CTRL

Definition at line 10859 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE   0x00000000UL

Mode ADC0SINGLE for DMA_CH_CTRL

Definition at line 10845 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_AESDATARD   0x00000002UL

Mode AESDATARD for DMA_CH_CTRL

Definition at line 10881 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_AESDATAWR   0x00000000UL

Mode AESDATAWR for DMA_CH_CTRL

Definition at line 10858 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_AESKEYWR   0x00000003UL

Mode AESKEYWR for DMA_CH_CTRL

Definition at line 10885 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR   0x00000001UL

Mode AESXORDATAWR for DMA_CH_CTRL

Definition at line 10871 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_DAC0CH0   0x00000000UL

Mode DAC0CH0 for DMA_CH_CTRL

Definition at line 10846 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_DAC0CH1   0x00000001UL

Mode DAC0CH1 for DMA_CH_CTRL

Definition at line 10860 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV   0x00000000UL

Mode I2C0RXDATAV for DMA_CH_CTRL

Definition at line 10852 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_I2C0TXBL   0x00000001UL

Mode I2C0TXBL for DMA_CH_CTRL

Definition at line 10866 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV   0x00000000UL

Mode LEUART0RXDATAV for DMA_CH_CTRL

Definition at line 10850 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL   0x00000001UL

Mode LEUART0TXBL for DMA_CH_CTRL

Definition at line 10864 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY   0x00000002UL

Mode LEUART0TXEMPTY for DMA_CH_CTRL

Definition at line 10875 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV   0x00000000UL

Mode LEUART1RXDATAV for DMA_CH_CTRL

Definition at line 10851 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_LEUART1TXBL   0x00000001UL

Mode LEUART1TXBL for DMA_CH_CTRL

Definition at line 10865 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY   0x00000002UL

Mode LEUART1TXEMPTY for DMA_CH_CTRL

Definition at line 10876 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_MASK   0xFUL

Bit mask for DMA_SIGSEL

Definition at line 10844 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_MSCWDATA   0x00000000UL

Mode MSCWDATA for DMA_CH_CTRL

Definition at line 10857 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_SHIFT   0

Shift value for DMA_SIGSEL

Definition at line 10843 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER0CC0   0x00000001UL

Mode TIMER0CC0 for DMA_CH_CTRL

Definition at line 10867 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER0CC1   0x00000002UL

Mode TIMER0CC1 for DMA_CH_CTRL

Definition at line 10877 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER0CC2   0x00000003UL

Mode TIMER0CC2 for DMA_CH_CTRL

Definition at line 10882 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF   0x00000000UL

Mode TIMER0UFOF for DMA_CH_CTRL

Definition at line 10853 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER1CC0   0x00000001UL

Mode TIMER1CC0 for DMA_CH_CTRL

Definition at line 10868 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER1CC1   0x00000002UL

Mode TIMER1CC1 for DMA_CH_CTRL

Definition at line 10878 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER1CC2   0x00000003UL

Mode TIMER1CC2 for DMA_CH_CTRL

Definition at line 10883 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF   0x00000000UL

Mode TIMER1UFOF for DMA_CH_CTRL

Definition at line 10854 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER2CC0   0x00000001UL

Mode TIMER2CC0 for DMA_CH_CTRL

Definition at line 10869 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER2CC1   0x00000002UL

Mode TIMER2CC1 for DMA_CH_CTRL

Definition at line 10879 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER2CC2   0x00000003UL

Mode TIMER2CC2 for DMA_CH_CTRL

Definition at line 10884 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF   0x00000000UL

Mode TIMER2UFOF for DMA_CH_CTRL

Definition at line 10855 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_UART0RXDATAV   0x00000000UL

Mode UART0RXDATAV for DMA_CH_CTRL

Definition at line 10856 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_UART0TXBL   0x00000001UL

Mode UART0TXBL for DMA_CH_CTRL

Definition at line 10870 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_UART0TXEMPTY   0x00000002UL

Mode UART0TXEMPTY for DMA_CH_CTRL

Definition at line 10880 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV   0x00000000UL

Mode USART0RXDATAV for DMA_CH_CTRL

Definition at line 10847 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_USART0TXBL   0x00000001UL

Mode USART0TXBL for DMA_CH_CTRL

Definition at line 10861 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY   0x00000002UL

Mode USART0TXEMPTY for DMA_CH_CTRL

Definition at line 10872 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV   0x00000000UL

Mode USART1RXDATAV for DMA_CH_CTRL

Definition at line 10848 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_USART1TXBL   0x00000001UL

Mode USART1TXBL for DMA_CH_CTRL

Definition at line 10862 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY   0x00000002UL

Mode USART1TXEMPTY for DMA_CH_CTRL

Definition at line 10873 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_USART2RXDATAV   0x00000000UL

Mode USART2RXDATAV for DMA_CH_CTRL

Definition at line 10849 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_USART2TXBL   0x00000001UL

Mode USART2TXBL for DMA_CH_CTRL

Definition at line 10863 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SIGSEL_USART2TXEMPTY   0x00000002UL

Mode USART2TXEMPTY for DMA_CH_CTRL

Definition at line 10874 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SOURCESEL_ADC0   0x00000008UL

Mode ADC0 for DMA_CH_CTRL

Definition at line 10930 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SOURCESEL_AES   0x00000031UL

Mode AES for DMA_CH_CTRL

Definition at line 10943 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SOURCESEL_DAC0   0x0000000AUL

Mode DAC0 for DMA_CH_CTRL

Definition at line 10931 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SOURCESEL_I2C0   0x00000014UL

Mode I2C0 for DMA_CH_CTRL

Definition at line 10937 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SOURCESEL_LEUART0   0x00000010UL

Mode LEUART0 for DMA_CH_CTRL

Definition at line 10935 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SOURCESEL_LEUART1   0x00000011UL

Mode LEUART1 for DMA_CH_CTRL

Definition at line 10936 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SOURCESEL_MASK   0x3F0000UL

Bit mask for DMA_SOURCESEL

Definition at line 10928 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SOURCESEL_MSC   0x00000030UL

Mode MSC for DMA_CH_CTRL

Definition at line 10942 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SOURCESEL_NONE   0x00000000UL

Mode NONE for DMA_CH_CTRL

Definition at line 10929 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SOURCESEL_SHIFT   16

Shift value for DMA_SOURCESEL

Definition at line 10927 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SOURCESEL_TIMER0   0x00000018UL

Mode TIMER0 for DMA_CH_CTRL

Definition at line 10938 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SOURCESEL_TIMER1   0x00000019UL

Mode TIMER1 for DMA_CH_CTRL

Definition at line 10939 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SOURCESEL_TIMER2   0x0000001AUL

Mode TIMER2 for DMA_CH_CTRL

Definition at line 10940 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SOURCESEL_UART0   0x0000002CUL

Mode UART0 for DMA_CH_CTRL

Definition at line 10941 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SOURCESEL_USART0   0x0000000CUL

Mode USART0 for DMA_CH_CTRL

Definition at line 10932 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SOURCESEL_USART1   0x0000000DUL

Mode USART1 for DMA_CH_CTRL

Definition at line 10933 of file efm32g890f128.h.

#define _DMA_CH_CTRL_SOURCESEL_USART2   0x0000000EUL

Mode USART2 for DMA_CH_CTRL

Definition at line 10934 of file efm32g890f128.h.

#define _DMA_CHALTC_CH0ALTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTC

Definition at line 10421 of file efm32g890f128.h.

#define _DMA_CHALTC_CH0ALTC_MASK   0x1UL

Bit mask for DMA_CH0ALTC

Definition at line 10420 of file efm32g890f128.h.

#define _DMA_CHALTC_CH0ALTC_SHIFT   0

Shift value for DMA_CH0ALTC

Definition at line 10419 of file efm32g890f128.h.

#define _DMA_CHALTC_CH1ALTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTC

Definition at line 10426 of file efm32g890f128.h.

#define _DMA_CHALTC_CH1ALTC_MASK   0x2UL

Bit mask for DMA_CH1ALTC

Definition at line 10425 of file efm32g890f128.h.

#define _DMA_CHALTC_CH1ALTC_SHIFT   1

Shift value for DMA_CH1ALTC

Definition at line 10424 of file efm32g890f128.h.

#define _DMA_CHALTC_CH2ALTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTC

Definition at line 10431 of file efm32g890f128.h.

#define _DMA_CHALTC_CH2ALTC_MASK   0x4UL

Bit mask for DMA_CH2ALTC

Definition at line 10430 of file efm32g890f128.h.

#define _DMA_CHALTC_CH2ALTC_SHIFT   2

Shift value for DMA_CH2ALTC

Definition at line 10429 of file efm32g890f128.h.

#define _DMA_CHALTC_CH3ALTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTC

Definition at line 10436 of file efm32g890f128.h.

#define _DMA_CHALTC_CH3ALTC_MASK   0x8UL

Bit mask for DMA_CH3ALTC

Definition at line 10435 of file efm32g890f128.h.

#define _DMA_CHALTC_CH3ALTC_SHIFT   3

Shift value for DMA_CH3ALTC

Definition at line 10434 of file efm32g890f128.h.

#define _DMA_CHALTC_CH4ALTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTC

Definition at line 10441 of file efm32g890f128.h.

#define _DMA_CHALTC_CH4ALTC_MASK   0x10UL

Bit mask for DMA_CH4ALTC

Definition at line 10440 of file efm32g890f128.h.

#define _DMA_CHALTC_CH4ALTC_SHIFT   4

Shift value for DMA_CH4ALTC

Definition at line 10439 of file efm32g890f128.h.

#define _DMA_CHALTC_CH5ALTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTC

Definition at line 10446 of file efm32g890f128.h.

#define _DMA_CHALTC_CH5ALTC_MASK   0x20UL

Bit mask for DMA_CH5ALTC

Definition at line 10445 of file efm32g890f128.h.

#define _DMA_CHALTC_CH5ALTC_SHIFT   5

Shift value for DMA_CH5ALTC

Definition at line 10444 of file efm32g890f128.h.

#define _DMA_CHALTC_CH6ALTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTC

Definition at line 10451 of file efm32g890f128.h.

#define _DMA_CHALTC_CH6ALTC_MASK   0x40UL

Bit mask for DMA_CH6ALTC

Definition at line 10450 of file efm32g890f128.h.

#define _DMA_CHALTC_CH6ALTC_SHIFT   6

Shift value for DMA_CH6ALTC

Definition at line 10449 of file efm32g890f128.h.

#define _DMA_CHALTC_CH7ALTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTC

Definition at line 10456 of file efm32g890f128.h.

#define _DMA_CHALTC_CH7ALTC_MASK   0x80UL

Bit mask for DMA_CH7ALTC

Definition at line 10455 of file efm32g890f128.h.

#define _DMA_CHALTC_CH7ALTC_SHIFT   7

Shift value for DMA_CH7ALTC

Definition at line 10454 of file efm32g890f128.h.

#define _DMA_CHALTC_MASK   0x000000FFUL

Mask for DMA_CHALTC

Definition at line 10417 of file efm32g890f128.h.

#define _DMA_CHALTC_RESETVALUE   0x00000000UL

Default value for DMA_CHALTC

Definition at line 10416 of file efm32g890f128.h.

#define _DMA_CHALTS_CH0ALTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTS

Definition at line 10377 of file efm32g890f128.h.

#define _DMA_CHALTS_CH0ALTS_MASK   0x1UL

Bit mask for DMA_CH0ALTS

Definition at line 10376 of file efm32g890f128.h.

#define _DMA_CHALTS_CH0ALTS_SHIFT   0

Shift value for DMA_CH0ALTS

Definition at line 10375 of file efm32g890f128.h.

#define _DMA_CHALTS_CH1ALTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTS

Definition at line 10382 of file efm32g890f128.h.

#define _DMA_CHALTS_CH1ALTS_MASK   0x2UL

Bit mask for DMA_CH1ALTS

Definition at line 10381 of file efm32g890f128.h.

#define _DMA_CHALTS_CH1ALTS_SHIFT   1

Shift value for DMA_CH1ALTS

Definition at line 10380 of file efm32g890f128.h.

#define _DMA_CHALTS_CH2ALTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTS

Definition at line 10387 of file efm32g890f128.h.

#define _DMA_CHALTS_CH2ALTS_MASK   0x4UL

Bit mask for DMA_CH2ALTS

Definition at line 10386 of file efm32g890f128.h.

#define _DMA_CHALTS_CH2ALTS_SHIFT   2

Shift value for DMA_CH2ALTS

Definition at line 10385 of file efm32g890f128.h.

#define _DMA_CHALTS_CH3ALTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTS

Definition at line 10392 of file efm32g890f128.h.

#define _DMA_CHALTS_CH3ALTS_MASK   0x8UL

Bit mask for DMA_CH3ALTS

Definition at line 10391 of file efm32g890f128.h.

#define _DMA_CHALTS_CH3ALTS_SHIFT   3

Shift value for DMA_CH3ALTS

Definition at line 10390 of file efm32g890f128.h.

#define _DMA_CHALTS_CH4ALTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTS

Definition at line 10397 of file efm32g890f128.h.

#define _DMA_CHALTS_CH4ALTS_MASK   0x10UL

Bit mask for DMA_CH4ALTS

Definition at line 10396 of file efm32g890f128.h.

#define _DMA_CHALTS_CH4ALTS_SHIFT   4

Shift value for DMA_CH4ALTS

Definition at line 10395 of file efm32g890f128.h.

#define _DMA_CHALTS_CH5ALTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTS

Definition at line 10402 of file efm32g890f128.h.

#define _DMA_CHALTS_CH5ALTS_MASK   0x20UL

Bit mask for DMA_CH5ALTS

Definition at line 10401 of file efm32g890f128.h.

#define _DMA_CHALTS_CH5ALTS_SHIFT   5

Shift value for DMA_CH5ALTS

Definition at line 10400 of file efm32g890f128.h.

#define _DMA_CHALTS_CH6ALTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTS

Definition at line 10407 of file efm32g890f128.h.

#define _DMA_CHALTS_CH6ALTS_MASK   0x40UL

Bit mask for DMA_CH6ALTS

Definition at line 10406 of file efm32g890f128.h.

#define _DMA_CHALTS_CH6ALTS_SHIFT   6

Shift value for DMA_CH6ALTS

Definition at line 10405 of file efm32g890f128.h.

#define _DMA_CHALTS_CH7ALTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTS

Definition at line 10412 of file efm32g890f128.h.

#define _DMA_CHALTS_CH7ALTS_MASK   0x80UL

Bit mask for DMA_CH7ALTS

Definition at line 10411 of file efm32g890f128.h.

#define _DMA_CHALTS_CH7ALTS_SHIFT   7

Shift value for DMA_CH7ALTS

Definition at line 10410 of file efm32g890f128.h.

#define _DMA_CHALTS_MASK   0x000000FFUL

Mask for DMA_CHALTS

Definition at line 10373 of file efm32g890f128.h.

#define _DMA_CHALTS_RESETVALUE   0x00000000UL

Default value for DMA_CHALTS

Definition at line 10372 of file efm32g890f128.h.

#define _DMA_CHENC_CH0ENC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENC

Definition at line 10333 of file efm32g890f128.h.

#define _DMA_CHENC_CH0ENC_MASK   0x1UL

Bit mask for DMA_CH0ENC

Definition at line 10332 of file efm32g890f128.h.

#define _DMA_CHENC_CH0ENC_SHIFT   0

Shift value for DMA_CH0ENC

Definition at line 10331 of file efm32g890f128.h.

#define _DMA_CHENC_CH1ENC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENC

Definition at line 10338 of file efm32g890f128.h.

#define _DMA_CHENC_CH1ENC_MASK   0x2UL

Bit mask for DMA_CH1ENC

Definition at line 10337 of file efm32g890f128.h.

#define _DMA_CHENC_CH1ENC_SHIFT   1

Shift value for DMA_CH1ENC

Definition at line 10336 of file efm32g890f128.h.

#define _DMA_CHENC_CH2ENC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENC

Definition at line 10343 of file efm32g890f128.h.

#define _DMA_CHENC_CH2ENC_MASK   0x4UL

Bit mask for DMA_CH2ENC

Definition at line 10342 of file efm32g890f128.h.

#define _DMA_CHENC_CH2ENC_SHIFT   2

Shift value for DMA_CH2ENC

Definition at line 10341 of file efm32g890f128.h.

#define _DMA_CHENC_CH3ENC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENC

Definition at line 10348 of file efm32g890f128.h.

#define _DMA_CHENC_CH3ENC_MASK   0x8UL

Bit mask for DMA_CH3ENC

Definition at line 10347 of file efm32g890f128.h.

#define _DMA_CHENC_CH3ENC_SHIFT   3

Shift value for DMA_CH3ENC

Definition at line 10346 of file efm32g890f128.h.

#define _DMA_CHENC_CH4ENC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENC

Definition at line 10353 of file efm32g890f128.h.

#define _DMA_CHENC_CH4ENC_MASK   0x10UL

Bit mask for DMA_CH4ENC

Definition at line 10352 of file efm32g890f128.h.

#define _DMA_CHENC_CH4ENC_SHIFT   4

Shift value for DMA_CH4ENC

Definition at line 10351 of file efm32g890f128.h.

#define _DMA_CHENC_CH5ENC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENC

Definition at line 10358 of file efm32g890f128.h.

#define _DMA_CHENC_CH5ENC_MASK   0x20UL

Bit mask for DMA_CH5ENC

Definition at line 10357 of file efm32g890f128.h.

#define _DMA_CHENC_CH5ENC_SHIFT   5

Shift value for DMA_CH5ENC

Definition at line 10356 of file efm32g890f128.h.

#define _DMA_CHENC_CH6ENC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENC

Definition at line 10363 of file efm32g890f128.h.

#define _DMA_CHENC_CH6ENC_MASK   0x40UL

Bit mask for DMA_CH6ENC

Definition at line 10362 of file efm32g890f128.h.

#define _DMA_CHENC_CH6ENC_SHIFT   6

Shift value for DMA_CH6ENC

Definition at line 10361 of file efm32g890f128.h.

#define _DMA_CHENC_CH7ENC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENC

Definition at line 10368 of file efm32g890f128.h.

#define _DMA_CHENC_CH7ENC_MASK   0x80UL

Bit mask for DMA_CH7ENC

Definition at line 10367 of file efm32g890f128.h.

#define _DMA_CHENC_CH7ENC_SHIFT   7

Shift value for DMA_CH7ENC

Definition at line 10366 of file efm32g890f128.h.

#define _DMA_CHENC_MASK   0x000000FFUL

Mask for DMA_CHENC

Definition at line 10329 of file efm32g890f128.h.

#define _DMA_CHENC_RESETVALUE   0x00000000UL

Default value for DMA_CHENC

Definition at line 10328 of file efm32g890f128.h.

#define _DMA_CHENS_CH0ENS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENS

Definition at line 10289 of file efm32g890f128.h.

#define _DMA_CHENS_CH0ENS_MASK   0x1UL

Bit mask for DMA_CH0ENS

Definition at line 10288 of file efm32g890f128.h.

#define _DMA_CHENS_CH0ENS_SHIFT   0

Shift value for DMA_CH0ENS

Definition at line 10287 of file efm32g890f128.h.

#define _DMA_CHENS_CH1ENS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENS

Definition at line 10294 of file efm32g890f128.h.

#define _DMA_CHENS_CH1ENS_MASK   0x2UL

Bit mask for DMA_CH1ENS

Definition at line 10293 of file efm32g890f128.h.

#define _DMA_CHENS_CH1ENS_SHIFT   1

Shift value for DMA_CH1ENS

Definition at line 10292 of file efm32g890f128.h.

#define _DMA_CHENS_CH2ENS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENS

Definition at line 10299 of file efm32g890f128.h.

#define _DMA_CHENS_CH2ENS_MASK   0x4UL

Bit mask for DMA_CH2ENS

Definition at line 10298 of file efm32g890f128.h.

#define _DMA_CHENS_CH2ENS_SHIFT   2

Shift value for DMA_CH2ENS

Definition at line 10297 of file efm32g890f128.h.

#define _DMA_CHENS_CH3ENS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENS

Definition at line 10304 of file efm32g890f128.h.

#define _DMA_CHENS_CH3ENS_MASK   0x8UL

Bit mask for DMA_CH3ENS

Definition at line 10303 of file efm32g890f128.h.

#define _DMA_CHENS_CH3ENS_SHIFT   3

Shift value for DMA_CH3ENS

Definition at line 10302 of file efm32g890f128.h.

#define _DMA_CHENS_CH4ENS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENS

Definition at line 10309 of file efm32g890f128.h.

#define _DMA_CHENS_CH4ENS_MASK   0x10UL

Bit mask for DMA_CH4ENS

Definition at line 10308 of file efm32g890f128.h.

#define _DMA_CHENS_CH4ENS_SHIFT   4

Shift value for DMA_CH4ENS

Definition at line 10307 of file efm32g890f128.h.

#define _DMA_CHENS_CH5ENS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENS

Definition at line 10314 of file efm32g890f128.h.

#define _DMA_CHENS_CH5ENS_MASK   0x20UL

Bit mask for DMA_CH5ENS

Definition at line 10313 of file efm32g890f128.h.

#define _DMA_CHENS_CH5ENS_SHIFT   5

Shift value for DMA_CH5ENS

Definition at line 10312 of file efm32g890f128.h.

#define _DMA_CHENS_CH6ENS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENS

Definition at line 10319 of file efm32g890f128.h.

#define _DMA_CHENS_CH6ENS_MASK   0x40UL

Bit mask for DMA_CH6ENS

Definition at line 10318 of file efm32g890f128.h.

#define _DMA_CHENS_CH6ENS_SHIFT   6

Shift value for DMA_CH6ENS

Definition at line 10317 of file efm32g890f128.h.

#define _DMA_CHENS_CH7ENS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENS

Definition at line 10324 of file efm32g890f128.h.

#define _DMA_CHENS_CH7ENS_MASK   0x80UL

Bit mask for DMA_CH7ENS

Definition at line 10323 of file efm32g890f128.h.

#define _DMA_CHENS_CH7ENS_SHIFT   7

Shift value for DMA_CH7ENS

Definition at line 10322 of file efm32g890f128.h.

#define _DMA_CHENS_MASK   0x000000FFUL

Mask for DMA_CHENS

Definition at line 10285 of file efm32g890f128.h.

#define _DMA_CHENS_RESETVALUE   0x00000000UL

Default value for DMA_CHENS

Definition at line 10284 of file efm32g890f128.h.

#define _DMA_CHPRIC_CH0PRIC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIC

Definition at line 10509 of file efm32g890f128.h.

#define _DMA_CHPRIC_CH0PRIC_MASK   0x1UL

Bit mask for DMA_CH0PRIC

Definition at line 10508 of file efm32g890f128.h.

#define _DMA_CHPRIC_CH0PRIC_SHIFT   0

Shift value for DMA_CH0PRIC

Definition at line 10507 of file efm32g890f128.h.

#define _DMA_CHPRIC_CH1PRIC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIC

Definition at line 10514 of file efm32g890f128.h.

#define _DMA_CHPRIC_CH1PRIC_MASK   0x2UL

Bit mask for DMA_CH1PRIC

Definition at line 10513 of file efm32g890f128.h.

#define _DMA_CHPRIC_CH1PRIC_SHIFT   1

Shift value for DMA_CH1PRIC

Definition at line 10512 of file efm32g890f128.h.

#define _DMA_CHPRIC_CH2PRIC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIC

Definition at line 10519 of file efm32g890f128.h.

#define _DMA_CHPRIC_CH2PRIC_MASK   0x4UL

Bit mask for DMA_CH2PRIC

Definition at line 10518 of file efm32g890f128.h.

#define _DMA_CHPRIC_CH2PRIC_SHIFT   2

Shift value for DMA_CH2PRIC

Definition at line 10517 of file efm32g890f128.h.

#define _DMA_CHPRIC_CH3PRIC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIC

Definition at line 10524 of file efm32g890f128.h.

#define _DMA_CHPRIC_CH3PRIC_MASK   0x8UL

Bit mask for DMA_CH3PRIC

Definition at line 10523 of file efm32g890f128.h.

#define _DMA_CHPRIC_CH3PRIC_SHIFT   3

Shift value for DMA_CH3PRIC

Definition at line 10522 of file efm32g890f128.h.

#define _DMA_CHPRIC_CH4PRIC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIC

Definition at line 10529 of file efm32g890f128.h.

#define _DMA_CHPRIC_CH4PRIC_MASK   0x10UL

Bit mask for DMA_CH4PRIC

Definition at line 10528 of file efm32g890f128.h.

#define _DMA_CHPRIC_CH4PRIC_SHIFT   4

Shift value for DMA_CH4PRIC

Definition at line 10527 of file efm32g890f128.h.

#define _DMA_CHPRIC_CH5PRIC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIC

Definition at line 10534 of file efm32g890f128.h.

#define _DMA_CHPRIC_CH5PRIC_MASK   0x20UL

Bit mask for DMA_CH5PRIC

Definition at line 10533 of file efm32g890f128.h.

#define _DMA_CHPRIC_CH5PRIC_SHIFT   5

Shift value for DMA_CH5PRIC

Definition at line 10532 of file efm32g890f128.h.

#define _DMA_CHPRIC_CH6PRIC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIC

Definition at line 10539 of file efm32g890f128.h.

#define _DMA_CHPRIC_CH6PRIC_MASK   0x40UL

Bit mask for DMA_CH6PRIC

Definition at line 10538 of file efm32g890f128.h.

#define _DMA_CHPRIC_CH6PRIC_SHIFT   6

Shift value for DMA_CH6PRIC

Definition at line 10537 of file efm32g890f128.h.

#define _DMA_CHPRIC_CH7PRIC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIC

Definition at line 10544 of file efm32g890f128.h.

#define _DMA_CHPRIC_CH7PRIC_MASK   0x80UL

Bit mask for DMA_CH7PRIC

Definition at line 10543 of file efm32g890f128.h.

#define _DMA_CHPRIC_CH7PRIC_SHIFT   7

Shift value for DMA_CH7PRIC

Definition at line 10542 of file efm32g890f128.h.

#define _DMA_CHPRIC_MASK   0x000000FFUL

Mask for DMA_CHPRIC

Definition at line 10505 of file efm32g890f128.h.

#define _DMA_CHPRIC_RESETVALUE   0x00000000UL

Default value for DMA_CHPRIC

Definition at line 10504 of file efm32g890f128.h.

#define _DMA_CHPRIS_CH0PRIS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIS

Definition at line 10465 of file efm32g890f128.h.

#define _DMA_CHPRIS_CH0PRIS_MASK   0x1UL

Bit mask for DMA_CH0PRIS

Definition at line 10464 of file efm32g890f128.h.

#define _DMA_CHPRIS_CH0PRIS_SHIFT   0

Shift value for DMA_CH0PRIS

Definition at line 10463 of file efm32g890f128.h.

#define _DMA_CHPRIS_CH1PRIS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIS

Definition at line 10470 of file efm32g890f128.h.

#define _DMA_CHPRIS_CH1PRIS_MASK   0x2UL

Bit mask for DMA_CH1PRIS

Definition at line 10469 of file efm32g890f128.h.

#define _DMA_CHPRIS_CH1PRIS_SHIFT   1

Shift value for DMA_CH1PRIS

Definition at line 10468 of file efm32g890f128.h.

#define _DMA_CHPRIS_CH2PRIS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIS

Definition at line 10475 of file efm32g890f128.h.

#define _DMA_CHPRIS_CH2PRIS_MASK   0x4UL

Bit mask for DMA_CH2PRIS

Definition at line 10474 of file efm32g890f128.h.

#define _DMA_CHPRIS_CH2PRIS_SHIFT   2

Shift value for DMA_CH2PRIS

Definition at line 10473 of file efm32g890f128.h.

#define _DMA_CHPRIS_CH3PRIS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIS

Definition at line 10480 of file efm32g890f128.h.

#define _DMA_CHPRIS_CH3PRIS_MASK   0x8UL

Bit mask for DMA_CH3PRIS

Definition at line 10479 of file efm32g890f128.h.

#define _DMA_CHPRIS_CH3PRIS_SHIFT   3

Shift value for DMA_CH3PRIS

Definition at line 10478 of file efm32g890f128.h.

#define _DMA_CHPRIS_CH4PRIS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIS

Definition at line 10485 of file efm32g890f128.h.

#define _DMA_CHPRIS_CH4PRIS_MASK   0x10UL

Bit mask for DMA_CH4PRIS

Definition at line 10484 of file efm32g890f128.h.

#define _DMA_CHPRIS_CH4PRIS_SHIFT   4

Shift value for DMA_CH4PRIS

Definition at line 10483 of file efm32g890f128.h.

#define _DMA_CHPRIS_CH5PRIS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIS

Definition at line 10490 of file efm32g890f128.h.

#define _DMA_CHPRIS_CH5PRIS_MASK   0x20UL

Bit mask for DMA_CH5PRIS

Definition at line 10489 of file efm32g890f128.h.

#define _DMA_CHPRIS_CH5PRIS_SHIFT   5

Shift value for DMA_CH5PRIS

Definition at line 10488 of file efm32g890f128.h.

#define _DMA_CHPRIS_CH6PRIS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIS

Definition at line 10495 of file efm32g890f128.h.

#define _DMA_CHPRIS_CH6PRIS_MASK   0x40UL

Bit mask for DMA_CH6PRIS

Definition at line 10494 of file efm32g890f128.h.

#define _DMA_CHPRIS_CH6PRIS_SHIFT   6

Shift value for DMA_CH6PRIS

Definition at line 10493 of file efm32g890f128.h.

#define _DMA_CHPRIS_CH7PRIS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIS

Definition at line 10500 of file efm32g890f128.h.

#define _DMA_CHPRIS_CH7PRIS_MASK   0x80UL

Bit mask for DMA_CH7PRIS

Definition at line 10499 of file efm32g890f128.h.

#define _DMA_CHPRIS_CH7PRIS_SHIFT   7

Shift value for DMA_CH7PRIS

Definition at line 10498 of file efm32g890f128.h.

#define _DMA_CHPRIS_MASK   0x000000FFUL

Mask for DMA_CHPRIS

Definition at line 10461 of file efm32g890f128.h.

#define _DMA_CHPRIS_RESETVALUE   0x00000000UL

Default value for DMA_CHPRIS

Definition at line 10460 of file efm32g890f128.h.

#define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKC

Definition at line 10245 of file efm32g890f128.h.

#define _DMA_CHREQMASKC_CH0REQMASKC_MASK   0x1UL

Bit mask for DMA_CH0REQMASKC

Definition at line 10244 of file efm32g890f128.h.

#define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT   0

Shift value for DMA_CH0REQMASKC

Definition at line 10243 of file efm32g890f128.h.

#define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKC

Definition at line 10250 of file efm32g890f128.h.

#define _DMA_CHREQMASKC_CH1REQMASKC_MASK   0x2UL

Bit mask for DMA_CH1REQMASKC

Definition at line 10249 of file efm32g890f128.h.

#define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT   1

Shift value for DMA_CH1REQMASKC

Definition at line 10248 of file efm32g890f128.h.

#define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKC

Definition at line 10255 of file efm32g890f128.h.

#define _DMA_CHREQMASKC_CH2REQMASKC_MASK   0x4UL

Bit mask for DMA_CH2REQMASKC

Definition at line 10254 of file efm32g890f128.h.

#define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT   2

Shift value for DMA_CH2REQMASKC

Definition at line 10253 of file efm32g890f128.h.

#define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKC

Definition at line 10260 of file efm32g890f128.h.

#define _DMA_CHREQMASKC_CH3REQMASKC_MASK   0x8UL

Bit mask for DMA_CH3REQMASKC

Definition at line 10259 of file efm32g890f128.h.

#define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT   3

Shift value for DMA_CH3REQMASKC

Definition at line 10258 of file efm32g890f128.h.

#define _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKC

Definition at line 10265 of file efm32g890f128.h.

#define _DMA_CHREQMASKC_CH4REQMASKC_MASK   0x10UL

Bit mask for DMA_CH4REQMASKC

Definition at line 10264 of file efm32g890f128.h.

#define _DMA_CHREQMASKC_CH4REQMASKC_SHIFT   4

Shift value for DMA_CH4REQMASKC

Definition at line 10263 of file efm32g890f128.h.

#define _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKC

Definition at line 10270 of file efm32g890f128.h.

#define _DMA_CHREQMASKC_CH5REQMASKC_MASK   0x20UL

Bit mask for DMA_CH5REQMASKC

Definition at line 10269 of file efm32g890f128.h.

#define _DMA_CHREQMASKC_CH5REQMASKC_SHIFT   5

Shift value for DMA_CH5REQMASKC

Definition at line 10268 of file efm32g890f128.h.

#define _DMA_CHREQMASKC_CH6REQMASKC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKC

Definition at line 10275 of file efm32g890f128.h.

#define _DMA_CHREQMASKC_CH6REQMASKC_MASK   0x40UL

Bit mask for DMA_CH6REQMASKC

Definition at line 10274 of file efm32g890f128.h.

#define _DMA_CHREQMASKC_CH6REQMASKC_SHIFT   6

Shift value for DMA_CH6REQMASKC

Definition at line 10273 of file efm32g890f128.h.

#define _DMA_CHREQMASKC_CH7REQMASKC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKC

Definition at line 10280 of file efm32g890f128.h.

#define _DMA_CHREQMASKC_CH7REQMASKC_MASK   0x80UL

Bit mask for DMA_CH7REQMASKC

Definition at line 10279 of file efm32g890f128.h.

#define _DMA_CHREQMASKC_CH7REQMASKC_SHIFT   7

Shift value for DMA_CH7REQMASKC

Definition at line 10278 of file efm32g890f128.h.

#define _DMA_CHREQMASKC_MASK   0x000000FFUL

Mask for DMA_CHREQMASKC

Definition at line 10241 of file efm32g890f128.h.

#define _DMA_CHREQMASKC_RESETVALUE   0x00000000UL

Default value for DMA_CHREQMASKC

Definition at line 10240 of file efm32g890f128.h.

#define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKS

Definition at line 10201 of file efm32g890f128.h.

#define _DMA_CHREQMASKS_CH0REQMASKS_MASK   0x1UL

Bit mask for DMA_CH0REQMASKS

Definition at line 10200 of file efm32g890f128.h.

#define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT   0

Shift value for DMA_CH0REQMASKS

Definition at line 10199 of file efm32g890f128.h.

#define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKS

Definition at line 10206 of file efm32g890f128.h.

#define _DMA_CHREQMASKS_CH1REQMASKS_MASK   0x2UL

Bit mask for DMA_CH1REQMASKS

Definition at line 10205 of file efm32g890f128.h.

#define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT   1

Shift value for DMA_CH1REQMASKS

Definition at line 10204 of file efm32g890f128.h.

#define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKS

Definition at line 10211 of file efm32g890f128.h.

#define _DMA_CHREQMASKS_CH2REQMASKS_MASK   0x4UL

Bit mask for DMA_CH2REQMASKS

Definition at line 10210 of file efm32g890f128.h.

#define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT   2

Shift value for DMA_CH2REQMASKS

Definition at line 10209 of file efm32g890f128.h.

#define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKS

Definition at line 10216 of file efm32g890f128.h.

#define _DMA_CHREQMASKS_CH3REQMASKS_MASK   0x8UL

Bit mask for DMA_CH3REQMASKS

Definition at line 10215 of file efm32g890f128.h.

#define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT   3

Shift value for DMA_CH3REQMASKS

Definition at line 10214 of file efm32g890f128.h.

#define _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKS

Definition at line 10221 of file efm32g890f128.h.

#define _DMA_CHREQMASKS_CH4REQMASKS_MASK   0x10UL

Bit mask for DMA_CH4REQMASKS

Definition at line 10220 of file efm32g890f128.h.

#define _DMA_CHREQMASKS_CH4REQMASKS_SHIFT   4

Shift value for DMA_CH4REQMASKS

Definition at line 10219 of file efm32g890f128.h.

#define _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKS

Definition at line 10226 of file efm32g890f128.h.

#define _DMA_CHREQMASKS_CH5REQMASKS_MASK   0x20UL

Bit mask for DMA_CH5REQMASKS

Definition at line 10225 of file efm32g890f128.h.

#define _DMA_CHREQMASKS_CH5REQMASKS_SHIFT   5

Shift value for DMA_CH5REQMASKS

Definition at line 10224 of file efm32g890f128.h.

#define _DMA_CHREQMASKS_CH6REQMASKS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKS

Definition at line 10231 of file efm32g890f128.h.

#define _DMA_CHREQMASKS_CH6REQMASKS_MASK   0x40UL

Bit mask for DMA_CH6REQMASKS

Definition at line 10230 of file efm32g890f128.h.

#define _DMA_CHREQMASKS_CH6REQMASKS_SHIFT   6

Shift value for DMA_CH6REQMASKS

Definition at line 10229 of file efm32g890f128.h.

#define _DMA_CHREQMASKS_CH7REQMASKS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKS

Definition at line 10236 of file efm32g890f128.h.

#define _DMA_CHREQMASKS_CH7REQMASKS_MASK   0x80UL

Bit mask for DMA_CH7REQMASKS

Definition at line 10235 of file efm32g890f128.h.

#define _DMA_CHREQMASKS_CH7REQMASKS_SHIFT   7

Shift value for DMA_CH7REQMASKS

Definition at line 10234 of file efm32g890f128.h.

#define _DMA_CHREQMASKS_MASK   0x000000FFUL

Mask for DMA_CHREQMASKS

Definition at line 10197 of file efm32g890f128.h.

#define _DMA_CHREQMASKS_RESETVALUE   0x00000000UL

Default value for DMA_CHREQMASKS

Definition at line 10196 of file efm32g890f128.h.

#define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQSTATUS

Definition at line 10562 of file efm32g890f128.h.

#define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK   0x1UL

Bit mask for DMA_CH0REQSTATUS

Definition at line 10561 of file efm32g890f128.h.

#define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT   0

Shift value for DMA_CH0REQSTATUS

Definition at line 10560 of file efm32g890f128.h.

#define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQSTATUS

Definition at line 10567 of file efm32g890f128.h.

#define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK   0x2UL

Bit mask for DMA_CH1REQSTATUS

Definition at line 10566 of file efm32g890f128.h.

#define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT   1

Shift value for DMA_CH1REQSTATUS

Definition at line 10565 of file efm32g890f128.h.

#define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQSTATUS

Definition at line 10572 of file efm32g890f128.h.

#define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK   0x4UL

Bit mask for DMA_CH2REQSTATUS

Definition at line 10571 of file efm32g890f128.h.

#define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT   2

Shift value for DMA_CH2REQSTATUS

Definition at line 10570 of file efm32g890f128.h.

#define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQSTATUS

Definition at line 10577 of file efm32g890f128.h.

#define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK   0x8UL

Bit mask for DMA_CH3REQSTATUS

Definition at line 10576 of file efm32g890f128.h.

#define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT   3

Shift value for DMA_CH3REQSTATUS

Definition at line 10575 of file efm32g890f128.h.

#define _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQSTATUS

Definition at line 10582 of file efm32g890f128.h.

#define _DMA_CHREQSTATUS_CH4REQSTATUS_MASK   0x10UL

Bit mask for DMA_CH4REQSTATUS

Definition at line 10581 of file efm32g890f128.h.

#define _DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT   4

Shift value for DMA_CH4REQSTATUS

Definition at line 10580 of file efm32g890f128.h.

#define _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQSTATUS

Definition at line 10587 of file efm32g890f128.h.

#define _DMA_CHREQSTATUS_CH5REQSTATUS_MASK   0x20UL

Bit mask for DMA_CH5REQSTATUS

Definition at line 10586 of file efm32g890f128.h.

#define _DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT   5

Shift value for DMA_CH5REQSTATUS

Definition at line 10585 of file efm32g890f128.h.

#define _DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQSTATUS

Definition at line 10592 of file efm32g890f128.h.

#define _DMA_CHREQSTATUS_CH6REQSTATUS_MASK   0x40UL

Bit mask for DMA_CH6REQSTATUS

Definition at line 10591 of file efm32g890f128.h.

#define _DMA_CHREQSTATUS_CH6REQSTATUS_SHIFT   6

Shift value for DMA_CH6REQSTATUS

Definition at line 10590 of file efm32g890f128.h.

#define _DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQSTATUS

Definition at line 10597 of file efm32g890f128.h.

#define _DMA_CHREQSTATUS_CH7REQSTATUS_MASK   0x80UL

Bit mask for DMA_CH7REQSTATUS

Definition at line 10596 of file efm32g890f128.h.

#define _DMA_CHREQSTATUS_CH7REQSTATUS_SHIFT   7

Shift value for DMA_CH7REQSTATUS

Definition at line 10595 of file efm32g890f128.h.

#define _DMA_CHREQSTATUS_MASK   0x000000FFUL

Mask for DMA_CHREQSTATUS

Definition at line 10558 of file efm32g890f128.h.

#define _DMA_CHREQSTATUS_RESETVALUE   0x00000000UL

Default value for DMA_CHREQSTATUS

Definition at line 10557 of file efm32g890f128.h.

#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 10606 of file efm32g890f128.h.

#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK   0x1UL

Bit mask for DMA_CH0SREQSTATUS

Definition at line 10605 of file efm32g890f128.h.

#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT   0

Shift value for DMA_CH0SREQSTATUS

Definition at line 10604 of file efm32g890f128.h.

#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 10611 of file efm32g890f128.h.

#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK   0x2UL

Bit mask for DMA_CH1SREQSTATUS

Definition at line 10610 of file efm32g890f128.h.

#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT   1

Shift value for DMA_CH1SREQSTATUS

Definition at line 10609 of file efm32g890f128.h.

#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 10616 of file efm32g890f128.h.

#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK   0x4UL

Bit mask for DMA_CH2SREQSTATUS

Definition at line 10615 of file efm32g890f128.h.

#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT   2

Shift value for DMA_CH2SREQSTATUS

Definition at line 10614 of file efm32g890f128.h.

#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 10621 of file efm32g890f128.h.

#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK   0x8UL

Bit mask for DMA_CH3SREQSTATUS

Definition at line 10620 of file efm32g890f128.h.

#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT   3

Shift value for DMA_CH3SREQSTATUS

Definition at line 10619 of file efm32g890f128.h.

#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 10626 of file efm32g890f128.h.

#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK   0x10UL

Bit mask for DMA_CH4SREQSTATUS

Definition at line 10625 of file efm32g890f128.h.

#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT   4

Shift value for DMA_CH4SREQSTATUS

Definition at line 10624 of file efm32g890f128.h.

#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 10631 of file efm32g890f128.h.

#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK   0x20UL

Bit mask for DMA_CH5SREQSTATUS

Definition at line 10630 of file efm32g890f128.h.

#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT   5

Shift value for DMA_CH5SREQSTATUS

Definition at line 10629 of file efm32g890f128.h.

#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 10636 of file efm32g890f128.h.

#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_MASK   0x40UL

Bit mask for DMA_CH6SREQSTATUS

Definition at line 10635 of file efm32g890f128.h.

#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_SHIFT   6

Shift value for DMA_CH6SREQSTATUS

Definition at line 10634 of file efm32g890f128.h.

#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 10641 of file efm32g890f128.h.

#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_MASK   0x80UL

Bit mask for DMA_CH7SREQSTATUS

Definition at line 10640 of file efm32g890f128.h.

#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_SHIFT   7

Shift value for DMA_CH7SREQSTATUS

Definition at line 10639 of file efm32g890f128.h.

#define _DMA_CHSREQSTATUS_MASK   0x000000FFUL

Mask for DMA_CHSREQSTATUS

Definition at line 10602 of file efm32g890f128.h.

#define _DMA_CHSREQSTATUS_RESETVALUE   0x00000000UL

Default value for DMA_CHSREQSTATUS

Definition at line 10601 of file efm32g890f128.h.

#define _DMA_CHSWREQ_CH0SWREQ_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSWREQ

Definition at line 10065 of file efm32g890f128.h.

#define _DMA_CHSWREQ_CH0SWREQ_MASK   0x1UL

Bit mask for DMA_CH0SWREQ

Definition at line 10064 of file efm32g890f128.h.

#define _DMA_CHSWREQ_CH0SWREQ_SHIFT   0

Shift value for DMA_CH0SWREQ

Definition at line 10063 of file efm32g890f128.h.

#define _DMA_CHSWREQ_CH1SWREQ_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSWREQ

Definition at line 10070 of file efm32g890f128.h.

#define _DMA_CHSWREQ_CH1SWREQ_MASK   0x2UL

Bit mask for DMA_CH1SWREQ

Definition at line 10069 of file efm32g890f128.h.

#define _DMA_CHSWREQ_CH1SWREQ_SHIFT   1

Shift value for DMA_CH1SWREQ

Definition at line 10068 of file efm32g890f128.h.

#define _DMA_CHSWREQ_CH2SWREQ_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSWREQ

Definition at line 10075 of file efm32g890f128.h.

#define _DMA_CHSWREQ_CH2SWREQ_MASK   0x4UL

Bit mask for DMA_CH2SWREQ

Definition at line 10074 of file efm32g890f128.h.

#define _DMA_CHSWREQ_CH2SWREQ_SHIFT   2

Shift value for DMA_CH2SWREQ

Definition at line 10073 of file efm32g890f128.h.

#define _DMA_CHSWREQ_CH3SWREQ_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSWREQ

Definition at line 10080 of file efm32g890f128.h.

#define _DMA_CHSWREQ_CH3SWREQ_MASK   0x8UL

Bit mask for DMA_CH3SWREQ

Definition at line 10079 of file efm32g890f128.h.

#define _DMA_CHSWREQ_CH3SWREQ_SHIFT   3

Shift value for DMA_CH3SWREQ

Definition at line 10078 of file efm32g890f128.h.

#define _DMA_CHSWREQ_CH4SWREQ_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSWREQ

Definition at line 10085 of file efm32g890f128.h.

#define _DMA_CHSWREQ_CH4SWREQ_MASK   0x10UL

Bit mask for DMA_CH4SWREQ

Definition at line 10084 of file efm32g890f128.h.

#define _DMA_CHSWREQ_CH4SWREQ_SHIFT   4

Shift value for DMA_CH4SWREQ

Definition at line 10083 of file efm32g890f128.h.

#define _DMA_CHSWREQ_CH5SWREQ_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSWREQ

Definition at line 10090 of file efm32g890f128.h.

#define _DMA_CHSWREQ_CH5SWREQ_MASK   0x20UL

Bit mask for DMA_CH5SWREQ

Definition at line 10089 of file efm32g890f128.h.

#define _DMA_CHSWREQ_CH5SWREQ_SHIFT   5

Shift value for DMA_CH5SWREQ

Definition at line 10088 of file efm32g890f128.h.

#define _DMA_CHSWREQ_CH6SWREQ_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSWREQ

Definition at line 10095 of file efm32g890f128.h.

#define _DMA_CHSWREQ_CH6SWREQ_MASK   0x40UL

Bit mask for DMA_CH6SWREQ

Definition at line 10094 of file efm32g890f128.h.

#define _DMA_CHSWREQ_CH6SWREQ_SHIFT   6

Shift value for DMA_CH6SWREQ

Definition at line 10093 of file efm32g890f128.h.

#define _DMA_CHSWREQ_CH7SWREQ_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSWREQ

Definition at line 10100 of file efm32g890f128.h.

#define _DMA_CHSWREQ_CH7SWREQ_MASK   0x80UL

Bit mask for DMA_CH7SWREQ

Definition at line 10099 of file efm32g890f128.h.

#define _DMA_CHSWREQ_CH7SWREQ_SHIFT   7

Shift value for DMA_CH7SWREQ

Definition at line 10098 of file efm32g890f128.h.

#define _DMA_CHSWREQ_MASK   0x000000FFUL

Mask for DMA_CHSWREQ

Definition at line 10061 of file efm32g890f128.h.

#define _DMA_CHSWREQ_RESETVALUE   0x00000000UL

Default value for DMA_CHSWREQ

Definition at line 10060 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 10157 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK   0x1UL

Bit mask for DMA_CH0USEBURSTC

Definition at line 10156 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT   0

Shift value for DMA_CH0USEBURSTC

Definition at line 10155 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 10162 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK   0x2UL

Bit mask for DMA_CH1USEBURSTC

Definition at line 10161 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT   1

Shift value for DMA_CH1USEBURSTC

Definition at line 10160 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 10167 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK   0x4UL

Bit mask for DMA_CH2USEBURSTC

Definition at line 10166 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT   2

Shift value for DMA_CH2USEBURSTC

Definition at line 10165 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 10172 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK   0x8UL

Bit mask for DMA_CH3USEBURSTC

Definition at line 10171 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT   3

Shift value for DMA_CH3USEBURSTC

Definition at line 10170 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 10177 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTC_CH4USEBURSTC_MASK   0x10UL

Bit mask for DMA_CH4USEBURSTC

Definition at line 10176 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT   4

Shift value for DMA_CH4USEBURSTC

Definition at line 10175 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 10182 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTC_CH5USEBURSTC_MASK   0x20UL

Bit mask for DMA_CH5USEBURSTC

Definition at line 10181 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT   5

Shift value for DMA_CH5USEBURSTC

Definition at line 10180 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 10187 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTC_CH6USEBURSTC_MASK   0x40UL

Bit mask for DMA_CH6USEBURSTC

Definition at line 10186 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTC_CH6USEBURSTC_SHIFT   6

Shift value for DMA_CH6USEBURSTC

Definition at line 10185 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 10192 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTC_CH7USEBURSTC_MASK   0x80UL

Bit mask for DMA_CH7USEBURSTC

Definition at line 10191 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTC_CH7USEBURSTC_SHIFT   7

Shift value for DMA_CH7USEBURSTC

Definition at line 10190 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTC_MASK   0x000000FFUL

Mask for DMA_CHUSEBURSTC

Definition at line 10153 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTC_RESETVALUE   0x00000000UL

Default value for DMA_CHUSEBURSTC

Definition at line 10152 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY   0x00000001UL

Mode BURSTONLY for DMA_CHUSEBURSTS

Definition at line 10111 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 10109 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK   0x1UL

Bit mask for DMA_CH0USEBURSTS

Definition at line 10108 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT   0

Shift value for DMA_CH0USEBURSTS

Definition at line 10107 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST   0x00000000UL

Mode SINGLEANDBURST for DMA_CHUSEBURSTS

Definition at line 10110 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 10118 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK   0x2UL

Bit mask for DMA_CH1USEBURSTS

Definition at line 10117 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT   1

Shift value for DMA_CH1USEBURSTS

Definition at line 10116 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 10123 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK   0x4UL

Bit mask for DMA_CH2USEBURSTS

Definition at line 10122 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT   2

Shift value for DMA_CH2USEBURSTS

Definition at line 10121 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 10128 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK   0x8UL

Bit mask for DMA_CH3USEBURSTS

Definition at line 10127 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT   3

Shift value for DMA_CH3USEBURSTS

Definition at line 10126 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 10133 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTS_CH4USEBURSTS_MASK   0x10UL

Bit mask for DMA_CH4USEBURSTS

Definition at line 10132 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT   4

Shift value for DMA_CH4USEBURSTS

Definition at line 10131 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 10138 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTS_CH5USEBURSTS_MASK   0x20UL

Bit mask for DMA_CH5USEBURSTS

Definition at line 10137 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT   5

Shift value for DMA_CH5USEBURSTS

Definition at line 10136 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 10143 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTS_CH6USEBURSTS_MASK   0x40UL

Bit mask for DMA_CH6USEBURSTS

Definition at line 10142 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTS_CH6USEBURSTS_SHIFT   6

Shift value for DMA_CH6USEBURSTS

Definition at line 10141 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 10148 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTS_CH7USEBURSTS_MASK   0x80UL

Bit mask for DMA_CH7USEBURSTS

Definition at line 10147 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTS_CH7USEBURSTS_SHIFT   7

Shift value for DMA_CH7USEBURSTS

Definition at line 10146 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTS_MASK   0x000000FFUL

Mask for DMA_CHUSEBURSTS

Definition at line 10105 of file efm32g890f128.h.

#define _DMA_CHUSEBURSTS_RESETVALUE   0x00000000UL

Default value for DMA_CHUSEBURSTS

Definition at line 10104 of file efm32g890f128.h.

#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT   0x00000001UL

Mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 10021 of file efm32g890f128.h.

#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK   0x1UL

Bit mask for DMA_CH0WAITSTATUS

Definition at line 10020 of file efm32g890f128.h.

#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT   0

Shift value for DMA_CH0WAITSTATUS

Definition at line 10019 of file efm32g890f128.h.

#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT   0x00000001UL

Mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 10026 of file efm32g890f128.h.

#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK   0x2UL

Bit mask for DMA_CH1WAITSTATUS

Definition at line 10025 of file efm32g890f128.h.

#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT   1

Shift value for DMA_CH1WAITSTATUS

Definition at line 10024 of file efm32g890f128.h.

#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT   0x00000001UL

Mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 10031 of file efm32g890f128.h.

#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK   0x4UL

Bit mask for DMA_CH2WAITSTATUS

Definition at line 10030 of file efm32g890f128.h.

#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT   2

Shift value for DMA_CH2WAITSTATUS

Definition at line 10029 of file efm32g890f128.h.

#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT   0x00000001UL

Mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 10036 of file efm32g890f128.h.

#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK   0x8UL

Bit mask for DMA_CH3WAITSTATUS

Definition at line 10035 of file efm32g890f128.h.

#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT   3

Shift value for DMA_CH3WAITSTATUS

Definition at line 10034 of file efm32g890f128.h.

#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT   0x00000001UL

Mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 10041 of file efm32g890f128.h.

#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK   0x10UL

Bit mask for DMA_CH4WAITSTATUS

Definition at line 10040 of file efm32g890f128.h.

#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT   4

Shift value for DMA_CH4WAITSTATUS

Definition at line 10039 of file efm32g890f128.h.

#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT   0x00000001UL

Mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 10046 of file efm32g890f128.h.

#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK   0x20UL

Bit mask for DMA_CH5WAITSTATUS

Definition at line 10045 of file efm32g890f128.h.

#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT   5

Shift value for DMA_CH5WAITSTATUS

Definition at line 10044 of file efm32g890f128.h.

#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT   0x00000001UL

Mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 10051 of file efm32g890f128.h.

#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_MASK   0x40UL

Bit mask for DMA_CH6WAITSTATUS

Definition at line 10050 of file efm32g890f128.h.

#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_SHIFT   6

Shift value for DMA_CH6WAITSTATUS

Definition at line 10049 of file efm32g890f128.h.

#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT   0x00000001UL

Mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 10056 of file efm32g890f128.h.

#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_MASK   0x80UL

Bit mask for DMA_CH7WAITSTATUS

Definition at line 10055 of file efm32g890f128.h.

#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_SHIFT   7

Shift value for DMA_CH7WAITSTATUS

Definition at line 10054 of file efm32g890f128.h.

#define _DMA_CHWAITSTATUS_MASK   0x000000FFUL

Mask for DMA_CHWAITSTATUS

Definition at line 10017 of file efm32g890f128.h.

#define _DMA_CHWAITSTATUS_RESETVALUE   0x000000FFUL

Default value for DMA_CHWAITSTATUS

Definition at line 10016 of file efm32g890f128.h.

#define _DMA_CONFIG_CHPROT_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CONFIG

Definition at line 9996 of file efm32g890f128.h.

#define _DMA_CONFIG_CHPROT_MASK   0x20UL

Bit mask for DMA_CHPROT

Definition at line 9995 of file efm32g890f128.h.

#define _DMA_CONFIG_CHPROT_SHIFT   5

Shift value for DMA_CHPROT

Definition at line 9994 of file efm32g890f128.h.

#define _DMA_CONFIG_EN_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CONFIG

Definition at line 9991 of file efm32g890f128.h.

#define _DMA_CONFIG_EN_MASK   0x1UL

Bit mask for DMA_EN

Definition at line 9990 of file efm32g890f128.h.

#define _DMA_CONFIG_EN_SHIFT   0

Shift value for DMA_EN

Definition at line 9989 of file efm32g890f128.h.

#define _DMA_CONFIG_MASK   0x00000021UL

Mask for DMA_CONFIG

Definition at line 9987 of file efm32g890f128.h.

#define _DMA_CONFIG_RESETVALUE   0x00000000UL

Default value for DMA_CONFIG

Definition at line 9986 of file efm32g890f128.h.

#define _DMA_CTRL_CYCLE_CTRL_AUTO   0x02

Auto cycle type

Definition at line 1156 of file efm32g890f128.h.

#define _DMA_CTRL_CYCLE_CTRL_BASIC   0x01

Basic cycle type

Definition at line 1155 of file efm32g890f128.h.

#define _DMA_CTRL_CYCLE_CTRL_INVALID   0x00

Invalid cycle type

Definition at line 1154 of file efm32g890f128.h.

#define _DMA_CTRL_CYCLE_CTRL_MASK   0x00000007UL

DMA Cycle control bit mask - basic/auto/ping-poing/scath-gath

Definition at line 1152 of file efm32g890f128.h.

#define _DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER   0x04

Memory scatter gather cycle type

Definition at line 1158 of file efm32g890f128.h.

#define _DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER_ALT   0x05

Memory scatter gather using alternate structure

Definition at line 1159 of file efm32g890f128.h.

#define _DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER   0x06

Peripheral scatter gather cycle type

Definition at line 1160 of file efm32g890f128.h.

#define _DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT   0x07

Peripheral scatter gather cycle type using alternate structure

Definition at line 1161 of file efm32g890f128.h.

#define _DMA_CTRL_CYCLE_CTRL_PINGPONG   0x03

PingPong cycle type

Definition at line 1157 of file efm32g890f128.h.

#define _DMA_CTRL_CYCLE_CTRL_SHIFT   0

DMA Cycle control bit shift

Definition at line 1153 of file efm32g890f128.h.

#define _DMA_CTRL_DST_INC_BYTE   0x00

Byte/8-bit increment

Definition at line 1076 of file efm32g890f128.h.

#define _DMA_CTRL_DST_INC_HALFWORD   0x01

Half word/16-bit increment

Definition at line 1077 of file efm32g890f128.h.

#define _DMA_CTRL_DST_INC_MASK   0xC0000000UL

DMA Control CTRL Register defines Data increment for destination, bit mask

Definition at line 1074 of file efm32g890f128.h.

#define _DMA_CTRL_DST_INC_NONE   0x03

No increment

Definition at line 1079 of file efm32g890f128.h.

#define _DMA_CTRL_DST_INC_SHIFT   30

Data increment for destination, shift value

Definition at line 1075 of file efm32g890f128.h.

#define _DMA_CTRL_DST_INC_WORD   0x02

Word/32-bit increment

Definition at line 1078 of file efm32g890f128.h.

#define _DMA_CTRL_DST_PROT_CTRL_MASK   0x00E00000UL

Protection flag for destination, bit mask

Definition at line 1114 of file efm32g890f128.h.

#define _DMA_CTRL_DST_PROT_CTRL_SHIFT   21

Protection flag for destination, shift value

Definition at line 1115 of file efm32g890f128.h.

#define _DMA_CTRL_DST_SIZE_BYTE   0x00

Byte/8-bit data size

Definition at line 1086 of file efm32g890f128.h.

#define _DMA_CTRL_DST_SIZE_HALFWORD   0x01

Half word/16-bit data size

Definition at line 1087 of file efm32g890f128.h.

#define _DMA_CTRL_DST_SIZE_MASK   0x30000000UL

Data size for destination - MUST be the same as source, bit mask

Definition at line 1084 of file efm32g890f128.h.

#define _DMA_CTRL_DST_SIZE_RSVD   0x03

Reserved

Definition at line 1089 of file efm32g890f128.h.

#define _DMA_CTRL_DST_SIZE_SHIFT   28

Data size for destination - MUST be the same as source, shift value

Definition at line 1085 of file efm32g890f128.h.

#define _DMA_CTRL_DST_SIZE_WORD   0x02

Word/32-bit data size

Definition at line 1088 of file efm32g890f128.h.

#define _DMA_CTRL_N_MINUS_1_MASK   0x00003FF0UL

Number of DMA transfers minus 1, bit mask. See PL230 documentation

Definition at line 1148 of file efm32g890f128.h.

#define _DMA_CTRL_N_MINUS_1_SHIFT   4

Number of DMA transfers minus 1, shift mask. See PL230 documentation

Definition at line 1149 of file efm32g890f128.h.

#define _DMA_CTRL_NEXT_USEBURST_MASK   0x00000008UL

DMA useburst_set[C] is 1 when using scatter-gather DMA and using alternate data

Definition at line 1150 of file efm32g890f128.h.

#define _DMA_CTRL_NEXT_USEBURST_SHIFT   3

DMA useburst shift

Definition at line 1151 of file efm32g890f128.h.

#define _DMA_CTRL_PROT_NON_PRIVILEGED   0x00

Protection bits to indicate non-privileged access

Definition at line 1122 of file efm32g890f128.h.

#define _DMA_CTRL_PROT_PRIVILEGED   0x01

Protection bits to indicate privileged access

Definition at line 1123 of file efm32g890f128.h.

#define _DMA_CTRL_R_POWER_1   0x00

Arbitrate after each transfer

Definition at line 1126 of file efm32g890f128.h.

#define _DMA_CTRL_R_POWER_1024   0x0a

Arbitrate after every 1024 transfers

Definition at line 1136 of file efm32g890f128.h.

#define _DMA_CTRL_R_POWER_128   0x07

Arbitrate after every 128 transfers

Definition at line 1133 of file efm32g890f128.h.

#define _DMA_CTRL_R_POWER_16   0x04

Arbitrate after every 16 transfers

Definition at line 1130 of file efm32g890f128.h.

#define _DMA_CTRL_R_POWER_2   0x01

Arbitrate after every 2 transfers

Definition at line 1127 of file efm32g890f128.h.

#define _DMA_CTRL_R_POWER_256   0x08

Arbitrate after every 256 transfers

Definition at line 1134 of file efm32g890f128.h.

#define _DMA_CTRL_R_POWER_32   0x05

Arbitrate after every 32 transfers

Definition at line 1131 of file efm32g890f128.h.

#define _DMA_CTRL_R_POWER_4   0x02

Arbitrate after every 4 transfers

Definition at line 1128 of file efm32g890f128.h.

#define _DMA_CTRL_R_POWER_512   0x09

Arbitrate after every 512 transfers

Definition at line 1135 of file efm32g890f128.h.

#define _DMA_CTRL_R_POWER_64   0x06

Arbitrate after every 64 transfers

Definition at line 1132 of file efm32g890f128.h.

#define _DMA_CTRL_R_POWER_8   0x03

Arbitrate after every 8 transfers

Definition at line 1129 of file efm32g890f128.h.

#define _DMA_CTRL_R_POWER_MASK   0x0003C000UL

DMA arbitration mask

Definition at line 1124 of file efm32g890f128.h.

#define _DMA_CTRL_R_POWER_SHIFT   14

Number of DMA cycles before controller does new arbitration in 2^R

Definition at line 1125 of file efm32g890f128.h.

#define _DMA_CTRL_SRC_INC_BYTE   0x00

Byte/8-bit increment

Definition at line 1096 of file efm32g890f128.h.

#define _DMA_CTRL_SRC_INC_HALFWORD   0x01

Half word/16-bit increment

Definition at line 1097 of file efm32g890f128.h.

#define _DMA_CTRL_SRC_INC_MASK   0x0C000000UL

Data increment for source, bit mask

Definition at line 1094 of file efm32g890f128.h.

#define _DMA_CTRL_SRC_INC_NONE   0x03

No increment

Definition at line 1099 of file efm32g890f128.h.

#define _DMA_CTRL_SRC_INC_SHIFT   26

Data increment for source, shift value

Definition at line 1095 of file efm32g890f128.h.

#define _DMA_CTRL_SRC_INC_WORD   0x02

Word/32-bit increment

Definition at line 1098 of file efm32g890f128.h.

#define _DMA_CTRL_SRC_PROT_CTRL_MASK   0x001C0000UL

Protection flag for source, bit mask

Definition at line 1118 of file efm32g890f128.h.

#define _DMA_CTRL_SRC_PROT_CTRL_SHIFT   18

Protection flag for source, shift value

Definition at line 1119 of file efm32g890f128.h.

#define _DMA_CTRL_SRC_SIZE_BYTE   0x00

Byte/8-bit data size

Definition at line 1106 of file efm32g890f128.h.

#define _DMA_CTRL_SRC_SIZE_HALFWORD   0x01

Half word/16-bit data size

Definition at line 1107 of file efm32g890f128.h.

#define _DMA_CTRL_SRC_SIZE_MASK   0x03000000UL

Data size for source - MUST be the same as destination, bit mask

Definition at line 1104 of file efm32g890f128.h.

#define _DMA_CTRL_SRC_SIZE_RSVD   0x03

Reserved

Definition at line 1109 of file efm32g890f128.h.

#define _DMA_CTRL_SRC_SIZE_SHIFT   24

Data size for source - MUST be the same as destination, shift value

Definition at line 1105 of file efm32g890f128.h.

#define _DMA_CTRL_SRC_SIZE_WORD   0x02

Word/32-bit data size

Definition at line 1108 of file efm32g890f128.h.

#define _DMA_CTRLBASE_CTRLBASE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CTRLBASE

Definition at line 10004 of file efm32g890f128.h.

#define _DMA_CTRLBASE_CTRLBASE_MASK   0xFFFFFFFFUL

Bit mask for DMA_CTRLBASE

Definition at line 10003 of file efm32g890f128.h.

#define _DMA_CTRLBASE_CTRLBASE_SHIFT   0

Shift value for DMA_CTRLBASE

Definition at line 10002 of file efm32g890f128.h.

#define _DMA_CTRLBASE_MASK   0xFFFFFFFFUL

Mask for DMA_CTRLBASE

Definition at line 10001 of file efm32g890f128.h.

#define _DMA_CTRLBASE_RESETVALUE   0x00000000UL

Default value for DMA_CTRLBASE

Definition at line 10000 of file efm32g890f128.h.

#define _DMA_ERRORC_ERRORC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_ERRORC

Definition at line 10553 of file efm32g890f128.h.

#define _DMA_ERRORC_ERRORC_MASK   0x1UL

Bit mask for DMA_ERRORC

Definition at line 10552 of file efm32g890f128.h.

#define _DMA_ERRORC_ERRORC_SHIFT   0

Shift value for DMA_ERRORC

Definition at line 10551 of file efm32g890f128.h.

#define _DMA_ERRORC_MASK   0x00000001UL

Mask for DMA_ERRORC

Definition at line 10549 of file efm32g890f128.h.

#define _DMA_ERRORC_RESETVALUE   0x00000000UL

Default value for DMA_ERRORC

Definition at line 10548 of file efm32g890f128.h.

#define _DMA_IEN_CH0DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IEN

Definition at line 10797 of file efm32g890f128.h.

#define _DMA_IEN_CH0DONE_MASK   0x1UL

Bit mask for DMA_CH0DONE

Definition at line 10796 of file efm32g890f128.h.

#define _DMA_IEN_CH0DONE_SHIFT   0

Shift value for DMA_CH0DONE

Definition at line 10795 of file efm32g890f128.h.

#define _DMA_IEN_CH1DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IEN

Definition at line 10802 of file efm32g890f128.h.

#define _DMA_IEN_CH1DONE_MASK   0x2UL

Bit mask for DMA_CH1DONE

Definition at line 10801 of file efm32g890f128.h.

#define _DMA_IEN_CH1DONE_SHIFT   1

Shift value for DMA_CH1DONE

Definition at line 10800 of file efm32g890f128.h.

#define _DMA_IEN_CH2DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IEN

Definition at line 10807 of file efm32g890f128.h.

#define _DMA_IEN_CH2DONE_MASK   0x4UL

Bit mask for DMA_CH2DONE

Definition at line 10806 of file efm32g890f128.h.

#define _DMA_IEN_CH2DONE_SHIFT   2

Shift value for DMA_CH2DONE

Definition at line 10805 of file efm32g890f128.h.

#define _DMA_IEN_CH3DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IEN

Definition at line 10812 of file efm32g890f128.h.

#define _DMA_IEN_CH3DONE_MASK   0x8UL

Bit mask for DMA_CH3DONE

Definition at line 10811 of file efm32g890f128.h.

#define _DMA_IEN_CH3DONE_SHIFT   3

Shift value for DMA_CH3DONE

Definition at line 10810 of file efm32g890f128.h.

#define _DMA_IEN_CH4DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IEN

Definition at line 10817 of file efm32g890f128.h.

#define _DMA_IEN_CH4DONE_MASK   0x10UL

Bit mask for DMA_CH4DONE

Definition at line 10816 of file efm32g890f128.h.

#define _DMA_IEN_CH4DONE_SHIFT   4

Shift value for DMA_CH4DONE

Definition at line 10815 of file efm32g890f128.h.

#define _DMA_IEN_CH5DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IEN

Definition at line 10822 of file efm32g890f128.h.

#define _DMA_IEN_CH5DONE_MASK   0x20UL

Bit mask for DMA_CH5DONE

Definition at line 10821 of file efm32g890f128.h.

#define _DMA_IEN_CH5DONE_SHIFT   5

Shift value for DMA_CH5DONE

Definition at line 10820 of file efm32g890f128.h.

#define _DMA_IEN_CH6DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IEN

Definition at line 10827 of file efm32g890f128.h.

#define _DMA_IEN_CH6DONE_MASK   0x40UL

Bit mask for DMA_CH6DONE

Definition at line 10826 of file efm32g890f128.h.

#define _DMA_IEN_CH6DONE_SHIFT   6

Shift value for DMA_CH6DONE

Definition at line 10825 of file efm32g890f128.h.

#define _DMA_IEN_CH7DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IEN

Definition at line 10832 of file efm32g890f128.h.

#define _DMA_IEN_CH7DONE_MASK   0x80UL

Bit mask for DMA_CH7DONE

Definition at line 10831 of file efm32g890f128.h.

#define _DMA_IEN_CH7DONE_SHIFT   7

Shift value for DMA_CH7DONE

Definition at line 10830 of file efm32g890f128.h.

#define _DMA_IEN_ERR_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IEN

Definition at line 10837 of file efm32g890f128.h.

#define _DMA_IEN_ERR_MASK   0x80000000UL

Bit mask for DMA_ERR

Definition at line 10836 of file efm32g890f128.h.

#define _DMA_IEN_ERR_SHIFT   31

Shift value for DMA_ERR

Definition at line 10835 of file efm32g890f128.h.

#define _DMA_IEN_MASK   0x800000FFUL

Mask for DMA_IEN

Definition at line 10793 of file efm32g890f128.h.

#define _DMA_IEN_RESETVALUE   0x00000000UL

Default value for DMA_IEN

Definition at line 10792 of file efm32g890f128.h.

#define _DMA_IF_CH0DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IF

Definition at line 10650 of file efm32g890f128.h.

#define _DMA_IF_CH0DONE_MASK   0x1UL

Bit mask for DMA_CH0DONE

Definition at line 10649 of file efm32g890f128.h.

#define _DMA_IF_CH0DONE_SHIFT   0

Shift value for DMA_CH0DONE

Definition at line 10648 of file efm32g890f128.h.

#define _DMA_IF_CH1DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IF

Definition at line 10655 of file efm32g890f128.h.

#define _DMA_IF_CH1DONE_MASK   0x2UL

Bit mask for DMA_CH1DONE

Definition at line 10654 of file efm32g890f128.h.

#define _DMA_IF_CH1DONE_SHIFT   1

Shift value for DMA_CH1DONE

Definition at line 10653 of file efm32g890f128.h.

#define _DMA_IF_CH2DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IF

Definition at line 10660 of file efm32g890f128.h.

#define _DMA_IF_CH2DONE_MASK   0x4UL

Bit mask for DMA_CH2DONE

Definition at line 10659 of file efm32g890f128.h.

#define _DMA_IF_CH2DONE_SHIFT   2

Shift value for DMA_CH2DONE

Definition at line 10658 of file efm32g890f128.h.

#define _DMA_IF_CH3DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IF

Definition at line 10665 of file efm32g890f128.h.

#define _DMA_IF_CH3DONE_MASK   0x8UL

Bit mask for DMA_CH3DONE

Definition at line 10664 of file efm32g890f128.h.

#define _DMA_IF_CH3DONE_SHIFT   3

Shift value for DMA_CH3DONE

Definition at line 10663 of file efm32g890f128.h.

#define _DMA_IF_CH4DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IF

Definition at line 10670 of file efm32g890f128.h.

#define _DMA_IF_CH4DONE_MASK   0x10UL

Bit mask for DMA_CH4DONE

Definition at line 10669 of file efm32g890f128.h.

#define _DMA_IF_CH4DONE_SHIFT   4

Shift value for DMA_CH4DONE

Definition at line 10668 of file efm32g890f128.h.

#define _DMA_IF_CH5DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IF

Definition at line 10675 of file efm32g890f128.h.

#define _DMA_IF_CH5DONE_MASK   0x20UL

Bit mask for DMA_CH5DONE

Definition at line 10674 of file efm32g890f128.h.

#define _DMA_IF_CH5DONE_SHIFT   5

Shift value for DMA_CH5DONE

Definition at line 10673 of file efm32g890f128.h.

#define _DMA_IF_CH6DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IF

Definition at line 10680 of file efm32g890f128.h.

#define _DMA_IF_CH6DONE_MASK   0x40UL

Bit mask for DMA_CH6DONE

Definition at line 10679 of file efm32g890f128.h.

#define _DMA_IF_CH6DONE_SHIFT   6

Shift value for DMA_CH6DONE

Definition at line 10678 of file efm32g890f128.h.

#define _DMA_IF_CH7DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IF

Definition at line 10685 of file efm32g890f128.h.

#define _DMA_IF_CH7DONE_MASK   0x80UL

Bit mask for DMA_CH7DONE

Definition at line 10684 of file efm32g890f128.h.

#define _DMA_IF_CH7DONE_SHIFT   7

Shift value for DMA_CH7DONE

Definition at line 10683 of file efm32g890f128.h.

#define _DMA_IF_ERR_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IF

Definition at line 10690 of file efm32g890f128.h.

#define _DMA_IF_ERR_MASK   0x80000000UL

Bit mask for DMA_ERR

Definition at line 10689 of file efm32g890f128.h.

#define _DMA_IF_ERR_SHIFT   31

Shift value for DMA_ERR

Definition at line 10688 of file efm32g890f128.h.

#define _DMA_IF_MASK   0x800000FFUL

Mask for DMA_IF

Definition at line 10646 of file efm32g890f128.h.

#define _DMA_IF_RESETVALUE   0x00000000UL

Default value for DMA_IF

Definition at line 10645 of file efm32g890f128.h.

#define _DMA_IFC_CH0DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFC

Definition at line 10748 of file efm32g890f128.h.

#define _DMA_IFC_CH0DONE_MASK   0x1UL

Bit mask for DMA_CH0DONE

Definition at line 10747 of file efm32g890f128.h.

#define _DMA_IFC_CH0DONE_SHIFT   0

Shift value for DMA_CH0DONE

Definition at line 10746 of file efm32g890f128.h.

#define _DMA_IFC_CH1DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFC

Definition at line 10753 of file efm32g890f128.h.

#define _DMA_IFC_CH1DONE_MASK   0x2UL

Bit mask for DMA_CH1DONE

Definition at line 10752 of file efm32g890f128.h.

#define _DMA_IFC_CH1DONE_SHIFT   1

Shift value for DMA_CH1DONE

Definition at line 10751 of file efm32g890f128.h.

#define _DMA_IFC_CH2DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFC

Definition at line 10758 of file efm32g890f128.h.

#define _DMA_IFC_CH2DONE_MASK   0x4UL

Bit mask for DMA_CH2DONE

Definition at line 10757 of file efm32g890f128.h.

#define _DMA_IFC_CH2DONE_SHIFT   2

Shift value for DMA_CH2DONE

Definition at line 10756 of file efm32g890f128.h.

#define _DMA_IFC_CH3DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFC

Definition at line 10763 of file efm32g890f128.h.

#define _DMA_IFC_CH3DONE_MASK   0x8UL

Bit mask for DMA_CH3DONE

Definition at line 10762 of file efm32g890f128.h.

#define _DMA_IFC_CH3DONE_SHIFT   3

Shift value for DMA_CH3DONE

Definition at line 10761 of file efm32g890f128.h.

#define _DMA_IFC_CH4DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFC

Definition at line 10768 of file efm32g890f128.h.

#define _DMA_IFC_CH4DONE_MASK   0x10UL

Bit mask for DMA_CH4DONE

Definition at line 10767 of file efm32g890f128.h.

#define _DMA_IFC_CH4DONE_SHIFT   4

Shift value for DMA_CH4DONE

Definition at line 10766 of file efm32g890f128.h.

#define _DMA_IFC_CH5DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFC

Definition at line 10773 of file efm32g890f128.h.

#define _DMA_IFC_CH5DONE_MASK   0x20UL

Bit mask for DMA_CH5DONE

Definition at line 10772 of file efm32g890f128.h.

#define _DMA_IFC_CH5DONE_SHIFT   5

Shift value for DMA_CH5DONE

Definition at line 10771 of file efm32g890f128.h.

#define _DMA_IFC_CH6DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFC

Definition at line 10778 of file efm32g890f128.h.

#define _DMA_IFC_CH6DONE_MASK   0x40UL

Bit mask for DMA_CH6DONE

Definition at line 10777 of file efm32g890f128.h.

#define _DMA_IFC_CH6DONE_SHIFT   6

Shift value for DMA_CH6DONE

Definition at line 10776 of file efm32g890f128.h.

#define _DMA_IFC_CH7DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFC

Definition at line 10783 of file efm32g890f128.h.

#define _DMA_IFC_CH7DONE_MASK   0x80UL

Bit mask for DMA_CH7DONE

Definition at line 10782 of file efm32g890f128.h.

#define _DMA_IFC_CH7DONE_SHIFT   7

Shift value for DMA_CH7DONE

Definition at line 10781 of file efm32g890f128.h.

#define _DMA_IFC_ERR_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFC

Definition at line 10788 of file efm32g890f128.h.

#define _DMA_IFC_ERR_MASK   0x80000000UL

Bit mask for DMA_ERR

Definition at line 10787 of file efm32g890f128.h.

#define _DMA_IFC_ERR_SHIFT   31

Shift value for DMA_ERR

Definition at line 10786 of file efm32g890f128.h.

#define _DMA_IFC_MASK   0x800000FFUL

Mask for DMA_IFC

Definition at line 10744 of file efm32g890f128.h.

#define _DMA_IFC_RESETVALUE   0x00000000UL

Default value for DMA_IFC

Definition at line 10743 of file efm32g890f128.h.

#define _DMA_IFS_CH0DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFS

Definition at line 10699 of file efm32g890f128.h.

#define _DMA_IFS_CH0DONE_MASK   0x1UL

Bit mask for DMA_CH0DONE

Definition at line 10698 of file efm32g890f128.h.

#define _DMA_IFS_CH0DONE_SHIFT   0

Shift value for DMA_CH0DONE

Definition at line 10697 of file efm32g890f128.h.

#define _DMA_IFS_CH1DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFS

Definition at line 10704 of file efm32g890f128.h.

#define _DMA_IFS_CH1DONE_MASK   0x2UL

Bit mask for DMA_CH1DONE

Definition at line 10703 of file efm32g890f128.h.

#define _DMA_IFS_CH1DONE_SHIFT   1

Shift value for DMA_CH1DONE

Definition at line 10702 of file efm32g890f128.h.

#define _DMA_IFS_CH2DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFS

Definition at line 10709 of file efm32g890f128.h.

#define _DMA_IFS_CH2DONE_MASK   0x4UL

Bit mask for DMA_CH2DONE

Definition at line 10708 of file efm32g890f128.h.

#define _DMA_IFS_CH2DONE_SHIFT   2

Shift value for DMA_CH2DONE

Definition at line 10707 of file efm32g890f128.h.

#define _DMA_IFS_CH3DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFS

Definition at line 10714 of file efm32g890f128.h.

#define _DMA_IFS_CH3DONE_MASK   0x8UL

Bit mask for DMA_CH3DONE

Definition at line 10713 of file efm32g890f128.h.

#define _DMA_IFS_CH3DONE_SHIFT   3

Shift value for DMA_CH3DONE

Definition at line 10712 of file efm32g890f128.h.

#define _DMA_IFS_CH4DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFS

Definition at line 10719 of file efm32g890f128.h.

#define _DMA_IFS_CH4DONE_MASK   0x10UL

Bit mask for DMA_CH4DONE

Definition at line 10718 of file efm32g890f128.h.

#define _DMA_IFS_CH4DONE_SHIFT   4

Shift value for DMA_CH4DONE

Definition at line 10717 of file efm32g890f128.h.

#define _DMA_IFS_CH5DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFS

Definition at line 10724 of file efm32g890f128.h.

#define _DMA_IFS_CH5DONE_MASK   0x20UL

Bit mask for DMA_CH5DONE

Definition at line 10723 of file efm32g890f128.h.

#define _DMA_IFS_CH5DONE_SHIFT   5

Shift value for DMA_CH5DONE

Definition at line 10722 of file efm32g890f128.h.

#define _DMA_IFS_CH6DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFS

Definition at line 10729 of file efm32g890f128.h.

#define _DMA_IFS_CH6DONE_MASK   0x40UL

Bit mask for DMA_CH6DONE

Definition at line 10728 of file efm32g890f128.h.

#define _DMA_IFS_CH6DONE_SHIFT   6

Shift value for DMA_CH6DONE

Definition at line 10727 of file efm32g890f128.h.

#define _DMA_IFS_CH7DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFS

Definition at line 10734 of file efm32g890f128.h.

#define _DMA_IFS_CH7DONE_MASK   0x80UL

Bit mask for DMA_CH7DONE

Definition at line 10733 of file efm32g890f128.h.

#define _DMA_IFS_CH7DONE_SHIFT   7

Shift value for DMA_CH7DONE

Definition at line 10732 of file efm32g890f128.h.

#define _DMA_IFS_ERR_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFS

Definition at line 10739 of file efm32g890f128.h.

#define _DMA_IFS_ERR_MASK   0x80000000UL

Bit mask for DMA_ERR

Definition at line 10738 of file efm32g890f128.h.

#define _DMA_IFS_ERR_SHIFT   31

Shift value for DMA_ERR

Definition at line 10737 of file efm32g890f128.h.

#define _DMA_IFS_MASK   0x800000FFUL

Mask for DMA_IFS

Definition at line 10695 of file efm32g890f128.h.

#define _DMA_IFS_RESETVALUE   0x00000000UL

Default value for DMA_IFS

Definition at line 10694 of file efm32g890f128.h.

#define _DMA_STATUS_CHNUM_DEFAULT   0x00000007UL

Mode DEFAULT for DMA_STATUS

Definition at line 9982 of file efm32g890f128.h.

#define _DMA_STATUS_CHNUM_MASK   0x1F0000UL

Bit mask for DMA_CHNUM

Definition at line 9981 of file efm32g890f128.h.

#define _DMA_STATUS_CHNUM_SHIFT   16

Shift value for DMA_CHNUM

Definition at line 9980 of file efm32g890f128.h.

#define _DMA_STATUS_EN_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_STATUS

Definition at line 9952 of file efm32g890f128.h.

#define _DMA_STATUS_EN_MASK   0x1UL

Bit mask for DMA_EN

Definition at line 9951 of file efm32g890f128.h.

#define _DMA_STATUS_EN_SHIFT   0

Shift value for DMA_EN

Definition at line 9950 of file efm32g890f128.h.

#define _DMA_STATUS_MASK   0xF01F00F1UL

Mask for DMA_STATUS

Definition at line 9948 of file efm32g890f128.h.

#define _DMA_STATUS_RESETVALUE   0x10070000UL

Default value for DMA_STATUS

Definition at line 9947 of file efm32g890f128.h.

#define _DMA_STATUS_STATE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_STATUS

Definition at line 9956 of file efm32g890f128.h.

#define _DMA_STATUS_STATE_DONE   0x00000009UL

Mode DONE for DMA_STATUS

Definition at line 9966 of file efm32g890f128.h.

#define _DMA_STATUS_STATE_IDLE   0x00000000UL

Mode IDLE for DMA_STATUS

Definition at line 9957 of file efm32g890f128.h.

#define _DMA_STATUS_STATE_MASK   0xF0UL

Bit mask for DMA_STATE

Definition at line 9955 of file efm32g890f128.h.

#define _DMA_STATUS_STATE_PERSCATTRANS   0x0000000AUL

Mode PERSCATTRANS for DMA_STATUS

Definition at line 9967 of file efm32g890f128.h.

#define _DMA_STATUS_STATE_RDCHCTRLDATA   0x00000001UL

Mode RDCHCTRLDATA for DMA_STATUS

Definition at line 9958 of file efm32g890f128.h.

#define _DMA_STATUS_STATE_RDDSTENDPTR   0x00000003UL

Mode RDDSTENDPTR for DMA_STATUS

Definition at line 9960 of file efm32g890f128.h.

#define _DMA_STATUS_STATE_RDSRCDATA   0x00000004UL

Mode RDSRCDATA for DMA_STATUS

Definition at line 9961 of file efm32g890f128.h.

#define _DMA_STATUS_STATE_RDSRCENDPTR   0x00000002UL

Mode RDSRCENDPTR for DMA_STATUS

Definition at line 9959 of file efm32g890f128.h.

#define _DMA_STATUS_STATE_SHIFT   4

Shift value for DMA_STATE

Definition at line 9954 of file efm32g890f128.h.

#define _DMA_STATUS_STATE_STALLED   0x00000008UL

Mode STALLED for DMA_STATUS

Definition at line 9965 of file efm32g890f128.h.

#define _DMA_STATUS_STATE_WAITREQCLR   0x00000006UL

Mode WAITREQCLR for DMA_STATUS

Definition at line 9963 of file efm32g890f128.h.

#define _DMA_STATUS_STATE_WRCHCTRLDATA   0x00000007UL

Mode WRCHCTRLDATA for DMA_STATUS

Definition at line 9964 of file efm32g890f128.h.

#define _DMA_STATUS_STATE_WRDSTDATA   0x00000005UL

Mode WRDSTDATA for DMA_STATUS

Definition at line 9962 of file efm32g890f128.h.

#define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT   (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0)

Shifted mode DEFAULT for DMA_ALTCTRLBASE

Definition at line 10013 of file efm32g890f128.h.

#define DMA_CH_CTRL_SIGSEL_ADC0SCAN   (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0)

Shifted mode ADC0SCAN for DMA_CH_CTRL

Definition at line 10900 of file efm32g890f128.h.

#define DMA_CH_CTRL_SIGSEL_ADC0SINGLE   (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0)

Shifted mode ADC0SINGLE for DMA_CH_CTRL

Definition at line 10886 of file efm32g890f128.h.

#define DMA_CH_CTRL_SIGSEL_AESDATARD   (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0)

Shifted mode AESDATARD for DMA_CH_CTRL

Definition at line 10922 of file efm32g890f128.h.

#define DMA_CH_CTRL_SIGSEL_AESDATAWR   (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0)

Shifted mode AESDATAWR for DMA_CH_CTRL

Definition at line 10899 of file efm32g890f128.h.

#define DMA_CH_CTRL_SIGSEL_AESKEYWR   (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0)

Shifted mode AESKEYWR for DMA_CH_CTRL

Definition at line 10926 of file efm32g890f128.h.

#define DMA_CH_CTRL_SIGSEL_AESXORDATAWR   (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0)

Shifted mode AESXORDATAWR for DMA_CH_CTRL

Definition at line 10912 of file efm32g890f128.h.

#define DMA_CH_CTRL_SIGSEL_DAC0CH0   (_DMA_CH_CTRL_SIGSEL_DAC0CH0 << 0)

Shifted mode DAC0CH0 for DMA_CH_CTRL

Definition at line 10887 of file efm32g890f128.h.

#define DMA_CH_CTRL_SIGSEL_DAC0CH1   (_DMA_CH_CTRL_SIGSEL_DAC0CH1 << 0)

Shifted mode DAC0CH1 for DMA_CH_CTRL

Definition at line 10901 of file efm32g890f128.h.

#define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV   (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0)

Shifted mode I2C0RXDATAV for DMA_CH_CTRL

Definition at line 10893 of file efm32g890f128.h.

#define DMA_CH_CTRL_SIGSEL_I2C0TXBL   (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0)

Shifted mode I2C0TXBL for DMA_CH_CTRL

Definition at line 10907 of file efm32g890f128.h.

#define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV   (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0)

Shifted mode LEUART0RXDATAV for DMA_CH_CTRL

Definition at line 10891 of file efm32g890f128.h.

#define DMA_CH_CTRL_SIGSEL_LEUART0TXBL   (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0)

Shifted mode LEUART0TXBL for DMA_CH_CTRL

Definition at line 10905 of file efm32g890f128.h.

#define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY   (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0)

Shifted mode LEUART0TXEMPTY for DMA_CH_CTRL

Definition at line 10916 of file efm32g890f128.h.

#define DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV   (_DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV << 0)

Shifted mode LEUART1RXDATAV for DMA_CH_CTRL

Definition at line 10892 of file efm32g890f128.h.

#define DMA_CH_CTRL_SIGSEL_LEUART1TXBL   (_DMA_CH_CTRL_SIGSEL_LEUART1TXBL << 0)

Shifted mode LEUART1TXBL for DMA_CH_CTRL

Definition at line 10906 of file efm32g890f128.h.

#define DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY   (_DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY << 0)

Shifted mode LEUART1TXEMPTY for DMA_CH_CTRL

Definition at line 10917 of file efm32g890f128.h.

#define DMA_CH_CTRL_SIGSEL_MSCWDATA   (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0)

Shifted mode MSCWDATA for DMA_CH_CTRL

Definition at line 10898 of file efm32g890f128.h.

#define DMA_CH_CTRL_SIGSEL_TIMER0CC0   (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0)

Shifted mode TIMER0CC0 for DMA_CH_CTRL

Definition at line 10908 of file efm32g890f128.h.

#define DMA_CH_CTRL_SIGSEL_TIMER0CC1   (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0)

Shifted mode TIMER0CC1 for DMA_CH_CTRL

Definition at line 10918 of file efm32g890f128.h.

#define DMA_CH_CTRL_SIGSEL_TIMER0CC2   (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0)

Shifted mode TIMER0CC2 for DMA_CH_CTRL

Definition at line 10923 of file efm32g890f128.h.

#define DMA_CH_CTRL_SIGSEL_TIMER0UFOF   (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0)

Shifted mode TIMER0UFOF for DMA_CH_CTRL

Definition at line 10894 of file efm32g890f128.h.

#define DMA_CH_CTRL_SIGSEL_TIMER1CC0   (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0)

Shifted mode TIMER1CC0 for DMA_CH_CTRL

Definition at line 10909 of file efm32g890f128.h.

#define DMA_CH_CTRL_SIGSEL_TIMER1CC1   (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0)

Shifted mode TIMER1CC1 for DMA_CH_CTRL

Definition at line 10919 of file efm32g890f128.h.

#define DMA_CH_CTRL_SIGSEL_TIMER1CC2   (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0)

Shifted mode TIMER1CC2 for DMA_CH_CTRL

Definition at line 10924 of file efm32g890f128.h.

#define DMA_CH_CTRL_SIGSEL_TIMER1UFOF   (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0)

Shifted mode TIMER1UFOF for DMA_CH_CTRL

Definition at line 10895 of file efm32g890f128.h.

#define DMA_CH_CTRL_SIGSEL_TIMER2CC0   (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0)

Shifted mode TIMER2CC0 for DMA_CH_CTRL

Definition at line 10910 of file efm32g890f128.h.

#define DMA_CH_CTRL_SIGSEL_TIMER2CC1   (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0)

Shifted mode TIMER2CC1 for DMA_CH_CTRL

Definition at line 10920 of file efm32g890f128.h.

#define DMA_CH_CTRL_SIGSEL_TIMER2CC2   (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0)

Shifted mode TIMER2CC2 for DMA_CH_CTRL

Definition at line 10925 of file efm32g890f128.h.

#define DMA_CH_CTRL_SIGSEL_TIMER2UFOF   (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0)

Shifted mode TIMER2UFOF for DMA_CH_CTRL

Definition at line 10896 of file efm32g890f128.h.

#define DMA_CH_CTRL_SIGSEL_UART0RXDATAV   (_DMA_CH_CTRL_SIGSEL_UART0RXDATAV << 0)

Shifted mode UART0RXDATAV for DMA_CH_CTRL

Definition at line 10897 of file efm32g890f128.h.

#define DMA_CH_CTRL_SIGSEL_UART0TXBL   (_DMA_CH_CTRL_SIGSEL_UART0TXBL << 0)

Shifted mode UART0TXBL for DMA_CH_CTRL

Definition at line 10911 of file efm32g890f128.h.

#define DMA_CH_CTRL_SIGSEL_UART0TXEMPTY   (_DMA_CH_CTRL_SIGSEL_UART0TXEMPTY << 0)

Shifted mode UART0TXEMPTY for DMA_CH_CTRL

Definition at line 10921 of file efm32g890f128.h.

#define DMA_CH_CTRL_SIGSEL_USART0RXDATAV   (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0)

Shifted mode USART0RXDATAV for DMA_CH_CTRL

Definition at line 10888 of file efm32g890f128.h.

#define DMA_CH_CTRL_SIGSEL_USART0TXBL   (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0)

Shifted mode USART0TXBL for DMA_CH_CTRL

Definition at line 10902 of file efm32g890f128.h.

#define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY   (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0)

Shifted mode USART0TXEMPTY for DMA_CH_CTRL

Definition at line 10913 of file efm32g890f128.h.

#define DMA_CH_CTRL_SIGSEL_USART1RXDATAV   (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0)

Shifted mode USART1RXDATAV for DMA_CH_CTRL

Definition at line 10889 of file efm32g890f128.h.

#define DMA_CH_CTRL_SIGSEL_USART1TXBL   (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0)

Shifted mode USART1TXBL for DMA_CH_CTRL

Definition at line 10903 of file efm32g890f128.h.

#define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY   (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0)

Shifted mode USART1TXEMPTY for DMA_CH_CTRL

Definition at line 10914 of file efm32g890f128.h.

#define DMA_CH_CTRL_SIGSEL_USART2RXDATAV   (_DMA_CH_CTRL_SIGSEL_USART2RXDATAV << 0)

Shifted mode USART2RXDATAV for DMA_CH_CTRL

Definition at line 10890 of file efm32g890f128.h.

#define DMA_CH_CTRL_SIGSEL_USART2TXBL   (_DMA_CH_CTRL_SIGSEL_USART2TXBL << 0)

Shifted mode USART2TXBL for DMA_CH_CTRL

Definition at line 10904 of file efm32g890f128.h.

#define DMA_CH_CTRL_SIGSEL_USART2TXEMPTY   (_DMA_CH_CTRL_SIGSEL_USART2TXEMPTY << 0)

Shifted mode USART2TXEMPTY for DMA_CH_CTRL

Definition at line 10915 of file efm32g890f128.h.

#define DMA_CH_CTRL_SOURCESEL_ADC0   (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16)

Shifted mode ADC0 for DMA_CH_CTRL

Definition at line 10945 of file efm32g890f128.h.

#define DMA_CH_CTRL_SOURCESEL_AES   (_DMA_CH_CTRL_SOURCESEL_AES << 16)

Shifted mode AES for DMA_CH_CTRL

Definition at line 10958 of file efm32g890f128.h.

#define DMA_CH_CTRL_SOURCESEL_DAC0   (_DMA_CH_CTRL_SOURCESEL_DAC0 << 16)

Shifted mode DAC0 for DMA_CH_CTRL

Definition at line 10946 of file efm32g890f128.h.

#define DMA_CH_CTRL_SOURCESEL_I2C0   (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16)

Shifted mode I2C0 for DMA_CH_CTRL

Definition at line 10952 of file efm32g890f128.h.

#define DMA_CH_CTRL_SOURCESEL_LEUART0   (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16)

Shifted mode LEUART0 for DMA_CH_CTRL

Definition at line 10950 of file efm32g890f128.h.

#define DMA_CH_CTRL_SOURCESEL_LEUART1   (_DMA_CH_CTRL_SOURCESEL_LEUART1 << 16)

Shifted mode LEUART1 for DMA_CH_CTRL

Definition at line 10951 of file efm32g890f128.h.

#define DMA_CH_CTRL_SOURCESEL_MSC   (_DMA_CH_CTRL_SOURCESEL_MSC << 16)

Shifted mode MSC for DMA_CH_CTRL

Definition at line 10957 of file efm32g890f128.h.

#define DMA_CH_CTRL_SOURCESEL_NONE   (_DMA_CH_CTRL_SOURCESEL_NONE << 16)

Shifted mode NONE for DMA_CH_CTRL

Definition at line 10944 of file efm32g890f128.h.

#define DMA_CH_CTRL_SOURCESEL_TIMER0   (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16)

Shifted mode TIMER0 for DMA_CH_CTRL

Definition at line 10953 of file efm32g890f128.h.

#define DMA_CH_CTRL_SOURCESEL_TIMER1   (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16)

Shifted mode TIMER1 for DMA_CH_CTRL

Definition at line 10954 of file efm32g890f128.h.

#define DMA_CH_CTRL_SOURCESEL_TIMER2   (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16)

Shifted mode TIMER2 for DMA_CH_CTRL

Definition at line 10955 of file efm32g890f128.h.

#define DMA_CH_CTRL_SOURCESEL_UART0   (_DMA_CH_CTRL_SOURCESEL_UART0 << 16)

Shifted mode UART0 for DMA_CH_CTRL

Definition at line 10956 of file efm32g890f128.h.

#define DMA_CH_CTRL_SOURCESEL_USART0   (_DMA_CH_CTRL_SOURCESEL_USART0 << 16)

Shifted mode USART0 for DMA_CH_CTRL

Definition at line 10947 of file efm32g890f128.h.

#define DMA_CH_CTRL_SOURCESEL_USART1   (_DMA_CH_CTRL_SOURCESEL_USART1 << 16)

Shifted mode USART1 for DMA_CH_CTRL

Definition at line 10948 of file efm32g890f128.h.

#define DMA_CH_CTRL_SOURCESEL_USART2   (_DMA_CH_CTRL_SOURCESEL_USART2 << 16)

Shifted mode USART2 for DMA_CH_CTRL

Definition at line 10949 of file efm32g890f128.h.

#define DMA_CHALTC_CH0ALTC   (0x1UL << 0)

Channel 0 Alternate Clear

Definition at line 10418 of file efm32g890f128.h.

#define DMA_CHALTC_CH0ALTC_DEFAULT   (_DMA_CHALTC_CH0ALTC_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHALTC

Definition at line 10422 of file efm32g890f128.h.

#define DMA_CHALTC_CH1ALTC   (0x1UL << 1)

Channel 1 Alternate Clear

Definition at line 10423 of file efm32g890f128.h.

#define DMA_CHALTC_CH1ALTC_DEFAULT   (_DMA_CHALTC_CH1ALTC_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHALTC

Definition at line 10427 of file efm32g890f128.h.

#define DMA_CHALTC_CH2ALTC   (0x1UL << 2)

Channel 2 Alternate Clear

Definition at line 10428 of file efm32g890f128.h.

#define DMA_CHALTC_CH2ALTC_DEFAULT   (_DMA_CHALTC_CH2ALTC_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHALTC

Definition at line 10432 of file efm32g890f128.h.

#define DMA_CHALTC_CH3ALTC   (0x1UL << 3)

Channel 3 Alternate Clear

Definition at line 10433 of file efm32g890f128.h.

#define DMA_CHALTC_CH3ALTC_DEFAULT   (_DMA_CHALTC_CH3ALTC_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHALTC

Definition at line 10437 of file efm32g890f128.h.

#define DMA_CHALTC_CH4ALTC   (0x1UL << 4)

Channel 4 Alternate Clear

Definition at line 10438 of file efm32g890f128.h.

#define DMA_CHALTC_CH4ALTC_DEFAULT   (_DMA_CHALTC_CH4ALTC_DEFAULT << 4)

Shifted mode DEFAULT for DMA_CHALTC

Definition at line 10442 of file efm32g890f128.h.

#define DMA_CHALTC_CH5ALTC   (0x1UL << 5)

Channel 5 Alternate Clear

Definition at line 10443 of file efm32g890f128.h.

#define DMA_CHALTC_CH5ALTC_DEFAULT   (_DMA_CHALTC_CH5ALTC_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CHALTC

Definition at line 10447 of file efm32g890f128.h.

#define DMA_CHALTC_CH6ALTC   (0x1UL << 6)

Channel 6 Alternate Clear

Definition at line 10448 of file efm32g890f128.h.

#define DMA_CHALTC_CH6ALTC_DEFAULT   (_DMA_CHALTC_CH6ALTC_DEFAULT << 6)

Shifted mode DEFAULT for DMA_CHALTC

Definition at line 10452 of file efm32g890f128.h.

#define DMA_CHALTC_CH7ALTC   (0x1UL << 7)

Channel 7 Alternate Clear

Definition at line 10453 of file efm32g890f128.h.

#define DMA_CHALTC_CH7ALTC_DEFAULT   (_DMA_CHALTC_CH7ALTC_DEFAULT << 7)

Shifted mode DEFAULT for DMA_CHALTC

Definition at line 10457 of file efm32g890f128.h.

#define DMA_CHALTS_CH0ALTS   (0x1UL << 0)

Channel 0 Alternate Structure Set

Definition at line 10374 of file efm32g890f128.h.

#define DMA_CHALTS_CH0ALTS_DEFAULT   (_DMA_CHALTS_CH0ALTS_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHALTS

Definition at line 10378 of file efm32g890f128.h.

#define DMA_CHALTS_CH1ALTS   (0x1UL << 1)

Channel 1 Alternate Structure Set

Definition at line 10379 of file efm32g890f128.h.

#define DMA_CHALTS_CH1ALTS_DEFAULT   (_DMA_CHALTS_CH1ALTS_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHALTS

Definition at line 10383 of file efm32g890f128.h.

#define DMA_CHALTS_CH2ALTS   (0x1UL << 2)

Channel 2 Alternate Structure Set

Definition at line 10384 of file efm32g890f128.h.

#define DMA_CHALTS_CH2ALTS_DEFAULT   (_DMA_CHALTS_CH2ALTS_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHALTS

Definition at line 10388 of file efm32g890f128.h.

#define DMA_CHALTS_CH3ALTS   (0x1UL << 3)

Channel 3 Alternate Structure Set

Definition at line 10389 of file efm32g890f128.h.

#define DMA_CHALTS_CH3ALTS_DEFAULT   (_DMA_CHALTS_CH3ALTS_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHALTS

Definition at line 10393 of file efm32g890f128.h.

#define DMA_CHALTS_CH4ALTS   (0x1UL << 4)

Channel 4 Alternate Structure Set

Definition at line 10394 of file efm32g890f128.h.

#define DMA_CHALTS_CH4ALTS_DEFAULT   (_DMA_CHALTS_CH4ALTS_DEFAULT << 4)

Shifted mode DEFAULT for DMA_CHALTS

Definition at line 10398 of file efm32g890f128.h.

#define DMA_CHALTS_CH5ALTS   (0x1UL << 5)

Channel 5 Alternate Structure Set

Definition at line 10399 of file efm32g890f128.h.

#define DMA_CHALTS_CH5ALTS_DEFAULT   (_DMA_CHALTS_CH5ALTS_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CHALTS

Definition at line 10403 of file efm32g890f128.h.

#define DMA_CHALTS_CH6ALTS   (0x1UL << 6)

Channel 6 Alternate Structure Set

Definition at line 10404 of file efm32g890f128.h.

#define DMA_CHALTS_CH6ALTS_DEFAULT   (_DMA_CHALTS_CH6ALTS_DEFAULT << 6)

Shifted mode DEFAULT for DMA_CHALTS

Definition at line 10408 of file efm32g890f128.h.

#define DMA_CHALTS_CH7ALTS   (0x1UL << 7)

Channel 7 Alternate Structure Set

Definition at line 10409 of file efm32g890f128.h.

#define DMA_CHALTS_CH7ALTS_DEFAULT   (_DMA_CHALTS_CH7ALTS_DEFAULT << 7)

Shifted mode DEFAULT for DMA_CHALTS

Definition at line 10413 of file efm32g890f128.h.

#define DMA_CHENC_CH0ENC   (0x1UL << 0)

Channel 0 Enable Clear

Definition at line 10330 of file efm32g890f128.h.

#define DMA_CHENC_CH0ENC_DEFAULT   (_DMA_CHENC_CH0ENC_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHENC

Definition at line 10334 of file efm32g890f128.h.

#define DMA_CHENC_CH1ENC   (0x1UL << 1)

Channel 1 Enable Clear

Definition at line 10335 of file efm32g890f128.h.

#define DMA_CHENC_CH1ENC_DEFAULT   (_DMA_CHENC_CH1ENC_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHENC

Definition at line 10339 of file efm32g890f128.h.

#define DMA_CHENC_CH2ENC   (0x1UL << 2)

Channel 2 Enable Clear

Definition at line 10340 of file efm32g890f128.h.

#define DMA_CHENC_CH2ENC_DEFAULT   (_DMA_CHENC_CH2ENC_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHENC

Definition at line 10344 of file efm32g890f128.h.

#define DMA_CHENC_CH3ENC   (0x1UL << 3)

Channel 3 Enable Clear

Definition at line 10345 of file efm32g890f128.h.

#define DMA_CHENC_CH3ENC_DEFAULT   (_DMA_CHENC_CH3ENC_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHENC

Definition at line 10349 of file efm32g890f128.h.

#define DMA_CHENC_CH4ENC   (0x1UL << 4)

Channel 4 Enable Clear

Definition at line 10350 of file efm32g890f128.h.

#define DMA_CHENC_CH4ENC_DEFAULT   (_DMA_CHENC_CH4ENC_DEFAULT << 4)

Shifted mode DEFAULT for DMA_CHENC

Definition at line 10354 of file efm32g890f128.h.

#define DMA_CHENC_CH5ENC   (0x1UL << 5)

Channel 5 Enable Clear

Definition at line 10355 of file efm32g890f128.h.

#define DMA_CHENC_CH5ENC_DEFAULT   (_DMA_CHENC_CH5ENC_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CHENC

Definition at line 10359 of file efm32g890f128.h.

#define DMA_CHENC_CH6ENC   (0x1UL << 6)

Channel 6 Enable Clear

Definition at line 10360 of file efm32g890f128.h.

#define DMA_CHENC_CH6ENC_DEFAULT   (_DMA_CHENC_CH6ENC_DEFAULT << 6)

Shifted mode DEFAULT for DMA_CHENC

Definition at line 10364 of file efm32g890f128.h.

#define DMA_CHENC_CH7ENC   (0x1UL << 7)

Channel 7 Enable Clear

Definition at line 10365 of file efm32g890f128.h.

#define DMA_CHENC_CH7ENC_DEFAULT   (_DMA_CHENC_CH7ENC_DEFAULT << 7)

Shifted mode DEFAULT for DMA_CHENC

Definition at line 10369 of file efm32g890f128.h.

#define DMA_CHENS_CH0ENS   (0x1UL << 0)

Channel 0 Enable Set

Definition at line 10286 of file efm32g890f128.h.

#define DMA_CHENS_CH0ENS_DEFAULT   (_DMA_CHENS_CH0ENS_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHENS

Definition at line 10290 of file efm32g890f128.h.

#define DMA_CHENS_CH1ENS   (0x1UL << 1)

Channel 1 Enable Set

Definition at line 10291 of file efm32g890f128.h.

#define DMA_CHENS_CH1ENS_DEFAULT   (_DMA_CHENS_CH1ENS_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHENS

Definition at line 10295 of file efm32g890f128.h.

#define DMA_CHENS_CH2ENS   (0x1UL << 2)

Channel 2 Enable Set

Definition at line 10296 of file efm32g890f128.h.

#define DMA_CHENS_CH2ENS_DEFAULT   (_DMA_CHENS_CH2ENS_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHENS

Definition at line 10300 of file efm32g890f128.h.

#define DMA_CHENS_CH3ENS   (0x1UL << 3)

Channel 3 Enable Set

Definition at line 10301 of file efm32g890f128.h.

#define DMA_CHENS_CH3ENS_DEFAULT   (_DMA_CHENS_CH3ENS_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHENS

Definition at line 10305 of file efm32g890f128.h.

#define DMA_CHENS_CH4ENS   (0x1UL << 4)

Channel 4 Enable Set

Definition at line 10306 of file efm32g890f128.h.

#define DMA_CHENS_CH4ENS_DEFAULT   (_DMA_CHENS_CH4ENS_DEFAULT << 4)

Shifted mode DEFAULT for DMA_CHENS

Definition at line 10310 of file efm32g890f128.h.

#define DMA_CHENS_CH5ENS   (0x1UL << 5)

Channel 5 Enable Set

Definition at line 10311 of file efm32g890f128.h.

#define DMA_CHENS_CH5ENS_DEFAULT   (_DMA_CHENS_CH5ENS_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CHENS

Definition at line 10315 of file efm32g890f128.h.

#define DMA_CHENS_CH6ENS   (0x1UL << 6)

Channel 6 Enable Set

Definition at line 10316 of file efm32g890f128.h.

#define DMA_CHENS_CH6ENS_DEFAULT   (_DMA_CHENS_CH6ENS_DEFAULT << 6)

Shifted mode DEFAULT for DMA_CHENS

Definition at line 10320 of file efm32g890f128.h.

#define DMA_CHENS_CH7ENS   (0x1UL << 7)

Channel 7 Enable Set

Definition at line 10321 of file efm32g890f128.h.

#define DMA_CHENS_CH7ENS_DEFAULT   (_DMA_CHENS_CH7ENS_DEFAULT << 7)

Shifted mode DEFAULT for DMA_CHENS

Definition at line 10325 of file efm32g890f128.h.

#define DMA_CHPRIC_CH0PRIC   (0x1UL << 0)

Channel 0 High Priority Clear

Definition at line 10506 of file efm32g890f128.h.

#define DMA_CHPRIC_CH0PRIC_DEFAULT   (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHPRIC

Definition at line 10510 of file efm32g890f128.h.

#define DMA_CHPRIC_CH1PRIC   (0x1UL << 1)

Channel 1 High Priority Clear

Definition at line 10511 of file efm32g890f128.h.

#define DMA_CHPRIC_CH1PRIC_DEFAULT   (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHPRIC

Definition at line 10515 of file efm32g890f128.h.

#define DMA_CHPRIC_CH2PRIC   (0x1UL << 2)

Channel 2 High Priority Clear

Definition at line 10516 of file efm32g890f128.h.

#define DMA_CHPRIC_CH2PRIC_DEFAULT   (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHPRIC

Definition at line 10520 of file efm32g890f128.h.

#define DMA_CHPRIC_CH3PRIC   (0x1UL << 3)

Channel 3 High Priority Clear

Definition at line 10521 of file efm32g890f128.h.

#define DMA_CHPRIC_CH3PRIC_DEFAULT   (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHPRIC

Definition at line 10525 of file efm32g890f128.h.

#define DMA_CHPRIC_CH4PRIC   (0x1UL << 4)

Channel 4 High Priority Clear

Definition at line 10526 of file efm32g890f128.h.

#define DMA_CHPRIC_CH4PRIC_DEFAULT   (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4)

Shifted mode DEFAULT for DMA_CHPRIC

Definition at line 10530 of file efm32g890f128.h.

#define DMA_CHPRIC_CH5PRIC   (0x1UL << 5)

Channel 5 High Priority Clear

Definition at line 10531 of file efm32g890f128.h.

#define DMA_CHPRIC_CH5PRIC_DEFAULT   (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CHPRIC

Definition at line 10535 of file efm32g890f128.h.

#define DMA_CHPRIC_CH6PRIC   (0x1UL << 6)

Channel 6 High Priority Clear

Definition at line 10536 of file efm32g890f128.h.

#define DMA_CHPRIC_CH6PRIC_DEFAULT   (_DMA_CHPRIC_CH6PRIC_DEFAULT << 6)

Shifted mode DEFAULT for DMA_CHPRIC

Definition at line 10540 of file efm32g890f128.h.

#define DMA_CHPRIC_CH7PRIC   (0x1UL << 7)

Channel 7 High Priority Clear

Definition at line 10541 of file efm32g890f128.h.

#define DMA_CHPRIC_CH7PRIC_DEFAULT   (_DMA_CHPRIC_CH7PRIC_DEFAULT << 7)

Shifted mode DEFAULT for DMA_CHPRIC

Definition at line 10545 of file efm32g890f128.h.

#define DMA_CHPRIS_CH0PRIS   (0x1UL << 0)

Channel 0 High Priority Set

Definition at line 10462 of file efm32g890f128.h.

#define DMA_CHPRIS_CH0PRIS_DEFAULT   (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHPRIS

Definition at line 10466 of file efm32g890f128.h.

#define DMA_CHPRIS_CH1PRIS   (0x1UL << 1)

Channel 1 High Priority Set

Definition at line 10467 of file efm32g890f128.h.

#define DMA_CHPRIS_CH1PRIS_DEFAULT   (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHPRIS

Definition at line 10471 of file efm32g890f128.h.

#define DMA_CHPRIS_CH2PRIS   (0x1UL << 2)

Channel 2 High Priority Set

Definition at line 10472 of file efm32g890f128.h.

#define DMA_CHPRIS_CH2PRIS_DEFAULT   (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHPRIS

Definition at line 10476 of file efm32g890f128.h.

#define DMA_CHPRIS_CH3PRIS   (0x1UL << 3)

Channel 3 High Priority Set

Definition at line 10477 of file efm32g890f128.h.

#define DMA_CHPRIS_CH3PRIS_DEFAULT   (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHPRIS

Definition at line 10481 of file efm32g890f128.h.

#define DMA_CHPRIS_CH4PRIS   (0x1UL << 4)

Channel 4 High Priority Set

Definition at line 10482 of file efm32g890f128.h.

#define DMA_CHPRIS_CH4PRIS_DEFAULT   (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4)

Shifted mode DEFAULT for DMA_CHPRIS

Definition at line 10486 of file efm32g890f128.h.

#define DMA_CHPRIS_CH5PRIS   (0x1UL << 5)

Channel 5 High Priority Set

Definition at line 10487 of file efm32g890f128.h.

#define DMA_CHPRIS_CH5PRIS_DEFAULT   (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CHPRIS

Definition at line 10491 of file efm32g890f128.h.

#define DMA_CHPRIS_CH6PRIS   (0x1UL << 6)

Channel 6 High Priority Set

Definition at line 10492 of file efm32g890f128.h.

#define DMA_CHPRIS_CH6PRIS_DEFAULT   (_DMA_CHPRIS_CH6PRIS_DEFAULT << 6)

Shifted mode DEFAULT for DMA_CHPRIS

Definition at line 10496 of file efm32g890f128.h.

#define DMA_CHPRIS_CH7PRIS   (0x1UL << 7)

Channel 7 High Priority Set

Definition at line 10497 of file efm32g890f128.h.

#define DMA_CHPRIS_CH7PRIS_DEFAULT   (_DMA_CHPRIS_CH7PRIS_DEFAULT << 7)

Shifted mode DEFAULT for DMA_CHPRIS

Definition at line 10501 of file efm32g890f128.h.

#define DMA_CHREQMASKC_CH0REQMASKC   (0x1UL << 0)

Channel 0 Request Mask Clear

Definition at line 10242 of file efm32g890f128.h.

#define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHREQMASKC

Definition at line 10246 of file efm32g890f128.h.

#define DMA_CHREQMASKC_CH1REQMASKC   (0x1UL << 1)

Channel 1 Request Mask Clear

Definition at line 10247 of file efm32g890f128.h.

#define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHREQMASKC

Definition at line 10251 of file efm32g890f128.h.

#define DMA_CHREQMASKC_CH2REQMASKC   (0x1UL << 2)

Channel 2 Request Mask Clear

Definition at line 10252 of file efm32g890f128.h.

#define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHREQMASKC

Definition at line 10256 of file efm32g890f128.h.

#define DMA_CHREQMASKC_CH3REQMASKC   (0x1UL << 3)

Channel 3 Request Mask Clear

Definition at line 10257 of file efm32g890f128.h.

#define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHREQMASKC

Definition at line 10261 of file efm32g890f128.h.

#define DMA_CHREQMASKC_CH4REQMASKC   (0x1UL << 4)

Channel 4 Request Mask Clear

Definition at line 10262 of file efm32g890f128.h.

#define DMA_CHREQMASKC_CH4REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4)

Shifted mode DEFAULT for DMA_CHREQMASKC

Definition at line 10266 of file efm32g890f128.h.

#define DMA_CHREQMASKC_CH5REQMASKC   (0x1UL << 5)

Channel 5 Request Mask Clear

Definition at line 10267 of file efm32g890f128.h.

#define DMA_CHREQMASKC_CH5REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CHREQMASKC

Definition at line 10271 of file efm32g890f128.h.

#define DMA_CHREQMASKC_CH6REQMASKC   (0x1UL << 6)

Channel 6 Request Mask Clear

Definition at line 10272 of file efm32g890f128.h.

#define DMA_CHREQMASKC_CH6REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH6REQMASKC_DEFAULT << 6)

Shifted mode DEFAULT for DMA_CHREQMASKC

Definition at line 10276 of file efm32g890f128.h.

#define DMA_CHREQMASKC_CH7REQMASKC   (0x1UL << 7)

Channel 7 Request Mask Clear

Definition at line 10277 of file efm32g890f128.h.

#define DMA_CHREQMASKC_CH7REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH7REQMASKC_DEFAULT << 7)

Shifted mode DEFAULT for DMA_CHREQMASKC

Definition at line 10281 of file efm32g890f128.h.

#define DMA_CHREQMASKS_CH0REQMASKS   (0x1UL << 0)

Channel 0 Request Mask Set

Definition at line 10198 of file efm32g890f128.h.

#define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHREQMASKS

Definition at line 10202 of file efm32g890f128.h.

#define DMA_CHREQMASKS_CH1REQMASKS   (0x1UL << 1)

Channel 1 Request Mask Set

Definition at line 10203 of file efm32g890f128.h.

#define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHREQMASKS

Definition at line 10207 of file efm32g890f128.h.

#define DMA_CHREQMASKS_CH2REQMASKS   (0x1UL << 2)

Channel 2 Request Mask Set

Definition at line 10208 of file efm32g890f128.h.

#define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHREQMASKS

Definition at line 10212 of file efm32g890f128.h.

#define DMA_CHREQMASKS_CH3REQMASKS   (0x1UL << 3)

Channel 3 Request Mask Set

Definition at line 10213 of file efm32g890f128.h.

#define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHREQMASKS

Definition at line 10217 of file efm32g890f128.h.

#define DMA_CHREQMASKS_CH4REQMASKS   (0x1UL << 4)

Channel 4 Request Mask Set

Definition at line 10218 of file efm32g890f128.h.

#define DMA_CHREQMASKS_CH4REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4)

Shifted mode DEFAULT for DMA_CHREQMASKS

Definition at line 10222 of file efm32g890f128.h.

#define DMA_CHREQMASKS_CH5REQMASKS   (0x1UL << 5)

Channel 5 Request Mask Set

Definition at line 10223 of file efm32g890f128.h.

#define DMA_CHREQMASKS_CH5REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CHREQMASKS

Definition at line 10227 of file efm32g890f128.h.

#define DMA_CHREQMASKS_CH6REQMASKS   (0x1UL << 6)

Channel 6 Request Mask Set

Definition at line 10228 of file efm32g890f128.h.

#define DMA_CHREQMASKS_CH6REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH6REQMASKS_DEFAULT << 6)

Shifted mode DEFAULT for DMA_CHREQMASKS

Definition at line 10232 of file efm32g890f128.h.

#define DMA_CHREQMASKS_CH7REQMASKS   (0x1UL << 7)

Channel 7 Request Mask Set

Definition at line 10233 of file efm32g890f128.h.

#define DMA_CHREQMASKS_CH7REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH7REQMASKS_DEFAULT << 7)

Shifted mode DEFAULT for DMA_CHREQMASKS

Definition at line 10237 of file efm32g890f128.h.

#define DMA_CHREQSTATUS_CH0REQSTATUS   (0x1UL << 0)

Channel 0 Request Status

Definition at line 10559 of file efm32g890f128.h.

#define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHREQSTATUS

Definition at line 10563 of file efm32g890f128.h.

#define DMA_CHREQSTATUS_CH1REQSTATUS   (0x1UL << 1)

Channel 1 Request Status

Definition at line 10564 of file efm32g890f128.h.

#define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHREQSTATUS

Definition at line 10568 of file efm32g890f128.h.

#define DMA_CHREQSTATUS_CH2REQSTATUS   (0x1UL << 2)

Channel 2 Request Status

Definition at line 10569 of file efm32g890f128.h.

#define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHREQSTATUS

Definition at line 10573 of file efm32g890f128.h.

#define DMA_CHREQSTATUS_CH3REQSTATUS   (0x1UL << 3)

Channel 3 Request Status

Definition at line 10574 of file efm32g890f128.h.

#define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHREQSTATUS

Definition at line 10578 of file efm32g890f128.h.

#define DMA_CHREQSTATUS_CH4REQSTATUS   (0x1UL << 4)

Channel 4 Request Status

Definition at line 10579 of file efm32g890f128.h.

#define DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4)

Shifted mode DEFAULT for DMA_CHREQSTATUS

Definition at line 10583 of file efm32g890f128.h.

#define DMA_CHREQSTATUS_CH5REQSTATUS   (0x1UL << 5)

Channel 5 Request Status

Definition at line 10584 of file efm32g890f128.h.

#define DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CHREQSTATUS

Definition at line 10588 of file efm32g890f128.h.

#define DMA_CHREQSTATUS_CH6REQSTATUS   (0x1UL << 6)

Channel 6 Request Status

Definition at line 10589 of file efm32g890f128.h.

#define DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT << 6)

Shifted mode DEFAULT for DMA_CHREQSTATUS

Definition at line 10593 of file efm32g890f128.h.

#define DMA_CHREQSTATUS_CH7REQSTATUS   (0x1UL << 7)

Channel 7 Request Status

Definition at line 10594 of file efm32g890f128.h.

#define DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT << 7)

Shifted mode DEFAULT for DMA_CHREQSTATUS

Definition at line 10598 of file efm32g890f128.h.

#define DMA_CHSREQSTATUS_CH0SREQSTATUS   (0x1UL << 0)

Channel 0 Single Request Status

Definition at line 10603 of file efm32g890f128.h.

#define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 10607 of file efm32g890f128.h.

#define DMA_CHSREQSTATUS_CH1SREQSTATUS   (0x1UL << 1)

Channel 1 Single Request Status

Definition at line 10608 of file efm32g890f128.h.

#define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 10612 of file efm32g890f128.h.

#define DMA_CHSREQSTATUS_CH2SREQSTATUS   (0x1UL << 2)

Channel 2 Single Request Status

Definition at line 10613 of file efm32g890f128.h.

#define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 10617 of file efm32g890f128.h.

#define DMA_CHSREQSTATUS_CH3SREQSTATUS   (0x1UL << 3)

Channel 3 Single Request Status

Definition at line 10618 of file efm32g890f128.h.

#define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 10622 of file efm32g890f128.h.

#define DMA_CHSREQSTATUS_CH4SREQSTATUS   (0x1UL << 4)

Channel 4 Single Request Status

Definition at line 10623 of file efm32g890f128.h.

#define DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4)

Shifted mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 10627 of file efm32g890f128.h.

#define DMA_CHSREQSTATUS_CH5SREQSTATUS   (0x1UL << 5)

Channel 5 Single Request Status

Definition at line 10628 of file efm32g890f128.h.

#define DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 10632 of file efm32g890f128.h.

#define DMA_CHSREQSTATUS_CH6SREQSTATUS   (0x1UL << 6)

Channel 6 Single Request Status

Definition at line 10633 of file efm32g890f128.h.

#define DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT << 6)

Shifted mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 10637 of file efm32g890f128.h.

#define DMA_CHSREQSTATUS_CH7SREQSTATUS   (0x1UL << 7)

Channel 7 Single Request Status

Definition at line 10638 of file efm32g890f128.h.

#define DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT << 7)

Shifted mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 10642 of file efm32g890f128.h.

#define DMA_CHSWREQ_CH0SWREQ   (0x1UL << 0)

Channel 0 Software Request

Definition at line 10062 of file efm32g890f128.h.

#define DMA_CHSWREQ_CH0SWREQ_DEFAULT   (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHSWREQ

Definition at line 10066 of file efm32g890f128.h.

#define DMA_CHSWREQ_CH1SWREQ   (0x1UL << 1)

Channel 1 Software Request

Definition at line 10067 of file efm32g890f128.h.

#define DMA_CHSWREQ_CH1SWREQ_DEFAULT   (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHSWREQ

Definition at line 10071 of file efm32g890f128.h.

#define DMA_CHSWREQ_CH2SWREQ   (0x1UL << 2)

Channel 2 Software Request

Definition at line 10072 of file efm32g890f128.h.

#define DMA_CHSWREQ_CH2SWREQ_DEFAULT   (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHSWREQ

Definition at line 10076 of file efm32g890f128.h.

#define DMA_CHSWREQ_CH3SWREQ   (0x1UL << 3)

Channel 3 Software Request

Definition at line 10077 of file efm32g890f128.h.

#define DMA_CHSWREQ_CH3SWREQ_DEFAULT   (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHSWREQ

Definition at line 10081 of file efm32g890f128.h.

#define DMA_CHSWREQ_CH4SWREQ   (0x1UL << 4)

Channel 4 Software Request

Definition at line 10082 of file efm32g890f128.h.

#define DMA_CHSWREQ_CH4SWREQ_DEFAULT   (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4)

Shifted mode DEFAULT for DMA_CHSWREQ

Definition at line 10086 of file efm32g890f128.h.

#define DMA_CHSWREQ_CH5SWREQ   (0x1UL << 5)

Channel 5 Software Request

Definition at line 10087 of file efm32g890f128.h.

#define DMA_CHSWREQ_CH5SWREQ_DEFAULT   (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CHSWREQ

Definition at line 10091 of file efm32g890f128.h.

#define DMA_CHSWREQ_CH6SWREQ   (0x1UL << 6)

Channel 6 Software Request

Definition at line 10092 of file efm32g890f128.h.

#define DMA_CHSWREQ_CH6SWREQ_DEFAULT   (_DMA_CHSWREQ_CH6SWREQ_DEFAULT << 6)

Shifted mode DEFAULT for DMA_CHSWREQ

Definition at line 10096 of file efm32g890f128.h.

#define DMA_CHSWREQ_CH7SWREQ   (0x1UL << 7)

Channel 7 Software Request

Definition at line 10097 of file efm32g890f128.h.

#define DMA_CHSWREQ_CH7SWREQ_DEFAULT   (_DMA_CHSWREQ_CH7SWREQ_DEFAULT << 7)

Shifted mode DEFAULT for DMA_CHSWREQ

Definition at line 10101 of file efm32g890f128.h.

#define DMA_CHUSEBURSTC_CH0USEBURSTC   (0x1UL << 0)

Channel 0 Useburst Clear

Definition at line 10154 of file efm32g890f128.h.

#define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 10158 of file efm32g890f128.h.

#define DMA_CHUSEBURSTC_CH1USEBURSTC   (0x1UL << 1)

Channel 1 Useburst Clear

Definition at line 10159 of file efm32g890f128.h.

#define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 10163 of file efm32g890f128.h.

#define DMA_CHUSEBURSTC_CH2USEBURSTC   (0x1UL << 2)

Channel 2 Useburst Clear

Definition at line 10164 of file efm32g890f128.h.

#define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 10168 of file efm32g890f128.h.

#define DMA_CHUSEBURSTC_CH3USEBURSTC   (0x1UL << 3)

Channel 3 Useburst Clear

Definition at line 10169 of file efm32g890f128.h.

#define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 10173 of file efm32g890f128.h.

#define DMA_CHUSEBURSTC_CH4USEBURSTC   (0x1UL << 4)

Channel 4 Useburst Clear

Definition at line 10174 of file efm32g890f128.h.

#define DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4)

Shifted mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 10178 of file efm32g890f128.h.

#define DMA_CHUSEBURSTC_CH5USEBURSTC   (0x1UL << 5)

Channel 5 Useburst Clear

Definition at line 10179 of file efm32g890f128.h.

#define DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 10183 of file efm32g890f128.h.

#define DMA_CHUSEBURSTC_CH6USEBURSTC   (0x1UL << 6)

Channel 6 Useburst Clear

Definition at line 10184 of file efm32g890f128.h.

#define DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT << 6)

Shifted mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 10188 of file efm32g890f128.h.

#define DMA_CHUSEBURSTC_CH7USEBURSTC   (0x1UL << 7)

Channel 7 Useburst Clear

Definition at line 10189 of file efm32g890f128.h.

#define DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT << 7)

Shifted mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 10193 of file efm32g890f128.h.

#define DMA_CHUSEBURSTS_CH0USEBURSTS   (0x1UL << 0)

Channel 0 Useburst Set

Definition at line 10106 of file efm32g890f128.h.

#define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY   (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0)

Shifted mode BURSTONLY for DMA_CHUSEBURSTS

Definition at line 10114 of file efm32g890f128.h.

#define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 10112 of file efm32g890f128.h.

#define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST   (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0)

Shifted mode SINGLEANDBURST for DMA_CHUSEBURSTS

Definition at line 10113 of file efm32g890f128.h.

#define DMA_CHUSEBURSTS_CH1USEBURSTS   (0x1UL << 1)

Channel 1 Useburst Set

Definition at line 10115 of file efm32g890f128.h.

#define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 10119 of file efm32g890f128.h.

#define DMA_CHUSEBURSTS_CH2USEBURSTS   (0x1UL << 2)

Channel 2 Useburst Set

Definition at line 10120 of file efm32g890f128.h.

#define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 10124 of file efm32g890f128.h.

#define DMA_CHUSEBURSTS_CH3USEBURSTS   (0x1UL << 3)

Channel 3 Useburst Set

Definition at line 10125 of file efm32g890f128.h.

#define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 10129 of file efm32g890f128.h.

#define DMA_CHUSEBURSTS_CH4USEBURSTS   (0x1UL << 4)

Channel 4 Useburst Set

Definition at line 10130 of file efm32g890f128.h.

#define DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4)

Shifted mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 10134 of file efm32g890f128.h.

#define DMA_CHUSEBURSTS_CH5USEBURSTS   (0x1UL << 5)

Channel 5 Useburst Set

Definition at line 10135 of file efm32g890f128.h.

#define DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 10139 of file efm32g890f128.h.

#define DMA_CHUSEBURSTS_CH6USEBURSTS   (0x1UL << 6)

Channel 6 Useburst Set

Definition at line 10140 of file efm32g890f128.h.

#define DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT << 6)

Shifted mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 10144 of file efm32g890f128.h.

#define DMA_CHUSEBURSTS_CH7USEBURSTS   (0x1UL << 7)

Channel 7 Useburst Set

Definition at line 10145 of file efm32g890f128.h.

#define DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT << 7)

Shifted mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 10149 of file efm32g890f128.h.

#define DMA_CHWAITSTATUS_CH0WAITSTATUS   (0x1UL << 0)

Channel 0 Wait on Request Status

Definition at line 10018 of file efm32g890f128.h.

#define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 10022 of file efm32g890f128.h.

#define DMA_CHWAITSTATUS_CH1WAITSTATUS   (0x1UL << 1)

Channel 1 Wait on Request Status

Definition at line 10023 of file efm32g890f128.h.

#define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 10027 of file efm32g890f128.h.

#define DMA_CHWAITSTATUS_CH2WAITSTATUS   (0x1UL << 2)

Channel 2 Wait on Request Status

Definition at line 10028 of file efm32g890f128.h.

#define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 10032 of file efm32g890f128.h.

#define DMA_CHWAITSTATUS_CH3WAITSTATUS   (0x1UL << 3)

Channel 3 Wait on Request Status

Definition at line 10033 of file efm32g890f128.h.

#define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 10037 of file efm32g890f128.h.

#define DMA_CHWAITSTATUS_CH4WAITSTATUS   (0x1UL << 4)

Channel 4 Wait on Request Status

Definition at line 10038 of file efm32g890f128.h.

#define DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4)

Shifted mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 10042 of file efm32g890f128.h.

#define DMA_CHWAITSTATUS_CH5WAITSTATUS   (0x1UL << 5)

Channel 5 Wait on Request Status

Definition at line 10043 of file efm32g890f128.h.

#define DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 10047 of file efm32g890f128.h.

#define DMA_CHWAITSTATUS_CH6WAITSTATUS   (0x1UL << 6)

Channel 6 Wait on Request Status

Definition at line 10048 of file efm32g890f128.h.

#define DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT << 6)

Shifted mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 10052 of file efm32g890f128.h.

#define DMA_CHWAITSTATUS_CH7WAITSTATUS   (0x1UL << 7)

Channel 7 Wait on Request Status

Definition at line 10053 of file efm32g890f128.h.

#define DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT << 7)

Shifted mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 10057 of file efm32g890f128.h.

#define DMA_CONFIG_CHPROT   (0x1UL << 5)

Channel Protection Control

Definition at line 9993 of file efm32g890f128.h.

#define DMA_CONFIG_CHPROT_DEFAULT   (_DMA_CONFIG_CHPROT_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CONFIG

Definition at line 9997 of file efm32g890f128.h.

#define DMA_CONFIG_EN   (0x1UL << 0)

Enable DMA

Definition at line 9988 of file efm32g890f128.h.

#define DMA_CONFIG_EN_DEFAULT   (_DMA_CONFIG_EN_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CONFIG

Definition at line 9992 of file efm32g890f128.h.

#define DMA_CTRL_CYCLE_CTRL_AUTO   0x00000002UL

Auto cycle type

Definition at line 1164 of file efm32g890f128.h.

#define DMA_CTRL_CYCLE_CTRL_BASIC   0x00000001UL

Basic cycle type

Definition at line 1163 of file efm32g890f128.h.

#define DMA_CTRL_CYCLE_CTRL_INVALID   0x00000000UL

Invalid cycle type

Definition at line 1162 of file efm32g890f128.h.

#define DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER   0x000000004UL

Memory scatter gather cycle type

Definition at line 1166 of file efm32g890f128.h.

#define DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER_ALT   0x000000005UL

Memory scatter gather using alternate structure

Definition at line 1167 of file efm32g890f128.h.

#define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER   0x000000006UL

Peripheral scatter gather cycle type

Definition at line 1168 of file efm32g890f128.h.

#define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT   0x000000007UL

Peripheral scatter gather cycle type using alternate structure

Definition at line 1169 of file efm32g890f128.h.

#define DMA_CTRL_CYCLE_CTRL_PINGPONG   0x00000003UL

PingPong cycle type

Definition at line 1165 of file efm32g890f128.h.

#define DMA_CTRL_DST_INC_BYTE   0x00000000UL

Byte/8-bit increment

Definition at line 1080 of file efm32g890f128.h.

#define DMA_CTRL_DST_INC_HALFWORD   0x40000000UL

Half word/16-bit increment

Definition at line 1081 of file efm32g890f128.h.

#define DMA_CTRL_DST_INC_NONE   0xC0000000UL

No increment

Definition at line 1083 of file efm32g890f128.h.

#define DMA_CTRL_DST_INC_WORD   0x80000000UL

Word/32-bit increment

Definition at line 1082 of file efm32g890f128.h.

#define DMA_CTRL_DST_PROT_NON_PRIVILEGED   0x00000000UL

Non-privileged mode for estination

Definition at line 1117 of file efm32g890f128.h.

#define DMA_CTRL_DST_PROT_PRIVILEGED   0x00200000UL

Privileged mode for destination

Definition at line 1116 of file efm32g890f128.h.

#define DMA_CTRL_DST_SIZE_BYTE   0x00000000UL

Byte/8-bit data size

Definition at line 1090 of file efm32g890f128.h.

#define DMA_CTRL_DST_SIZE_HALFWORD   0x10000000UL

Half word/16-bit data size

Definition at line 1091 of file efm32g890f128.h.

#define DMA_CTRL_DST_SIZE_RSVD   0x30000000UL

Reserved - do not use

Definition at line 1093 of file efm32g890f128.h.

#define DMA_CTRL_DST_SIZE_WORD   0x20000000UL

Word/32-bit data size

Definition at line 1092 of file efm32g890f128.h.

#define DMA_CTRL_R_POWER_1   0x00000000UL

Arbitrate after each transfer

Definition at line 1137 of file efm32g890f128.h.

#define DMA_CTRL_R_POWER_1024   0x00028000UL

Arbitrate after every 1024 transfers

Definition at line 1147 of file efm32g890f128.h.

#define DMA_CTRL_R_POWER_128   0x0001c000UL

Arbitrate after every 128 transfers

Definition at line 1144 of file efm32g890f128.h.

#define DMA_CTRL_R_POWER_16   0x00010000UL

Arbitrate after every 16 transfers

Definition at line 1141 of file efm32g890f128.h.

#define DMA_CTRL_R_POWER_2   0x00004000UL

Arbitrate after every 2 transfers

Definition at line 1138 of file efm32g890f128.h.

#define DMA_CTRL_R_POWER_256   0x00020000UL

Arbitrate after every 256 transfers

Definition at line 1145 of file efm32g890f128.h.

#define DMA_CTRL_R_POWER_32   0x00014000UL

Arbitrate after every 32 transfers

Definition at line 1142 of file efm32g890f128.h.

#define DMA_CTRL_R_POWER_4   0x00008000UL

Arbitrate after every 4 transfers

Definition at line 1139 of file efm32g890f128.h.

#define DMA_CTRL_R_POWER_512   0x00024000UL

Arbitrate after every 512 transfers

Definition at line 1146 of file efm32g890f128.h.

#define DMA_CTRL_R_POWER_64   0x00018000UL

Arbitrate after every 64 transfers

Definition at line 1143 of file efm32g890f128.h.

#define DMA_CTRL_R_POWER_8   0x0000c000UL

Arbitrate after every 8 transfers

Definition at line 1140 of file efm32g890f128.h.

#define DMA_CTRL_SRC_INC_BYTE   0x00000000UL

Byte/8-bit increment

Definition at line 1100 of file efm32g890f128.h.

#define DMA_CTRL_SRC_INC_HALFWORD   0x04000000UL

Half word/16-bit increment

Definition at line 1101 of file efm32g890f128.h.

#define DMA_CTRL_SRC_INC_NONE   0x0C000000UL

No increment

Definition at line 1103 of file efm32g890f128.h.

#define DMA_CTRL_SRC_INC_WORD   0x08000000UL

Word/32-bit increment

Definition at line 1102 of file efm32g890f128.h.

#define DMA_CTRL_SRC_PROT_NON_PRIVILEGED   0x00000000UL

Non-privileged mode for estination

Definition at line 1121 of file efm32g890f128.h.

#define DMA_CTRL_SRC_PROT_PRIVILEGED   0x00040000UL

Privileged mode for destination

Definition at line 1120 of file efm32g890f128.h.

#define DMA_CTRL_SRC_SIZE_BYTE   0x00000000UL

Byte/8-bit data size

Definition at line 1110 of file efm32g890f128.h.

#define DMA_CTRL_SRC_SIZE_HALFWORD   0x01000000UL

Half word/16-bit data size

Definition at line 1111 of file efm32g890f128.h.

#define DMA_CTRL_SRC_SIZE_RSVD   0x03000000UL

Reserved - do not use

Definition at line 1113 of file efm32g890f128.h.

#define DMA_CTRL_SRC_SIZE_WORD   0x02000000UL

Word/32-bit data size

Definition at line 1112 of file efm32g890f128.h.

#define DMA_CTRLBASE_CTRLBASE_DEFAULT   (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CTRLBASE

Definition at line 10005 of file efm32g890f128.h.

#define DMA_ERRORC_ERRORC   (0x1UL << 0)

Bus Error Clear

Definition at line 10550 of file efm32g890f128.h.

#define DMA_ERRORC_ERRORC_DEFAULT   (_DMA_ERRORC_ERRORC_DEFAULT << 0)

Shifted mode DEFAULT for DMA_ERRORC

Definition at line 10554 of file efm32g890f128.h.

#define DMA_IEN_CH0DONE   (0x1UL << 0)

DMA Channel 0 Complete Interrupt Enable

Definition at line 10794 of file efm32g890f128.h.

#define DMA_IEN_CH0DONE_DEFAULT   (_DMA_IEN_CH0DONE_DEFAULT << 0)

Shifted mode DEFAULT for DMA_IEN

Definition at line 10798 of file efm32g890f128.h.

#define DMA_IEN_CH1DONE   (0x1UL << 1)

DMA Channel 1 Complete Interrupt Enable

Definition at line 10799 of file efm32g890f128.h.

#define DMA_IEN_CH1DONE_DEFAULT   (_DMA_IEN_CH1DONE_DEFAULT << 1)

Shifted mode DEFAULT for DMA_IEN

Definition at line 10803 of file efm32g890f128.h.

#define DMA_IEN_CH2DONE   (0x1UL << 2)

DMA Channel 2 Complete Interrupt Enable

Definition at line 10804 of file efm32g890f128.h.

#define DMA_IEN_CH2DONE_DEFAULT   (_DMA_IEN_CH2DONE_DEFAULT << 2)

Shifted mode DEFAULT for DMA_IEN

Definition at line 10808 of file efm32g890f128.h.

#define DMA_IEN_CH3DONE   (0x1UL << 3)

DMA Channel 3 Complete Interrupt Enable

Definition at line 10809 of file efm32g890f128.h.

#define DMA_IEN_CH3DONE_DEFAULT   (_DMA_IEN_CH3DONE_DEFAULT << 3)

Shifted mode DEFAULT for DMA_IEN

Definition at line 10813 of file efm32g890f128.h.

#define DMA_IEN_CH4DONE   (0x1UL << 4)

DMA Channel 4 Complete Interrupt Enable

Definition at line 10814 of file efm32g890f128.h.

#define DMA_IEN_CH4DONE_DEFAULT   (_DMA_IEN_CH4DONE_DEFAULT << 4)

Shifted mode DEFAULT for DMA_IEN

Definition at line 10818 of file efm32g890f128.h.

#define DMA_IEN_CH5DONE   (0x1UL << 5)

DMA Channel 5 Complete Interrupt Enable

Definition at line 10819 of file efm32g890f128.h.

#define DMA_IEN_CH5DONE_DEFAULT   (_DMA_IEN_CH5DONE_DEFAULT << 5)

Shifted mode DEFAULT for DMA_IEN

Definition at line 10823 of file efm32g890f128.h.

#define DMA_IEN_CH6DONE   (0x1UL << 6)

DMA Channel 6 Complete Interrupt Enable

Definition at line 10824 of file efm32g890f128.h.

#define DMA_IEN_CH6DONE_DEFAULT   (_DMA_IEN_CH6DONE_DEFAULT << 6)

Shifted mode DEFAULT for DMA_IEN

Definition at line 10828 of file efm32g890f128.h.

#define DMA_IEN_CH7DONE   (0x1UL << 7)

DMA Channel 7 Complete Interrupt Enable

Definition at line 10829 of file efm32g890f128.h.

#define DMA_IEN_CH7DONE_DEFAULT   (_DMA_IEN_CH7DONE_DEFAULT << 7)

Shifted mode DEFAULT for DMA_IEN

Definition at line 10833 of file efm32g890f128.h.

#define DMA_IEN_ERR   (0x1UL << 31)

DMA Error Interrupt Flag Enable

Definition at line 10834 of file efm32g890f128.h.

#define DMA_IEN_ERR_DEFAULT   (_DMA_IEN_ERR_DEFAULT << 31)

Shifted mode DEFAULT for DMA_IEN

Definition at line 10838 of file efm32g890f128.h.

#define DMA_IF_CH0DONE   (0x1UL << 0)

DMA Channel 1 Complete Interrupt Flag

Definition at line 10647 of file efm32g890f128.h.

#define DMA_IF_CH0DONE_DEFAULT   (_DMA_IF_CH0DONE_DEFAULT << 0)

Shifted mode DEFAULT for DMA_IF

Definition at line 10651 of file efm32g890f128.h.

#define DMA_IF_CH1DONE   (0x1UL << 1)

DMA Channel 2 Complete Interrupt Flag

Definition at line 10652 of file efm32g890f128.h.

#define DMA_IF_CH1DONE_DEFAULT   (_DMA_IF_CH1DONE_DEFAULT << 1)

Shifted mode DEFAULT for DMA_IF

Definition at line 10656 of file efm32g890f128.h.

#define DMA_IF_CH2DONE   (0x1UL << 2)

DMA Channel 3 Complete Interrupt Flag

Definition at line 10657 of file efm32g890f128.h.

#define DMA_IF_CH2DONE_DEFAULT   (_DMA_IF_CH2DONE_DEFAULT << 2)

Shifted mode DEFAULT for DMA_IF

Definition at line 10661 of file efm32g890f128.h.

#define DMA_IF_CH3DONE   (0x1UL << 3)

DMA Channel 3 Complete Interrupt Flag

Definition at line 10662 of file efm32g890f128.h.

#define DMA_IF_CH3DONE_DEFAULT   (_DMA_IF_CH3DONE_DEFAULT << 3)

Shifted mode DEFAULT for DMA_IF

Definition at line 10666 of file efm32g890f128.h.

#define DMA_IF_CH4DONE   (0x1UL << 4)

DMA Channel 4 Complete Interrupt Flag

Definition at line 10667 of file efm32g890f128.h.

#define DMA_IF_CH4DONE_DEFAULT   (_DMA_IF_CH4DONE_DEFAULT << 4)

Shifted mode DEFAULT for DMA_IF

Definition at line 10671 of file efm32g890f128.h.

#define DMA_IF_CH5DONE   (0x1UL << 5)

DMA Channel 5 Complete Interrupt Flag

Definition at line 10672 of file efm32g890f128.h.

#define DMA_IF_CH5DONE_DEFAULT   (_DMA_IF_CH5DONE_DEFAULT << 5)

Shifted mode DEFAULT for DMA_IF

Definition at line 10676 of file efm32g890f128.h.

#define DMA_IF_CH6DONE   (0x1UL << 6)

DMA Channel 6 Complete Interrupt Flag

Definition at line 10677 of file efm32g890f128.h.

#define DMA_IF_CH6DONE_DEFAULT   (_DMA_IF_CH6DONE_DEFAULT << 6)

Shifted mode DEFAULT for DMA_IF

Definition at line 10681 of file efm32g890f128.h.

#define DMA_IF_CH7DONE   (0x1UL << 7)

DMA Channel 7 Complete Interrupt Flag

Definition at line 10682 of file efm32g890f128.h.

#define DMA_IF_CH7DONE_DEFAULT   (_DMA_IF_CH7DONE_DEFAULT << 7)

Shifted mode DEFAULT for DMA_IF

Definition at line 10686 of file efm32g890f128.h.

#define DMA_IF_ERR   (0x1UL << 31)

DMA Error Interrupt Flag

Definition at line 10687 of file efm32g890f128.h.

#define DMA_IF_ERR_DEFAULT   (_DMA_IF_ERR_DEFAULT << 31)

Shifted mode DEFAULT for DMA_IF

Definition at line 10691 of file efm32g890f128.h.

#define DMA_IFC_CH0DONE   (0x1UL << 0)

DMA Channel 0 Complete Interrupt Flag Clear

Definition at line 10745 of file efm32g890f128.h.

#define DMA_IFC_CH0DONE_DEFAULT   (_DMA_IFC_CH0DONE_DEFAULT << 0)

Shifted mode DEFAULT for DMA_IFC

Definition at line 10749 of file efm32g890f128.h.

#define DMA_IFC_CH1DONE   (0x1UL << 1)

DMA Channel 1 Complete Interrupt Flag Clear

Definition at line 10750 of file efm32g890f128.h.

#define DMA_IFC_CH1DONE_DEFAULT   (_DMA_IFC_CH1DONE_DEFAULT << 1)

Shifted mode DEFAULT for DMA_IFC

Definition at line 10754 of file efm32g890f128.h.

#define DMA_IFC_CH2DONE   (0x1UL << 2)

DMA Channel 2 Complete Interrupt Flag Clear

Definition at line 10755 of file efm32g890f128.h.

#define DMA_IFC_CH2DONE_DEFAULT   (_DMA_IFC_CH2DONE_DEFAULT << 2)

Shifted mode DEFAULT for DMA_IFC

Definition at line 10759 of file efm32g890f128.h.

#define DMA_IFC_CH3DONE   (0x1UL << 3)

DMA Channel 3 Complete Interrupt Flag Clear

Definition at line 10760 of file efm32g890f128.h.

#define DMA_IFC_CH3DONE_DEFAULT   (_DMA_IFC_CH3DONE_DEFAULT << 3)

Shifted mode DEFAULT for DMA_IFC

Definition at line 10764 of file efm32g890f128.h.

#define DMA_IFC_CH4DONE   (0x1UL << 4)

DMA Channel 4 Complete Interrupt Flag Clear

Definition at line 10765 of file efm32g890f128.h.

#define DMA_IFC_CH4DONE_DEFAULT   (_DMA_IFC_CH4DONE_DEFAULT << 4)

Shifted mode DEFAULT for DMA_IFC

Definition at line 10769 of file efm32g890f128.h.

#define DMA_IFC_CH5DONE   (0x1UL << 5)

DMA Channel 5 Complete Interrupt Flag Clear

Definition at line 10770 of file efm32g890f128.h.

#define DMA_IFC_CH5DONE_DEFAULT   (_DMA_IFC_CH5DONE_DEFAULT << 5)

Shifted mode DEFAULT for DMA_IFC

Definition at line 10774 of file efm32g890f128.h.

#define DMA_IFC_CH6DONE   (0x1UL << 6)

DMA Channel 6 Complete Interrupt Flag Clear

Definition at line 10775 of file efm32g890f128.h.

#define DMA_IFC_CH6DONE_DEFAULT   (_DMA_IFC_CH6DONE_DEFAULT << 6)

Shifted mode DEFAULT for DMA_IFC

Definition at line 10779 of file efm32g890f128.h.

#define DMA_IFC_CH7DONE   (0x1UL << 7)

DMA Channel 7 Complete Interrupt Flag Clear

Definition at line 10780 of file efm32g890f128.h.

#define DMA_IFC_CH7DONE_DEFAULT   (_DMA_IFC_CH7DONE_DEFAULT << 7)

Shifted mode DEFAULT for DMA_IFC

Definition at line 10784 of file efm32g890f128.h.

#define DMA_IFC_ERR   (0x1UL << 31)

DMA Error Interrupt Flag Clear

Definition at line 10785 of file efm32g890f128.h.

#define DMA_IFC_ERR_DEFAULT   (_DMA_IFC_ERR_DEFAULT << 31)

Shifted mode DEFAULT for DMA_IFC

Definition at line 10789 of file efm32g890f128.h.

#define DMA_IFS_CH0DONE   (0x1UL << 0)

DMA Channel 0 Complete Interrupt Flag Set

Definition at line 10696 of file efm32g890f128.h.

#define DMA_IFS_CH0DONE_DEFAULT   (_DMA_IFS_CH0DONE_DEFAULT << 0)

Shifted mode DEFAULT for DMA_IFS

Definition at line 10700 of file efm32g890f128.h.

#define DMA_IFS_CH1DONE   (0x1UL << 1)

DMA Channel 1 Complete Interrupt Flag Set

Definition at line 10701 of file efm32g890f128.h.

#define DMA_IFS_CH1DONE_DEFAULT   (_DMA_IFS_CH1DONE_DEFAULT << 1)

Shifted mode DEFAULT for DMA_IFS

Definition at line 10705 of file efm32g890f128.h.

#define DMA_IFS_CH2DONE   (0x1UL << 2)

DMA Channel 2 Complete Interrupt Flag Set

Definition at line 10706 of file efm32g890f128.h.

#define DMA_IFS_CH2DONE_DEFAULT   (_DMA_IFS_CH2DONE_DEFAULT << 2)

Shifted mode DEFAULT for DMA_IFS

Definition at line 10710 of file efm32g890f128.h.

#define DMA_IFS_CH3DONE   (0x1UL << 3)

DMA Channel 3 Complete Interrupt Flag Set

Definition at line 10711 of file efm32g890f128.h.

#define DMA_IFS_CH3DONE_DEFAULT   (_DMA_IFS_CH3DONE_DEFAULT << 3)

Shifted mode DEFAULT for DMA_IFS

Definition at line 10715 of file efm32g890f128.h.

#define DMA_IFS_CH4DONE   (0x1UL << 4)

DMA Channel 4 Complete Interrupt Flag Set

Definition at line 10716 of file efm32g890f128.h.

#define DMA_IFS_CH4DONE_DEFAULT   (_DMA_IFS_CH4DONE_DEFAULT << 4)

Shifted mode DEFAULT for DMA_IFS

Definition at line 10720 of file efm32g890f128.h.

#define DMA_IFS_CH5DONE   (0x1UL << 5)

DMA Channel 5 Complete Interrupt Flag Set

Definition at line 10721 of file efm32g890f128.h.

#define DMA_IFS_CH5DONE_DEFAULT   (_DMA_IFS_CH5DONE_DEFAULT << 5)

Shifted mode DEFAULT for DMA_IFS

Definition at line 10725 of file efm32g890f128.h.

#define DMA_IFS_CH6DONE   (0x1UL << 6)

DMA Channel 6 Complete Interrupt Flag Set

Definition at line 10726 of file efm32g890f128.h.

#define DMA_IFS_CH6DONE_DEFAULT   (_DMA_IFS_CH6DONE_DEFAULT << 6)

Shifted mode DEFAULT for DMA_IFS

Definition at line 10730 of file efm32g890f128.h.

#define DMA_IFS_CH7DONE   (0x1UL << 7)

DMA Channel 7 Complete Interrupt Flag Set

Definition at line 10731 of file efm32g890f128.h.

#define DMA_IFS_CH7DONE_DEFAULT   (_DMA_IFS_CH7DONE_DEFAULT << 7)

Shifted mode DEFAULT for DMA_IFS

Definition at line 10735 of file efm32g890f128.h.

#define DMA_IFS_ERR   (0x1UL << 31)

DMA Error Interrupt Flag Set

Definition at line 10736 of file efm32g890f128.h.

#define DMA_IFS_ERR_DEFAULT   (_DMA_IFS_ERR_DEFAULT << 31)

Shifted mode DEFAULT for DMA_IFS

Definition at line 10740 of file efm32g890f128.h.

#define DMA_STATUS_CHNUM_DEFAULT   (_DMA_STATUS_CHNUM_DEFAULT << 16)

Shifted mode DEFAULT for DMA_STATUS

Definition at line 9983 of file efm32g890f128.h.

#define DMA_STATUS_EN   (0x1UL << 0)

DMA Enable Status

Definition at line 9949 of file efm32g890f128.h.

#define DMA_STATUS_EN_DEFAULT   (_DMA_STATUS_EN_DEFAULT << 0)

Shifted mode DEFAULT for DMA_STATUS

Definition at line 9953 of file efm32g890f128.h.

#define DMA_STATUS_STATE_DEFAULT   (_DMA_STATUS_STATE_DEFAULT << 4)

Shifted mode DEFAULT for DMA_STATUS

Definition at line 9968 of file efm32g890f128.h.

#define DMA_STATUS_STATE_DONE   (_DMA_STATUS_STATE_DONE << 4)

Shifted mode DONE for DMA_STATUS

Definition at line 9978 of file efm32g890f128.h.

#define DMA_STATUS_STATE_IDLE   (_DMA_STATUS_STATE_IDLE << 4)

Shifted mode IDLE for DMA_STATUS

Definition at line 9969 of file efm32g890f128.h.

#define DMA_STATUS_STATE_PERSCATTRANS   (_DMA_STATUS_STATE_PERSCATTRANS << 4)

Shifted mode PERSCATTRANS for DMA_STATUS

Definition at line 9979 of file efm32g890f128.h.

#define DMA_STATUS_STATE_RDCHCTRLDATA   (_DMA_STATUS_STATE_RDCHCTRLDATA << 4)

Shifted mode RDCHCTRLDATA for DMA_STATUS

Definition at line 9970 of file efm32g890f128.h.

#define DMA_STATUS_STATE_RDDSTENDPTR   (_DMA_STATUS_STATE_RDDSTENDPTR << 4)

Shifted mode RDDSTENDPTR for DMA_STATUS

Definition at line 9972 of file efm32g890f128.h.

#define DMA_STATUS_STATE_RDSRCDATA   (_DMA_STATUS_STATE_RDSRCDATA << 4)

Shifted mode RDSRCDATA for DMA_STATUS

Definition at line 9973 of file efm32g890f128.h.

#define DMA_STATUS_STATE_RDSRCENDPTR   (_DMA_STATUS_STATE_RDSRCENDPTR << 4)

Shifted mode RDSRCENDPTR for DMA_STATUS

Definition at line 9971 of file efm32g890f128.h.

#define DMA_STATUS_STATE_STALLED   (_DMA_STATUS_STATE_STALLED << 4)

Shifted mode STALLED for DMA_STATUS

Definition at line 9977 of file efm32g890f128.h.

#define DMA_STATUS_STATE_WAITREQCLR   (_DMA_STATUS_STATE_WAITREQCLR << 4)

Shifted mode WAITREQCLR for DMA_STATUS

Definition at line 9975 of file efm32g890f128.h.

#define DMA_STATUS_STATE_WRCHCTRLDATA   (_DMA_STATUS_STATE_WRCHCTRLDATA << 4)

Shifted mode WRCHCTRLDATA for DMA_STATUS

Definition at line 9976 of file efm32g890f128.h.

#define DMA_STATUS_STATE_WRDSTDATA   (_DMA_STATUS_STATE_WRDSTDATA << 4)

Shifted mode WRDSTDATA for DMA_STATUS

Definition at line 9974 of file efm32g890f128.h.

#define DMAREQ_ADC0_SCAN   ((8 << 16) + 1)

DMA channel select for ADC0_SCAN

Definition at line 1017 of file efm32g890f128.h.

#define DMAREQ_ADC0_SINGLE   ((8 << 16) + 0)

DMA channel select for ADC0_SINGLE

Definition at line 1016 of file efm32g890f128.h.

#define DMAREQ_AES_DATARD   ((49 << 16) + 2)

DMA channel select for AES_DATARD

Definition at line 1055 of file efm32g890f128.h.

#define DMAREQ_AES_DATAWR   ((49 << 16) + 0)

DMA channel select for AES_DATAWR

Definition at line 1053 of file efm32g890f128.h.

#define DMAREQ_AES_KEYWR   ((49 << 16) + 3)

DMA channel select for AES_KEYWR

Definition at line 1056 of file efm32g890f128.h.

#define DMAREQ_AES_XORDATAWR   ((49 << 16) + 1)

DMA channel select for AES_XORDATAWR

Definition at line 1054 of file efm32g890f128.h.

#define DMAREQ_DAC0_CH0   ((10 << 16) + 0)

DMA channel select for DAC0_CH0

Definition at line 1018 of file efm32g890f128.h.

#define DMAREQ_DAC0_CH1   ((10 << 16) + 1)

DMA channel select for DAC0_CH1

Definition at line 1019 of file efm32g890f128.h.

#define DMAREQ_I2C0_RXDATAV   ((20 << 16) + 0)

DMA channel select for I2C0_RXDATAV

Definition at line 1035 of file efm32g890f128.h.

#define DMAREQ_I2C0_TXBL   ((20 << 16) + 1)

DMA channel select for I2C0_TXBL

Definition at line 1036 of file efm32g890f128.h.

#define DMAREQ_LEUART0_RXDATAV   ((16 << 16) + 0)

DMA channel select for LEUART0_RXDATAV

Definition at line 1029 of file efm32g890f128.h.

#define DMAREQ_LEUART0_TXBL   ((16 << 16) + 1)

DMA channel select for LEUART0_TXBL

Definition at line 1030 of file efm32g890f128.h.

#define DMAREQ_LEUART0_TXEMPTY   ((16 << 16) + 2)

DMA channel select for LEUART0_TXEMPTY

Definition at line 1031 of file efm32g890f128.h.

#define DMAREQ_LEUART1_RXDATAV   ((17 << 16) + 0)

DMA channel select for LEUART1_RXDATAV

Definition at line 1032 of file efm32g890f128.h.

#define DMAREQ_LEUART1_TXBL   ((17 << 16) + 1)

DMA channel select for LEUART1_TXBL

Definition at line 1033 of file efm32g890f128.h.

#define DMAREQ_LEUART1_TXEMPTY   ((17 << 16) + 2)

DMA channel select for LEUART1_TXEMPTY

Definition at line 1034 of file efm32g890f128.h.

#define DMAREQ_MSC_WDATA   ((48 << 16) + 0)

DMA channel select for MSC_WDATA

Definition at line 1052 of file efm32g890f128.h.

#define DMAREQ_TIMER0_CC0   ((24 << 16) + 1)

DMA channel select for TIMER0_CC0

Definition at line 1038 of file efm32g890f128.h.

#define DMAREQ_TIMER0_CC1   ((24 << 16) + 2)

DMA channel select for TIMER0_CC1

Definition at line 1039 of file efm32g890f128.h.

#define DMAREQ_TIMER0_CC2   ((24 << 16) + 3)

DMA channel select for TIMER0_CC2

Definition at line 1040 of file efm32g890f128.h.

#define DMAREQ_TIMER0_UFOF   ((24 << 16) + 0)

DMA channel select for TIMER0_UFOF

Definition at line 1037 of file efm32g890f128.h.

#define DMAREQ_TIMER1_CC0   ((25 << 16) + 1)

DMA channel select for TIMER1_CC0

Definition at line 1042 of file efm32g890f128.h.

#define DMAREQ_TIMER1_CC1   ((25 << 16) + 2)

DMA channel select for TIMER1_CC1

Definition at line 1043 of file efm32g890f128.h.

#define DMAREQ_TIMER1_CC2   ((25 << 16) + 3)

DMA channel select for TIMER1_CC2

Definition at line 1044 of file efm32g890f128.h.

#define DMAREQ_TIMER1_UFOF   ((25 << 16) + 0)

DMA channel select for TIMER1_UFOF

Definition at line 1041 of file efm32g890f128.h.

#define DMAREQ_TIMER2_CC0   ((26 << 16) + 1)

DMA channel select for TIMER2_CC0

Definition at line 1046 of file efm32g890f128.h.

#define DMAREQ_TIMER2_CC1   ((26 << 16) + 2)

DMA channel select for TIMER2_CC1

Definition at line 1047 of file efm32g890f128.h.

#define DMAREQ_TIMER2_CC2   ((26 << 16) + 3)

DMA channel select for TIMER2_CC2

Definition at line 1048 of file efm32g890f128.h.

#define DMAREQ_TIMER2_UFOF   ((26 << 16) + 0)

DMA channel select for TIMER2_UFOF

Definition at line 1045 of file efm32g890f128.h.

#define DMAREQ_UART0_RXDATAV   ((44 << 16) + 0)

DMA channel select for UART0_RXDATAV

Definition at line 1049 of file efm32g890f128.h.

#define DMAREQ_UART0_TXBL   ((44 << 16) + 1)

DMA channel select for UART0_TXBL

Definition at line 1050 of file efm32g890f128.h.

#define DMAREQ_UART0_TXEMPTY   ((44 << 16) + 2)

DMA channel select for UART0_TXEMPTY

Definition at line 1051 of file efm32g890f128.h.

#define DMAREQ_USART0_RXDATAV   ((12 << 16) + 0)

DMA channel select for USART0_RXDATAV

Definition at line 1020 of file efm32g890f128.h.

#define DMAREQ_USART0_TXBL   ((12 << 16) + 1)

DMA channel select for USART0_TXBL

Definition at line 1021 of file efm32g890f128.h.

#define DMAREQ_USART0_TXEMPTY   ((12 << 16) + 2)

DMA channel select for USART0_TXEMPTY

Definition at line 1022 of file efm32g890f128.h.

#define DMAREQ_USART1_RXDATAV   ((13 << 16) + 0)

DMA channel select for USART1_RXDATAV

Definition at line 1023 of file efm32g890f128.h.

#define DMAREQ_USART1_TXBL   ((13 << 16) + 1)

DMA channel select for USART1_TXBL

Definition at line 1024 of file efm32g890f128.h.

#define DMAREQ_USART1_TXEMPTY   ((13 << 16) + 2)

DMA channel select for USART1_TXEMPTY

Definition at line 1025 of file efm32g890f128.h.

#define DMAREQ_USART2_RXDATAV   ((14 << 16) + 0)

DMA channel select for USART2_RXDATAV

Definition at line 1026 of file efm32g890f128.h.

#define DMAREQ_USART2_TXBL   ((14 << 16) + 1)

DMA channel select for USART2_TXBL

Definition at line 1027 of file efm32g890f128.h.

#define DMAREQ_USART2_TXEMPTY   ((14 << 16) + 2)

DMA channel select for USART2_TXEMPTY

Definition at line 1028 of file efm32g890f128.h.