 |
Energy Micro IEC60355 Library Example Project 1.0 (internal use only!) GCC-Version
Example project demonstrating POST and BIST library functions
|
|
Energy Micro IEC60355 Library Example Project 1.0 (internal use only!) GCC-Version
Example project demonstrating POST and BIST library functions
|
|
Data Structures | |
| struct | MSC_TypeDef |
Defines | |
| #define | _MSC_CTRL_RESETVALUE 0x00000001UL |
| #define | _MSC_CTRL_MASK 0x00000001UL |
| #define | MSC_CTRL_BUSFAULT (0x1UL << 0) |
| #define | _MSC_CTRL_BUSFAULT_SHIFT 0 |
| #define | _MSC_CTRL_BUSFAULT_MASK 0x1UL |
| #define | _MSC_CTRL_BUSFAULT_GENERATE 0x00000000UL |
| #define | _MSC_CTRL_BUSFAULT_DEFAULT 0x00000001UL |
| #define | _MSC_CTRL_BUSFAULT_IGNORE 0x00000001UL |
| #define | MSC_CTRL_BUSFAULT_GENERATE (_MSC_CTRL_BUSFAULT_GENERATE << 0) |
| #define | MSC_CTRL_BUSFAULT_DEFAULT (_MSC_CTRL_BUSFAULT_DEFAULT << 0) |
| #define | MSC_CTRL_BUSFAULT_IGNORE (_MSC_CTRL_BUSFAULT_IGNORE << 0) |
| #define | _MSC_READCTRL_RESETVALUE 0x00000001UL |
| #define | _MSC_READCTRL_MASK 0x00000007UL |
| #define | _MSC_READCTRL_MODE_SHIFT 0 |
| #define | _MSC_READCTRL_MODE_MASK 0x7UL |
| #define | _MSC_READCTRL_MODE_WS0 0x00000000UL |
| #define | _MSC_READCTRL_MODE_DEFAULT 0x00000001UL |
| #define | _MSC_READCTRL_MODE_WS1 0x00000001UL |
| #define | _MSC_READCTRL_MODE_WS0SCBTP 0x00000002UL |
| #define | _MSC_READCTRL_MODE_WS1SCBTP 0x00000003UL |
| #define | MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 0) |
| #define | MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 0) |
| #define | MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 0) |
| #define | MSC_READCTRL_MODE_WS0SCBTP (_MSC_READCTRL_MODE_WS0SCBTP << 0) |
| #define | MSC_READCTRL_MODE_WS1SCBTP (_MSC_READCTRL_MODE_WS1SCBTP << 0) |
| #define | _MSC_WRITECTRL_RESETVALUE 0x00000000UL |
| #define | _MSC_WRITECTRL_MASK 0x00000003UL |
| #define | MSC_WRITECTRL_WREN (0x1UL << 0) |
| #define | _MSC_WRITECTRL_WREN_SHIFT 0 |
| #define | _MSC_WRITECTRL_WREN_MASK 0x1UL |
| #define | _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL |
| #define | MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) |
| #define | MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) |
| #define | _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 |
| #define | _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL |
| #define | _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL |
| #define | MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) |
| #define | _MSC_WRITECMD_RESETVALUE 0x00000000UL |
| #define | _MSC_WRITECMD_MASK 0x0000001FUL |
| #define | MSC_WRITECMD_LADDRIM (0x1UL << 0) |
| #define | _MSC_WRITECMD_LADDRIM_SHIFT 0 |
| #define | _MSC_WRITECMD_LADDRIM_MASK 0x1UL |
| #define | _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL |
| #define | MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) |
| #define | MSC_WRITECMD_ERASEPAGE (0x1UL << 1) |
| #define | _MSC_WRITECMD_ERASEPAGE_SHIFT 1 |
| #define | _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL |
| #define | _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL |
| #define | MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) |
| #define | MSC_WRITECMD_WRITEEND (0x1UL << 2) |
| #define | _MSC_WRITECMD_WRITEEND_SHIFT 2 |
| #define | _MSC_WRITECMD_WRITEEND_MASK 0x4UL |
| #define | _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL |
| #define | MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) |
| #define | MSC_WRITECMD_WRITEONCE (0x1UL << 3) |
| #define | _MSC_WRITECMD_WRITEONCE_SHIFT 3 |
| #define | _MSC_WRITECMD_WRITEONCE_MASK 0x8UL |
| #define | _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL |
| #define | MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) |
| #define | MSC_WRITECMD_WRITETRIG (0x1UL << 4) |
| #define | _MSC_WRITECMD_WRITETRIG_SHIFT 4 |
| #define | _MSC_WRITECMD_WRITETRIG_MASK 0x10UL |
| #define | _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL |
| #define | MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) |
| #define | _MSC_ADDRB_RESETVALUE 0x00000000UL |
| #define | _MSC_ADDRB_MASK 0xFFFFFFFFUL |
| #define | _MSC_ADDRB_ADDRB_SHIFT 0 |
| #define | _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL |
| #define | _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL |
| #define | MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) |
| #define | _MSC_WDATA_RESETVALUE 0x00000000UL |
| #define | _MSC_WDATA_MASK 0xFFFFFFFFUL |
| #define | _MSC_WDATA_WDATA_SHIFT 0 |
| #define | _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL |
| #define | _MSC_WDATA_WDATA_DEFAULT 0x00000000UL |
| #define | MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) |
| #define | _MSC_STATUS_RESETVALUE 0x00000008UL |
| #define | _MSC_STATUS_MASK 0x0000003FUL |
| #define | MSC_STATUS_BUSY (0x1UL << 0) |
| #define | _MSC_STATUS_BUSY_SHIFT 0 |
| #define | _MSC_STATUS_BUSY_MASK 0x1UL |
| #define | _MSC_STATUS_BUSY_DEFAULT 0x00000000UL |
| #define | MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) |
| #define | MSC_STATUS_LOCKED (0x1UL << 1) |
| #define | _MSC_STATUS_LOCKED_SHIFT 1 |
| #define | _MSC_STATUS_LOCKED_MASK 0x2UL |
| #define | _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL |
| #define | MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) |
| #define | MSC_STATUS_INVADDR (0x1UL << 2) |
| #define | _MSC_STATUS_INVADDR_SHIFT 2 |
| #define | _MSC_STATUS_INVADDR_MASK 0x4UL |
| #define | _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL |
| #define | MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) |
| #define | MSC_STATUS_WDATAREADY (0x1UL << 3) |
| #define | _MSC_STATUS_WDATAREADY_SHIFT 3 |
| #define | _MSC_STATUS_WDATAREADY_MASK 0x8UL |
| #define | _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL |
| #define | MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) |
| #define | MSC_STATUS_WORDTIMEOUT (0x1UL << 4) |
| #define | _MSC_STATUS_WORDTIMEOUT_SHIFT 4 |
| #define | _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL |
| #define | _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL |
| #define | MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) |
| #define | MSC_STATUS_ERASEABORTED (0x1UL << 5) |
| #define | _MSC_STATUS_ERASEABORTED_SHIFT 5 |
| #define | _MSC_STATUS_ERASEABORTED_MASK 0x20UL |
| #define | _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL |
| #define | MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) |
| #define | _MSC_IF_RESETVALUE 0x00000000UL |
| #define | _MSC_IF_MASK 0x00000003UL |
| #define | MSC_IF_ERASE (0x1UL << 0) |
| #define | _MSC_IF_ERASE_SHIFT 0 |
| #define | _MSC_IF_ERASE_MASK 0x1UL |
| #define | _MSC_IF_ERASE_DEFAULT 0x00000000UL |
| #define | MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) |
| #define | MSC_IF_WRITE (0x1UL << 1) |
| #define | _MSC_IF_WRITE_SHIFT 1 |
| #define | _MSC_IF_WRITE_MASK 0x2UL |
| #define | _MSC_IF_WRITE_DEFAULT 0x00000000UL |
| #define | MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) |
| #define | _MSC_IFS_RESETVALUE 0x00000000UL |
| #define | _MSC_IFS_MASK 0x00000003UL |
| #define | MSC_IFS_ERASE (0x1UL << 0) |
| #define | _MSC_IFS_ERASE_SHIFT 0 |
| #define | _MSC_IFS_ERASE_MASK 0x1UL |
| #define | _MSC_IFS_ERASE_DEFAULT 0x00000000UL |
| #define | MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) |
| #define | MSC_IFS_WRITE (0x1UL << 1) |
| #define | _MSC_IFS_WRITE_SHIFT 1 |
| #define | _MSC_IFS_WRITE_MASK 0x2UL |
| #define | _MSC_IFS_WRITE_DEFAULT 0x00000000UL |
| #define | MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) |
| #define | _MSC_IFC_RESETVALUE 0x00000000UL |
| #define | _MSC_IFC_MASK 0x00000003UL |
| #define | MSC_IFC_ERASE (0x1UL << 0) |
| #define | _MSC_IFC_ERASE_SHIFT 0 |
| #define | _MSC_IFC_ERASE_MASK 0x1UL |
| #define | _MSC_IFC_ERASE_DEFAULT 0x00000000UL |
| #define | MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) |
| #define | MSC_IFC_WRITE (0x1UL << 1) |
| #define | _MSC_IFC_WRITE_SHIFT 1 |
| #define | _MSC_IFC_WRITE_MASK 0x2UL |
| #define | _MSC_IFC_WRITE_DEFAULT 0x00000000UL |
| #define | MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) |
| #define | _MSC_IEN_RESETVALUE 0x00000000UL |
| #define | _MSC_IEN_MASK 0x00000003UL |
| #define | MSC_IEN_ERASE (0x1UL << 0) |
| #define | _MSC_IEN_ERASE_SHIFT 0 |
| #define | _MSC_IEN_ERASE_MASK 0x1UL |
| #define | _MSC_IEN_ERASE_DEFAULT 0x00000000UL |
| #define | MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) |
| #define | MSC_IEN_WRITE (0x1UL << 1) |
| #define | _MSC_IEN_WRITE_SHIFT 1 |
| #define | _MSC_IEN_WRITE_MASK 0x2UL |
| #define | _MSC_IEN_WRITE_DEFAULT 0x00000000UL |
| #define | MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) |
| #define | _MSC_LOCK_RESETVALUE 0x00000000UL |
| #define | _MSC_LOCK_MASK 0x0000FFFFUL |
| #define | _MSC_LOCK_LOCKKEY_SHIFT 0 |
| #define | _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL |
| #define | _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL |
| #define | _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL |
| #define | _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL |
| #define | _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL |
| #define | _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL |
| #define | MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) |
| #define | MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) |
| #define | MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) |
| #define | MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) |
| #define | MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) |
| #define | MSC_UNLOCK_CODE 0x1B71 |
\}
| #define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL |
Mode DEFAULT for MSC_ADDRB
Definition at line 7078 of file efm32g890f128.h.
| #define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL |
Bit mask for MSC_ADDRB
Definition at line 7077 of file efm32g890f128.h.
| #define _MSC_ADDRB_ADDRB_SHIFT 0 |
Shift value for MSC_ADDRB
Definition at line 7076 of file efm32g890f128.h.
| #define _MSC_ADDRB_MASK 0xFFFFFFFFUL |
Mask for MSC_ADDRB
Definition at line 7075 of file efm32g890f128.h.
| #define _MSC_ADDRB_RESETVALUE 0x00000000UL |
Default value for MSC_ADDRB
Definition at line 7074 of file efm32g890f128.h.
| #define _MSC_CTRL_BUSFAULT_DEFAULT 0x00000001UL |
Mode DEFAULT for MSC_CTRL
Definition at line 7008 of file efm32g890f128.h.
| #define _MSC_CTRL_BUSFAULT_GENERATE 0x00000000UL |
Mode GENERATE for MSC_CTRL
Definition at line 7007 of file efm32g890f128.h.
| #define _MSC_CTRL_BUSFAULT_IGNORE 0x00000001UL |
Mode IGNORE for MSC_CTRL
Definition at line 7009 of file efm32g890f128.h.
| #define _MSC_CTRL_BUSFAULT_MASK 0x1UL |
Bit mask for MSC_BUSFAULT
Definition at line 7006 of file efm32g890f128.h.
| #define _MSC_CTRL_BUSFAULT_SHIFT 0 |
Shift value for MSC_BUSFAULT
Definition at line 7005 of file efm32g890f128.h.
| #define _MSC_CTRL_MASK 0x00000001UL |
Mask for MSC_CTRL
Definition at line 7003 of file efm32g890f128.h.
| #define _MSC_CTRL_RESETVALUE 0x00000001UL |
Default value for MSC_CTRL
Definition at line 7002 of file efm32g890f128.h.
| #define _MSC_IEN_ERASE_DEFAULT 0x00000000UL |
Mode DEFAULT for MSC_IEN
Definition at line 7171 of file efm32g890f128.h.
| #define _MSC_IEN_ERASE_MASK 0x1UL |
Bit mask for MSC_ERASE
Definition at line 7170 of file efm32g890f128.h.
| #define _MSC_IEN_ERASE_SHIFT 0 |
Shift value for MSC_ERASE
Definition at line 7169 of file efm32g890f128.h.
| #define _MSC_IEN_MASK 0x00000003UL |
Mask for MSC_IEN
Definition at line 7167 of file efm32g890f128.h.
| #define _MSC_IEN_RESETVALUE 0x00000000UL |
Default value for MSC_IEN
Definition at line 7166 of file efm32g890f128.h.
| #define _MSC_IEN_WRITE_DEFAULT 0x00000000UL |
Mode DEFAULT for MSC_IEN
Definition at line 7176 of file efm32g890f128.h.
| #define _MSC_IEN_WRITE_MASK 0x2UL |
Bit mask for MSC_WRITE
Definition at line 7175 of file efm32g890f128.h.
| #define _MSC_IEN_WRITE_SHIFT 1 |
Shift value for MSC_WRITE
Definition at line 7174 of file efm32g890f128.h.
| #define _MSC_IF_ERASE_DEFAULT 0x00000000UL |
Mode DEFAULT for MSC_IF
Definition at line 7129 of file efm32g890f128.h.
| #define _MSC_IF_ERASE_MASK 0x1UL |
Bit mask for MSC_ERASE
Definition at line 7128 of file efm32g890f128.h.
| #define _MSC_IF_ERASE_SHIFT 0 |
Shift value for MSC_ERASE
Definition at line 7127 of file efm32g890f128.h.
| #define _MSC_IF_MASK 0x00000003UL |
Mask for MSC_IF
Definition at line 7125 of file efm32g890f128.h.
| #define _MSC_IF_RESETVALUE 0x00000000UL |
Default value for MSC_IF
Definition at line 7124 of file efm32g890f128.h.
| #define _MSC_IF_WRITE_DEFAULT 0x00000000UL |
Mode DEFAULT for MSC_IF
Definition at line 7134 of file efm32g890f128.h.
| #define _MSC_IF_WRITE_MASK 0x2UL |
Bit mask for MSC_WRITE
Definition at line 7133 of file efm32g890f128.h.
| #define _MSC_IF_WRITE_SHIFT 1 |
Shift value for MSC_WRITE
Definition at line 7132 of file efm32g890f128.h.
| #define _MSC_IFC_ERASE_DEFAULT 0x00000000UL |
Mode DEFAULT for MSC_IFC
Definition at line 7157 of file efm32g890f128.h.
| #define _MSC_IFC_ERASE_MASK 0x1UL |
Bit mask for MSC_ERASE
Definition at line 7156 of file efm32g890f128.h.
| #define _MSC_IFC_ERASE_SHIFT 0 |
Shift value for MSC_ERASE
Definition at line 7155 of file efm32g890f128.h.
| #define _MSC_IFC_MASK 0x00000003UL |
Mask for MSC_IFC
Definition at line 7153 of file efm32g890f128.h.
| #define _MSC_IFC_RESETVALUE 0x00000000UL |
Default value for MSC_IFC
Definition at line 7152 of file efm32g890f128.h.
| #define _MSC_IFC_WRITE_DEFAULT 0x00000000UL |
Mode DEFAULT for MSC_IFC
Definition at line 7162 of file efm32g890f128.h.
| #define _MSC_IFC_WRITE_MASK 0x2UL |
Bit mask for MSC_WRITE
Definition at line 7161 of file efm32g890f128.h.
| #define _MSC_IFC_WRITE_SHIFT 1 |
Shift value for MSC_WRITE
Definition at line 7160 of file efm32g890f128.h.
| #define _MSC_IFS_ERASE_DEFAULT 0x00000000UL |
Mode DEFAULT for MSC_IFS
Definition at line 7143 of file efm32g890f128.h.
| #define _MSC_IFS_ERASE_MASK 0x1UL |
Bit mask for MSC_ERASE
Definition at line 7142 of file efm32g890f128.h.
| #define _MSC_IFS_ERASE_SHIFT 0 |
Shift value for MSC_ERASE
Definition at line 7141 of file efm32g890f128.h.
| #define _MSC_IFS_MASK 0x00000003UL |
Mask for MSC_IFS
Definition at line 7139 of file efm32g890f128.h.
| #define _MSC_IFS_RESETVALUE 0x00000000UL |
Default value for MSC_IFS
Definition at line 7138 of file efm32g890f128.h.
| #define _MSC_IFS_WRITE_DEFAULT 0x00000000UL |
Mode DEFAULT for MSC_IFS
Definition at line 7148 of file efm32g890f128.h.
| #define _MSC_IFS_WRITE_MASK 0x2UL |
Bit mask for MSC_WRITE
Definition at line 7147 of file efm32g890f128.h.
| #define _MSC_IFS_WRITE_SHIFT 1 |
Shift value for MSC_WRITE
Definition at line 7146 of file efm32g890f128.h.
| #define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL |
Mode DEFAULT for MSC_LOCK
Definition at line 7184 of file efm32g890f128.h.
| #define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL |
Mode LOCK for MSC_LOCK
Definition at line 7185 of file efm32g890f128.h.
| #define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL |
Mode LOCKED for MSC_LOCK
Definition at line 7187 of file efm32g890f128.h.
| #define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL |
Bit mask for MSC_LOCKKEY
Definition at line 7183 of file efm32g890f128.h.
| #define _MSC_LOCK_LOCKKEY_SHIFT 0 |
Shift value for MSC_LOCKKEY
Definition at line 7182 of file efm32g890f128.h.
| #define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL |
Mode UNLOCK for MSC_LOCK
Definition at line 7188 of file efm32g890f128.h.
| #define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL |
Mode UNLOCKED for MSC_LOCK
Definition at line 7186 of file efm32g890f128.h.
| #define _MSC_LOCK_MASK 0x0000FFFFUL |
Mask for MSC_LOCK
Definition at line 7181 of file efm32g890f128.h.
| #define _MSC_LOCK_RESETVALUE 0x00000000UL |
Default value for MSC_LOCK
Definition at line 7180 of file efm32g890f128.h.
| #define _MSC_READCTRL_MASK 0x00000007UL |
Mask for MSC_READCTRL
Definition at line 7016 of file efm32g890f128.h.
| #define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL |
Mode DEFAULT for MSC_READCTRL
Definition at line 7020 of file efm32g890f128.h.
| #define _MSC_READCTRL_MODE_MASK 0x7UL |
Bit mask for MSC_MODE
Definition at line 7018 of file efm32g890f128.h.
| #define _MSC_READCTRL_MODE_SHIFT 0 |
Shift value for MSC_MODE
Definition at line 7017 of file efm32g890f128.h.
| #define _MSC_READCTRL_MODE_WS0 0x00000000UL |
Mode WS0 for MSC_READCTRL
Definition at line 7019 of file efm32g890f128.h.
| #define _MSC_READCTRL_MODE_WS0SCBTP 0x00000002UL |
Mode WS0SCBTP for MSC_READCTRL
Definition at line 7022 of file efm32g890f128.h.
| #define _MSC_READCTRL_MODE_WS1 0x00000001UL |
Mode WS1 for MSC_READCTRL
Definition at line 7021 of file efm32g890f128.h.
| #define _MSC_READCTRL_MODE_WS1SCBTP 0x00000003UL |
Mode WS1SCBTP for MSC_READCTRL
Definition at line 7023 of file efm32g890f128.h.
| #define _MSC_READCTRL_RESETVALUE 0x00000001UL |
Default value for MSC_READCTRL
Definition at line 7015 of file efm32g890f128.h.
| #define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL |
Mode DEFAULT for MSC_STATUS
Definition at line 7095 of file efm32g890f128.h.
| #define _MSC_STATUS_BUSY_MASK 0x1UL |
Bit mask for MSC_BUSY
Definition at line 7094 of file efm32g890f128.h.
| #define _MSC_STATUS_BUSY_SHIFT 0 |
Shift value for MSC_BUSY
Definition at line 7093 of file efm32g890f128.h.
| #define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL |
Mode DEFAULT for MSC_STATUS
Definition at line 7120 of file efm32g890f128.h.
| #define _MSC_STATUS_ERASEABORTED_MASK 0x20UL |
Bit mask for MSC_ERASEABORTED
Definition at line 7119 of file efm32g890f128.h.
| #define _MSC_STATUS_ERASEABORTED_SHIFT 5 |
Shift value for MSC_ERASEABORTED
Definition at line 7118 of file efm32g890f128.h.
| #define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL |
Mode DEFAULT for MSC_STATUS
Definition at line 7105 of file efm32g890f128.h.
| #define _MSC_STATUS_INVADDR_MASK 0x4UL |
Bit mask for MSC_INVADDR
Definition at line 7104 of file efm32g890f128.h.
| #define _MSC_STATUS_INVADDR_SHIFT 2 |
Shift value for MSC_INVADDR
Definition at line 7103 of file efm32g890f128.h.
| #define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL |
Mode DEFAULT for MSC_STATUS
Definition at line 7100 of file efm32g890f128.h.
| #define _MSC_STATUS_LOCKED_MASK 0x2UL |
Bit mask for MSC_LOCKED
Definition at line 7099 of file efm32g890f128.h.
| #define _MSC_STATUS_LOCKED_SHIFT 1 |
Shift value for MSC_LOCKED
Definition at line 7098 of file efm32g890f128.h.
| #define _MSC_STATUS_MASK 0x0000003FUL |
Mask for MSC_STATUS
Definition at line 7091 of file efm32g890f128.h.
| #define _MSC_STATUS_RESETVALUE 0x00000008UL |
Default value for MSC_STATUS
Definition at line 7090 of file efm32g890f128.h.
| #define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL |
Mode DEFAULT for MSC_STATUS
Definition at line 7110 of file efm32g890f128.h.
| #define _MSC_STATUS_WDATAREADY_MASK 0x8UL |
Bit mask for MSC_WDATAREADY
Definition at line 7109 of file efm32g890f128.h.
| #define _MSC_STATUS_WDATAREADY_SHIFT 3 |
Shift value for MSC_WDATAREADY
Definition at line 7108 of file efm32g890f128.h.
| #define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL |
Mode DEFAULT for MSC_STATUS
Definition at line 7115 of file efm32g890f128.h.
| #define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL |
Bit mask for MSC_WORDTIMEOUT
Definition at line 7114 of file efm32g890f128.h.
| #define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 |
Shift value for MSC_WORDTIMEOUT
Definition at line 7113 of file efm32g890f128.h.
| #define _MSC_WDATA_MASK 0xFFFFFFFFUL |
Mask for MSC_WDATA
Definition at line 7083 of file efm32g890f128.h.
| #define _MSC_WDATA_RESETVALUE 0x00000000UL |
Default value for MSC_WDATA
Definition at line 7082 of file efm32g890f128.h.
| #define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL |
Mode DEFAULT for MSC_WDATA
Definition at line 7086 of file efm32g890f128.h.
| #define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL |
Bit mask for MSC_WDATA
Definition at line 7085 of file efm32g890f128.h.
| #define _MSC_WDATA_WDATA_SHIFT 0 |
Shift value for MSC_WDATA
Definition at line 7084 of file efm32g890f128.h.
| #define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL |
Mode DEFAULT for MSC_WRITECMD
Definition at line 7055 of file efm32g890f128.h.
| #define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL |
Bit mask for MSC_ERASEPAGE
Definition at line 7054 of file efm32g890f128.h.
| #define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 |
Shift value for MSC_ERASEPAGE
Definition at line 7053 of file efm32g890f128.h.
| #define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL |
Mode DEFAULT for MSC_WRITECMD
Definition at line 7050 of file efm32g890f128.h.
| #define _MSC_WRITECMD_LADDRIM_MASK 0x1UL |
Bit mask for MSC_LADDRIM
Definition at line 7049 of file efm32g890f128.h.
| #define _MSC_WRITECMD_LADDRIM_SHIFT 0 |
Shift value for MSC_LADDRIM
Definition at line 7048 of file efm32g890f128.h.
| #define _MSC_WRITECMD_MASK 0x0000001FUL |
Mask for MSC_WRITECMD
Definition at line 7046 of file efm32g890f128.h.
| #define _MSC_WRITECMD_RESETVALUE 0x00000000UL |
Default value for MSC_WRITECMD
Definition at line 7045 of file efm32g890f128.h.
| #define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL |
Mode DEFAULT for MSC_WRITECMD
Definition at line 7060 of file efm32g890f128.h.
| #define _MSC_WRITECMD_WRITEEND_MASK 0x4UL |
Bit mask for MSC_WRITEEND
Definition at line 7059 of file efm32g890f128.h.
| #define _MSC_WRITECMD_WRITEEND_SHIFT 2 |
Shift value for MSC_WRITEEND
Definition at line 7058 of file efm32g890f128.h.
| #define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL |
Mode DEFAULT for MSC_WRITECMD
Definition at line 7065 of file efm32g890f128.h.
| #define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL |
Bit mask for MSC_WRITEONCE
Definition at line 7064 of file efm32g890f128.h.
| #define _MSC_WRITECMD_WRITEONCE_SHIFT 3 |
Shift value for MSC_WRITEONCE
Definition at line 7063 of file efm32g890f128.h.
| #define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL |
Mode DEFAULT for MSC_WRITECMD
Definition at line 7070 of file efm32g890f128.h.
| #define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL |
Bit mask for MSC_WRITETRIG
Definition at line 7069 of file efm32g890f128.h.
| #define _MSC_WRITECMD_WRITETRIG_SHIFT 4 |
Shift value for MSC_WRITETRIG
Definition at line 7068 of file efm32g890f128.h.
| #define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL |
Mode DEFAULT for MSC_WRITECTRL
Definition at line 7041 of file efm32g890f128.h.
| #define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL |
Bit mask for MSC_IRQERASEABORT
Definition at line 7040 of file efm32g890f128.h.
| #define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 |
Shift value for MSC_IRQERASEABORT
Definition at line 7039 of file efm32g890f128.h.
| #define _MSC_WRITECTRL_MASK 0x00000003UL |
Mask for MSC_WRITECTRL
Definition at line 7032 of file efm32g890f128.h.
| #define _MSC_WRITECTRL_RESETVALUE 0x00000000UL |
Default value for MSC_WRITECTRL
Definition at line 7031 of file efm32g890f128.h.
| #define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL |
Mode DEFAULT for MSC_WRITECTRL
Definition at line 7036 of file efm32g890f128.h.
| #define _MSC_WRITECTRL_WREN_MASK 0x1UL |
Bit mask for MSC_WREN
Definition at line 7035 of file efm32g890f128.h.
| #define _MSC_WRITECTRL_WREN_SHIFT 0 |
Shift value for MSC_WREN
Definition at line 7034 of file efm32g890f128.h.
| #define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) |
Shifted mode DEFAULT for MSC_ADDRB
Definition at line 7079 of file efm32g890f128.h.
| #define MSC_CTRL_BUSFAULT (0x1UL << 0) |
Bus Fault Response Enable
Definition at line 7004 of file efm32g890f128.h.
| #define MSC_CTRL_BUSFAULT_DEFAULT (_MSC_CTRL_BUSFAULT_DEFAULT << 0) |
Shifted mode DEFAULT for MSC_CTRL
Definition at line 7011 of file efm32g890f128.h.
| #define MSC_CTRL_BUSFAULT_GENERATE (_MSC_CTRL_BUSFAULT_GENERATE << 0) |
Shifted mode GENERATE for MSC_CTRL
Definition at line 7010 of file efm32g890f128.h.
| #define MSC_CTRL_BUSFAULT_IGNORE (_MSC_CTRL_BUSFAULT_IGNORE << 0) |
Shifted mode IGNORE for MSC_CTRL
Definition at line 7012 of file efm32g890f128.h.
| #define MSC_IEN_ERASE (0x1UL << 0) |
Erase Done Interrupt Enable
Definition at line 7168 of file efm32g890f128.h.
| #define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) |
Shifted mode DEFAULT for MSC_IEN
Definition at line 7172 of file efm32g890f128.h.
| #define MSC_IEN_WRITE (0x1UL << 1) |
Write Done Interrupt Enable
Definition at line 7173 of file efm32g890f128.h.
| #define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) |
Shifted mode DEFAULT for MSC_IEN
Definition at line 7177 of file efm32g890f128.h.
| #define MSC_IF_ERASE (0x1UL << 0) |
Erase Done Interrupt Read Flag
Definition at line 7126 of file efm32g890f128.h.
| #define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) |
Shifted mode DEFAULT for MSC_IF
Definition at line 7130 of file efm32g890f128.h.
| #define MSC_IF_WRITE (0x1UL << 1) |
Write Done Interrupt Read Flag
Definition at line 7131 of file efm32g890f128.h.
| #define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) |
Shifted mode DEFAULT for MSC_IF
Definition at line 7135 of file efm32g890f128.h.
| #define MSC_IFC_ERASE (0x1UL << 0) |
Erase Done Interrupt Clear
Definition at line 7154 of file efm32g890f128.h.
| #define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) |
Shifted mode DEFAULT for MSC_IFC
Definition at line 7158 of file efm32g890f128.h.
| #define MSC_IFC_WRITE (0x1UL << 1) |
Write Done Interrupt Clear
Definition at line 7159 of file efm32g890f128.h.
| #define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) |
Shifted mode DEFAULT for MSC_IFC
Definition at line 7163 of file efm32g890f128.h.
| #define MSC_IFS_ERASE (0x1UL << 0) |
Erase Done Interrupt Set
Definition at line 7140 of file efm32g890f128.h.
| #define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) |
Shifted mode DEFAULT for MSC_IFS
Definition at line 7144 of file efm32g890f128.h.
| #define MSC_IFS_WRITE (0x1UL << 1) |
Write Done Interrupt Set
Definition at line 7145 of file efm32g890f128.h.
| #define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) |
Shifted mode DEFAULT for MSC_IFS
Definition at line 7149 of file efm32g890f128.h.
| #define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) |
Shifted mode DEFAULT for MSC_LOCK
Definition at line 7189 of file efm32g890f128.h.
| #define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) |
Shifted mode LOCK for MSC_LOCK
Definition at line 7190 of file efm32g890f128.h.
| #define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) |
Shifted mode LOCKED for MSC_LOCK
Definition at line 7192 of file efm32g890f128.h.
| #define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) |
Shifted mode UNLOCK for MSC_LOCK
Definition at line 7193 of file efm32g890f128.h.
| #define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) |
Shifted mode UNLOCKED for MSC_LOCK
Definition at line 7191 of file efm32g890f128.h.
| #define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 0) |
Shifted mode DEFAULT for MSC_READCTRL
Definition at line 7025 of file efm32g890f128.h.
| #define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 0) |
Shifted mode WS0 for MSC_READCTRL
Definition at line 7024 of file efm32g890f128.h.
| #define MSC_READCTRL_MODE_WS0SCBTP (_MSC_READCTRL_MODE_WS0SCBTP << 0) |
Shifted mode WS0SCBTP for MSC_READCTRL
Definition at line 7027 of file efm32g890f128.h.
| #define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 0) |
Shifted mode WS1 for MSC_READCTRL
Definition at line 7026 of file efm32g890f128.h.
| #define MSC_READCTRL_MODE_WS1SCBTP (_MSC_READCTRL_MODE_WS1SCBTP << 0) |
Shifted mode WS1SCBTP for MSC_READCTRL
Definition at line 7028 of file efm32g890f128.h.
| #define MSC_STATUS_BUSY (0x1UL << 0) |
Erase/Write Busy
Definition at line 7092 of file efm32g890f128.h.
| #define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) |
Shifted mode DEFAULT for MSC_STATUS
Definition at line 7096 of file efm32g890f128.h.
| #define MSC_STATUS_ERASEABORTED (0x1UL << 5) |
The Current Flash Erase Operation Aborted
Definition at line 7117 of file efm32g890f128.h.
| #define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) |
Shifted mode DEFAULT for MSC_STATUS
Definition at line 7121 of file efm32g890f128.h.
| #define MSC_STATUS_INVADDR (0x1UL << 2) |
Invalid Write Address or Erase Page
Definition at line 7102 of file efm32g890f128.h.
| #define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) |
Shifted mode DEFAULT for MSC_STATUS
Definition at line 7106 of file efm32g890f128.h.
| #define MSC_STATUS_LOCKED (0x1UL << 1) |
Access Locked
Definition at line 7097 of file efm32g890f128.h.
| #define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) |
Shifted mode DEFAULT for MSC_STATUS
Definition at line 7101 of file efm32g890f128.h.
| #define MSC_STATUS_WDATAREADY (0x1UL << 3) |
WDATA Write Ready
Definition at line 7107 of file efm32g890f128.h.
| #define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) |
Shifted mode DEFAULT for MSC_STATUS
Definition at line 7111 of file efm32g890f128.h.
| #define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) |
Flash Write Word Timeout
Definition at line 7112 of file efm32g890f128.h.
| #define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) |
Shifted mode DEFAULT for MSC_STATUS
Definition at line 7116 of file efm32g890f128.h.
| #define MSC_UNLOCK_CODE 0x1B71 |
MSC unlock code
Definition at line 11864 of file efm32g890f128.h.
| #define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) |
Shifted mode DEFAULT for MSC_WDATA
Definition at line 7087 of file efm32g890f128.h.
| #define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) |
Erase Page
Definition at line 7052 of file efm32g890f128.h.
| #define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) |
Shifted mode DEFAULT for MSC_WRITECMD
Definition at line 7056 of file efm32g890f128.h.
| #define MSC_WRITECMD_LADDRIM (0x1UL << 0) |
Load MSC_ADDRB into ADDR
Definition at line 7047 of file efm32g890f128.h.
| #define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) |
Shifted mode DEFAULT for MSC_WRITECMD
Definition at line 7051 of file efm32g890f128.h.
| #define MSC_WRITECMD_WRITEEND (0x1UL << 2) |
End Write Mode
Definition at line 7057 of file efm32g890f128.h.
| #define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) |
Shifted mode DEFAULT for MSC_WRITECMD
Definition at line 7061 of file efm32g890f128.h.
| #define MSC_WRITECMD_WRITEONCE (0x1UL << 3) |
Word Write-Once Trigger
Definition at line 7062 of file efm32g890f128.h.
| #define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) |
Shifted mode DEFAULT for MSC_WRITECMD
Definition at line 7066 of file efm32g890f128.h.
| #define MSC_WRITECMD_WRITETRIG (0x1UL << 4) |
Word Write Sequence Trigger
Definition at line 7067 of file efm32g890f128.h.
| #define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) |
Shifted mode DEFAULT for MSC_WRITECMD
Definition at line 7071 of file efm32g890f128.h.
| #define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) |
Abort Page Erase on Interrupt
Definition at line 7038 of file efm32g890f128.h.
| #define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) |
Shifted mode DEFAULT for MSC_WRITECTRL
Definition at line 7042 of file efm32g890f128.h.
| #define MSC_WRITECTRL_WREN (0x1UL << 0) |
Enable Write/Erase Controller
Definition at line 7033 of file efm32g890f128.h.
| #define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) |
Shifted mode DEFAULT for MSC_WRITECTRL
Definition at line 7037 of file efm32g890f128.h.
1.7.3