 |
Energy Micro IEC60355 Library Example Project 1.0 (internal use only!) GCC-Version
Example project demonstrating POST and BIST library functions
|
|
Energy Micro IEC60355 Library Example Project 1.0 (internal use only!) GCC-Version
Example project demonstrating POST and BIST library functions
|
|
Data Structures | |
| struct | RTC_TypeDef |
Defines | |
| #define | _RTC_CTRL_RESETVALUE 0x00000000UL |
| #define | _RTC_CTRL_MASK 0x00000007UL |
| #define | RTC_CTRL_EN (0x1UL << 0) |
| #define | _RTC_CTRL_EN_SHIFT 0 |
| #define | _RTC_CTRL_EN_MASK 0x1UL |
| #define | _RTC_CTRL_EN_DEFAULT 0x00000000UL |
| #define | RTC_CTRL_EN_DEFAULT (_RTC_CTRL_EN_DEFAULT << 0) |
| #define | RTC_CTRL_DEBUGRUN (0x1UL << 1) |
| #define | _RTC_CTRL_DEBUGRUN_SHIFT 1 |
| #define | _RTC_CTRL_DEBUGRUN_MASK 0x2UL |
| #define | _RTC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL |
| #define | RTC_CTRL_DEBUGRUN_DEFAULT (_RTC_CTRL_DEBUGRUN_DEFAULT << 1) |
| #define | RTC_CTRL_COMP0TOP (0x1UL << 2) |
| #define | _RTC_CTRL_COMP0TOP_SHIFT 2 |
| #define | _RTC_CTRL_COMP0TOP_MASK 0x4UL |
| #define | _RTC_CTRL_COMP0TOP_DEFAULT 0x00000000UL |
| #define | _RTC_CTRL_COMP0TOP_DISABLE 0x00000000UL |
| #define | _RTC_CTRL_COMP0TOP_ENABLE 0x00000001UL |
| #define | RTC_CTRL_COMP0TOP_DEFAULT (_RTC_CTRL_COMP0TOP_DEFAULT << 2) |
| #define | RTC_CTRL_COMP0TOP_DISABLE (_RTC_CTRL_COMP0TOP_DISABLE << 2) |
| #define | RTC_CTRL_COMP0TOP_ENABLE (_RTC_CTRL_COMP0TOP_ENABLE << 2) |
| #define | _RTC_CNT_RESETVALUE 0x00000000UL |
| #define | _RTC_CNT_MASK 0x00FFFFFFUL |
| #define | _RTC_CNT_CNT_SHIFT 0 |
| #define | _RTC_CNT_CNT_MASK 0xFFFFFFUL |
| #define | _RTC_CNT_CNT_DEFAULT 0x00000000UL |
| #define | RTC_CNT_CNT_DEFAULT (_RTC_CNT_CNT_DEFAULT << 0) |
| #define | _RTC_COMP0_RESETVALUE 0x00000000UL |
| #define | _RTC_COMP0_MASK 0x00FFFFFFUL |
| #define | _RTC_COMP0_COMP0_SHIFT 0 |
| #define | _RTC_COMP0_COMP0_MASK 0xFFFFFFUL |
| #define | _RTC_COMP0_COMP0_DEFAULT 0x00000000UL |
| #define | RTC_COMP0_COMP0_DEFAULT (_RTC_COMP0_COMP0_DEFAULT << 0) |
| #define | _RTC_COMP1_RESETVALUE 0x00000000UL |
| #define | _RTC_COMP1_MASK 0x00FFFFFFUL |
| #define | _RTC_COMP1_COMP1_SHIFT 0 |
| #define | _RTC_COMP1_COMP1_MASK 0xFFFFFFUL |
| #define | _RTC_COMP1_COMP1_DEFAULT 0x00000000UL |
| #define | RTC_COMP1_COMP1_DEFAULT (_RTC_COMP1_COMP1_DEFAULT << 0) |
| #define | _RTC_IF_RESETVALUE 0x00000000UL |
| #define | _RTC_IF_MASK 0x00000007UL |
| #define | RTC_IF_OF (0x1UL << 0) |
| #define | _RTC_IF_OF_SHIFT 0 |
| #define | _RTC_IF_OF_MASK 0x1UL |
| #define | _RTC_IF_OF_DEFAULT 0x00000000UL |
| #define | RTC_IF_OF_DEFAULT (_RTC_IF_OF_DEFAULT << 0) |
| #define | RTC_IF_COMP0 (0x1UL << 1) |
| #define | _RTC_IF_COMP0_SHIFT 1 |
| #define | _RTC_IF_COMP0_MASK 0x2UL |
| #define | _RTC_IF_COMP0_DEFAULT 0x00000000UL |
| #define | RTC_IF_COMP0_DEFAULT (_RTC_IF_COMP0_DEFAULT << 1) |
| #define | RTC_IF_COMP1 (0x1UL << 2) |
| #define | _RTC_IF_COMP1_SHIFT 2 |
| #define | _RTC_IF_COMP1_MASK 0x4UL |
| #define | _RTC_IF_COMP1_DEFAULT 0x00000000UL |
| #define | RTC_IF_COMP1_DEFAULT (_RTC_IF_COMP1_DEFAULT << 2) |
| #define | _RTC_IFS_RESETVALUE 0x00000000UL |
| #define | _RTC_IFS_MASK 0x00000007UL |
| #define | RTC_IFS_OF (0x1UL << 0) |
| #define | _RTC_IFS_OF_SHIFT 0 |
| #define | _RTC_IFS_OF_MASK 0x1UL |
| #define | _RTC_IFS_OF_DEFAULT 0x00000000UL |
| #define | RTC_IFS_OF_DEFAULT (_RTC_IFS_OF_DEFAULT << 0) |
| #define | RTC_IFS_COMP0 (0x1UL << 1) |
| #define | _RTC_IFS_COMP0_SHIFT 1 |
| #define | _RTC_IFS_COMP0_MASK 0x2UL |
| #define | _RTC_IFS_COMP0_DEFAULT 0x00000000UL |
| #define | RTC_IFS_COMP0_DEFAULT (_RTC_IFS_COMP0_DEFAULT << 1) |
| #define | RTC_IFS_COMP1 (0x1UL << 2) |
| #define | _RTC_IFS_COMP1_SHIFT 2 |
| #define | _RTC_IFS_COMP1_MASK 0x4UL |
| #define | _RTC_IFS_COMP1_DEFAULT 0x00000000UL |
| #define | RTC_IFS_COMP1_DEFAULT (_RTC_IFS_COMP1_DEFAULT << 2) |
| #define | _RTC_IFC_RESETVALUE 0x00000000UL |
| #define | _RTC_IFC_MASK 0x00000007UL |
| #define | RTC_IFC_OF (0x1UL << 0) |
| #define | _RTC_IFC_OF_SHIFT 0 |
| #define | _RTC_IFC_OF_MASK 0x1UL |
| #define | _RTC_IFC_OF_DEFAULT 0x00000000UL |
| #define | RTC_IFC_OF_DEFAULT (_RTC_IFC_OF_DEFAULT << 0) |
| #define | RTC_IFC_COMP0 (0x1UL << 1) |
| #define | _RTC_IFC_COMP0_SHIFT 1 |
| #define | _RTC_IFC_COMP0_MASK 0x2UL |
| #define | _RTC_IFC_COMP0_DEFAULT 0x00000000UL |
| #define | RTC_IFC_COMP0_DEFAULT (_RTC_IFC_COMP0_DEFAULT << 1) |
| #define | RTC_IFC_COMP1 (0x1UL << 2) |
| #define | _RTC_IFC_COMP1_SHIFT 2 |
| #define | _RTC_IFC_COMP1_MASK 0x4UL |
| #define | _RTC_IFC_COMP1_DEFAULT 0x00000000UL |
| #define | RTC_IFC_COMP1_DEFAULT (_RTC_IFC_COMP1_DEFAULT << 2) |
| #define | _RTC_IEN_RESETVALUE 0x00000000UL |
| #define | _RTC_IEN_MASK 0x00000007UL |
| #define | RTC_IEN_OF (0x1UL << 0) |
| #define | _RTC_IEN_OF_SHIFT 0 |
| #define | _RTC_IEN_OF_MASK 0x1UL |
| #define | _RTC_IEN_OF_DEFAULT 0x00000000UL |
| #define | RTC_IEN_OF_DEFAULT (_RTC_IEN_OF_DEFAULT << 0) |
| #define | RTC_IEN_COMP0 (0x1UL << 1) |
| #define | _RTC_IEN_COMP0_SHIFT 1 |
| #define | _RTC_IEN_COMP0_MASK 0x2UL |
| #define | _RTC_IEN_COMP0_DEFAULT 0x00000000UL |
| #define | RTC_IEN_COMP0_DEFAULT (_RTC_IEN_COMP0_DEFAULT << 1) |
| #define | RTC_IEN_COMP1 (0x1UL << 2) |
| #define | _RTC_IEN_COMP1_SHIFT 2 |
| #define | _RTC_IEN_COMP1_MASK 0x4UL |
| #define | _RTC_IEN_COMP1_DEFAULT 0x00000000UL |
| #define | RTC_IEN_COMP1_DEFAULT (_RTC_IEN_COMP1_DEFAULT << 2) |
| #define | _RTC_FREEZE_RESETVALUE 0x00000000UL |
| #define | _RTC_FREEZE_MASK 0x00000001UL |
| #define | RTC_FREEZE_REGFREEZE (0x1UL << 0) |
| #define | _RTC_FREEZE_REGFREEZE_SHIFT 0 |
| #define | _RTC_FREEZE_REGFREEZE_MASK 0x1UL |
| #define | _RTC_FREEZE_REGFREEZE_DEFAULT 0x00000000UL |
| #define | _RTC_FREEZE_REGFREEZE_UPDATE 0x00000000UL |
| #define | _RTC_FREEZE_REGFREEZE_FREEZE 0x00000001UL |
| #define | RTC_FREEZE_REGFREEZE_DEFAULT (_RTC_FREEZE_REGFREEZE_DEFAULT << 0) |
| #define | RTC_FREEZE_REGFREEZE_UPDATE (_RTC_FREEZE_REGFREEZE_UPDATE << 0) |
| #define | RTC_FREEZE_REGFREEZE_FREEZE (_RTC_FREEZE_REGFREEZE_FREEZE << 0) |
| #define | _RTC_SYNCBUSY_RESETVALUE 0x00000000UL |
| #define | _RTC_SYNCBUSY_MASK 0x00000007UL |
| #define | RTC_SYNCBUSY_CTRL (0x1UL << 0) |
| #define | _RTC_SYNCBUSY_CTRL_SHIFT 0 |
| #define | _RTC_SYNCBUSY_CTRL_MASK 0x1UL |
| #define | _RTC_SYNCBUSY_CTRL_DEFAULT 0x00000000UL |
| #define | RTC_SYNCBUSY_CTRL_DEFAULT (_RTC_SYNCBUSY_CTRL_DEFAULT << 0) |
| #define | RTC_SYNCBUSY_COMP0 (0x1UL << 1) |
| #define | _RTC_SYNCBUSY_COMP0_SHIFT 1 |
| #define | _RTC_SYNCBUSY_COMP0_MASK 0x2UL |
| #define | _RTC_SYNCBUSY_COMP0_DEFAULT 0x00000000UL |
| #define | RTC_SYNCBUSY_COMP0_DEFAULT (_RTC_SYNCBUSY_COMP0_DEFAULT << 1) |
| #define | RTC_SYNCBUSY_COMP1 (0x1UL << 2) |
| #define | _RTC_SYNCBUSY_COMP1_SHIFT 2 |
| #define | _RTC_SYNCBUSY_COMP1_MASK 0x4UL |
| #define | _RTC_SYNCBUSY_COMP1_DEFAULT 0x00000000UL |
| #define | RTC_SYNCBUSY_COMP1_DEFAULT (_RTC_SYNCBUSY_COMP1_DEFAULT << 2) |
| #define _RTC_CNT_CNT_DEFAULT 0x00000000UL |
Mode DEFAULT for RTC_CNT
Definition at line 11539 of file efm32g890f128.h.
| #define _RTC_CNT_CNT_MASK 0xFFFFFFUL |
Bit mask for RTC_CNT
Definition at line 11538 of file efm32g890f128.h.
| #define _RTC_CNT_CNT_SHIFT 0 |
Shift value for RTC_CNT
Definition at line 11537 of file efm32g890f128.h.
| #define _RTC_CNT_MASK 0x00FFFFFFUL |
Mask for RTC_CNT
Definition at line 11536 of file efm32g890f128.h.
| #define _RTC_CNT_RESETVALUE 0x00000000UL |
Default value for RTC_CNT
Definition at line 11535 of file efm32g890f128.h.
| #define _RTC_COMP0_COMP0_DEFAULT 0x00000000UL |
Mode DEFAULT for RTC_COMP0
Definition at line 11547 of file efm32g890f128.h.
| #define _RTC_COMP0_COMP0_MASK 0xFFFFFFUL |
Bit mask for RTC_COMP0
Definition at line 11546 of file efm32g890f128.h.
| #define _RTC_COMP0_COMP0_SHIFT 0 |
Shift value for RTC_COMP0
Definition at line 11545 of file efm32g890f128.h.
| #define _RTC_COMP0_MASK 0x00FFFFFFUL |
Mask for RTC_COMP0
Definition at line 11544 of file efm32g890f128.h.
| #define _RTC_COMP0_RESETVALUE 0x00000000UL |
Default value for RTC_COMP0
Definition at line 11543 of file efm32g890f128.h.
| #define _RTC_COMP1_COMP1_DEFAULT 0x00000000UL |
Mode DEFAULT for RTC_COMP1
Definition at line 11555 of file efm32g890f128.h.
| #define _RTC_COMP1_COMP1_MASK 0xFFFFFFUL |
Bit mask for RTC_COMP1
Definition at line 11554 of file efm32g890f128.h.
| #define _RTC_COMP1_COMP1_SHIFT 0 |
Shift value for RTC_COMP1
Definition at line 11553 of file efm32g890f128.h.
| #define _RTC_COMP1_MASK 0x00FFFFFFUL |
Mask for RTC_COMP1
Definition at line 11552 of file efm32g890f128.h.
| #define _RTC_COMP1_RESETVALUE 0x00000000UL |
Default value for RTC_COMP1
Definition at line 11551 of file efm32g890f128.h.
| #define _RTC_CTRL_COMP0TOP_DEFAULT 0x00000000UL |
Mode DEFAULT for RTC_CTRL
Definition at line 11527 of file efm32g890f128.h.
| #define _RTC_CTRL_COMP0TOP_DISABLE 0x00000000UL |
Mode DISABLE for RTC_CTRL
Definition at line 11528 of file efm32g890f128.h.
| #define _RTC_CTRL_COMP0TOP_ENABLE 0x00000001UL |
Mode ENABLE for RTC_CTRL
Definition at line 11529 of file efm32g890f128.h.
| #define _RTC_CTRL_COMP0TOP_MASK 0x4UL |
Bit mask for RTC_COMP0TOP
Definition at line 11526 of file efm32g890f128.h.
| #define _RTC_CTRL_COMP0TOP_SHIFT 2 |
Shift value for RTC_COMP0TOP
Definition at line 11525 of file efm32g890f128.h.
| #define _RTC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL |
Mode DEFAULT for RTC_CTRL
Definition at line 11522 of file efm32g890f128.h.
| #define _RTC_CTRL_DEBUGRUN_MASK 0x2UL |
Bit mask for RTC_DEBUGRUN
Definition at line 11521 of file efm32g890f128.h.
| #define _RTC_CTRL_DEBUGRUN_SHIFT 1 |
Shift value for RTC_DEBUGRUN
Definition at line 11520 of file efm32g890f128.h.
| #define _RTC_CTRL_EN_DEFAULT 0x00000000UL |
Mode DEFAULT for RTC_CTRL
Definition at line 11517 of file efm32g890f128.h.
| #define _RTC_CTRL_EN_MASK 0x1UL |
Bit mask for RTC_EN
Definition at line 11516 of file efm32g890f128.h.
| #define _RTC_CTRL_EN_SHIFT 0 |
Shift value for RTC_EN
Definition at line 11515 of file efm32g890f128.h.
| #define _RTC_CTRL_MASK 0x00000007UL |
Mask for RTC_CTRL
Definition at line 11513 of file efm32g890f128.h.
| #define _RTC_CTRL_RESETVALUE 0x00000000UL |
Default value for RTC_CTRL
Definition at line 11512 of file efm32g890f128.h.
| #define _RTC_FREEZE_MASK 0x00000001UL |
Mask for RTC_FREEZE
Definition at line 11636 of file efm32g890f128.h.
| #define _RTC_FREEZE_REGFREEZE_DEFAULT 0x00000000UL |
Mode DEFAULT for RTC_FREEZE
Definition at line 11640 of file efm32g890f128.h.
| #define _RTC_FREEZE_REGFREEZE_FREEZE 0x00000001UL |
Mode FREEZE for RTC_FREEZE
Definition at line 11642 of file efm32g890f128.h.
| #define _RTC_FREEZE_REGFREEZE_MASK 0x1UL |
Bit mask for RTC_REGFREEZE
Definition at line 11639 of file efm32g890f128.h.
| #define _RTC_FREEZE_REGFREEZE_SHIFT 0 |
Shift value for RTC_REGFREEZE
Definition at line 11638 of file efm32g890f128.h.
| #define _RTC_FREEZE_REGFREEZE_UPDATE 0x00000000UL |
Mode UPDATE for RTC_FREEZE
Definition at line 11641 of file efm32g890f128.h.
| #define _RTC_FREEZE_RESETVALUE 0x00000000UL |
Default value for RTC_FREEZE
Definition at line 11635 of file efm32g890f128.h.
| #define _RTC_IEN_COMP0_DEFAULT 0x00000000UL |
Mode DEFAULT for RTC_IEN
Definition at line 11626 of file efm32g890f128.h.
| #define _RTC_IEN_COMP0_MASK 0x2UL |
Bit mask for RTC_COMP0
Definition at line 11625 of file efm32g890f128.h.
| #define _RTC_IEN_COMP0_SHIFT 1 |
Shift value for RTC_COMP0
Definition at line 11624 of file efm32g890f128.h.
| #define _RTC_IEN_COMP1_DEFAULT 0x00000000UL |
Mode DEFAULT for RTC_IEN
Definition at line 11631 of file efm32g890f128.h.
| #define _RTC_IEN_COMP1_MASK 0x4UL |
Bit mask for RTC_COMP1
Definition at line 11630 of file efm32g890f128.h.
| #define _RTC_IEN_COMP1_SHIFT 2 |
Shift value for RTC_COMP1
Definition at line 11629 of file efm32g890f128.h.
| #define _RTC_IEN_MASK 0x00000007UL |
Mask for RTC_IEN
Definition at line 11617 of file efm32g890f128.h.
| #define _RTC_IEN_OF_DEFAULT 0x00000000UL |
Mode DEFAULT for RTC_IEN
Definition at line 11621 of file efm32g890f128.h.
| #define _RTC_IEN_OF_MASK 0x1UL |
Bit mask for RTC_OF
Definition at line 11620 of file efm32g890f128.h.
| #define _RTC_IEN_OF_SHIFT 0 |
Shift value for RTC_OF
Definition at line 11619 of file efm32g890f128.h.
| #define _RTC_IEN_RESETVALUE 0x00000000UL |
Default value for RTC_IEN
Definition at line 11616 of file efm32g890f128.h.
| #define _RTC_IF_COMP0_DEFAULT 0x00000000UL |
Mode DEFAULT for RTC_IF
Definition at line 11569 of file efm32g890f128.h.
| #define _RTC_IF_COMP0_MASK 0x2UL |
Bit mask for RTC_COMP0
Definition at line 11568 of file efm32g890f128.h.
| #define _RTC_IF_COMP0_SHIFT 1 |
Shift value for RTC_COMP0
Definition at line 11567 of file efm32g890f128.h.
| #define _RTC_IF_COMP1_DEFAULT 0x00000000UL |
Mode DEFAULT for RTC_IF
Definition at line 11574 of file efm32g890f128.h.
| #define _RTC_IF_COMP1_MASK 0x4UL |
Bit mask for RTC_COMP1
Definition at line 11573 of file efm32g890f128.h.
| #define _RTC_IF_COMP1_SHIFT 2 |
Shift value for RTC_COMP1
Definition at line 11572 of file efm32g890f128.h.
| #define _RTC_IF_MASK 0x00000007UL |
Mask for RTC_IF
Definition at line 11560 of file efm32g890f128.h.
| #define _RTC_IF_OF_DEFAULT 0x00000000UL |
Mode DEFAULT for RTC_IF
Definition at line 11564 of file efm32g890f128.h.
| #define _RTC_IF_OF_MASK 0x1UL |
Bit mask for RTC_OF
Definition at line 11563 of file efm32g890f128.h.
| #define _RTC_IF_OF_SHIFT 0 |
Shift value for RTC_OF
Definition at line 11562 of file efm32g890f128.h.
| #define _RTC_IF_RESETVALUE 0x00000000UL |
Default value for RTC_IF
Definition at line 11559 of file efm32g890f128.h.
| #define _RTC_IFC_COMP0_DEFAULT 0x00000000UL |
Mode DEFAULT for RTC_IFC
Definition at line 11607 of file efm32g890f128.h.
| #define _RTC_IFC_COMP0_MASK 0x2UL |
Bit mask for RTC_COMP0
Definition at line 11606 of file efm32g890f128.h.
| #define _RTC_IFC_COMP0_SHIFT 1 |
Shift value for RTC_COMP0
Definition at line 11605 of file efm32g890f128.h.
| #define _RTC_IFC_COMP1_DEFAULT 0x00000000UL |
Mode DEFAULT for RTC_IFC
Definition at line 11612 of file efm32g890f128.h.
| #define _RTC_IFC_COMP1_MASK 0x4UL |
Bit mask for RTC_COMP1
Definition at line 11611 of file efm32g890f128.h.
| #define _RTC_IFC_COMP1_SHIFT 2 |
Shift value for RTC_COMP1
Definition at line 11610 of file efm32g890f128.h.
| #define _RTC_IFC_MASK 0x00000007UL |
Mask for RTC_IFC
Definition at line 11598 of file efm32g890f128.h.
| #define _RTC_IFC_OF_DEFAULT 0x00000000UL |
Mode DEFAULT for RTC_IFC
Definition at line 11602 of file efm32g890f128.h.
| #define _RTC_IFC_OF_MASK 0x1UL |
Bit mask for RTC_OF
Definition at line 11601 of file efm32g890f128.h.
| #define _RTC_IFC_OF_SHIFT 0 |
Shift value for RTC_OF
Definition at line 11600 of file efm32g890f128.h.
| #define _RTC_IFC_RESETVALUE 0x00000000UL |
Default value for RTC_IFC
Definition at line 11597 of file efm32g890f128.h.
| #define _RTC_IFS_COMP0_DEFAULT 0x00000000UL |
Mode DEFAULT for RTC_IFS
Definition at line 11588 of file efm32g890f128.h.
| #define _RTC_IFS_COMP0_MASK 0x2UL |
Bit mask for RTC_COMP0
Definition at line 11587 of file efm32g890f128.h.
| #define _RTC_IFS_COMP0_SHIFT 1 |
Shift value for RTC_COMP0
Definition at line 11586 of file efm32g890f128.h.
| #define _RTC_IFS_COMP1_DEFAULT 0x00000000UL |
Mode DEFAULT for RTC_IFS
Definition at line 11593 of file efm32g890f128.h.
| #define _RTC_IFS_COMP1_MASK 0x4UL |
Bit mask for RTC_COMP1
Definition at line 11592 of file efm32g890f128.h.
| #define _RTC_IFS_COMP1_SHIFT 2 |
Shift value for RTC_COMP1
Definition at line 11591 of file efm32g890f128.h.
| #define _RTC_IFS_MASK 0x00000007UL |
Mask for RTC_IFS
Definition at line 11579 of file efm32g890f128.h.
| #define _RTC_IFS_OF_DEFAULT 0x00000000UL |
Mode DEFAULT for RTC_IFS
Definition at line 11583 of file efm32g890f128.h.
| #define _RTC_IFS_OF_MASK 0x1UL |
Bit mask for RTC_OF
Definition at line 11582 of file efm32g890f128.h.
| #define _RTC_IFS_OF_SHIFT 0 |
Shift value for RTC_OF
Definition at line 11581 of file efm32g890f128.h.
| #define _RTC_IFS_RESETVALUE 0x00000000UL |
Default value for RTC_IFS
Definition at line 11578 of file efm32g890f128.h.
| #define _RTC_SYNCBUSY_COMP0_DEFAULT 0x00000000UL |
Mode DEFAULT for RTC_SYNCBUSY
Definition at line 11658 of file efm32g890f128.h.
| #define _RTC_SYNCBUSY_COMP0_MASK 0x2UL |
Bit mask for RTC_COMP0
Definition at line 11657 of file efm32g890f128.h.
| #define _RTC_SYNCBUSY_COMP0_SHIFT 1 |
Shift value for RTC_COMP0
Definition at line 11656 of file efm32g890f128.h.
| #define _RTC_SYNCBUSY_COMP1_DEFAULT 0x00000000UL |
Mode DEFAULT for RTC_SYNCBUSY
Definition at line 11663 of file efm32g890f128.h.
| #define _RTC_SYNCBUSY_COMP1_MASK 0x4UL |
Bit mask for RTC_COMP1
Definition at line 11662 of file efm32g890f128.h.
| #define _RTC_SYNCBUSY_COMP1_SHIFT 2 |
Shift value for RTC_COMP1
Definition at line 11661 of file efm32g890f128.h.
| #define _RTC_SYNCBUSY_CTRL_DEFAULT 0x00000000UL |
Mode DEFAULT for RTC_SYNCBUSY
Definition at line 11653 of file efm32g890f128.h.
| #define _RTC_SYNCBUSY_CTRL_MASK 0x1UL |
Bit mask for RTC_CTRL
Definition at line 11652 of file efm32g890f128.h.
| #define _RTC_SYNCBUSY_CTRL_SHIFT 0 |
Shift value for RTC_CTRL
Definition at line 11651 of file efm32g890f128.h.
| #define _RTC_SYNCBUSY_MASK 0x00000007UL |
Mask for RTC_SYNCBUSY
Definition at line 11649 of file efm32g890f128.h.
| #define _RTC_SYNCBUSY_RESETVALUE 0x00000000UL |
Default value for RTC_SYNCBUSY
Definition at line 11648 of file efm32g890f128.h.
| #define RTC_CNT_CNT_DEFAULT (_RTC_CNT_CNT_DEFAULT << 0) |
Shifted mode DEFAULT for RTC_CNT
Definition at line 11540 of file efm32g890f128.h.
| #define RTC_COMP0_COMP0_DEFAULT (_RTC_COMP0_COMP0_DEFAULT << 0) |
Shifted mode DEFAULT for RTC_COMP0
Definition at line 11548 of file efm32g890f128.h.
| #define RTC_COMP1_COMP1_DEFAULT (_RTC_COMP1_COMP1_DEFAULT << 0) |
Shifted mode DEFAULT for RTC_COMP1
Definition at line 11556 of file efm32g890f128.h.
| #define RTC_CTRL_COMP0TOP (0x1UL << 2) |
Compare Channel 0 is Top Value
Definition at line 11524 of file efm32g890f128.h.
| #define RTC_CTRL_COMP0TOP_DEFAULT (_RTC_CTRL_COMP0TOP_DEFAULT << 2) |
Shifted mode DEFAULT for RTC_CTRL
Definition at line 11530 of file efm32g890f128.h.
| #define RTC_CTRL_COMP0TOP_DISABLE (_RTC_CTRL_COMP0TOP_DISABLE << 2) |
Shifted mode DISABLE for RTC_CTRL
Definition at line 11531 of file efm32g890f128.h.
| #define RTC_CTRL_COMP0TOP_ENABLE (_RTC_CTRL_COMP0TOP_ENABLE << 2) |
Shifted mode ENABLE for RTC_CTRL
Definition at line 11532 of file efm32g890f128.h.
| #define RTC_CTRL_DEBUGRUN (0x1UL << 1) |
Debug Mode Run Enable
Definition at line 11519 of file efm32g890f128.h.
| #define RTC_CTRL_DEBUGRUN_DEFAULT (_RTC_CTRL_DEBUGRUN_DEFAULT << 1) |
Shifted mode DEFAULT for RTC_CTRL
Definition at line 11523 of file efm32g890f128.h.
| #define RTC_CTRL_EN (0x1UL << 0) |
RTC Enable
Definition at line 11514 of file efm32g890f128.h.
| #define RTC_CTRL_EN_DEFAULT (_RTC_CTRL_EN_DEFAULT << 0) |
Shifted mode DEFAULT for RTC_CTRL
Definition at line 11518 of file efm32g890f128.h.
| #define RTC_FREEZE_REGFREEZE (0x1UL << 0) |
Register Update Freeze
Definition at line 11637 of file efm32g890f128.h.
| #define RTC_FREEZE_REGFREEZE_DEFAULT (_RTC_FREEZE_REGFREEZE_DEFAULT << 0) |
Shifted mode DEFAULT for RTC_FREEZE
Definition at line 11643 of file efm32g890f128.h.
| #define RTC_FREEZE_REGFREEZE_FREEZE (_RTC_FREEZE_REGFREEZE_FREEZE << 0) |
Shifted mode FREEZE for RTC_FREEZE
Definition at line 11645 of file efm32g890f128.h.
| #define RTC_FREEZE_REGFREEZE_UPDATE (_RTC_FREEZE_REGFREEZE_UPDATE << 0) |
Shifted mode UPDATE for RTC_FREEZE
Definition at line 11644 of file efm32g890f128.h.
| #define RTC_IEN_COMP0 (0x1UL << 1) |
Compare Match 0 Interrupt Enable
Definition at line 11623 of file efm32g890f128.h.
| #define RTC_IEN_COMP0_DEFAULT (_RTC_IEN_COMP0_DEFAULT << 1) |
Shifted mode DEFAULT for RTC_IEN
Definition at line 11627 of file efm32g890f128.h.
| #define RTC_IEN_COMP1 (0x1UL << 2) |
Compare Match 1 Interrupt Enable
Definition at line 11628 of file efm32g890f128.h.
| #define RTC_IEN_COMP1_DEFAULT (_RTC_IEN_COMP1_DEFAULT << 2) |
Shifted mode DEFAULT for RTC_IEN
Definition at line 11632 of file efm32g890f128.h.
| #define RTC_IEN_OF (0x1UL << 0) |
Overflow Interrupt Enable
Definition at line 11618 of file efm32g890f128.h.
| #define RTC_IEN_OF_DEFAULT (_RTC_IEN_OF_DEFAULT << 0) |
Shifted mode DEFAULT for RTC_IEN
Definition at line 11622 of file efm32g890f128.h.
| #define RTC_IF_COMP0 (0x1UL << 1) |
Compare Match 0 Interrupt Flag
Definition at line 11566 of file efm32g890f128.h.
| #define RTC_IF_COMP0_DEFAULT (_RTC_IF_COMP0_DEFAULT << 1) |
Shifted mode DEFAULT for RTC_IF
Definition at line 11570 of file efm32g890f128.h.
| #define RTC_IF_COMP1 (0x1UL << 2) |
Compare Match 1 Interrupt Flag
Definition at line 11571 of file efm32g890f128.h.
| #define RTC_IF_COMP1_DEFAULT (_RTC_IF_COMP1_DEFAULT << 2) |
Shifted mode DEFAULT for RTC_IF
Definition at line 11575 of file efm32g890f128.h.
| #define RTC_IF_OF (0x1UL << 0) |
Overflow Interrupt Flag
Definition at line 11561 of file efm32g890f128.h.
| #define RTC_IF_OF_DEFAULT (_RTC_IF_OF_DEFAULT << 0) |
Shifted mode DEFAULT for RTC_IF
Definition at line 11565 of file efm32g890f128.h.
| #define RTC_IFC_COMP0 (0x1UL << 1) |
Clear Compare match 0 Interrupt Flag
Definition at line 11604 of file efm32g890f128.h.
| #define RTC_IFC_COMP0_DEFAULT (_RTC_IFC_COMP0_DEFAULT << 1) |
Shifted mode DEFAULT for RTC_IFC
Definition at line 11608 of file efm32g890f128.h.
| #define RTC_IFC_COMP1 (0x1UL << 2) |
Clear Compare match 1 Interrupt Flag
Definition at line 11609 of file efm32g890f128.h.
| #define RTC_IFC_COMP1_DEFAULT (_RTC_IFC_COMP1_DEFAULT << 2) |
Shifted mode DEFAULT for RTC_IFC
Definition at line 11613 of file efm32g890f128.h.
| #define RTC_IFC_OF (0x1UL << 0) |
Clear Overflow Interrupt Flag
Definition at line 11599 of file efm32g890f128.h.
| #define RTC_IFC_OF_DEFAULT (_RTC_IFC_OF_DEFAULT << 0) |
Shifted mode DEFAULT for RTC_IFC
Definition at line 11603 of file efm32g890f128.h.
| #define RTC_IFS_COMP0 (0x1UL << 1) |
Set Compare match 0 Interrupt Flag
Definition at line 11585 of file efm32g890f128.h.
| #define RTC_IFS_COMP0_DEFAULT (_RTC_IFS_COMP0_DEFAULT << 1) |
Shifted mode DEFAULT for RTC_IFS
Definition at line 11589 of file efm32g890f128.h.
| #define RTC_IFS_COMP1 (0x1UL << 2) |
Set Compare match 1 Interrupt Flag
Definition at line 11590 of file efm32g890f128.h.
| #define RTC_IFS_COMP1_DEFAULT (_RTC_IFS_COMP1_DEFAULT << 2) |
Shifted mode DEFAULT for RTC_IFS
Definition at line 11594 of file efm32g890f128.h.
| #define RTC_IFS_OF (0x1UL << 0) |
Set Overflow Interrupt Flag
Definition at line 11580 of file efm32g890f128.h.
| #define RTC_IFS_OF_DEFAULT (_RTC_IFS_OF_DEFAULT << 0) |
Shifted mode DEFAULT for RTC_IFS
Definition at line 11584 of file efm32g890f128.h.
| #define RTC_SYNCBUSY_COMP0 (0x1UL << 1) |
RTC_COMP0 Register Busy
Definition at line 11655 of file efm32g890f128.h.
| #define RTC_SYNCBUSY_COMP0_DEFAULT (_RTC_SYNCBUSY_COMP0_DEFAULT << 1) |
Shifted mode DEFAULT for RTC_SYNCBUSY
Definition at line 11659 of file efm32g890f128.h.
| #define RTC_SYNCBUSY_COMP1 (0x1UL << 2) |
RTC_COMP1 Register Busy
Definition at line 11660 of file efm32g890f128.h.
| #define RTC_SYNCBUSY_COMP1_DEFAULT (_RTC_SYNCBUSY_COMP1_DEFAULT << 2) |
Shifted mode DEFAULT for RTC_SYNCBUSY
Definition at line 11664 of file efm32g890f128.h.
| #define RTC_SYNCBUSY_CTRL (0x1UL << 0) |
RTC_CTRL Register Busy
Definition at line 11650 of file efm32g890f128.h.
| #define RTC_SYNCBUSY_CTRL_DEFAULT (_RTC_SYNCBUSY_CTRL_DEFAULT << 0) |
Shifted mode DEFAULT for RTC_SYNCBUSY
Definition at line 11654 of file efm32g890f128.h.
1.7.3