# Si4455 revC2A Command/Property API Documentation

#### Interface Version: 1.0

#### Document Version: 2.0.5

#### Generated: 2015-03-18T10:15:42-05:00

## Introduction

This document provides API descriptions for the commands and properties used to control and configure the part. The interface version tracks any functional changes to the API (command, property, field, enumeration, etc.). The documentation version tracks any text changes to the summary or description text of the API components.
The commands are listed in a summary table with links to command details. The properties are listed in a summary table with links to property details. The feature available column in the summary tables lists the firmware revision which first implemented the command or property.
An entry in the summary table will link to a details section, which contains a register view with fields. Clicking a field in the register view will auto-expand the corresponding field details. An up button in the field detail links back to the register view. Each register view title links back to the summary table entry. These hyper-links provide two-click access from top to bottom.

## Command Summary

| COMMON_COMMANDS
--- | ---
| Number | Name | Summary | Feature Available
| 0x00 | NOP | No Operation command. |
| 0x01 | PART_INFO | Reports basic information about the device. |
| 0x10 | FUNC_INFO | Returns the Function revision information of the device. |
| 0x11 | SET_PROPERTY | Sets the value of one or more properties. |
| 0x12 | GET_PROPERTY | Retrieves the value of one or more properties |
| 0x13 | GPIO_PIN_CFG | Configures the GPIO pins. |
| 0x15 | FIFO_INFO | Access the current byte counts in the TX and RX FIFOs, and provide for resetting the FIFOs. |
| 0x20 | GET_INT_STATUS | Returns the interrupt status of ALL the possible interrupt events (both STATUS and PENDING). Optionally, it may be used to clear latched (PENDING) interrupt events. |
| 0x33 | REQUEST_DEVICE_STATE | Request current device state and channel. |
| 0x34 | CHANGE_STATE | Manually switch the chip to a desired operating state. |
| 0x44 | READ_CMD_BUFF | Used to read CTS and the command response. |
| 0x50 | FRR_A_READ | Reads the fast response registers (FRR) starting with FRR_A. |
| 0x51 | FRR_B_READ | Reads the fast response registers (FRR) starting with FRR_B. |
| 0x53 | FRR_C_READ | Reads the fast response registers (FRR) starting with FRR_C. |
| 0x57 | FRR_D_READ | Reads the fast response registers (FRR) starting with FRR_D. |

| TX_COMMANDS
--- | ---
| Number | Name | Summary | Feature Available
| 0x31 | START_TX | Switches to TX state and starts transmission of a packet. |
| 0x66 | WRITE_TX_FIFO | Writes data byte(s) to the TX FIFO. |

| RX_COMMANDS
--- | ---
| Number | Name | Summary | Feature Available
| 0x16 | PACKET_INFO | Returns information about the length of the variable field in the last packet received, and (optionally) overrides field length. |
| 0x22 | GET_MODEM_STATUS | Returns the interrupt status of the Modem Interrupt Group (both STATUS and PENDING). Optionally, it may be used to clear latched (PENDING) interrupt events. |
| 0x32 | START_RX | Switches to RX state and starts reception of a packet. |
| 0x77 | READ_RX_FIFO | Reads data byte(s) from the RX FIFO. |

| ADVANCED_COMMANDS
--- | ---
| Number | Name | Summary | Feature Available
| 0x14 | GET_ADC_READING | Performs conversions using the Auxiliary ADC and returns the results of those conversions. |
| 0x21 | GET_PH_STATUS | Returns the interrupt status of the Packet Handler Interrupt Group (both STATUS and PENDING). Optionally, it may be used to clear latched (PENDING) interrupt events. |
| 0x23 | GET_CHIP_STATUS | Returns the interrupt status of the Chip Interrupt Group (both STATUS and PENDING). Optionally, it may be used to clear latched (PENDING) interrupt events. |

| EZCONFIG_COMMANDS
--- | ---
| Number | Name | Summary | Feature Available
| 0x19 | EZCONFIG_CHECK | Validates the EZConfig array was written correctly. |
| 0x66 | EZCONFIG_ARRAY_WRITE | Writes data byte(s) to the EZConfig array. |

## Property Summary

| INT_CTL (0x01)
--- | ---
| Group | Number | Name | Default | Summary | Feature Available
| 0x01 | 0x00 | INT_CTL_ENABLE | 0x04 | This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin. |
| 0x01 | 0x01 | INT_CTL_PH_ENABLE | 0x00 | Enable individual interrupt sources within the Packet Handler Interrupt Group to generate a HW interrupt on the NIRQ output pin. |
| 0x01 | 0x02 | INT_CTL_MODEM_ENABLE | 0x00 | Enable individual interrupt sources within the Modem Interrupt Group to generate a HW interrupt on the NIRQ output pin. |
| 0x01 | 0x03 | INT_CTL_CHIP_ENABLE | 0x04 | Enable individual interrupt sources within the Chip Interrupt Group to generate a HW interrupt on the NIRQ output pin. |

| FRR_CTL (0x02)
--- | ---
| Group | Number | Name | Default | Summary | Feature Available
| 0x02 | 0x00 | FRR_CTL_A_MODE | 0x01 | Fast Response Register A Configuration. |
| 0x02 | 0x01 | FRR_CTL_B_MODE | 0x02 | Fast Response Register B Configuration. |
| 0x02 | 0x02 | FRR_CTL_C_MODE | 0x09 | Fast Response Register C Configuration. |
| 0x02 | 0x03 | FRR_CTL_D_MODE | 0x00 | Fast Response Register D Configuration. |

| SYNC (0x11)
--- | ---
| Group | Number | Name | Default | Summary | Feature Available
| 0x11 | 0x00 | SYNC_CONFIG | 0x01 | Sync Word configuration bits. |
| 0x11 | 0x01 0x02 0x03 0x04 | SYNC_BITS | 0x2d 0xd4 0x2d 0xd4 | Sync word. |

| PA (0x22)
--- | ---
| Group | Number | Name | Default | Summary | Feature Available
| 0x22 | 0x01 | PA_PWR_LVL | 0x7f | Configuration of PA output power level. |

| EZCONFIG (0x24)
--- | ---
| Group | Number | Name | Default | Summary | Feature Available
| 0x24 | 0x00 | EZCONFIG_MODULATION | 0x02 | Selects the type of modulation using the EZConfig feature. |
| 0x24 | 0x03 | EZCONFIG_XO_TUNE | 0x40 | Configure the internal capacitor frequency tuning bank for the crystal oscillator. |

| FREQ_CONTROL (0x40)
--- | ---
| Group | Number | Name | Default | Summary | Feature Available
| 0x40 | 0x00 | FREQ_CONTROL_INTE | 0x3c | Frac-N PLL Synthesizer integer divide number. |
| 0x40 | 0x01 0x02 0x03 | FREQ_CONTROL_FRAC | 0x08 0x00 0x00 | Frac-N PLL fraction number. |
| 0x40 | 0x04 0x05 | FREQ_CONTROL_CHANNEL_STEP_SIZE | 0x00 0x00 | EZ Frequency Programming channel step size. |

| PTI (0xf0)
--- | ---
| Group | Number | Name | Default | Summary | Feature Available
| 0xf0 | 0x00 | PTI_CTL | 0x80 | Packet Trace Interface control fields. |
| 0xf0 | 0x01 0x02 | PTI_BAUD | 0x13 0x88 | Desired baud rate for the PTI interface. |
| 0xf0 | 0x03 | PTI_LOG_EN | 0x00 | Enables what the PTI logs. |

## Command Details

### COMMON_COMMANDS

#### NOP

- Number: 0x00
- Summary: No Operation command.
- Purpose:
  - This command may be used to ensure that communication with the device has been established. Upon receipt of this command, the chip performs no action except to return CTS.
- Argument Stream:

  NOP Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x00

- Reply Stream:

  NOP Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CTS | CTS

- Argument Fields:
- Reply Fields:

  ###### CTS

  CTS[7:0]
  Description:
    Clear to Send. Indicates that the previous command has completed execution and the response byte stream (if any) is valid. The next command may be sent.
  Type:
    U8

#### PART_INFO

- Number: 0x01
- Summary: Reports basic information about the device.
- Purpose:
  - Returns Part Number, Part Version, ROM ID, etc.
- Argument Stream:

  PART_INFO Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x01

- Reply Stream:

  PART_INFO Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CTS | CTS
  | 0x01 | CHIPREV | CHIPREV
  | 0x02 | PART | PART[15:8]
  0x03 | PART[7:0]
  | 0x04 | PBUILD | PBUILD
  | 0x05 | ID | ID[15:8]
  0x06 | ID[7:0]
  | 0x07 | CUSTOMER | CUSTOMER
  | 0x08 | ROMID | ROMID

- Argument Fields:
- Reply Fields:

  ###### CTS

  CTS[7:0]
  Description:
    Clear to Send. Indicates that the previous command has completed execution and the response byte stream (if any) is valid. The next command may be sent.
  Type:
    U8

  ###### CHIPREV

  CHIPREV[7:0]
  Description:
    Chip Mask Revision.
  Type:
    U8

  ###### PART

  PART[15:0]
  Description:
    Part Number (e.g., si4461 will return - 0x4461).
  Type:
    U16

  ###### PBUILD

  PBUILD[7:0]
  Description:
    Part Build.
  Type:
    U8

  ###### ID

  ID[15:0]
  Description:
    Id.
  Type:
    U16

  ###### CUSTOMER

  CUSTOMER[7:0]
  Description:
    Customer ID.
  Type:
    U8

  ###### ROMID

  ROMID[7:0]
  Description:
    ROM Id.
  Type:
    U8

#### FUNC_INFO

- Number: 0x10
- Summary: Returns the Function revision information of the device.
- Purpose:
  - Return Function revision numbers for currently loaded functional mode. Contrast with PART_INFO.
- Argument Stream:

  FUNC_INFO Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x10

- Reply Stream:

  FUNC_INFO Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CTS | CTS
  | 0x01 | REVEXT | REVEXT
  | 0x02 | REVBRANCH | REVBRANCH
  | 0x03 | REVINT | REVINT
  | 0x04 | PATCH | PATCH[15:8]
  0x05 | PATCH[7:0]
  | 0x06 | FUNC | FUNC

- Argument Fields:
- Reply Fields:

  ###### CTS

  CTS[7:0]
  Description:
    Clear to Send. Indicates that the previous command has completed execution and the response byte stream (if any) is valid. The next command may be sent.
  Type:
    U8

  ###### REVEXT

  REVEXT[7:0]
  Description:
    External revision number.
  Type:
    U8
  Min:
    0x0
  Max:
    0xff

  ###### REVBRANCH

  REVBRANCH[7:0]
  Description:
    Branch revision number.
  Type:
    U8
  Min:
    0x0
  Max:
    0xff

  ###### REVINT

  REVINT[7:0]
  Description:
    Internal revision number.
  Type:
    U8
  Min:
    0x0
  Max:
    0xff

  ###### PATCH

  PATCH[15:0]
  Description:
    - ID of applied patch. This is also the last 2 bytes in the associated patch file (*.csg).
    - 0x0000 = No patch applied.
  Type:
    U16

  ###### FUNC

  FUNC[7:0]
  Description:
    Current functional mode.
  Type:
    U8

#### SET_PROPERTY

- Number: 0x11
- Summary: Sets the value of one or more properties.
- Purpose:
  - This command sets the value of one or more properties. Properties are similar to parameters passed to an API command, but are not expected to change frequently. They are typically used to configure the operation of various internal circuit blocks.
  - Properties may be controlled by higher layers of the user's software. Setting some properties may not cause the device to take immediate action; however, the property will take effect once a command which uses that property is issued.
  - Properties that affect similar circuit blocks or functions (e.g., MODEM or PA or SYNTH properties) are grouped together and share the same GROUP parameter value. Each property within that GROUP has a different offset number or index.
  - A single property may be configured by setting the NUM_PROPS parameter = 0x01, setting the START_PROP parameter to the offset number of that particular property, followed by a single data byte representing the desired value of the property.
  - Multiple contiguous properties may be configured by setting the NUM_PROPS parameter equal to the number of desired properties, setting the START_PROP parameter to the offset number of the first property within that contiguous block of properties, followed by a string of data bytes representing the desired values of the properties.
  - The maximum number of properties that may be set with a single SET_PROPERTY command is 12.
- Argument Stream:

  SET_PROPERTY Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x11
  | 0x01 | GROUP | GROUP
  | 0x02 | NUM_PROPS | NUM_PROPS
  | 0x03 | START_PROP | START_PROP
  | 0x04 | DATA[0] | DATA
  | ... | ... | ...
  | 0x0f | DATA[11] | DATA

- Reply Stream:

  SET_PROPERTY Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CTS | CTS

- Argument Fields:

  ###### GROUP

  GROUP[7:0]
  Description:
    Selects the property group to be configured.
  Type:
    U8

  ###### NUM_PROPS

  NUM_PROPS[7:0]
  Description:
    Selects the number of contiguous properties to be written, starting at START_PROP.
  Type:
    U8
  Min:
    0x1
  Max:
    0xc

  ###### START_PROP

  START_PROP[7:0]
  Description:
    Selects the offset number or index of the property within the specified group. The available properties are determined by the part number and the POWER_UP:FUNC selection.
  Type:
    U8

  ###### DATA[0...11]

  DATA[7:0]
  Description:
    Value to be written to the property located at START_PROP + N. this parameter is not relevant if NUM_PROPS < N + 1. (where N is the Data index)
  Type:
    U8
- Reply Fields:

  ###### CTS

  CTS[7:0]
  Description:
    Clear to Send. Indicates that the previous command has completed execution and the response byte stream (if any) is valid. The next command may be sent.
  Type:
    U8

#### GET_PROPERTY

- Number: 0x12
- Summary: Retrieves the value of one or more properties
- Purpose:
  - This command retrieves the value of one or more properties. Properties are similar to parameters passed to an API command, but are not expected to change frequently. They are typically used to configure the operation of various internal circuit blocks. The returned value represents the default property value upon POWER_UP or the value set previously with a SET_PROPERTY command.
  - Properties that affect similar circuit blocks or functions (e.g., MODEM or PA or SYNTH properties) are grouped together and share the same GROUP parameter value. Each property within that GROUP has a different offset number or index.
  - A single property may be retrieved by setting the NUM_PROPS parameter = 0x01 and setting the START_PROP parameter to the offset number of that particular property. The first data byte of the reply stream represents the value of that property.
  - Multiple contiguous properties may be retrieved by setting the NUM_PROPS parameter equal to the number of desired properties and setting the START_PROP parameter to the offset number of the first property within that contiguous block of properties. The data bytes of the reply stream represent the values of the contiguous properties in sequential order of their offset number.
  - The maximum number of properties that may be retrieved with a single GET_PROPERTY command is 16.
- Argument Stream:

  GET_PROPERTY Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x12
  | 0x01 | GROUP | GROUP
  | 0x02 | NUM_PROPS | NUM_PROPS
  | 0x03 | START_PROP | START_PROP

- Reply Stream:

  GET_PROPERTY Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CTS | CTS
  | 0x01 | DATA[0] | DATA
  | ... | ... | ...
  | 0x10 | DATA[15] | DATA

- Argument Fields:

  ###### GROUP

  GROUP[7:0]
  Description:
    Selects the property group to be retrieved.
  Type:
    U8

  ###### NUM_PROPS

  NUM_PROPS[7:0]
  Description:
    Selects the number of contiguous properties to be retrieved, starting at START_PROP.
  Type:
    U8
  Min:
    0x1
  Max:
    0x10

  ###### START_PROP

  START_PROP[7:0]
  Description:
    Selects the offset number or index of the property within the specified group. the available properties are determined by the part number and the POWER_UP:FUNC selection
  Type:
    U8
- Reply Fields:

  ###### CTS

  CTS[7:0]
  Description:
    Clear to Send. Indicates that the previous command has completed execution and the response byte stream (if any) is valid. The next command may be sent.
  Type:
    U8

  ###### DATA[0...15]

  DATA[7:0]
  Description:
    Retrieved value of the properties located starting at START_PROP. Response bytes in this field are not relevant starting at DATA[NUM_PROPS] and contiuing to the end of the DATA response field.
  Type:
    U8

#### GPIO_PIN_CFG

- Number: 0x13
- Summary: Configures the GPIO pins.
- Purpose:
  - The chip provides General Purpose Input/Output (GPIO) pins for handling a variety of signals. This command is used to select the desired signal for each GPIO pin from an enumerated list of available signals.
  - The drive strength is selectable for those pins configured as outputs. The selected drive strength is applied simultaneously to all outputs; it is currently not possible to individually configure each GPIO pin for different drive strengths.
  - Each pin provides a weak pull-up resistor (~1 Megohm) that may be individually enabled or disabled. It is recommended to disable the pull-up resistor when the pin is configured as an input and driven from an external source (other than an open-drain source).
  - The pins referenced by this command share similar hardware characteristics (i.e., drive strength, pull-up resistors, input/output configurability) but may provide access to different sets of signals. Specifically, the NIRQ and SDO pins are not "signal equivalent" to the GPIO pins.
- Argument Stream:

  GPIO_PIN_CFG Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x13
  | 0x01 | GPIO[0] | 0 | PULL_CTL | GPIO_MODE
  | ... | ... | ... | ... | ...
  | 0x04 | GPIO[3] | 0 | PULL_CTL | GPIO_MODE
  | 0x05 | NIRQ | 0 | PULL_CTL | NIRQ_MODE
  | 0x06 | SDO | 0 | PULL_CTL | SDO_MODE
  | 0x07 | GEN_CONFIG | 0 | DRV_STRENGTH | 0 | 0 | 0 | 0 | 0

- Reply Stream:

  GPIO_PIN_CFG Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CTS | CTS
  | 0x01 | GPIO[0] | GPIO_STATE | X | GPIO_MODE
  | ... | ... | ... | ... | ...
  | 0x04 | GPIO[3] | GPIO_STATE | X | GPIO_MODE
  | 0x05 | NIRQ | NIRQ_STATE | X | NIRQ_MODE
  | 0x06 | SDO | SDO_STATE | X | SDO_MODE
  | 0x07 | GEN_CONFIG | X | DRV_STRENGTH | X | X | X | X | X

- Argument Fields:

  ###### GPIO[0...3]

  PULL_CTL
  Description:
    The pin pull-up control.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    PULL_DIS | 0 | Disable pull-up resistor (recommended setting if the pin is driven from an external source, other than an open-drain source). | revB1A
    PULL_EN | 1 | Enable pull-up resistor. | revB1A

  GPIO_MODE[5:0]
  Description:
    The pin mode.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DONOTHING | 0 | Behavior of this pin is not modified. | revB1A
    TRISTATE | 1 | Input and output drivers disabled. | revB1A
    DRIVE0 | 2 | Pin is configured as a CMOS output and driven low. | revB1A
    DRIVE1 | 3 | Pin is configured as a CMOS output and driven high. | revB1A
    INPUT | 4 | Pin is configured as a CMOS input. This is used for all GPIO functions that require the pin to be an input (e.g., TXDATA input for TX Direct Mode). However, configuration of this pin as an input does NOT additionally select which internal circuit receives that input; that functionality is controlled by other properties, as appropriate. | revB1A
    SDO | 11 | Outputs the Serial Data Out (SDO) signal for the SPI bus. | revB1A
    POR | 12 | This output goes low during Power-On Reset and goes high upon completion of POR. | revB1A
    EN_PA | 15 | This output goes high when the internal PA is enabled. | revB1A
    TX_DATA_CLK | 16 | Outputs the TX Data Clock signal. This signal is a square wave at the selected TX data rate, and is intended for use in TX Direct Synchronous Mode (i.e., in conjunction with a pin configured for TX Data Input). | revB1A
    RX_DATA_CLK | 17 | Outputs the RX Data CLK signal. This signal is nominally a square wave that is synchronized to the received data rate, and is typically used to latch the RX Data signal into the host MCU. | revB1A
    EN_LNA | 18 | This output goes low when the internal LNA is enabled. | revB1A
    TX_DATA | 19 | Outputs the TX data bits pulled from the TX FIFO and sent to the TX modulator. This is an output signal (primarily for diagnostic purposes) and is NOT used as an input for TX Direct Sync/Async mode. | revB1A
    RX_DATA | 20 | Outputs the demodulated RX Data stream, after synchronization and re-timing by the local RX Data Clock. | revB1A
    RX_RAW_DATA | 21 | Outputs the demodulated RX Raw Data stream, prior to synchronization and re-timing by the local RX Data Clock. | revB1A
    VALID_PREAMBLE | 24 | This output goes high when a valid preamble is detected, and returns low after the packet is received or Sync Word timeout occurs. | revB1A
    INVALID_PREAMBLE | 25 | Output low normally, pulses output high when the preamble is not detected within a period time after the demodulator is enabled. | revB1A
    SYNC_WORD_DETECT | 26 | This output goes high when a Sync Word is detected, and returns low after the packet is received. | revB1A
    CCA | 27 | Clear Channel Assessment. This output goes high when the Current RSSI signal exceeds the threshold, and is low when the Current RSSI is below threshold. This is a real-time (non-latched) signal. | revB1A
    IN_SLEEP | 28 | This output goes high when the chip is NOT in SLEEP state, and goes low when in SLEEP state. | revB1A
    PKT_TRACE | 29 | Outputs packet trace data when not in sleep state. Output low when in sleep state. |
    TX_STATE | 32 | This output is set high while in TX state and is low otherwise. The TX_STATE and RX_STATE signals are typically used for control of peripheral circuits (e.g., a T/R Switch). | revB1A
    RX_STATE | 33 | This output is set high while in RX state and is low otherwise. The TX_STATE and RX_STATE signals are typically used for control of peripheral circuits (e.g., a T/R Switch). | revB1A
    RX_FIFO_FULL | 34 | This output is high while the number of bytes stored in the RX FIFO exceeds the threshold value set by the ezconfig array, and is low otherwise. | revB1A
    TX_FIFO_EMPTY | 35 | This output is high while the number of bytes of empty space in the TX FIFO exceeds the threshold value set by the ezconfig array, and is low otherwise. | revB1A
    CCA_LATCH | 37 | This output goes high if the Current RSSI signal exceeds the threshold and remains high (i.e., is latched) even if the Current RSSI signal subsequently drops below the threshold value. The signal returns low upon detection of the Sync Word or upon exiting RX state. | revB1A

  ###### NIRQ

  PULL_CTL
  Description:
    The pin pull-up control.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    PULL_DIS | 0 | Disable pull-up resistor (recommended setting if the pin is driven from an external source, other than an open-drain source). | revB1A
    PULL_EN | 1 | Enable pull-up resistor. | revB1A

  NIRQ_MODE[5:0]
  Description:
    The pin mode.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DONOTHING | 0 | Behavior of this pin is not modified. | revB1A
    TRISTATE | 1 | Input and output drivers disabled. | revB1A
    DRIVE0 | 2 | Pin is configured as a CMOS output and driven low. | revB1A
    DRIVE1 | 3 | Pin is configured as a CMOS output and driven high. | revB1A
    INPUT | 4 | Pin is configured as a CMOS input. This is used for all GPIO functions that require the pin to be an input (e.g., TXDATA input for TX Direct Mode). However, configuration of this pin as an input does NOT additionally select which internal circuit receives that input; that functionality is controlled by other properties, as appropriate. | revB1A
    SDO | 11 | Outputs the Serial Data Out (SDO) signal for the SPI bus. | revB1A
    POR | 12 | This output goes low during Power-On Reset and goes high upon completion of POR. | revB1A
    EN_PA | 15 | This output goes high when the internal PA is enabled. | revB1A
    TX_DATA_CLK | 16 | Outputs the TX Data Clock signal. This signal is a square wave at the selected TX data rate, and is intended for use in TX Direct Synchronous Mode (i.e., in conjunction with a pin configured for TX Data Input). | revB1A
    RX_DATA_CLK | 17 | Outputs the RX Data CLK signal. This signal is nominally a square wave that is synchronized to the received data rate, and is typically used to latch the RX Data signal into the host MCU. | revB1A
    EN_LNA | 18 | This output goes low when the internal LNA is enabled. | revB1A
    TX_DATA | 19 | Outputs the TX data bits pulled from the TX FIFO and sent to the TX modulator. This is an output signal (primarily for diagnostic purposes) and is NOT used as an input for TX Direct Sync/Async mode. | revB1A
    RX_DATA | 20 | Outputs the demodulated RX Data stream, after synchronization and re-timing by the local RX Data Clock. | revB1A
    RX_RAW_DATA | 21 | Outputs the demodulated RX Raw Data stream, prior to synchronization and re-timing by the local RX Data Clock. | revB1A
    VALID_PREAMBLE | 24 | This output goes high when a valid preamble is detected, and returns low after the packet is received or Sync Word timeout occurs. | revB1A
    INVALID_PREAMBLE | 25 | Output low normally, pulses output high when the preamble is not detected within a period time after the demodulator is enabled. | revB1A
    SYNC_WORD_DETECT | 26 | This output goes high when a Sync Word is detected, and returns low after the packet is received. | revB1A
    CCA | 27 | Clear Channel Assessment. This output goes high when the Current RSSI signal exceeds the threshold, and is low when the Current RSSI is below threshold. This is a real-time (non-latched) signal. | revB1A
    PKT_TRACE | 29 | Outputs packet trace data when not in sleep state. Output low when in sleep state. |
    NIRQ | 39 | Active low interrupt signal. | revBlA

  ###### SDO

  PULL_CTL
  Description:
    The pin pull-up control.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    PULL_DIS | 0 | Disable pull-up resistor (recommended setting if the pin is driven from an external source, other than an open-drain source). | revB1A
    PULL_EN | 1 | Enable pull-up resistor. | revB1A

  SDO_MODE[5:0]
  Description:
    The pin mode.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DONOTHING | 0 | Behavior of this pin is not modified. | revB1A
    TRISTATE | 1 | Input and output drivers disabled. | revB1A
    DRIVE0 | 2 | Pin is configured as a CMOS output and driven low. | revB1A
    DRIVE1 | 3 | Pin is configured as a CMOS output and driven high. | revB1A
    INPUT | 4 | Pin is configured as a CMOS input. This is used for all GPIO functions that require the pin to be an input (e.g., TXDATA input for TX Direct Mode). However, configuration of this pin as an input does NOT additionally select which internal circuit receives that input; that functionality is controlled by other properties, as appropriate. | revB1A
    SDO | 11 | Outputs the Serial Data Out (SDO) signal for the SPI bus. | revB1A
    POR | 12 | This output goes low during Power-On Reset and goes high upon completion of POR. | revB1A
    EN_PA | 15 | This output goes high when the internal PA is enabled. | revB1A
    TX_DATA_CLK | 16 | Outputs the TX Data Clock signal. This signal is a square wave at the selected TX data rate, and is intended for use in TX Direct Synchronous Mode (i.e., in conjunction with a pin configured for TX Data Input). | revB1A
    RX_DATA_CLK | 17 | Outputs the RX Data CLK signal. This signal is nominally a square wave that is synchronized to the received data rate, and is typically used to latch the RX Data signal into the host MCU. | revB1A
    EN_LNA | 18 | This output goes low when the internal LNA is enabled. | revB1A
    TX_DATA | 19 | Outputs the TX data bits pulled from the TX FIFO and sent to the TX modulator. This is an output signal (primarily for diagnostic purposes) and is NOT used as an input for TX Direct Sync/Async mode. | revB1A
    RX_DATA | 20 | Outputs the demodulated RX Data stream, after synchronization and re-timing by the local RX Data Clock. | revB1A
    RX_RAW_DATA | 21 | Outputs the demodulated RX Raw Data stream, prior to synchronization and re-timing by the local RX Data Clock. | revB1A
    VALID_PREAMBLE | 24 | This output goes high when a valid preamble is detected, and returns low after the packet is received or Sync Word timeout occurs. | revB1A
    INVALID_PREAMBLE | 25 | Output low normally, pulses output high when the preamble is not detected within a period time after the demodulator is enabled. | revB1A
    SYNC_WORD_DETECT | 26 | This output goes high when a Sync Word is detected, and returns low after the packet is received. | revB1A
    CCA | 27 | Clear Channel Assessment. This output goes high when the Current RSSI signal exceeds the threshold, and is low when the Current RSSI is below threshold. This is a real-time (non-latched) signal. | revB1A

  ###### GEN_CONFIG

  DRV_STRENGTH[1:0]
  Description:
    - Selects the level of drive strength for those GPIO/NIRQ/SDO pins configured as outputs.
    - The selected level of drive strength is applied simultaneously to all output pins, with the following exception: GPIO0 will exhibit a weaker drive strength than the other GPIO pins but only in the lowest drive strength setting; its drive strength is the same for all other settings.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    HIGH | 0 | GPIOs configured as outputs will have the highest drive strength. | revB1A
    MED_HIGH | 1 | GPIOs configured as outputs will have a medium drive strength. | revB1A
    MED_LOW | 2 | GPIOs configured as outputs will have a medium drive strength. | revB1A
    LOW | 3 | GPIOs configured as outputs will have the lowest drive strength. | revB1A

- Reply Fields:

  ###### CTS

  CTS[7:0]
  Description:
    Clear to Send. Indicates that the previous command has completed execution and the response byte stream (if any) is valid. The next command may be sent.
  Type:
    U8

  ###### GPIO[0...3]

  GPIO_STATE
  Description:
    Reads back the logic level on the pin.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    INACTIVE | 0 | Pin was read back as a 0. | revB1A
    ACTIVE | 1 | Pin was read back as a 1. | revB1A

  GPIO_MODE[5:0]
  Description:
    Reads back the enumeration of the currently selected function for the pin.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DONOTHING | 0 | Behavior of this pin is not modified. | revB1A
    TRISTATE | 1 | Input and output drivers disabled. | revB1A
    DRIVE0 | 2 | Pin is configured as a CMOS output and driven low. | revB1A
    DRIVE1 | 3 | Pin is configured as a CMOS output and driven high. | revB1A
    INPUT | 4 | Pin is configured as a CMOS input. This is used for all GPIO functions that require the pin to be an input (e.g., TXDATA input for TX Direct Mode). However, configuration of this pin as an input does NOT additionally select which internal circuit receives that input; that functionality is controlled by other properties, as appropriate. | revB1A
    SDO | 11 | Outputs the Serial Data Out (SDO) signal for the SPI bus. | revB1A
    POR | 12 | This output goes low during Power-On Reset and goes high upon completion of POR. | revB1A
    EN_PA | 15 | This output goes high when the internal PA is enabled. | revB1A
    TX_DATA_CLK | 16 | Outputs the TX Data Clock signal. This signal is a square wave at the selected TX data rate, and is intended for use in TX Direct Synchronous Mode (i.e., in conjunction with a pin configured for TX Data Input). | revB1A
    RX_DATA_CLK | 17 | Outputs the RX Data CLK signal. This signal is nominally a square wave that is synchronized to the received data rate, and is typically used to latch the RX Data signal into the host MCU. | revB1A
    EN_LNA | 18 | This output goes low when the internal LNA is enabled. | revB1A
    TX_DATA | 19 | Outputs the TX data bits pulled from the TX FIFO and sent to the TX modulator. This is an output signal (primarily for diagnostic purposes) and is NOT used as an input for TX Direct Sync/Async mode. | revB1A
    RX_DATA | 20 | Outputs the demodulated RX Data stream, after synchronization and re-timing by the local RX Data Clock. | revB1A
    RX_RAW_DATA | 21 | Outputs the demodulated RX Raw Data stream, prior to synchronization and re-timing by the local RX Data Clock. | revB1A
    VALID_PREAMBLE | 24 | This output goes high when a valid preamble is detected, and returns low after the packet is received or Sync Word timeout occurs. | revB1A
    INVALID_PREAMBLE | 25 | Output low normally, pulses output high when the preamble is not detected within a period time after the demodulator is enabled. | revB1A
    SYNC_WORD_DETECT | 26 | This output goes high when a Sync Word is detected, and returns low after the packet is received. | revB1A
    CCA | 27 | Clear Channel Assessment. This output goes high when the Current RSSI signal exceeds the threshold, and is low when the Current RSSI is below threshold. This is a real-time (non-latched) signal. | revB1A
    IN_SLEEP | 28 | This output goes high when the chip is NOT in SLEEP state, and goes low when in SLEEP state. | revB1A
    PKT_TRACE | 29 | Outputs packet trace data when not in sleep state. Output low when in sleep state. |
    TX_STATE | 32 | This output is set high while in TX state and is low otherwise. The TX_STATE and RX_STATE signals are typically used for control of peripheral circuits (e.g., a T/R Switch). | revB1A
    RX_STATE | 33 | This output is set high while in RX state and is low otherwise. The TX_STATE and RX_STATE signals are typically used for control of peripheral circuits (e.g., a T/R Switch). | revB1A
    RX_FIFO_FULL | 34 | This output is high while the number of bytes stored in the RX FIFO exceeds the threshold value set by the ezconfig array, and is low otherwise. | revB1A
    TX_FIFO_EMPTY | 35 | This output is high while the number of bytes of empty space in the TX FIFO exceeds the threshold value set by the ezconfig array, and is low otherwise. | revB1A
    CCA_LATCH | 37 | This output goes high if the Current RSSI signal exceeds the threshold and remains high (i.e., is latched) even if the Current RSSI signal subsequently drops below the threshold value. The signal returns low upon detection of the Sync Word or upon exiting RX state. | revB1A

  ###### NIRQ

  NIRQ_STATE
  Description:
    Reads back the logic level on the NIRQ pin.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    INACTIVE | 0 | Pin was read back as a 0. | revB1A
    ACTIVE | 1 | Pin was read back as a 1. | revB1A

  NIRQ_MODE[5:0]
  Description:
    Reads back the enumeration of the currently selected function for the NIRQ pin.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DONOTHING | 0 | Behavior of this pin is not modified. | revB1A
    TRISTATE | 1 | Input and output drivers disabled. | revB1A
    DRIVE0 | 2 | Pin is configured as a CMOS output and driven low. | revB1A
    DRIVE1 | 3 | Pin is configured as a CMOS output and driven high. | revB1A
    INPUT | 4 | Pin is configured as a CMOS input. This is used for all GPIO functions that require the pin to be an input (e.g., TXDATA input for TX Direct Mode). However, configuration of this pin as an input does NOT additionally select which internal circuit receives that input; that functionality is controlled by other properties, as appropriate. | revB1A
    SDO | 11 | Outputs the Serial Data Out (SDO) signal for the SPI bus. | revB1A
    POR | 12 | This output goes low during Power-On Reset and goes high upon completion of POR. | revB1A
    EN_PA | 15 | This output goes high when the internal PA is enabled. | revB1A
    TX_DATA_CLK | 16 | Outputs the TX Data Clock signal. This signal is a square wave at the selected TX data rate, and is intended for use in TX Direct Synchronous Mode (i.e., in conjunction with a pin configured for TX Data Input). | revB1A
    RX_DATA_CLK | 17 | Outputs the RX Data CLK signal. This signal is nominally a square wave that is synchronized to the received data rate, and is typically used to latch the RX Data signal into the host MCU. | revB1A
    EN_LNA | 18 | This output goes low when the internal LNA is enabled. | revB1A
    TX_DATA | 19 | Outputs the TX data bits pulled from the TX FIFO and sent to the TX modulator. This is an output signal (primarily for diagnostic purposes) and is NOT used as an input for TX Direct Sync/Async mode. | revB1A
    RX_DATA | 20 | Outputs the demodulated RX Data stream, after synchronization and re-timing by the local RX Data Clock. | revB1A
    RX_RAW_DATA | 21 | Outputs the demodulated RX Raw Data stream, prior to synchronization and re-timing by the local RX Data Clock. | revB1A
    VALID_PREAMBLE | 24 | This output goes high when a valid preamble is detected, and returns low after the packet is received or Sync Word timeout occurs. | revB1A
    INVALID_PREAMBLE | 25 | Output low normally, pulses output high when the preamble is not detected within a period time after the demodulator is enabled. | revB1A
    SYNC_WORD_DETECT | 26 | This output goes high when a Sync Word is detected, and returns low after the packet is received. | revB1A
    CCA | 27 | Clear Channel Assessment. This output goes high when the Current RSSI signal exceeds the threshold, and is low when the Current RSSI is below threshold. This is a real-time (non-latched) signal. | revB1A
    PKT_TRACE | 29 | Outputs packet trace data when not in sleep state. Output low when in sleep state. |
    NIRQ | 39 | Active low interrupt signal. | revBlA

  ###### SDO

  SDO_STATE
  Description:
    Reads back the logic level on the SDO pin.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    INACTIVE | 0 | Pin was read back as a 0. | revB1A
    ACTIVE | 1 | Pin was read back as a 1. | revB1A

  SDO_MODE[5:0]
  Description:
    Reads back the enumeration of the currently selected function for the SDO pin.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DONOTHING | 0 | Behavior of this pin is not modified. | revB1A
    TRISTATE | 1 | Input and output drivers disabled. | revB1A
    DRIVE0 | 2 | Pin is configured as a CMOS output and driven low. | revB1A
    DRIVE1 | 3 | Pin is configured as a CMOS output and driven high. | revB1A
    INPUT | 4 | Pin is configured as a CMOS input. This is used for all GPIO functions that require the pin to be an input (e.g., TXDATA input for TX Direct Mode). However, configuration of this pin as an input does NOT additionally select which internal circuit receives that input; that functionality is controlled by other properties, as appropriate. | revB1A
    SDO | 11 | Outputs the Serial Data Out (SDO) signal for the SPI bus. | revB1A
    POR | 12 | This output goes low during Power-On Reset and goes high upon completion of POR. | revB1A
    EN_PA | 15 | This output goes high when the internal PA is enabled. | revB1A
    TX_DATA_CLK | 16 | Outputs the TX Data Clock signal. This signal is a square wave at the selected TX data rate, and is intended for use in TX Direct Synchronous Mode (i.e., in conjunction with a pin configured for TX Data Input). | revB1A
    RX_DATA_CLK | 17 | Outputs the RX Data CLK signal. This signal is nominally a square wave that is synchronized to the received data rate, and is typically used to latch the RX Data signal into the host MCU. | revB1A
    EN_LNA | 18 | This output goes low when the internal LNA is enabled. | revB1A
    TX_DATA | 19 | Outputs the TX data bits pulled from the TX FIFO and sent to the TX modulator. This is an output signal (primarily for diagnostic purposes) and is NOT used as an input for TX Direct Sync/Async mode. | revB1A
    RX_DATA | 20 | Outputs the demodulated RX Data stream, after synchronization and re-timing by the local RX Data Clock. | revB1A
    RX_RAW_DATA | 21 | Outputs the demodulated RX Raw Data stream, prior to synchronization and re-timing by the local RX Data Clock. | revB1A
    VALID_PREAMBLE | 24 | This output goes high when a valid preamble is detected, and returns low after the packet is received or Sync Word timeout occurs. | revB1A
    INVALID_PREAMBLE | 25 | Output low normally, pulses output high when the preamble is not detected within a period time after the demodulator is enabled. | revB1A
    SYNC_WORD_DETECT | 26 | This output goes high when a Sync Word is detected, and returns low after the packet is received. | revB1A
    CCA | 27 | Clear Channel Assessment. This output goes high when the Current RSSI signal exceeds the threshold, and is low when the Current RSSI is below threshold. This is a real-time (non-latched) signal. | revB1A

  ###### GEN_CONFIG

  DRV_STRENGTH[1:0]
  Description:
    Reads back the enumeration of the currently selected drive strength.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    HIGH | 0 | GPIOs configured as outputs will have the highest drive strength. | revB1A
    MED_HIGH | 1 | GPIOs configured as outputs will have a medium drive strength. | revB1A
    MED_LOW | 2 | GPIOs configured as outputs will have a medium drive strength. | revB1A
    LOW | 3 | GPIOs configured as outputs will have the lowest drive strength. | revB1A

#### FIFO_INFO

- Number: 0x15
- Summary: Access the current byte counts in the TX and RX FIFOs, and provide for resetting the FIFOs.
- Purpose:
  - The chip provides for two separate 64-byte FIFO memories for the purpose of storing transmit and receive data.
  - The reply stream for this command returns the current number of received bytes stored in the RX FIFO, and the number of remaining empty bytes in the TX FIFO.
  - The command may also be used to reset the individual FIFOs. This is typically used for error recovery (e.g., after encountering a CRC error in RX mode). Any valid data that has not yet been retrieved from the RX FIFO will be lost as a result of a reset; it is recommended to read such data prior to a reset. The FIFOs do not need to be reset prior to initial use after power-up.
  - The FIFO reset function (if enabled) is processed prior to returning the byte count in the FIFOs. Thus the reply stream to a FIFO_INFO command that resets the FIFOs will return byte counts that indicate the FIFOs are empty.
  - A FIFO reset command should not be sent while actively receiving or transmitting a packet, as this may corrupt the index pointers into the FIFOs and result in loss of stored information.
  - The FIFO:TX and FIFO:RX bits are self-clearing; that is, there is no need to send the command twice (e.g., with the reset bits set the first time, and cleared the second time).
- Argument Stream:

  FIFO_INFO Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x15
  | 0x01 | FIFO | 0 | 0 | 0 | 0 | 0 | 0 | RX | TX

- Reply Stream:

  FIFO_INFO Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CTS | CTS
  | 0x01 | RX_FIFO_COUNT | RX_FIFO_COUNT
  | 0x02 | TX_FIFO_SPACE | TX_FIFO_SPACE

- Argument Fields:

  ###### FIFO

  RX
  Description:
    - Resets the RX FIFO.
    - The RX FIFO mode specified in property GLOBAL_CONFIG:FIFO_MODE will be effective after reset.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    FALSE | 0 | Do not reset the RX data FIFO. | revB1A
    TRUE | 1 | Reset the RX data FIFO. | revB1A

  TX
  Description:
    - Resets the TX FIFO.
    - The TX FIFO mode specified in property GLOBAL_CONFIG:FIFO_MODE will be effective after reset.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    FALSE | 0 | Do not reset the TX data FIFO. | revB1A
    TRUE | 1 | Reset the TX data FIFO. | revB1A

- Reply Fields:

  ###### CTS

  CTS[7:0]
  Description:
    Clear to Send. Indicates that the previous command has completed execution and the response byte stream (if any) is valid. The next command may be sent.
  Type:
    U8

  ###### RX_FIFO_COUNT

  RX_FIFO_COUNT[7:0]
  Description:
    Returns the number of received bytes currently stored in the RX FIFO.
  Type:
    U8

  ###### TX_FIFO_SPACE

  TX_FIFO_SPACE[7:0]
  Description:
    Returns the number of empty bytes (i.e., space) currently available in the TX FIFO.
  Type:
    U8

#### GET_INT_STATUS

- Number: 0x20
- Summary: Returns the interrupt status of ALL the possible interrupt events (both STATUS and PENDING). Optionally, it may be used to clear latched (PENDING) interrupt events.
- Purpose:
  - Returns the current interrupt status of ALL the possible interrupt events (both STATUS and PENDING) and optionally clears PENDING interrupts.
  - STATUS indicates the current state of an internal interrupt event such as preamble/sync word detection, packet sent/received, etc. For example, PREAMBLE_DETECT is low before detection of a valid preamble, but goes high when the preamble arrives and is successfully detected. STATUS is cleared automatically upon termination or cessation of the corresponding internal interrupt event.
  - PENDING simply latches the rising edge of the corresponding STATUS, and does not change until cleared by a GET_INT_STATUS command (or GET_CHIP_STATUS, GET_PH_STATUS, GET_MODEM_STATUS). For example, PREAMBLE_DETECT_PEND is low before detection of a valid preamble, goes high with PREAMBLE_DETECT, and remains high until cleared.
  - It is possible to poll for interrupts by reading the STATUS and PENDING response bytes, as they are always up-to-date. Additionally, PENDING interrupts may generate a HW interrupt on the NIRQ output pin, if the interrupt is enabled via INT_CTL_ENABLE, INT_CTL_PH_ENABLE, INT_CTL_MODEM_ENABLE, and INT_CTL_CHIP_ENABLE properties.
  - Sending the GET_INT_STATUS command with NO input parameters results in clearing all of the PENDING interrupts.
  - When PENDING interrupts are being cleared, the reply stream reflects their status prior to clearing.
- Argument Stream:

  GET_INT_STATUS Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x20
  | 0x01 | PH_CLR_PEND | 0 | 0 | PACKET_SENT_PEND_CLR | PACKET_RX_PEND_CLR | CRC_ERROR_PEND_CLR | ALT_CRC_ERROR_PEND_CLR | TX_FIFO_ALMOST_EMPTY_PEND_CLR | RX_FIFO_ALMOST_FULL_PEND_CLR
  | 0x02 | MODEM_CLR_PEND | RSSI_LATCH_PEND_CLR | 0 | INVALID_SYNC_PEND_CLR | 0 | RSSI_PEND_CLR | INVALID_PREAMBLE_PEND_CLR | PREAMBLE_DETECT_PEND_CLR | SYNC_DETECT_PEND_CLR
  | 0x03 | CHIP_CLR_PEND | 0 | 0 | FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_CLR | STATE_CHANGE_PEND_CLR | CMD_ERROR_PEND_CLR | CHIP_READY_PEND_CLR | 0 | 0

- Reply Stream:

  GET_INT_STATUS Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CTS | CTS
  | 0x01 | INT_PEND | X | X | X | X | X | CHIP_INT_PEND | MODEM_INT_PEND | PH_INT_PEND
  | 0x02 | INT_STATUS | X | X | X | X | X | CHIP_INT_STATUS | MODEM_INT_STATUS | PH_INT_STATUS
  | 0x03 | PH_PEND | X | X | PACKET_SENT_PEND | PACKET_RX_PEND | CRC_ERROR_PEND | ALT_CRC_ERROR_PEND | TX_FIFO_ALMOST_EMPTY_PEND | RX_FIFO_ALMOST_FULL_PEND
  | 0x04 | PH_STATUS | X | X | PACKET_SENT | PACKET_RX | CRC_ERROR | ALT_CRC_ERROR | TX_FIFO_ALMOST_EMPTY | RX_FIFO_ALMOST_FULL
  | 0x05 | MODEM_PEND | RSSI_LATCH_PEND | X | INVALID_SYNC_PEND | X | RSSI_PEND | INVALID_PREAMBLE_PEND | PREAMBLE_DETECT_PEND | SYNC_DETECT_PEND
  | 0x06 | MODEM_STATUS | RSSI_LATCH | X | INVALID_SYNC | X | RSSI | INVALID_PREAMBLE | PREAMBLE_DETECT | SYNC_DETECT
  | 0x07 | CHIP_PEND | X | X | FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND | STATE_CHANGE_PEND | CMD_ERROR_PEND | CHIP_READY_PEND | X | X
  | 0x08 | CHIP_STATUS | X | X | FIFO_UNDERFLOW_OVERFLOW_ERROR | STATE_CHANGE | CMD_ERROR | CHIP_READY | X | X

- Argument Fields:

  ###### PH_CLR_PEND

  PACKET_SENT_PEND_CLR
  Description:
    If clear, clear any pending PACKET_SENT interrupt. If set, leave interrupt pending.
  Type:
    BOOL
  PACKET_RX_PEND_CLR
  Description:
    If clear, clear any pending PACKET_RX interrupt. If set, leave interrupt pending.
  Type:
    BOOL
  CRC_ERROR_PEND_CLR
  Description:
    If clear, clear any pending CRC_ERROR interrupt. If set, leave interrupt pending.
  Type:
    BOOL
  ALT_CRC_ERROR_PEND_CLR
  Description:
    If clear, clear any pending ALT_CRC_ERROR interrupt. If set, leave interrupt pending.
  Type:
    BOOL
  TX_FIFO_ALMOST_EMPTY_PEND_CLR
  Description:
    If clear, clear any pending TX_FIFO_ALMOST_EMPTY interrupt. If set, leave interrupt pending.
  Type:
    BOOL
  RX_FIFO_ALMOST_FULL_PEND_CLR
  Description:
    If clear, clear any pending RX_FIFO_ALMOST_FULL interrupt. If set, leave interrupt pending.
  Type:
    BOOL

  ###### MODEM_CLR_PEND

  RSSI_LATCH_PEND_CLR
  Description:
    If clear, clear any pending RSSI_LATCH interrupt. If set, leave interrupt pending.
  Type:
    BOOL
  INVALID_SYNC_PEND_CLR
  Description:
    If clear, clear any pending INVALID_SYNC interrupt. If set, leave interrupt pending.
  Type:
    BOOL
  RSSI_PEND_CLR
  Description:
    If clear, clear any pending RSSI interrupt. If set, leave interrupt pending.
  Type:
    BOOL
  INVALID_PREAMBLE_PEND_CLR
  Description:
    If clear, clear any pending INVALID_PREAMBLE interrupt. If set, leave interrupt pending.
  Type:
    BOOL
  PREAMBLE_DETECT_PEND_CLR
  Description:
    If clear, clear any pending PREAMBLE_DETECT interrupt. If set, leave interrupt pending.
  Type:
    BOOL
  SYNC_DETECT_PEND_CLR
  Description:
    If clear, clear any pending SYNC_DETECT interrupt. If set, leave interrupt pending.
  Type:
    BOOL

  ###### CHIP_CLR_PEND

  FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_CLR
  Description:
    If clear, clear any pending FIFO_UNDERFLOW_OVERFLOW_ERROR interrupt. If set, leave interrupt pending.
  Type:
    BOOL
  STATE_CHANGE_PEND_CLR
  Description:
    If clear, clear any pending STATE_CHANGE interrupt. If set, leave interrupt pending.
  Type:
    BOOL
  CMD_ERROR_PEND_CLR
  Description:
    If clear, clear any pending CMD_ERROR interrupt. If set, leave interrupt pending.
  Type:
    BOOL
  CHIP_READY_PEND_CLR
  Description:
    If clear, clear any pending CHIP_READY interrupt. If set, leave interrupt pending.
  Type:
    BOOL
- Reply Fields:

  ###### CTS

  CTS[7:0]
  Description:
    Clear to Send. Indicates that the previous command has completed execution and the response byte stream (if any) is valid. The next command may be sent.
  Type:
    U8

  ###### INT_PEND

  CHIP_INT_PEND
  Description:
    If set, an enabled CHIP_PEND bit is set indicating an interrupt is pending. See the GET_INT_STATUS:CHIP_STATUS field for the triggering events within the Chip Status Interrupt group.
  Type:
    BOOL
  MODEM_INT_PEND
  Description:
    If set, an enabled MODEM_PEND bit is set indicating an interrupt is pending. See the GET_INT_STATUS:MODEM_STATUS field for the triggering events within the Modem Interrupt group.
  Type:
    BOOL
  PH_INT_PEND
  Description:
    If set, an enabled PH_PEND bit is set indicating an interrupt is pending. See the GET_INT_STATUS:PH_STATUS field for the triggering events within the Packet Handler Interrupt group.
  Type:
    BOOL

  ###### INT_STATUS

  CHIP_INT_STATUS
  Description:
    If set, the Chip Status Interrupt group has an interrupt pending. See the GET_INT_STATUS:CHIP_STATUS field for the triggering events within the Chip Status Interrupt group.
  Type:
    BOOL
  MODEM_INT_STATUS
  Description:
    If set, the Modem Interrupt group has an interrupt pending. See the GET_INT_STATUS:MODEM_STATUS field for the triggering events within the Modem Interrupt group.
  Type:
    BOOL
  PH_INT_STATUS
  Description:
    If set, the Packet Handler Interrupt group has an interrupt pending. See the GET_INT_STATUS:PH_STATUS field for the triggering events within the Packet Handler Interrupt group.
  Type:
    BOOL

  ###### PH_PEND

  PACKET_SENT_PEND
  Description:
    If set, a rising edge of the PACKET_SENT status bit has been detected and therefore a PACKET_SENT interrupt is pending. See associated PACKET_SENT status bit for more details.
  Type:
    BOOL
  PACKET_RX_PEND
  Description:
    If set, a rising edge of the PACKET_RX status bit has been detected and therefore a PACKET_RX interrupt is pending. See associated PACKET_RX status bit for more details.
  Type:
    BOOL
  CRC_ERROR_PEND
  Description:
    If set, a rising edge of the CRC_ERROR status bit has been detected and therefore a CRC_ERROR interrupt is pending. See associated CRC_ERROR status bit for more details.
  Type:
    BOOL
  ALT_CRC_ERROR_PEND
  Description:
    If set, a rising edge of the ALT_CRC_ERROR status bit has been detected and therefore a ALT_CRC_ERROR interrupt is pending. See associated ALT_CRC_ERROR status bit for more details.
  Type:
    BOOL
  TX_FIFO_ALMOST_EMPTY_PEND
  Description:
    If set, a rising edge of the TX_FIFO_ALMOST_EMPTY status bit has been detected and therefore a TX_FIFO_ALMOST_EMPTY interrupt is pending. See associated TX_FIFO_ALMOST_EMPTY status bit for more details.
  Type:
    BOOL
  RX_FIFO_ALMOST_FULL_PEND
  Description:
    If set, a rising edge of the RX_FIFO_ALMOST_FULL status bit has been detected and therefore a RX_FIFO_ALMOST_FULL interrupt is pending. See associated RX_FIFO_ALMOST_FULL status bit for more details.
  Type:
    BOOL

  ###### PH_STATUS

  PACKET_SENT
  Description:
    Set to indicate that data bytes in the TX FIFO were transmitted successfully. Cleared upon entry into TX state.
  Type:
    BOOL
  PACKET_RX
  Description:
    Set to indicate that the expected number of data bytes have been successfully received and placed in the RX FIFO. All enabled Packet Handler functions (e.g., CRC check, Filter Matching) must be successfully completed in order to generate a PACKET_RX interrupt.
  Type:
    BOOL
  CRC_ERROR
  Description:
    Set to indicate that the received CRC checksum byte(s) do not match the calculated CRC checksum value. Cleared upon entry into RX state or if RX is restarted.
  Type:
    BOOL
  ALT_CRC_ERROR
  Description:
    Set to indicate that the received CRC checksum byte(s) do not match the calculated alternate CRC checksum value. For the difference between the two CRC engines (CRC, ALT_CRC), see PKT_CRC_CONFIG property. Cleared upon entry into RX state or if RX is restarted.
  Type:
    BOOL
  TX_FIFO_ALMOST_EMPTY
  Description:
    Set to indicate that the amount of space in the TX FIFO is equal to or greater than the threshold value for the TX FIFO provided by the ezconfig array. This interrupt may be used to signal the host MCU to store more data bytes into the TX FIFO, thus providing a means for handling packets with lengths greater than the size of the TX FIFO. Cleared if the amount of space in the TX FIFO is more than the threshold value for the TX FIFO provided by the ezconfig array.
  Type:
    BOOL
  RX_FIFO_ALMOST_FULL
  Description:
    Set to indicate that the number of bytes stored in the RX FIFO is equal to or greater than the threshold value for the RX FIFO provided by the ezconfig array. This interrupt may be used to signal the host MCU to read more data bytes from the RX FIFO, thus providing a means for handling packets with lengths greater than the size of the RX FIFO. Cleared if the amount of data in the RX FIFO is less than the threshold value for the RX FIFO provided by the ezconfig array.
  Type:
    BOOL

  ###### MODEM_PEND

  RSSI_LATCH_PEND
  Description:
    If set, a rising edge of the RSSI_LATCH status bit has been detected and therefore a RSSI_LATCH interrupt is pending. See associated RSSI_LATCH status bit for more details.
  Type:
    BOOL
  INVALID_SYNC_PEND
  Description:
    If set, a rising edge of the INVALID_SYNC status bit has been detected and therefore a INVALID_SYNC interrupt is pending. See associated INVALID_SYNC status bit for more details.
  Type:
    BOOL
  RSSI_PEND
  Description:
    If set, a rising edge of the RSSI status bit has been detected and therefore a RSSI interrupt is pending. See associated RSSI status bit for more details.
  Type:
    BOOL
  INVALID_PREAMBLE_PEND
  Description:
    If set, a rising edge of the INVALID_PREAMBLE status bit has been detected and therefore a INVALID_PREAMBLE interrupt is pending. See associated INVALID_PREAMBLE status bit for more details.
  Type:
    BOOL
  PREAMBLE_DETECT_PEND
  Description:
    If set, a rising edge of the PREAMBLE_DETECT status bit has been detected and therefore a PREAMBLE_DETECT interrupt is pending. See associated PREAMBLE_DETECT status bit for more details.
  Type:
    BOOL
  SYNC_DETECT_PEND
  Description:
    If set, a rising edge of the SYNC_DETECT status bit has been detected and therefore a SYNC_DETECT interrupt is pending. See associated SYNC_DETECT status bit for more details.
  Type:
    BOOL

  ###### MODEM_STATUS

  RSSI_LATCH
  Description:
    Set if the latched RSSI value (defined in MODEM_RSSI_CONTROL has exceeded the threshold value defined in the MODEM_RSSI_THRESH property. Cleared upon entry into RX state or if RX is restarted.
  Type:
    BOOL
  INVALID_SYNC
  Description:
    Self clearing signal that pulses high when a valid Sync Word (matching the pattern of bits defined in the SYNC_BITS_XX properties) was not detected within the allowed search timeout period. If configured to receive a standard preamble, the search timeout period is Sync Word Length + 4bits. If configured to receive a non-standard preamble, the search timeout period is defined by the EZConfig array.
  Type:
    BOOL
  RSSI
  Description:
    Set if the current RSSI value has exceeded the threshold value defined by the EZConfig array.Cleared upon entry into RX state or if RX is restarted.
  Type:
    BOOL
  INVALID_PREAMBLE
  Description:
    Self clearing signal that pulses high indicating that one of the following has occurred: a) a valid Preamble was not detected within the allowed search timeout period, or b) the Latched RSSI value is below the rssi threshold set as part of the EZConfig array and the chip has been enabled to check for this condition. The search timeout period for Preamble and the CHECK_THRESH_AT_LATCH function are configured in the EZConfig array.
  Type:
    BOOL
  PREAMBLE_DETECT
  Description:
    Set when a pattern of bits was received that matched the expected Preamble pattern. If configured to receive a standard preamble, the expected pattern of bits is '...010101...' with a threshold length defined in the EZConfig array. If configured to receive a non-standard preamble, the expected pattern of bits is defined by the PREAMBLE_PATTERN_XX properties and the pattern length defined in the EZConfig array. Cleared when SYNC is detected, upon entering RX state, or RX is restarted.
  Type:
    BOOL
  SYNC_DETECT
  Description:
    Set when the received Sync Word pattern matched the pattern of bits defined in the SYNC_BITS property. If SYNC_CONFIG2:DUAL_SYNC_EN is enabled, the pattern in SYNC_BITS2 is also used to match. Cleared when a packet is received (valid or invalid), upon entry into RX state, or if RX is restarted.
  Type:
    BOOL

  ###### CHIP_PEND

  FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND
  Description:
    If set, a rising edge of the FIFO_UNDERFLOW_OVERFLOW_ERROR status bit has been detected and therefore a FIFO_UNDERFLOW_OVERFLOW_ERROR interrupt is pending. See associated FIFO_UNDERFLOW_OVERFLOW_ERROR status bit for more details.
  Type:
    BOOL
  STATE_CHANGE_PEND
  Description:
    If set, a rising edge of the STATE_CHANGE status bit has been detected and therefore a STATE_CHANGE interrupt is pending. See associated STATE_CHANGE status bit for more details.
  Type:
    BOOL
  CMD_ERROR_PEND
  Description:
    If set, a rising edge of the CMD_ERROR status bit has been detected and therefore a CMD_ERROR interrupt is pending. See associated CMD_ERROR status bit for more details.
  Type:
    BOOL
  CHIP_READY_PEND
  Description:
    If set, a rising edge of the CHIP_READY status bit has been detected and therefore a CHIP_READY interrupt is pending. See associated CHIP_READY status bit for more details.
  Type:
    BOOL

  ###### CHIP_STATUS

  FIFO_UNDERFLOW_OVERFLOW_ERROR
  Description:
    Set to indicate that the number of received or transmitted bytes exceeds the size of the RX or TX FIFO, respectively. Upon such an underflow/overflow event, the FIFO(s) will need to be reset. Cleared by issuing a FIFO_INFO command to reset the FIFOs.
  Type:
    BOOL
  STATE_CHANGE
  Description:
    Set to indicate a successful transition from one state to another operating state. Cleared when a state transition is in progress.
  Type:
    BOOL
  CMD_ERROR
  Description:
    Self clearing signal that pulses high to indicate an error has occurred in the processing of a command. For example, an incorrect command/property ID is sent, or an attempt was made to write a property that is outside of the given property group.
  Type:
    BOOL
  CHIP_READY
  Description:
    Set to indicate the chip (upon completion of the POWER_UP sequence) has reached the state where it is ready to accept commands. Cleared when the chip is shutdown.
  Type:
    BOOL

#### REQUEST_DEVICE_STATE

- Number: 0x33
- Summary: Request current device state and channel.
- Purpose:
  - This command returns information regarding the current operating state and tuned frequency channel of the device.
  - Returning the current channel number is often useful in automatic frequency hopping applications, to determine the frequency on which the device found a valid signal.
  - It is not possible for this command to return a device state value indicating the chip is in SLEEP or STANDBY mode, as the very act of sending an SPI command while the chip is in SLEEP or STANDBY mode assures that it wakes into SPI_ACTIVE mode.
- Argument Stream:

  REQUEST_DEVICE_STATE Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x33

- Reply Stream:

  REQUEST_DEVICE_STATE Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CTS | CTS
  | 0x01 | CURR_STATE | X | X | X | X | MAIN_STATE
  | 0x02 | CURRENT_CHANNEL | CURRENT_CHANNEL

- Argument Fields:
- Reply Fields:

  ###### CTS

  CTS[7:0]
  Description:
    Clear to Send. Indicates that the previous command has completed execution and the response byte stream (if any) is valid. The next command may be sent.
  Type:
    U8

  ###### CURR_STATE

  MAIN_STATE[3:0]
  Description:
    Returns the current operating state of the device. Please refer to the published datasheet for more details regarding these operational modes.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    SLEEP | 1 | (Not Applicable) | revB1A
    SPI_ACTIVE | 2 | SPI_ACTIVE state. | revB1A
    READY | 3 | READY state. | revB1A
    READY2 | 4 | Another enumeration for READY state. | revB1A
    TX_TUNE | 5 | TX_TUNE state. | revB1A
    RX_TUNE | 6 | RX_TUNE state. | revB1A
    TX | 7 | TX state. | revB1A
    RX | 8 | RX state. | revB1A

  ###### CURRENT_CHANNEL

  CURRENT_CHANNEL[7:0]
  Description:
    Returns the current tuned channel.
  Type:
    U8

#### CHANGE_STATE

- Number: 0x34
- Summary: Manually switch the chip to a desired operating state.
- Purpose:
  - The chip normally manages the required steps in transitioning between operating states automatically. For example, transmission of a packet may require: waking the chip from SLEEP mode, enabling the Xtal Oscillator (READY mode), calibrating the VCO and tuning the PLL Synthesizer (TX_TUNE mode), enabling the PA and transmission of the packet (TX mode), and returning to an IDLE state. This sequencing is normally handled by the internal state machine.
  - This command provides for manually switching to a desired operating state.
  - This command may be used to enter TX or RX mode, if desired. However, those modes of operation typically require specification of additional parameters (e.g., channel number, number of packet bytes, etc.) prior to switching mode. For this reason, separate START_TX and START_RX commands are provided that essentially accomplish the CHANGE_STATE = TX or RX functionality, while simultaneously passing the required parameter bytes.
- Argument Stream:

  CHANGE_STATE Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x34
  | 0x01 | NEXT_STATE1 | 0 | 0 | 0 | 0 | NEW_STATE

- Reply Stream:

  CHANGE_STATE Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CTS | CTS

- Argument Fields:

  ###### NEXT_STATE1

  NEW_STATE[3:0]
  Description:
    Operating state to switch to immediately. Please refer to the published datasheet for more details regarding these operational modes.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    NOCHANGE | 0 | No change, remain in current state. | revB1A
    SLEEP | 1 | SLEEP state. | revB1A
    SPI_ACTIVE | 2 | SPI_ACTIVE state. | revB1A
    READY | 3 | READY state. | revB1A
    TX_TUNE | 5 | TX_TUNE state. | revB1A
    RX_TUNE | 6 | RX_TUNE state. | revB1A
    TX | 7 | TX state. | revB1A
    RX | 8 | RX state. | revB1A

- Reply Fields:

  ###### CTS

  CTS[7:0]
  Description:
    Clear to Send. Indicates that the previous command has completed execution and the response byte stream (if any) is valid. The next command may be sent.
  Type:
    U8

#### READ_CMD_BUFF

- Number: 0x44
- Summary: Used to read CTS and the command response.
- Purpose:
  - Processing of API commands is handled by the command handler in the chip. A subsequent command may not be sent until the chip has completed processing of the first command. The chip indicates the ability to receive another command and the availability of response data by issuing a Clear To Send (CTS) signal; it is necessary for the host MCU to poll the chip for this CTS signal. The CTS signal may be polled via SPI command, or monitored on a GPIO line or as an interrupt on the nIRQ pin.
  - This command is used to poll the CTS signal via the SPI bus. The NSEL line should be pulled low, followed by sending the READ_CMD_BUFF command on SDI. While NSEL remains asserted low, an additional eight clock pulses are sent on SCLK and the CTS response byte is read on SDO. If the CTS response byte is not 0xFF, the host MCU should pull NSEL high and repeat the polling procedure.
  - If the CTS response byte is 0xFF, the host MCU should keep NSEL asserted low and provide additional clock cycles on SCLK to read out as many response bytes (on SDO) as necessary. The host MCU should pull NSEL high upon completion of reading the response stream.
  - A primary function of this command is to determine when CTS goes high, and thus by definition this command may be sent while CTS is low. This command itself does not cause CTS to go low.
  - Attempting to read response bytes from the command buffer while CTS is not 0xFF will return invalid results. The response bytes are valid only if CTS = 0xFF.
- Argument Stream:

  READ_CMD_BUFF Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x44

- Reply Stream:

  READ_CMD_BUFF Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CTS | CTS
  | 0x01 | BYTE[0] | CMD_BUFF
  | ... | ... | ...
  | 0x10 | BYTE[15] | CMD_BUFF

- Argument Fields:
- Reply Fields:

  ###### CTS

  CTS[7:0]
  Description:
    Clear to Send. Indicates that the previous command has completed execution and the response byte stream (if any) is valid. The next command may be sent.
  Type:
    U8

  ###### BYTE[0...15]

  CMD_BUFF[7:0]
  Description:
    Byte 0-15 of the command response buffer.
  Type:
    U8

#### FRR_A_READ

- Number: 0x50
- Summary: Reads the fast response registers (FRR) starting with FRR_A.
- Purpose:
  - The chip provides four Fast Response Registers (FRR) that may be read immediately without the need to monitor and check CTS, thus improving the speed at which the contents may be retrieved.
  - The FRR registers may be read in a burst fashion through the FRR_X_READ commands. After the initial 16 clock cycles, each additional eight clock cycles will clock out the contents of the next fast response register in a circular fashion. Example: If the FRR_A_READ command is issued, the registers will be read in the order A-B-C-D, while if the FRR_B_READ command is issued, the registers will be read in the order B-C-D-A, etc.
  - This command does not cause CTS to go low, and can be sent and the reply read while CTS is low. The command ID should be clocked in on SDI then the reply should be clocked out on SDO without deasserting NSEL.
  - The FRR_CTL_X_MODE properties are used to select the specific parameter values that will be returned by the FRR_X_READ commands. Please refer to the text description for FRR_CTL_X_MODE for more details regarding selection of the parameter(s) held within the FRR registers.
- Argument Stream:

  FRR_A_READ Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x50

- Reply Stream:

  FRR_A_READ Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | FRR_A_VALUE | FRR_A_VALUE
  | 0x01 | FRR_B_VALUE | FRR_B_VALUE
  | 0x02 | FRR_C_VALUE | FRR_C_VALUE
  | 0x03 | FRR_D_VALUE | FRR_D_VALUE

- Argument Fields:
- Reply Fields:

  ###### FRR_A_VALUE

  FRR_A_VALUE[7:0]
  Description:
    Value in Fast Response Register A.
  Type:
    U8

  ###### FRR_B_VALUE

  FRR_B_VALUE[7:0]
  Description:
    Value in Fast Response Register B.
  Type:
    U8

  ###### FRR_C_VALUE

  FRR_C_VALUE[7:0]
  Description:
    Value in Fast Response Register C.
  Type:
    U8

  ###### FRR_D_VALUE

  FRR_D_VALUE[7:0]
  Description:
    Value in Fast Response Register D.
  Type:
    U8

#### FRR_B_READ

- Number: 0x51
- Summary: Reads the fast response registers (FRR) starting with FRR_B.
- Purpose:
  - The chip provides four Fast Response Registers (FRR) that may be read immediately without the need to monitor and check CTS, thus improving the speed at which the contents may be retrieved.
  - The FRR registers may be read in a burst fashion through the FRR_X_READ commands. After the initial 16 clock cycles, each additional eight clock cycles will clock out the contents of the next fast response register in a circular fashion. Example: If the FRR_A_READ command is issued, the registers will be read in the order A-B-C-D, while if the FRR_B_READ command is issued, the registers will be read in the order B-C-D-A, etc.
  - This command does not cause CTS to go low, and can be sent and the reply read while CTS is low. The command ID should be clocked in on SDI then the reply should be clocked out on SDO without deasserting NSEL.
  - The FRR_CTL_X_MODE properties are used to select the specific parameter values that will be returned by the FRR_X_READ commands. Please refer to the text description for FRR_CTL_X_MODE for more details regarding selection of the parameter(s) held within the FRR registers.
- Argument Stream:

  FRR_B_READ Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x51

- Reply Stream:

  FRR_B_READ Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | FRR_B_VALUE | FRR_B_VALUE
  | 0x01 | FRR_C_VALUE | FRR_C_VALUE
  | 0x02 | FRR_D_VALUE | FRR_D_VALUE
  | 0x03 | FRR_A_VALUE | FRR_A_VALUE

- Argument Fields:
- Reply Fields:

  ###### FRR_B_VALUE

  FRR_B_VALUE[7:0]
  Description:
    Value in Fast Response Register B.
  Type:
    U8

  ###### FRR_C_VALUE

  FRR_C_VALUE[7:0]
  Description:
    Value in Fast Response Register C.
  Type:
    U8

  ###### FRR_D_VALUE

  FRR_D_VALUE[7:0]
  Description:
    Value in Fast Response Register D.
  Type:
    U8

  ###### FRR_A_VALUE

  FRR_A_VALUE[7:0]
  Description:
    Value in Fast Response Register A.
  Type:
    U8

#### FRR_C_READ

- Number: 0x53
- Summary: Reads the fast response registers (FRR) starting with FRR_C.
- Purpose:
  - The chip provides four Fast Response Registers (FRR) that may be read immediately without the need to monitor and check CTS, thus improving the speed at which the contents may be retrieved.
  - The FRR registers may be read in a burst fashion through the FRR_X_READ commands. After the initial 16 clock cycles, each additional eight clock cycles will clock out the contents of the next fast response register in a circular fashion. Example: If the FRR_A_READ command is issued, the registers will be read in the order A-B-C-D, while if the FRR_B_READ command is issued, the registers will be read in the order B-C-D-A, etc.
  - This command does not cause CTS to go low, and can be sent and the reply read while CTS is low. The command ID should be clocked in on SDI then the reply should be clocked out on SDO without deasserting NSEL.
  - The FRR_CTL_X_MODE properties are used to select the specific parameter values that will be returned by the FRR_X_READ commands. Please refer to the text description for FRR_CTL_X_MODE for more details regarding selection of the parameter(s) held within the FRR registers.
- Argument Stream:

  FRR_C_READ Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x53

- Reply Stream:

  FRR_C_READ Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | FRR_C_VALUE | FRR_C_VALUE
  | 0x01 | FRR_D_VALUE | FRR_D_VALUE
  | 0x02 | FRR_A_VALUE | FRR_A_VALUE
  | 0x03 | FRR_B_VALUE | FRR_B_VALUE

- Argument Fields:
- Reply Fields:

  ###### FRR_C_VALUE

  FRR_C_VALUE[7:0]
  Description:
    Value in Fast Response Register C.
  Type:
    U8

  ###### FRR_D_VALUE

  FRR_D_VALUE[7:0]
  Description:
    Value in Fast Response Register D.
  Type:
    U8

  ###### FRR_A_VALUE

  FRR_A_VALUE[7:0]
  Description:
    Value in Fast Response Register A.
  Type:
    U8

  ###### FRR_B_VALUE

  FRR_B_VALUE[7:0]
  Description:
    Value in Fast Response Register B.
  Type:
    U8

#### FRR_D_READ

- Number: 0x57
- Summary: Reads the fast response registers (FRR) starting with FRR_D.
- Purpose:
  - The chip provides four Fast Response Registers (FRR) that may be read immediately without the need to monitor and check CTS, thus improving the speed at which the contents may be retrieved.
  - The FRR registers may be read in a burst fashion through the FRR_X_READ commands. After the initial 16 clock cycles, each additional eight clock cycles will clock out the contents of the next fast response register in a circular fashion. Example: If the FRR_A_READ command is issued, the registers will be read in the order A-B-C-D, while if the FRR_B_READ command is issued, the registers will be read in the order B-C-D-A, etc.
  - This command does not cause CTS to go low, and can be sent and the reply read while CTS is low. The command ID should be clocked in on SDI then the reply should be clocked out on SDO without deasserting NSEL.
  - The FRR_CTL_X_MODE properties are used to select the specific parameter values that will be returned by the FRR_X_READ commands. Please refer to the text description for FRR_CTL_X_MODE for more details regarding selection of the parameter(s) held within the FRR registers.
- Argument Stream:

  FRR_D_READ Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x57

- Reply Stream:

  FRR_D_READ Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | FRR_D_VALUE | FRR_D_VALUE
  | 0x01 | FRR_A_VALUE | FRR_A_VALUE
  | 0x02 | FRR_B_VALUE | FRR_B_VALUE
  | 0x03 | FRR_C_VALUE | FRR_C_VALUE

- Argument Fields:
- Reply Fields:

  ###### FRR_D_VALUE

  FRR_D_VALUE[7:0]
  Description:
    Value in Fast Response Register D.
  Type:
    U8

  ###### FRR_A_VALUE

  FRR_A_VALUE[7:0]
  Description:
    Value in Fast Response Register A.
  Type:
    U8

  ###### FRR_B_VALUE

  FRR_B_VALUE[7:0]
  Description:
    Value in Fast Response Register B.
  Type:
    U8

  ###### FRR_C_VALUE

  FRR_C_VALUE[7:0]
  Description:
    Value in Fast Response Register C.
  Type:
    U8

### TX_COMMANDS

#### START_TX

- Number: 0x31
- Summary: Switches to TX state and starts transmission of a packet.
- Purpose:
  - This command switches the chip to TX state and begins transmission of a packet. Depending upon the value of the START parameter, the start of transmission may be delayed until a certain condition is met.
  - Several optional parameters may be passed with this command. If these parameter values are not sent, their previously configured values remain in use. The parameter values are retained while in SLEEP mode, and thus only need to be written when they change.
  - The chip may be configured to automatically enter a desired operational state after transmission of the packet.
  - The chip will not return CTS high until the chip has entered the TX state.
- Argument Stream:

  START_TX Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x31
  | 0x01 | CHANNEL | CHANNEL
  | 0x02 | CONDITION | TXCOMPLETE_STATE | 0 | RETRANSMIT | 00
  | 0x03 | TX_LEN | 0 | 0 | 0 | TX_LEN[12:8]
  0x04 | TX_LEN[7:0]
  | 0x05 | TX_DELAY | TX_DELAY

- Reply Stream:

  START_TX Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CTS | CTS

- Argument Fields:

  ###### CHANNEL

  CHANNEL[7:0]
  Description:
    - Selects the channel number on which to transmit. Please refer to FREQ_CONTROL_CHANNEL_STEP_SIZE for more details regarding the channelized approach to frequency tuning of the chip.
    - If the CHANNEL parameter byte is not passed with the command, the chip will tune to the last channel specified in either a START_TX or START_RX command; the internal variable that retains the CHANNEL value is shared by these two commands.
  Type:
    U8
  Min:
    0x0
  Max:
    0xff

  ###### CONDITION

  TXCOMPLETE_STATE[3:0]
  Description:
    - This parameter selects the desired operational state of the chip to automatically enter upon completion of the packet transmission.
    - If this parameter is not passed with the command, the chip continues to use the previously configured value. If no value has been previously configured (i.e., upon POWER_UP), the default value of 3 = READY state is used.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    NOCHANGE | 0 | Do not change from previously sent TXCOMPLETE_STATE. (No Change does not have the effect of remaining in TX mode.) | revB1A
    SLEEP | 1 | SLEEP or STANDBY state, according to the mode of operotion of the 32K R-C Osc selected by GLOBAL_CLK_CFG:CLK_32K_SEL. | revB1A
    SPI_ACTIVE | 2 | SPI ACTIVE state. | revB1A
    READY | 3 | READY state. | revB1A
    READY2 | 4 | Another enumeration for READY state. | revB1A
    TX_TUNE | 5 | TX_TUNE state. | revB1A
    RX_TUNE | 6 | RX_TUNE state. | revB1A
    TX | 7 | TX state. | revC2A
    RX | 8 | RX state. | revB1A

  RETRANSMIT
  Description:
    - Selects whether the current packet will simply be a retransmission of the previous packet, or whether the current packet will transmit new data from the TX FIFO.
    - In the event of a retransmission, new (additional) data should not be written to the TX FIFO prior to the retransmission.
    - The RETRANSMIT bit should be set prior to sending the first packet, as well as on all subsequent retransmissions.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Send data that has been written to the TX FIFO. If the TX FIFO is empty, a FIFO underflow interrupt will occur. | revB1A
    ENUM_1 | 1 | Send last packet again. | revB1A

  ###### TX_LEN

  TX_LEN[12:0]
  Description:
    - Specifies the number of bytes to transmit in the data field(s) of the packet.
    - If this field is non-zero, the packet will be transmitted with TX_LEN number of data bytes, using the data field configuration options (e.g., CRC, data whitening, Manchester coding, etc.) of only PKT_FIELD_1_X. The Payload length is limited to 8191 bytes in this scenario.
    - If this field is zero, the number of data bytes to be transmitted is specified by the value(s) of the PKT_FIELD_X_LENGTH properties. The Payload length is limited to 5 x 8191 = 40955 bytes in this scenario (as each of the five data fields may be configured for a length of 8191 bytes). This approach is necessary if field-specific processing is desired (e.g., data whitening on one field but not another, Manchester coding on one field but not another, etc).
    - The TX_LEN parameter should still be passed even if the RETRANSMIT bit is set.
  Type:
    U16
  Min:
    0x0
  Max:
    0x1fff

  ###### TX_DELAY

  TX_DELAY[7:0]
  Description:
    Specifies a time delay (in µsec) between transmissions of packets, in the event another transmission is scheduled.
  Type:
    U8
  Min:
    0x0
  Max:
    0x80
- Reply Fields:

  ###### CTS

  CTS[7:0]
  Description:
    Clear to Send. Indicates that the previous command has completed execution and the response byte stream (if any) is valid. The next command may be sent.
  Type:
    U8

#### WRITE_TX_FIFO

- Number: 0x66
- Summary: Writes data byte(s) to the TX FIFO.
- Purpose:
  - The chip provides for two separate 64-byte FIFO memories for the purpose of storing transmit and receive data.
  - This command is used to write data byte(s) into the TX FIFO. The WRITE_TX_FIFO command should be clocked in on SDI (followed by the data byte(s) to be written) without deasserting NSEL. If you write more data bytes than the TX FIFO can hold it will generate a FIFO Overflow interrupt event.
  - This command does not cause CTS to go low, and can be sent while CTS is low. This command has no response to be read and thus there is no need to monitor CTS after sending this command.
- Argument Stream:

  WRITE_TX_FIFO Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x66
  | 0x01 | DATA[0] | DATA
  | ... | ... | ...
  | M | DATA[N] | DATA

- Argument Fields:

  ###### DATA[0...N]

  (indefinite length array stream)
  DATA[7:0]
  Description:
    Data to write to the TX FIFO
  Type:
    U8

### RX_COMMANDS

#### PACKET_INFO

- Number: 0x16
- Summary: Returns information about the length of the variable field in the last packet received, and (optionally) overrides field length.
- Purpose:
  - The chip provides the ability for receiving packets in which one of the Payload field(s) is variable in length, with its length specified by received byte(s) embedded within a prior fixed-length field. This command may be used to retrieve the value of the length byte(s) (i.e., return the length of the variable length field). Please refer to the text descriptions for PKT_LEN and PKT_LEN_FIELD_SOURCE for more details regarding reception of a variable length packet.
  - The value returned by this command describes the length of only the variable length field pointed to by the PKT_LEN:DST_FIELD parameter. This value may not be the same as the total length of the Payload, as the Payload may consist of several fixed-length fields in addition to the variable-length field. If no previous variable-length packet has been received, the return value will be 0.
  - The LENGTH[15:0] response value is cleared upon entry into RX mode; therefore, the PACKET_INFO command should be sent after reception of a valid packet and prior to re-entering RX mode, else the response value will always be zero.
  - This command may be issued with five optional arguments. If these arguments follow, their values are used to override the packet length value that was originally configured by issuing the START_RX command with a non-zero RX_LEN value, or by programming the PKT_RX_FIELD_X_LENGTH properties.
  - This feature is provided to support variable-length packet functionality in applications where the length value cannot be extracted by the chip itself (due to special encoding, e.g., 3-of-6 encoding). In such an application, all data fields are defined as fixed-length fields; the host MCU decodes the received length byte(s) in the first field and subsequently issues the PACKET_INFO command during reception of the RX packet to modify the "fixed" length of a subsequent field. Please contact Silicon Labs Support for assistance with this functionality.
  - In 802.15.4g receive mode, the FCS byte length embedded in the FHR is included to inform the host of the number of FCS bytes in the FIFO following the MAC Payload. If FCS is 0, 2 is added to the return length; if FCS is 1, 4 is added to the return length.
- Argument Stream:

  PACKET_INFO Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x16
  | 0x01 | FIELD_NUMBER | 0 | 0 | 0 | FIELD_NUM
  | 0x02 | LEN | LEN[15:8]
  0x03 | LEN[7:0]
  | 0x04 | LEN_DIFF | LEN_DIFF[15:8]
  0x05 | LEN_DIFF[7:0]

- Reply Stream:

  PACKET_INFO Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CTS | CTS
  | 0x01 | LENGTH | LENGTH[15:8]
  0x02 | LENGTH[7:0]

- Argument Fields:

  ###### FIELD_NUMBER

  FIELD_NUM[4:0]
  Description:
    Selects the data field whose length will be modified per the LEN[15:0] and LEN_DIFF[15:0] parameters.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Do not override the length of any data fields. |
    ENUM_1 | 1 | Override the programmed value of PKT_FIELD_1_LENGTH, or the value of RX_LEN in the START_RX command. |
    ENUM_2 | 2 | Override the programmed value of PKT_FIELD_2_LENGTH. |
    ENUM_3 | 4 | Override the programmed value of PKT_FIELD_3_LENGTH. |
    ENUM_4 | 8 | Override the programmed value of PKT_FIELD_4_LENGTH. |
    ENUM_5 | 16 | Override the programmed value of PKT_FIELD_5_LENGTH. |

  ###### LEN

  LEN[15:0]
  Description:
    Selects the new length (in bytes) of the data field specified by the FIELD_NUM parameter.
  Type:
    U16
  Min:
    0x1
  Max:
    0x1fff

  ###### LEN_DIFF

  LEN_DIFF[15:0]
  Description:
    - Specifies the difference (in bytes) between the new length value (specified in LEN[15:0]) and the original length value (specified in the corresponding PKT_FIELD_X_LENGTH property, or passed in the START_RX:RX_LEN parameter).
    - This is a signed 16-bit value, with a positive value indicating an increase in field length and a negative value indicating a decrease in field length.
    - Passing the LEN_DIFF parameter as part of the PACKET_INFO command improves the speed with which the chip can process the requested change in packet length (compared with the chip internally performing that computation).
  Type:
    S16
  Min:
    -0x8000
  Max:
    0x7fff
- Reply Fields:

  ###### CTS

  CTS[7:0]
  Description:
    Clear to Send. Indicates that the previous command has completed execution and the response byte stream (if any) is valid. The next command may be sent.
  Type:
    U8

  ###### LENGTH

  LENGTH[15:0]
  Description:
    Returns the variable length field value, extracted from the last received variable-length packet
  Type:
    U16

#### GET_MODEM_STATUS

- Number: 0x22
- Summary: Returns the interrupt status of the Modem Interrupt Group (both STATUS and PENDING). Optionally, it may be used to clear latched (PENDING) interrupt events.
- Purpose:
  - Returns the current interrupt status of Modem interrupt events (both STATUS and PENDING) and optionally clears PENDING interrupts.
  - Please refer to the GET_INT_STATUS command for more details regarding the difference between STATUS and PENDING interrupts.
  - Sending the GET_MODEM_STATUS command with NO input parameter results in clearing all of the PENDING interrupts.
  - When PENDING interrupts are being cleared, the reply stream reflects their status prior to clearing.
- Argument Stream:

  GET_MODEM_STATUS Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x22
  | 0x01 | MODEM_CLR_PEND | RSSI_LATCH_PEND_CLR | 0 | INVALID_SYNC_PEND_CLR | 0 | RSSI_PEND_CLR | INVALID_PREAMBLE_PEND_CLR | PREAMBLE_DETECT_PEND_CLR | SYNC_DETECT_PEND_CLR

- Reply Stream:

  GET_MODEM_STATUS Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CTS | CTS
  | 0x01 | MODEM_PEND | RSSI_LATCH_PEND | X | INVALID_SYNC_PEND | X | RSSI_PEND | INVALID_PREAMBLE_PEND | PREAMBLE_DETECT_PEND | SYNC_DETECT_PEND
  | 0x02 | MODEM_STATUS | RSSI_LATCH | X | INVALID_SYNC | X | RSSI | INVALID_PREAMBLE | PREAMBLE_DETECT | SYNC_DETECT
  | 0x03 | CURR_RSSI | CURR_RSSI
  | 0x04 | LATCH_RSSI | LATCH_RSSI
  | 0x05 | RESERVED0 | X | X | X | X | X | X | X | X
  | 0x06 | RESERVED1 | X | X | X | X | X | X | X | X
  | 0x07 | AFC_FREQ_OFFSET | AFC_FREQ_OFFSET[15:8]
  0x08 | AFC_FREQ_OFFSET[7:0]

- Argument Fields:

  ###### MODEM_CLR_PEND

  RSSI_LATCH_PEND_CLR
  Description:
    If clear, clear any pending RSSI_LATCH interrupt. If set, leave interrupt pending.
  Type:
    BOOL
  INVALID_SYNC_PEND_CLR
  Description:
    If clear, clear any pending INVALID_SYNC interrupt. If set, leave interrupt pending.
  Type:
    BOOL
  RSSI_PEND_CLR
  Description:
    If clear, clear any pending RSSI interrupt. If set, leave interrupt pending.
  Type:
    BOOL
  INVALID_PREAMBLE_PEND_CLR
  Description:
    If clear, clear any pending INVALID_PREAMBLE interrupt. If set, leave interrupt pending.
  Type:
    BOOL
  PREAMBLE_DETECT_PEND_CLR
  Description:
    If clear, clear any pending PREAMBLE_DETECT interrupt. If set, leave interrupt pending.
  Type:
    BOOL
  SYNC_DETECT_PEND_CLR
  Description:
    If clear, clear any pending SYNC_DETECT interrupt. If set, leave interrupt pending.
  Type:
    BOOL
- Reply Fields:

  ###### CTS

  CTS[7:0]
  Description:
    Clear to Send. Indicates that the previous command has completed execution and the response byte stream (if any) is valid. The next command may be sent.
  Type:
    U8

  ###### MODEM_PEND

  RSSI_LATCH_PEND
  Description:
    If set, a rising edge of the RSSI_LATCH status bit has been detected and therefore a RSSI_LATCH interrupt is pending. See associated RSSI_LATCH status bit for more details.
  Type:
    BOOL
  INVALID_SYNC_PEND
  Description:
    If set, a rising edge of the INVALID_SYNC status bit has been detected and therefore a INVALID_SYNC interrupt is pending. See associated INVALID_SYNC status bit for more details.
  Type:
    BOOL
  RSSI_PEND
  Description:
    If set, a rising edge of the RSSI status bit has been detected and therefore a RSSI interrupt is pending. See associated RSSI status bit for more details.
  Type:
    BOOL
  INVALID_PREAMBLE_PEND
  Description:
    If set, a rising edge of the INVALID_PREAMBLE status bit has been detected and therefore a INVALID_PREAMBLE interrupt is pending. See associated INVALID_PREAMBLE status bit for more details.
  Type:
    BOOL
  PREAMBLE_DETECT_PEND
  Description:
    If set, a rising edge of the PREAMBLE_DETECT status bit has been detected and therefore a PREAMBLE_DETECT interrupt is pending. See associated PREAMBLE_DETECT status bit for more details.
  Type:
    BOOL
  SYNC_DETECT_PEND
  Description:
    If set, a rising edge of the SYNC_DETECT status bit has been detected and therefore a SYNC_DETECT interrupt is pending. See associated SYNC_DETECT status bit for more details.
  Type:
    BOOL

  ###### MODEM_STATUS

  RSSI_LATCH
  Description:
    Set if the latched RSSI value (defined in MODEM_RSSI_CONTROL has exceeded the threshold value defined in the MODEM_RSSI_THRESH property. Cleared upon entry into RX state or if RX is restarted.
  Type:
    BOOL
  INVALID_SYNC
  Description:
    Self clearing signal that pulses high when a valid Sync Word (matching the pattern of bits defined in the SYNC_BITS_XX properties) was not detected within the allowed search timeout period. If configured to receive a standard preamble, the search timeout period is Sync Word Length + 4bits. If configured to receive a non-standard preamble, the search timeout period is defined by the EZConfig array.
  Type:
    BOOL
  RSSI
  Description:
    Set if the current RSSI value has exceeded the threshold value defined by the EZConfig array.Cleared upon entry into RX state or if RX is restarted.
  Type:
    BOOL
  INVALID_PREAMBLE
  Description:
    Self clearing signal that pulses high indicating that one of the following has occurred: a) a valid Preamble was not detected within the allowed search timeout period, or b) the Latched RSSI value is below the rssi threshold set as part of the EZConfig array and the chip has been enabled to check for this condition. The search timeout period for Preamble and the CHECK_THRESH_AT_LATCH function are configured in the EZConfig array.
  Type:
    BOOL
  PREAMBLE_DETECT
  Description:
    Set when a pattern of bits was received that matched the expected Preamble pattern. If configured to receive a standard preamble, the expected pattern of bits is '...010101...' with a threshold length defined in the EZConfig array. If configured to receive a non-standard preamble, the expected pattern of bits is defined by the PREAMBLE_PATTERN_XX properties and the pattern length defined in the EZConfig array. Cleared when SYNC is detected, upon entering RX state, or RX is restarted.
  Type:
    BOOL
  SYNC_DETECT
  Description:
    Set when the received Sync Word pattern matched the pattern of bits defined in the SYNC_BITS property. If SYNC_CONFIG2:DUAL_SYNC_EN is enabled, the pattern in SYNC_BITS2 is also used to match. Cleared when a packet is received (valid or invalid), upon entry into RX state, or if RX is restarted.
  Type:
    BOOL

  ###### CURR_RSSI

  CURR_RSSI[7:0]
  Description:
    Current RSSI reading from the modem.
  Type:
    U8

  ###### LATCH_RSSI

  LATCH_RSSI[7:0]
  Description:
    Latched RSSI reading from the modem as configured by MODEM_RSSI_CONTROL. Reset to 0 upon entering RX mode or if RX is restarted.
  Type:
    U8

  ###### AFC_FREQ_OFFSET

  AFC_FREQ_OFFSET[15:0]
  Description:
    The AFC value that is generated by the PLL AFC feedback loop during receive mode.
  Type:
    U16

#### START_RX

- Number: 0x32
- Summary: Switches to RX state and starts reception of a packet.
- Purpose:
  - This command switches the chip to RX state and begins reception of a packet. Depending upon the value of the START parameter, the start of reception may be delayed until a certain condition is met.
  - Several optional parameters may be passed with this command. If these parameter values are not sent, their previously configured values remain in use. The parameter values are retained while in SLEEP mode, and thus only need to be written when they change.
  - The chip may be configured to automatically enter different operational states after reception of the packet, depending upon the success or failure of the packet reception.
  - The chip will not return CTS high until the chip has entered the RX state.
- Argument Stream:

  START_RX Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x32
  | 0x01 | CHANNEL | CHANNEL
  | 0x02 | RESERVED0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
  | 0x03 | RX_LEN | 0 | 0 | 0 | RX_LEN[12:8]
  0x04 | RX_LEN[7:0]
  | 0x05 | NEXT_STATE1 | 0 | 0 | 0 | 0 | RXTIMEOUT_STATE
  | 0x06 | NEXT_STATE2 | 0 | 0 | 0 | 0 | RXVALID_STATE
  | 0x07 | NEXT_STATE3 | 0 | 0 | 0 | 0 | RXINVALID_STATE

- Reply Stream:

  START_RX Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CTS | CTS

- Argument Fields:

  ###### CHANNEL

  CHANNEL[7:0]
  Description:
    - Selects the channel number on which to receive. Please refer to FREQ_CONTROL_CHANNEL_STEP_SIZE for more details regarding the channelized approach to frequency tuning of the chip.
    - If the CHANNEL parameter byte is not passed with the command, the chip will tune to the last channel specified in either a START_TX or START_RX command ; the internal variable that retains the CHANNEL value is shared by these two commands.
  Type:
    U8
  Min:
    0x0
  Max:
    0xff

  ###### RX_LEN

  RX_LEN[12:0]
  Description:
    - Specifies the number of bytes to receive in the data field(s) of the packet.
    - If this field is non-zero, the packet will be received with RX_LEN number of data bytes, using the data field configuration options (e.g., CRC, data whitening, Manchester coding, etc.) of only PKT_FIELD_1_X. The Payload length is limited to 8191 bytes in this scenario.
    - If this field is zero, the number of data bytes to be received is specified by the value(s) of the PKT_FIELD_X_LENGTH properties. The Payload length is limited to 5 x 8191 = 40955 bytes in this scenario (as each of the five data fields may be configured for a length of 8191 bytes). This approach is necessary if field-specific processing is desired (e.g., data whitening on one field but not another, Manchester coding on one field but not another, etc).
  Type:
    U16
  Min:
    0x0
  Max:
    0x1fff

  ###### NEXT_STATE1

  RXTIMEOUT_STATE[3:0]
  Description:
    - This parameter selects the desired operational state of the chip to automatically enter upon timeout of Preamble detection. Please refer to PREAMBLE_CONFIG_STD_2 for details regarding configuration of Preamble detection timeout.
    - If this parameter is not passed with the command, the chip continues to use the previously configured value. If no value has been previously configured (i.e., upon POWER_UP), the default value of 0 = Remain in RX state is used.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    NOCHANGE | 0 | Remain in RX state if RXTIMEOUT occurs. |
    SLEEP | 1 | SLEEP or STANDBY state, according to the mode of operation of the 32K R-C Osc selected by GLOBAL_CLK_CFG:CLK_32K_SEL. |
    SPI_ACTIVE | 2 | SPI ACTIVE state. |
    READY | 3 | READY state. |
    READY2 | 4 | Another enumeration for READY state. |
    TX_TUNE | 5 | TX_TUNE state. |
    RX_TUNE | 6 | RX_TUNE state. |
    TX | 7 | TX state. |
    RX | 8 | RX state (briefly exit and re-enter RX state to re-arm for acquisition of another packet). |
    RX_IDLE | 9 | RX_IDLE state. |

  ###### NEXT_STATE2

  RXVALID_STATE[3:0]
  Description:
    - This parameter selects the desired operational state of the chip to automatically enter upon reception of a valid packet. A packet is considered valid if the CRC check passes, and if the MATCH byte check is verified (if enabled). If neither CRC nor MATCH functionality is enabled, a packet is considered valid when the specified number of bytes are received.
    - If this parameter is not passed with the command, the chip continues to use the previously configured value. If no value has been previously configured (i.e., upon POWER_UP), the default value of 3 = READY state is used.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    REMAIN | 0 | Remain in RX state (but do not re-arm to acquire another packet). | revB1A
    SLEEP | 1 | SLEEP or STANDBY state, according to the mode of operotion of the 32K R-C Osc selected by GLOBAL_CLK_CFG:CLK_32K_SEL. | revB1A
    SPI_ACTIVE | 2 | SPI ACTIVE state. | revB1A
    READY | 3 | READY state. | revB1A
    READY2 | 4 | Another enumeration for READY state. | revB1A
    TX_TUNE | 5 | TX_TUNE state. | revB1A
    RX_TUNE | 6 | RX_TUNE state. | revB1A
    TX | 7 | TX state. | revB1A
    RX | 8 | RX state (briefly exit and re-enter RX state to re-arm for acquisition of another packet). | revB1A

  ###### NEXT_STATE3

  RXINVALID_STATE[3:0]
  Description:
    - This parameter selects the desired operational state of the chip to automatically enter upon reception of an invalid packet. A packet is considered invalid if the CRC check fails or if the MATCH byte check fails (if enabled).
    - If this parameter is not passed with the command, the chip continues to use the previously configured value. If no value has been previously configured (i.e., upon POWER_UP), the default value of 3 = READY state is used.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    REMAIN | 0 | Remain in RX state (but do not re-arm to acquire another packet). | revB1A
    SLEEP | 1 | SLEEP or STANDBY state, according to the mode of operotion of the 32K R-C Osc selected by GLOBAL_CLK_CFG:CLK_32K_SEL. | revB1A
    SPI_ACTIVE | 2 | SPI ACTIVE state. | revB1A
    READY | 3 | READY state. | revB1A
    READY2 | 4 | Another enumeration for READY state. | revB1A
    TX_TUNE | 5 | TX_TUNE state. | revB1A
    RX_TUNE | 6 | RX_TUNE state. | revB1A
    TX | 7 | TX state. | revB1A
    RX | 8 | RX state (briefly exit and re-enter RX state to re-arm for acquisition of another packet). | revB1A

- Reply Fields:

  ###### CTS

  CTS[7:0]
  Description:
    Clear to Send. Indicates that the previous command has completed execution and the response byte stream (if any) is valid. The next command may be sent.
  Type:
    U8

#### READ_RX_FIFO

- Number: 0x77
- Summary: Reads data byte(s) from the RX FIFO.
- Purpose:
  - The chip provides for two separate 64-byte FIFO memories for the purpose of storing transmit and receive data.
  - This command is used to read data byte(s) from the RX FIFO. The READ_RX_FIFO command should be clocked in on SDI and the reply should be clocked out on SDO without deasserting NSEL. If you read more data bytes than the RX FIFO contains it will generate a FIFO Underflow interrupt event.
  - This command does not cause CTS to go low, and can be sent while CTS is low. This command has no response to be read and thus there is no need to monitor CTS after sending this command.
- Argument Stream:

  READ_RX_FIFO Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x77

- Reply Stream:

  READ_RX_FIFO Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | DATA[0] | DATA
  | ... | ... | ...
  | M | DATA[N] | DATA

- Argument Fields:
- Reply Fields:

  ###### DATA[0...N]

  (indefinite length array stream)
  DATA[7:0]
  Description:
    Data read from the RX FIFO
  Type:
    U8

### ADVANCED_COMMANDS

#### GET_ADC_READING

- Number: 0x14
- Summary: Performs conversions using the Auxiliary ADC and returns the results of those conversions.
- Purpose:
  - The chip provides an Auxiliary Analog-to-Digital Converter (ADC) for the purpose of measuring various analog parameters and returning their values in digital form. The ADC utilizes a Successive Approximation Register (SAR) architecture and achieves 11-bit resolution, with a 9-bit Effective Number of Bits (ENOB).
  - The ADC may be configured to measure the internal battery voltage, an internal temperature sensor, or an external voltage applied to a selected GPIO pin. More than one type of measurement may be enabled at the same time; the conversions will be performed sequentially and all converted values returned.
  - The ADC is capable of converting any battery voltage within the chip's operating supply voltage range of 1.8VDC to 3.6VDC.
  - The GPIO pin carrying the external voltage to be measured is selected by the ADC_GPIO_PIN parameter, and must also be configured as an input pin or tri-state pin (through the GPIO_PIN_CFG command).
  - The voltage on the selected GPIO pin may be internally attenuated prior to conversion, thus effectively extending the range of voltages which may be converted. The attenuation factor is configurable through the GPIO_ATT parameter.
- Argument Stream:

  GET_ADC_READING Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x14
  | 0x01 | ADC_EN | 0 | 0 | 0 | 0 | BATTERY_VOLTAGE_EN | ADC_GPIO_EN | ADC_GPIO_PIN
  | 0x02 | ADC_CFG | UDTIME | GPIO_ATT

- Reply Stream:

  GET_ADC_READING Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CTS | CTS
  | 0x01 | GPIO_ADC | X | X | X | X | X | GPIO_ADC[10:8]
  0x02 | GPIO_ADC[7:0]
  | 0x03 | BATTERY_ADC | X | X | X | X | X | BATTERY_ADC[10:8]
  0x04 | BATTERY_ADC[7:0]

- Argument Fields:

  ###### ADC_EN

  BATTERY_VOLTAGE_EN
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Do not perform ADC conversion of the battery voltage. The reply value in BATTERY_ADC will always be 0x000. | revB1A
    ENUM_1 | 1 | Perform ADC conversion of the battery voltage. The reply value in BATTERY_ADC will be VBAT(V) = 3*BATTERY_ADC/1280. | revB1A

  ADC_GPIO_EN
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Do not perform ADC conversion of the voltage applied to the selected GPIO pin. The reply value in GPIO_ADC will always be 0x000. | revB1A
    ENUM_1 | 1 | Perform ADC conversion of the voltage applied to the selected GPIO pin. The reply value in GPIO_ADC will be VGPIO(V) = GPIO_ADC/GPIO_ADC_DIV, where GPIO_ADC_DIV is an attenuation factor defined by the selection of the GPIO_ATT parameter. | revB1A

  ADC_GPIO_PIN[1:0]
  Description:
    - Select the GPIO pin on which to perform conversion of an externally applied voltage.
    - The selected GPIO pin must also be configured as an input pin or tri-state pin (through use of the GPIO_PIN_CFG command).
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | The voltage on GPIO0 will be converted by the ADC. | revB1A
    ENUM_1 | 1 | The voltage on GPIO1 will be converted by the ADC. | revB1A
    ENUM_2 | 2 | The voltage on GPIO2 will be converted by the ADC. | revB1A
    ENUM_3 | 3 | The voltage on GPIO3 will be converted by the ADC. | revB1A

  ###### ADC_CFG

  UDTIME[3:0]
  Description:
    - Selects the rate of ADC conversion, where ADC_RATE = SYS_CLK / 12 / 2^(UDTIME + 1). Selecting shorter conversion times (i.e., faster conversion rates) will result in lower ADC resolution and longer conversion times will result in higher ADC resolution.
    - An ADC conversion rate of 305 Hz (UDTIME = 0xC) to 1.22 kHz (UDTIME = 0xA) is recommended.
    - If the ADC_CFG parameter byte is not sent, or is set ADC_CFG = 0x00, the UDTIME parameter will assume a default value of 0xC = 305 Hz ADC conversion rate (for nominal SYS_CLK = 30 MHz).
  Type:
    U8
  GPIO_ATT[3:0]
  Description:
    - Selects the attenuation factor to be internally applied to the voltage on the GPIO pin, prior to conversion by the ADC. This effectively extends the range of voltages which may be converted.
    - If the ADC_CFG parameter byte is not sent, or is set ADC_CFG = 0x00, the GPIO_ATT parameter will assume a default value of 0x5 = 0 to 3.2V range.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    0P8 | 0 | ADC measurement range is 0 to 0.8 V. GPIO_ADC_DIV = 2560. | revB1A
    1P6 | 4 | ADC measurement range is 0 to 1.6 V. GPIO_ADC_DIV = 1280. | revB1A
    3P2 | 5 | ADC measurement range is 0 to 3.2 V. GPIO_ADC_DIV = 640. | revB1A
    2P4 | 8 | ADC measurement range is 0 to 2.4 V. GPIO_ADC_DIV = 853.33. | revB1A
    3P6 | 9 | ADC measurement range is 0 to 3.6 V. GPIO_ADC_DIV = 426.66. | revB1A

- Reply Fields:

  ###### CTS

  CTS[7:0]
  Description:
    Clear to Send. Indicates that the previous command has completed execution and the response byte stream (if any) is valid. The next command may be sent.
  Type:
    U8

  ###### GPIO_ADC

  GPIO_ADC[10:0]
  Description:
    - Returns the voltage on the selected GPIO pin, as converted by the Auxiliary ADC.
    - The reply value will be VGPIO(V) = GPIO_ADC/GPIO_ADC_DIV, where GPIO_ADC_DIV is an attenuation factor defined by the selection of the GPIO_ATT parameter.
  Type:
    U16

  ###### BATTERY_ADC

  BATTERY_ADC[10:0]
  Description:
    - Returns the battery voltage, as converted by the Auxiliary ADC.
    - The reply value will be VBAT(V) = 3*BATTERY_ADC/1280.
  Type:
    U16

#### GET_PH_STATUS

- Number: 0x21
- Summary: Returns the interrupt status of the Packet Handler Interrupt Group (both STATUS and PENDING). Optionally, it may be used to clear latched (PENDING) interrupt events.
- Purpose:
  - Returns the current interrupt status of Packet Handler interrupt events (both STATUS and PENDING) and optionally clears PENDING interrupts.
  - Please refer to the GET_INT_STATUS command for more details regarding the difference between STATUS and PENDING interrupts.
  - Sending the GET_PH_STATUS command with NO input parameter results in clearing all of the PENDING interrupts.
  - When PENDING interrupts are being cleared, the reply stream reflects their status prior to clearing.
- Argument Stream:

  GET_PH_STATUS Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x21
  | 0x01 | PH_CLR_PEND | 0 | 0 | PACKET_SENT_PEND_CLR | PACKET_RX_PEND_CLR | CRC_ERROR_PEND_CLR | ALT_CRC_ERROR_PEND_CLR | TX_FIFO_ALMOST_EMPTY_PEND_CLR | RX_FIFO_ALMOST_FULL_PEND_CLR

- Reply Stream:

  GET_PH_STATUS Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CTS | CTS
  | 0x01 | PH_PEND | X | X | PACKET_SENT_PEND | PACKET_RX_PEND | CRC_ERROR_PEND | ALT_CRC_ERROR_PEND | TX_FIFO_ALMOST_EMPTY_PEND | RX_FIFO_ALMOST_FULL_PEND
  | 0x02 | PH_STATUS | X | X | PACKET_SENT | PACKET_RX | CRC_ERROR | ALT_CRC_ERROR | TX_FIFO_ALMOST_EMPTY | RX_FIFO_ALMOST_FULL

- Argument Fields:

  ###### PH_CLR_PEND

  PACKET_SENT_PEND_CLR
  Description:
    If clear, clear any pending PACKET_SENT interrupt. If set, leave interrupt pending.
  Type:
    BOOL
  PACKET_RX_PEND_CLR
  Description:
    If clear, clear any pending PACKET_RX interrupt. If set, leave interrupt pending.
  Type:
    BOOL
  CRC_ERROR_PEND_CLR
  Description:
    If clear, clear any pending CRC_ERROR interrupt. If set, leave interrupt pending.
  Type:
    BOOL
  ALT_CRC_ERROR_PEND_CLR
  Description:
    If clear, clear any pending ALT_CRC_ERROR interrupt. If set, leave interrupt pending.
  Type:
    BOOL
  TX_FIFO_ALMOST_EMPTY_PEND_CLR
  Description:
    If clear, clear any pending TX_FIFO_ALMOST_EMPTY interrupt. If set, leave interrupt pending.
  Type:
    BOOL
  RX_FIFO_ALMOST_FULL_PEND_CLR
  Description:
    If clear, clear any pending RX_FIFO_ALMOST_FULL interrupt. If set, leave interrupt pending.
  Type:
    BOOL
- Reply Fields:

  ###### CTS

  CTS[7:0]
  Description:
    Clear to Send. Indicates that the previous command has completed execution and the response byte stream (if any) is valid. The next command may be sent.
  Type:
    U8

  ###### PH_PEND

  PACKET_SENT_PEND
  Description:
    If set, a rising edge of the PACKET_SENT status bit has been detected and therefore a PACKET_SENT interrupt is pending. See associated PACKET_SENT status bit for more details.
  Type:
    BOOL
  PACKET_RX_PEND
  Description:
    If set, a rising edge of the PACKET_RX status bit has been detected and therefore a PACKET_RX interrupt is pending. See associated PACKET_RX status bit for more details.
  Type:
    BOOL
  CRC_ERROR_PEND
  Description:
    If set, a rising edge of the CRC_ERROR status bit has been detected and therefore a CRC_ERROR interrupt is pending. See associated CRC_ERROR status bit for more details.
  Type:
    BOOL
  ALT_CRC_ERROR_PEND
  Description:
    If set, a rising edge of the ALT_CRC_ERROR status bit has been detected and therefore a ALT_CRC_ERROR interrupt is pending. See associated ALT_CRC_ERROR status bit for more details.
  Type:
    BOOL
  TX_FIFO_ALMOST_EMPTY_PEND
  Description:
    If set, a rising edge of the TX_FIFO_ALMOST_EMPTY status bit has been detected and therefore a TX_FIFO_ALMOST_EMPTY interrupt is pending. See associated TX_FIFO_ALMOST_EMPTY status bit for more details.
  Type:
    BOOL
  RX_FIFO_ALMOST_FULL_PEND
  Description:
    If set, a rising edge of the RX_FIFO_ALMOST_FULL status bit has been detected and therefore a RX_FIFO_ALMOST_FULL interrupt is pending. See associated RX_FIFO_ALMOST_FULL status bit for more details.
  Type:
    BOOL

  ###### PH_STATUS

  PACKET_SENT
  Description:
    Set to indicate that data bytes in the TX FIFO were transmitted successfully. Cleared upon entry into TX state.
  Type:
    BOOL
  PACKET_RX
  Description:
    Set to indicate that the expected number of data bytes have been successfully received and placed in the RX FIFO. All enabled Packet Handler functions (e.g., CRC check, Filter Matching) must be successfully completed in order to generate a PACKET_RX interrupt.
  Type:
    BOOL
  CRC_ERROR
  Description:
    Set to indicate that the received CRC checksum byte(s) do not match the calculated CRC checksum value. Cleared upon entry into RX state or if RX is restarted.
  Type:
    BOOL
  ALT_CRC_ERROR
  Description:
    Set to indicate that the received CRC checksum byte(s) do not match the calculated alternate CRC checksum value. For the difference between the two CRC engines (CRC, ALT_CRC), see PKT_CRC_CONFIG property. Cleared upon entry into RX state or if RX is restarted.
  Type:
    BOOL
  TX_FIFO_ALMOST_EMPTY
  Description:
    Set to indicate that the amount of space in the TX FIFO is equal to or greater than the threshold value for the TX FIFO provided by the ezconfig array. This interrupt may be used to signal the host MCU to store more data bytes into the TX FIFO, thus providing a means for handling packets with lengths greater than the size of the TX FIFO. Cleared if the amount of space in the TX FIFO is more than the threshold value for the TX FIFO provided by the ezconfig array.
  Type:
    BOOL
  RX_FIFO_ALMOST_FULL
  Description:
    Set to indicate that the number of bytes stored in the RX FIFO is equal to or greater than the threshold value for the RX FIFO provided by the ezconfig array. This interrupt may be used to signal the host MCU to read more data bytes from the RX FIFO, thus providing a means for handling packets with lengths greater than the size of the RX FIFO. Cleared if the amount of data in the RX FIFO is less than the threshold value for the RX FIFO provided by the ezconfig array.
  Type:
    BOOL

#### GET_CHIP_STATUS

- Number: 0x23
- Summary: Returns the interrupt status of the Chip Interrupt Group (both STATUS and PENDING). Optionally, it may be used to clear latched (PENDING) interrupt events.
- Purpose:
  - Returns the current interrupt status of Chip interrupt events (both STATUS and PENDING) and optionally clears PENDING interrupts.
  - Please refer to the GET_INT_STATUS command for more details regarding the difference between STATUS and PENDING interrupts.
  - Sending the GET_CHIP_STATUS command with NO input parameter results in clearing all of the PENDING interrupts.
  - When PENDING interrupts are being cleared, the reply stream reflects their status prior to clearing.
- Argument Stream:

  GET_CHIP_STATUS Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x23
  | 0x01 | CHIP_CLR_PEND | 0 | 0 | FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_CLR | STATE_CHANGE_PEND_CLR | CMD_ERROR_PEND_CLR | CHIP_READY_PEND_CLR | 0 | 0

- Reply Stream:

  GET_CHIP_STATUS Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CTS | CTS
  | 0x01 | CHIP_PEND | X | X | FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND | STATE_CHANGE_PEND | CMD_ERROR_PEND | CHIP_READY_PEND | X | X
  | 0x02 | CHIP_STATUS | X | X | FIFO_UNDERFLOW_OVERFLOW_ERROR | STATE_CHANGE | CMD_ERROR | CHIP_READY | X | X
  | 0x03 | CMD_ERR_STATUS | CMD_ERR_STATUS
  | 0x04 | CMD_ERR_CMD_ID | CMD_ERR_CMD_ID

- Argument Fields:

  ###### CHIP_CLR_PEND

  FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_CLR
  Description:
    If clear, clear any pending FIFO_UNDERFLOW_OVERFLOW_ERROR interrupt. If set, leave interrupt pending.
  Type:
    BOOL
  STATE_CHANGE_PEND_CLR
  Description:
    If clear, clear any pending STATE_CHANGE interrupt. If set, leave interrupt pending.
  Type:
    BOOL
  CMD_ERROR_PEND_CLR
  Description:
    If clear, clear any pending CMD_ERROR interrupt. If set, leave interrupt pending.
  Type:
    BOOL
  CHIP_READY_PEND_CLR
  Description:
    If clear, clear any pending CHIP_READY interrupt. If set, leave interrupt pending.
  Type:
    BOOL
- Reply Fields:

  ###### CTS

  CTS[7:0]
  Description:
    Clear to Send. Indicates that the previous command has completed execution and the response byte stream (if any) is valid. The next command may be sent.
  Type:
    U8

  ###### CHIP_PEND

  FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND
  Description:
    If set, a rising edge of the FIFO_UNDERFLOW_OVERFLOW_ERROR status bit has been detected and therefore a FIFO_UNDERFLOW_OVERFLOW_ERROR interrupt is pending. See associated FIFO_UNDERFLOW_OVERFLOW_ERROR status bit for more details.
  Type:
    BOOL
  STATE_CHANGE_PEND
  Description:
    If set, a rising edge of the STATE_CHANGE status bit has been detected and therefore a STATE_CHANGE interrupt is pending. See associated STATE_CHANGE status bit for more details.
  Type:
    BOOL
  CMD_ERROR_PEND
  Description:
    If set, a rising edge of the CMD_ERROR status bit has been detected and therefore a CMD_ERROR interrupt is pending. See associated CMD_ERROR status bit for more details.
  Type:
    BOOL
  CHIP_READY_PEND
  Description:
    If set, a rising edge of the CHIP_READY status bit has been detected and therefore a CHIP_READY interrupt is pending. See associated CHIP_READY status bit for more details.
  Type:
    BOOL

  ###### CHIP_STATUS

  FIFO_UNDERFLOW_OVERFLOW_ERROR
  Description:
    Set to indicate that the number of received or transmitted bytes exceeds the size of the RX or TX FIFO, respectively. Upon such an underflow/overflow event, the FIFO(s) will need to be reset. Cleared by issuing a FIFO_INFO command to reset the FIFOs.
  Type:
    BOOL
  STATE_CHANGE
  Description:
    Set to indicate a successful transition from one state to another operating state. Cleared when a state transition is in progress.
  Type:
    BOOL
  CMD_ERROR
  Description:
    Self clearing signal that pulses high to indicate an error has occurred in the processing of a command. For example, an incorrect command/property ID is sent, or an attempt was made to write a property that is outside of the given property group.
  Type:
    BOOL
  CHIP_READY
  Description:
    Set to indicate the chip (upon completion of the POWER_UP sequence) has reached the state where it is ready to accept commands. Cleared when the chip is shutdown.
  Type:
    BOOL

  ###### CMD_ERR_STATUS

  CMD_ERR_STATUS[7:0]
  Description:
    Last command error cause. Only valid if CMD_ERROR status bit is set.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    CMD_ERROR_NONE | 0 | No error. |
    CMD_ERROR_BAD_COMMAND | 16 | Bad command issued. |
    CMD_ERROR_BAD_ARG | 17 | Argment(s) in issued command were invalid. |
    CMD_ERROR_COMMAND_BUSY | 18 | Command was issued before previous command was completed. |
    CMD_ERROR_INVALID_STATE | 19 | Command issued was not allowed while in the current device state. |
    CMD_ERROR_BAD_BOOTMODE | 49 | Invalid bootmode supplied. |
    CMD_ERROR_BAD_PROPERTY | 64 | Bad Property ID was provided. |

  ###### CMD_ERR_CMD_ID

  CMD_ERR_CMD_ID[7:0]
  Description:
    Command ID that was being proccessed at the time of the last command error.
  Type:
    ENUM

### EZCONFIG_COMMANDS

#### EZCONFIG_CHECK

- Number: 0x19
- Summary: Validates the EZConfig array was written correctly.
- Purpose:
  - This command compares the calculated checksum of the written EZConfig against its expected value, and returns the result of that validation.
  - This command should be issued immediately following writing of the EZConfig array, and will return an error condition if issued at any other time.
- Argument Stream:

  EZCONFIG_CHECK Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x19
  | 0x01 | CHECKSUM | CHECKSUM[15:8]
  0x02 | CHECKSUM[7:0]

- Reply Stream:

  EZCONFIG_CHECK Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CTS | CTS
  | 0x01 | RESULT | RESULT

- Argument Fields:

  ###### CHECKSUM

  CHECKSUM[15:0]
  Description:
    Expected checksum of the EZConfig array passed to the chip.
  Type:
    U16
- Reply Fields:

  ###### CTS

  CTS[7:0]
  Description:
    Clear to Send. Indicates that the previous command has completed execution and the response byte stream (if any) is valid. The next command may be sent.
  Type:
    U8

  ###### RESULT

  RESULT[7:0]
  Description:
    Returns the result of comparing the expected checksum value against the calculated checksum of the written EZConfig array.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    VALID | 0 | EZConfig array is valid. The chip is now in normal operating state. |
    BAD_CHECKSUM | 1 | EZConfig array is invalid. EZConfig state re-started. |
    INVALID_STATE | 2 | The chip was not in the EZConfig state at the time the EZCONFIG_CHECK command was issued. |

#### EZCONFIG_ARRAY_WRITE

- Number: 0x66
- Summary: Writes data byte(s) to the EZConfig array.
- Purpose:
  - This command is used to configure the chip using a generated EZConfig configuration array.
  - This command is only valid immediatly following the POWER_UP command and before the EZCONFIG_CHECK command. The EZCONFIG_ARRAY_WRITE command ID should be clocked in on SDI (followed by the data byte(s) to be written) without deasserting NSEL.
  - No more than 128 bytes can be written at one time. If the configuration array is longer than this a NOP followed by a poll of CTS should be issued before writing the next block of data.
  - This command does not cause CTS to go low, and can be sent while CTS is low. This command has no response to be read and thus there is no need to monitor CTS after sending this command.
- Argument Stream:

  EZCONFIG_ARRAY_WRITE Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x66
  | 0x01 | DATA[0] | DATA
  | ... | ... | ...
  | M | DATA[N] | DATA

- Argument Fields:

  ###### DATA[0...N]

  (indefinite length array stream)
  DATA[7:0]
  Description:
    Data to write to the EZConfig array
  Type:
    U8

## Property Details

### INT_CTL

#### INT_CTL_ENABLE

- Group: 0x01
- Index: 0x00

- Summary: This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin.
- Purpose:
  - Enables top-level interrupt sources to generate HW interrupts at the NIRQ pin.
  - The three interrupt groups are Chip, Modem and Packet Handler. Each of them contains multiple possible interrupt sources that must be individually enabled via the INT_CTL_PH_ENABLE, INT_CTL_MODEM_ENABLE, INT_CTL_CHIP_ENABLE properties.
  - Note that this property only provides for global enabling/disabling of the HW interrupt indication on the NIRQ output pin. An internal interrupt event may still be generated even if the indication on the NIRQ output pin is disabled. The interrupt event may always be monitored by polling a GPIO pin, or via GET_INT_STATUS, GET_CHIP_STATUS, GET_PH_STATUS, or GET_MODEM_STATUS commands.
- Default: 0x04
- Register View:

| INT_CTL_ENABLE
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x00 | 0 | 0 | 0 | 0 | 0 | CHIP_INT_STATUS_EN | MODEM_INT_STATUS_EN | PH_INT_STATUS_EN
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x1 | 0x0 | 0x0

- Field Details:

  ###### INT_CTL_ENABLE

  CHIP_INT_STATUS_EN
  Description:
    Enables chip interrupts to assert NIRQ.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DISABLED | 0 | Disable pending interrupts in the Chip Status group from asserting nNIRQ. | revB1A
    ENABLED | 1 | Enable pending interrupts in the Chip Status group to assert nNIRQ. | revB1A

  MODEM_INT_STATUS_EN
  Description:
    Enables modem interrupts to assert NIRQ.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DISABLED | 0 | Disable pending interrupts in rx mode group from asserting nNIRQ. |
    ENABLED | 1 | Enable pending interrupts in rx mode group to assert nNIRQ. |

  PH_INT_STATUS_EN
  Description:
    Enables packet handler interrupts to assert NIRQ.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DISABLED | 0 | Disable pending interrupts in tx mode group from asserting nNIRQ. |
    ENABLED | 1 | Enable pending interrupts in tx mode group to assert nNIRQ. |

#### INT_CTL_PH_ENABLE

- Group: 0x01
- Index: 0x01

- Summary: Enable individual interrupt sources within the Packet Handler Interrupt Group to generate a HW interrupt on the NIRQ output pin.
- Purpose:
  - Enable individual interrupt sources within the Packet Handler Interrupt Group in order to generate a HW interrupt at the NIRQ output pin.
  - In order to fully enable a HW interrupt, it is necessary to enable both the individual interrupt source (within this property) as well as the corresponding interrupt group (e.g., set INT_CTL_ENABLE:PH_INT_STATUS_EN).
  - Note that even if an interrupt source is not enabled to generate a HW NIRQ interrupt, the given interrupt event still may occur inside the chip and may be monitored by polling a GPIO pin, or via the GET_INT_STATUS or GET_PH_STATUS commands.
- Default: 0x00
- Register View:

| INT_CTL_PH_ENABLE
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x01 | 0 | 0 | PACKET_SENT_EN | PACKET_RX_EN | CRC_ERROR_EN | ALT_CRC_ERROR_EN | TX_FIFO_ALMOST_EMPTY_EN | RX_FIFO_ALMOST_FULL_EN
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0

- Field Details:

  ###### INT_CTL_PH_ENABLE

  PACKET_SENT_EN
  Description:
    If set, Enables PACKET_SENT interrupt on rising edge of PACKET_SENT status bit. See the status bits in GET_INT_STATUS for more details on the interrupt sources.
  Default:
    0x0
  PACKET_RX_EN
  Description:
    If set, Enables PACKET_RX interrupt on rising edge of PACKET_RX status bit. See the status bits in GET_INT_STATUS for more details on the interrupt sources.
  Default:
    0x0
  CRC_ERROR_EN
  Description:
    If set, Enables CRC_ERROR interrupt on rising edge of CRC_ERROR status bit. See the status bits in GET_INT_STATUS for more details on the interrupt sources.
  Default:
    0x0
  ALT_CRC_ERROR_EN
  Description:
    If set, Enables ALT_CRC_ERROR interrupt on rising edge of ALT_CRC_ERROR status bit. See the status bits in GET_INT_STATUS for more details on the interrupt sources.
  Default:
    0x0
  TX_FIFO_ALMOST_EMPTY_EN
  Description:
    If set, Enables TX_FIFO_ALMOST_EMPTY interrupt on rising edge of TX_FIFO_ALMOST_EMPTY status bit. See the status bits in GET_INT_STATUS for more details on the interrupt sources.
  Default:
    0x0
  RX_FIFO_ALMOST_FULL_EN
  Description:
    If set, Enables RX_FIFO_ALMOST_FULL interrupt on rising edge of RX_FIFO_ALMOST_FULL status bit. See the status bits in GET_INT_STATUS for more details on the interrupt sources.
  Default:
    0x0

#### INT_CTL_MODEM_ENABLE

- Group: 0x01
- Index: 0x02

- Summary: Enable individual interrupt sources within the Modem Interrupt Group to generate a HW interrupt on the NIRQ output pin.
- Purpose:
  - Enable individual interrupt sources within the Modem Interrupt Group in order to generate a HW interrupt at the NIRQ output pin.
  - In order to fully enable a HW interrupt, it is necessary to enable both the individual interrupt source (within this property) as well as the corresponding interrupt group (e.g., set INT_CTL_ENABLE:MODEM_INT_STATUS_EN ).
  - Note that even if an interrupt source is not enabled to generate a HW NIRQ interrupt, the given interrupt event still may occur inside the chip and may be monitored by polling a GPIO pin, or via the GET_INT_STATUS or GET_MODEM_STATUS commands.
- Default: 0x00
- Register View:

| INT_CTL_MODEM_ENABLE
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x02 | RSSI_LATCH_EN | 0 | INVALID_SYNC_EN | 0 | RSSI_EN | INVALID_PREAMBLE_EN | PREAMBLE_DETECT_EN | SYNC_DETECT_EN
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0

- Field Details:

  ###### INT_CTL_MODEM_ENABLE

  RSSI_LATCH_EN
  Description:
    If set, Enables RSSI_LATCH interrupt on rising edge of RSSI_LATCH status bit. See the status bits in GET_INT_STATUS for more details on the interrupt sources.
  Default:
    0x0
  INVALID_SYNC_EN
  Description:
    If set, Enables INVALID_SYNC interrupt on rising edge of INVALID_SYNC status bit. See the status bits in GET_INT_STATUS for more details on the interrupt sources.
  Default:
    0x0
  RSSI_EN
  Description:
    If set, Enables RSSI interrupt on rising edge of RSSI status bit. See the status bits in GET_INT_STATUS for more details on the interrupt sources.
  Default:
    0x0
  INVALID_PREAMBLE_EN
  Description:
    If set, Enables INVALID_PREAMBLE interrupt on rising edge of INVALID_PREAMBLE status bit. See the status bits in GET_INT_STATUS for more details on the interrupt sources.
  Default:
    0x0
  PREAMBLE_DETECT_EN
  Description:
    If set, Enables PREAMBLE_DETECT interrupt on rising edge of PREAMBLE_DETECT status bit. See the status bits in GET_INT_STATUS for more details on the interrupt sources.
  Default:
    0x0
  SYNC_DETECT_EN
  Description:
    If set, Enables SYNC_DETECT interrupt on rising edge of SYNC_DETECT status bit. See the status bits in GET_INT_STATUS for more details on the interrupt sources. If dual sync words are configured via SYNC_CONFIG2:DUAL_SYNC_EN, then either sync word can trigger this interrupt.
  Default:
    0x0

#### INT_CTL_CHIP_ENABLE

- Group: 0x01
- Index: 0x03

- Summary: Enable individual interrupt sources within the Chip Interrupt Group to generate a HW interrupt on the NIRQ output pin.
- Purpose:
  - Enable individual interrupt sources within the Chip Interrupt Group in order to generate a HW interrupt at the NIRQ output pin.
  - In order to fully enable a HW interrupt, it is necessary to enable both the individual interrupt source (within this property) as well as the corresponding interrupt group (e.g., set INT_CTL_ENABLE:CHIP_INT_STATUS_EN).
  - Note that even if an interrupt source is not enabled to generate a HW NIRQ interrupt, the given interrupt event still may occur inside the chip and may be monitored by polling a GPIO pin, or via the GET_INT_STATUS or GET_CHIP_STATUS commands.
- Default: 0x04
- Register View:

| INT_CTL_CHIP_ENABLE
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x03 | 0 | 0 | FIFO_UNDERFLOW_OVERFLOW_ERROR_EN | STATE_CHANGE_EN | CMD_ERROR_EN | CHIP_READY_EN | 0 | 0
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x1 | 0x0 | 0x0

- Field Details:

  ###### INT_CTL_CHIP_ENABLE

  FIFO_UNDERFLOW_OVERFLOW_ERROR_EN
  Description:
    If set, Enables FIFO_UNDERFLOW_OVERFLOW_ERROR interrupt on rising edge of FIFO_UNDERFLOW_OVERFLOW_ERROR status bit. See the status bits in GET_INT_STATUS for more details on the interrupt sources.
  Default:
    0x0
  STATE_CHANGE_EN
  Description:
    If set, Enables STATE_CHANGE interrupt on rising edge of STATE_CHANGE status bit. See the status bits in GET_INT_STATUS for more details on the interrupt sources.
  Default:
    0x0
  CMD_ERROR_EN
  Description:
    If set, Enables CMD_ERROR interrupt on rising edge of CMD_ERROR status bit. See the status bits in GET_INT_STATUS for more details on the interrupt sources.
  Default:
    0x0
  CHIP_READY_EN
  Description:
    If set, Enables CHIP_READY interrupt on rising edge of CHIP_READY status bit. See the status bits in GET_INT_STATUS for more details on the interrupt sources.
  Default:
    0x1

### FRR_CTL

#### FRR_CTL_A_MODE

- Group: 0x02
- Index: 0x00

- Summary: Fast Response Register A Configuration.
- Purpose:
  - The chip provides four Fast Response Registers (FRR) that may be read immediately without the need to monitor and check CTS, thus improving the speed at which the contents may be retrieved.
  - The FRR_CTL_X_MODE properties are used to select the specific parameter values (selected from the enumeration list below) that will be returned by the FRR_X_READ commands. This property selects the parameter held in FRR_A and returned by the FRR_A_READ command.
  - The FRR registers may be read in a burst fashion through the FRR_X_READ commands. After the initial 16 clock cycles, each additional eight clock cycles will clock out the contents of the next fast response register in a circular fashion. Example: If the FRR_A_READ command is issued, the registers will be read in the order A-B-C-D, while if the FRR_B_READ command is issued, the registers will be read in the order B-C-D-A, etc.
- Default: 0x01
- Register View:

| FRR_CTL_A_MODE
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x00 | FRR_A_MODE
| Default
| 0x1

- Field Details:

  ###### FRR_CTL_A_MODE

  FRR_A_MODE[7:0]
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DISABLED | 0 | Disabled. Will always read back 0. | revB1A
    INT_STATUS | 1 | Global status. | revB1A
    INT_PEND | 2 | Global interrupt pending. | revB1A
    INT_PH_STATUS | 3 | Packet Handler status. | revB1A
    INT_PH_PEND | 4 | Packet Handler interrupt pending. | revB1A
    INT_MODEM_STATUS | 5 | Modem status. | revB1A
    INT_MODEM_PEND | 6 | Modem interrupt pending. | revB1A
    INT_CHIP_STATUS | 7 | Chip status. | revB1A
    INT_CHIP_PEND | 8 | Chip status interrupt pending. | revB1A
    CURRENT_STATE | 9 | Current state. | revB1A
    LATCHED_RSSI | 10 | Latched RSSI value as defined in MODEM_RSSI_CONTROL:LATCH. | revB1A

#### FRR_CTL_B_MODE

- Group: 0x02
- Index: 0x01

- Summary: Fast Response Register B Configuration.
- Purpose:
  - This property selects the parameter held in FRR_B and returned by the FRR_B_READ command.
  - Please refer to the text description for FRR_CTL_A_MODE for more details regarding the Fast Response Register (FRR) function.
- Default: 0x02
- Register View:

| FRR_CTL_B_MODE
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x01 | FRR_B_MODE
| Default
| 0x2

- Field Details:

  ###### FRR_CTL_B_MODE

  FRR_B_MODE[7:0]
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DISABLED | 0 | Disabled. Will always read back 0. | revB1A
    INT_STATUS | 1 | Global status. | revB1A
    INT_PEND | 2 | Global interrupt pending. | revB1A
    INT_PH_STATUS | 3 | Packet Handler status. | revB1A
    INT_PH_PEND | 4 | Packet Handler interrupt pending. | revB1A
    INT_MODEM_STATUS | 5 | Modem status. | revB1A
    INT_MODEM_PEND | 6 | Modem interrupt pending. | revB1A
    INT_CHIP_STATUS | 7 | Chip status. | revB1A
    INT_CHIP_PEND | 8 | Chip status interrupt pending. | revB1A
    CURRENT_STATE | 9 | Current state. | revB1A
    LATCHED_RSSI | 10 | Latched RSSI value as defined in MODEM_RSSI_CONTROL:LATCH. | revB1A

#### FRR_CTL_C_MODE

- Group: 0x02
- Index: 0x02

- Summary: Fast Response Register C Configuration.
- Purpose:
  - This property selects the parameter held in FRR_C and returned by the FRR_C_READ command.
  - Please refer to the text description for FRR_CTL_A_MODE for more details regarding the Fast Response Register (FRR) function.
- Default: 0x09
- Register View:

| FRR_CTL_C_MODE
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x02 | FRR_C_MODE
| Default
| 0x9

- Field Details:

  ###### FRR_CTL_C_MODE

  FRR_C_MODE[7:0]
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DISABLED | 0 | Disabled. Will always read back 0. | revB1A
    INT_STATUS | 1 | Global status. | revB1A
    INT_PEND | 2 | Global interrupt pending. | revB1A
    INT_PH_STATUS | 3 | Packet Handler status. | revB1A
    INT_PH_PEND | 4 | Packet Handler interrupt pending. | revB1A
    INT_MODEM_STATUS | 5 | Modem status. | revB1A
    INT_MODEM_PEND | 6 | Modem interrupt pending. | revB1A
    INT_CHIP_STATUS | 7 | Chip status. | revB1A
    INT_CHIP_PEND | 8 | Chip status interrupt pending. | revB1A
    CURRENT_STATE | 9 | Current state. | revB1A
    LATCHED_RSSI | 10 | Latched RSSI value as defined in MODEM_RSSI_CONTROL:LATCH. | revB1A

#### FRR_CTL_D_MODE

- Group: 0x02
- Index: 0x03

- Summary: Fast Response Register D Configuration.
- Purpose:
  - This property selects the parameter held in FRR_D and returned by the FRR_D_READ command.
  - Please refer to the text description for FRR_CTL_A_MODE for more details regarding the Fast Response Register (FRR) function.
- Default: 0x00
- Register View:

| FRR_CTL_D_MODE
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x03 | FRR_D_MODE
| Default
| 0x0

- Field Details:

  ###### FRR_CTL_D_MODE

  FRR_D_MODE[7:0]
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DISABLED | 0 | Disabled. Will always read back 0. | revB1A
    INT_STATUS | 1 | Global status. | revB1A
    INT_PEND | 2 | Global interrupt pending. | revB1A
    INT_PH_STATUS | 3 | Packet Handler status. | revB1A
    INT_PH_PEND | 4 | Packet Handler interrupt pending. | revB1A
    INT_MODEM_STATUS | 5 | Modem status. | revB1A
    INT_MODEM_PEND | 6 | Modem interrupt pending. | revB1A
    INT_CHIP_STATUS | 7 | Chip status. | revB1A
    INT_CHIP_PEND | 8 | Chip status interrupt pending. | revB1A
    CURRENT_STATE | 9 | Current state. | revB1A
    LATCHED_RSSI | 10 | Latched RSSI value as defined in MODEM_RSSI_CONTROL:LATCH. | revB1A

### SYNC

#### SYNC_CONFIG

- Group: 0x11
- Index: 0x00

- Summary: Sync Word configuration bits.
- Purpose:
  - Configuration of miscellaneous Sync Word bits. NOTE: each byte of the Sync Word is transmitted/received in little-endian fashion (i.e., least significant bit first). Byte(s) of the Sync Word are transmitted/received in descending order (i.e., Byte 3 first, followed by Byte 2, etc.)
- Default: 0x01
- Register View:

| SYNC_CONFIG
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x00 | SKIP_TX | RX_ERRORS | 0 | MANCH | LENGTH
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0x1

- Field Details:

  ###### SYNC_CONFIG

  SKIP_TX
  Description:
    This property allows the user to choose if the sync word is transmitted. Note: This field only affects TX operation and does not affect reception of the Sync Word.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    SYNC_XMIT | 0 | Sync Word is transmitted. The number of bytes comprising the Sync Word is defined by the LENGTH field within this same property. | revB1A
    NO_SYNC_XMIT | 1 | Sync Word is not transmitted. NOTE: the SKIP_TX bit only affects TX operation, and does not affect reception of the Sync Word. | revB1A

  RX_ERRORS[2:0]
  Description:
    Defines the number of bit errors that are allowed in the Sync Word field during receive Sync Word detection.
  Min:
    0x0
  Max:
    0x7
  Default:
    0x0
  MANCH
  Description:
    If Manchester decoding of the Sync Word in RX mode is enabled, MODEM_MAP_CONTROL:ENMANCH should also be set; this results in an extended search timeout period for the Sync Word to allow for the increased number of bits/chips.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DISABLED | 0 | Sync word is not manchester encoded. | revB1A
    ENABLED | 1 | Sync word is manchester encoded. | revB1A

  LENGTH[1:0]
  Description:
    Determines the length of the Sync Word in bytes. The Sync Word is defined in SYNC_BITS and SYNC_BITS2. This length can be modified by ref_prop_field SYNC_CONFIG2 LENGTH_SUB] to allow 2 bit granularity.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    LEN_1_BYTES | 0 | Sync Word is 1-byte (8 bits) in length. Sync Word byte 3 [31:24] is used, with its value defined in the SYNC_BITS property. | revB1A
    LEN_2_BYTES | 1 | Sync Word is 2-bytes (16 bits) in length. Sync Word bytes 3 and 2 [31:16] are used (in descending order), with their values defined in the SYNC_BITS property. | revB1A
    LEN_3_BYTES | 2 | Sync Word is 3-bytes (24 bits) in length. Sync Word bytes 3, 2, and 1 [31:8] are used (in descending order), with their values defined in the SYNC_BITS property. | revB1A
    LEN_4_BYTES | 3 | Sync Word is 4-bytes (32 bits) in length. Sync Word bytes 3, 2, 1, and 0 [31:0] are used (in descending order), with their values defined in the SYNC_BITS property. | revB1A

#### SYNC_BITS

- Group: 0x11
- Indexes: 0x01 ... 0x04

- Summary: Sync word.
- Purpose:
  - Define the value of the Sync Word for both TX and RX operation. NOTE: Although the Sync Word byte(s) are transmitted/received in descending order (i.e., Byte 3 first, followed by Byte 2, etc.), each byte is transmitted/received in little-endian fashion (i.e., least significant bit first).
- Defaults: 0x2d,0xd4,0x2d,0xd4
- Register View:

| SYNC_BITS
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x01 | BITS[31:24]
0x02 | BITS[23:16]
0x03 | BITS[15:8]
0x04 | BITS[7:0]
| Defaults
0x01 | 0x2d
0x02 | 0xd4
0x03 | 0x2d
0x04 | 0xd4

- Field Details:

  ###### SYNC_BITS

  BITS[31:0]
  Description:
    bits
  Min:
    0x0
  Max:
    0xffffffff
  Default:
    0x2dd42dd4

### PA

#### PA_PWR_LVL

- Group: 0x22
- Index: 0x01

- Summary: Configuration of PA output power level.
- Purpose:
  - The PA circuitry in the chip contains an output device whose size may be adjusted by enabling/disabling different numbers of device fingers. Selection of a higher value results in an increase in TX output power.
  - The relationship between output power and the number of enabled device fingers is not necessarily linear, and is dependent upon the PA mode of operation (e.g., Class-E or Switched Current), the duty cycle of the drive signal to the output circuit, the VDD supply voltage, and the output match. As a result, there is no simple formula to relate the setting of the PA_PWR_LVL property to an absolute value of output power in dBm.
  - The adjustment resolution of the TX output power is very fine (step size < 0.1 dB) when operating near the maximum power setting, but becomes coarser as the output power level is reduced.
- Default: 0x7f
- Register View:

| PA_PWR_LVL
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x01 | 0 | DDAC
| Default
| 0x0 | 0x7f

- Field Details:

  ###### PA_PWR_LVL

  DDAC[6:0]
  Description:
    Selects the number of enabled output device fingers, with a larger value resulting in increased output power.
  Min:
    0x0
  Max:
    0x7f
  Default:
    0x7f

### EZCONFIG

#### EZCONFIG_MODULATION

- Group: 0x24
- Index: 0x00

- Summary: Selects the type of modulation using the EZConfig feature.
- Purpose:
  - This property configures the Modem in the chip for transmission/reception of the following modulation types: OOK, 2FSK, and 2GFSK modulation.
  - In TX mode, this property is additionally used to select the source of the TX data stream,
    and whether that TX data stream is from a synchronous or asynchronous source (in Direct mode only)."
  - The Modem must be configured for transmission/reception of only one type of modulation throughout the entire packet; it is not possible (for example) to use OOK modulation over certain fields and (G)FSK modulation over other fields.
- Default: 0x02
- Register View:

| EZCONFIG_MODULATION
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x00 | TX_DIRECT_MODE_TYPE | TX_DIRECT_MODE_GPIO | MOD_SOURCE | 0 | MOD_TYPE
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0x2

- Field Details:

  ###### EZCONFIG_MODULATION

  TX_DIRECT_MODE_TYPE
  Description:
    - This bit determines whether a real-time TX data stream (applied to the chip on a selected GPIO input pin) is processed in synchronous or asynchronous fashion. This bit is applicable only in TX mode, and only when the MOD_SOURCE field is also set for TX Direct mode.
    - In TX Direct Synchronous mode, the chip controls the transmit data rate by outputting a TX bit clock (GPIO_PIN_CFG=0x10). The host MCU receives the rising edge of the TX clock and responds by outputting one bit for each clock tick; the chip clocks in this new data bit on the subsequent falling edge of the TX clock. All 2-level modulation modes (OOK, 2FSK, 2GFSK) are supported.
    - In TX Direct Asynchronous mode, the host MCU controls the transmit data rate; the RFIC has no knowledge of the rate of the incoming TX data stream but simply oversamples the data as fast as possible to determine the bit edge transitions. OOK and 2FSK are supported, but 2GFSK is not supported in this mode.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    SYNC | 0 | TX Direct Synchronous mode | revB1A
    ASYNC | 1 | TX Direct Asynchronous mode | revB1A

  TX_DIRECT_MODE_GPIO[1:0]
  Description:
    - This field determines which GPIO pin is selected by the Modem as the modulation data source during TX Direct mode. This field is applicable only in TX mode, and only when the MOD_SOURCE field is also set for TX Direct mode.
    - This bit does not automatically configure the selected GPIO pin as a digital input pin; it remains necessary to additionally configure the desired GPIO pin as a CMOS-compatible input pin by setting GPIO_PIN_CFG=0x04.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    GPIO0 | 0 | Use GPIO0 as the data source in TX Direct mode. | revB1A
    GPIO1 | 1 | Use GPIO1 as the data source in TX Direct mode. | revB1A
    GPIO2 | 2 | Use GPIO2 as the data source in TX Direct mode. | revB1A
    GPIO3 | 3 | Use GPIO3 as the data source in TX Direct mode. | revB1A

  MOD_SOURCE[1:0]
  Description:
    This field selects the source of modulation during TX mode. It is applicable only in TX mode.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    PACKET | 0 | The modulation is sourced from the TX FIFO in the packet handler. | revB1A
    DIRECT | 1 | The modulation is sourced in real-time (i.e., TX Direct Mode) from a GPIO pin, as selected by the TX_DIRECT_MODE_GPIO field. | revB1A
    PSEUDO | 2 | The modulation is sourced from the internal pseudo-random generator. | revB1A

  MOD_TYPE[1:0]
  Description:
    - This field configures the Modem for transmission or reception of the desired type of modulation.
    - With the exception of CW mode (a TX-only function), this field is applicable in both TX and RX modes.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    CW | 0 | CW. | revB1A
    OOK | 1 | OOK. | revB1A
    2FSK | 2 | 2FSK. | revB1A
    2GFSK | 3 | 2GFSK. | revB1A

#### EZCONFIG_XO_TUNE

- Group: 0x24
- Index: 0x03

- Summary: Configure the internal capacitor frequency tuning bank for the crystal oscillator.
- Purpose:
  - The chip provides internal adjustable capacitor banks for the purpose of tuning the frequency of the crystal oscillator. These capacitances effectively appear in shunt from the XIN and XOUT pins to GND.
  - TUNE_VALUE = 0x00 corresponds to the lowest tuning capacitance value and thus the highest frequency of oscillation, while TUNE_VALUE = 0x7F corresponds to the highest tuning capacitance value and the lowest frequency of oscillation. Each LSB code corresponds to ~70 fF change in capacitance.
  - The total frequency adjustment range (for a typical 30 MHz crystal blank) is approximately ±100 ppm.
- Default: 0x40
- Register View:

| EZCONFIG_XO_TUNE
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x03 | 0 | TUNE_VALUE
| Default
| 0x0 | 0x40

- Field Details:

  ###### EZCONFIG_XO_TUNE

  TUNE_VALUE[6:0]
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    FASTEST_FREQUENCY | 0 | Lowest capacitance (i.e., highest oscillation frequency). | revB1A
    SLOWEST_FREQUENCY | 127 | Highest capacitance (i.e., lowest oscillation frequency). | revB1A

### FREQ_CONTROL

#### FREQ_CONTROL_INTE

- Group: 0x40
- Index: 0x00

- Summary: Frac-N PLL Synthesizer integer divide number.
- Purpose:
  - The total divide ratio for the Fractional-N PLL Synthesizer consists of an integer portion and a fractional portion. This property defines the integer divide number; the fractional divide value is specified in property FREQ_CONTROL_FRAC.
  - The formula for calculating RF channel frequency as a function of integer and fractional divide values is as follows:

  - The output divider value OUTDIV is automatically configured by WDS as a function of the desired frequency band.
  - The prescaler divider value NPRESC=4
  - The entire fcfrac word is 20-bits in length, but the MSB should always be set to 1, and thus the term fcfrac/219 will always be between 1 and 2 in value. As a result, the integer term fcinte should be reduced by 1. Example: a total desired divide ratio of N = 60.135 should be implemented as fcinte = 59, fcfrac/219 = 1.135.
  - Modifying this property will have no effect until the chip exits from TX or RX state, and then re-enters the state.
- Default: 0x3c
- Register View:

| FREQ_CONTROL_INTE
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x00 | 0 | INTE
| Default
| 0x0 | 0x3c

- Field Details:

  ###### FREQ_CONTROL_INTE

  INTE[6:0]
  Min:
    0x0
  Max:
    0x7f
  Default:
    0x3c

#### FREQ_CONTROL_FRAC

- Group: 0x40
- Indexes: 0x01 ... 0x03

- Summary: Frac-N PLL fraction number.
- Purpose:
  - Please refer to the text description for FREQ_CONTROL_INTE for more details regarding frequency calculation.
- Defaults: 0x08,0x00,0x00
- Register View:

| FREQ_CONTROL_FRAC
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x01 | 0 | 0 | 0 | 0 | FRAC[19:16]
0x02 | FRAC[15:8]
0x03 | FRAC[7:0]
| Defaults
0x01 | 0x0 | 0x0 | 0x0 | 0x0 | 0x8
0x02 | 0x0
0x03 | 0x0

- Field Details:

  ###### FREQ_CONTROL_FRAC

  FRAC[19:0]
  Description:
    Frequency control fractional part
  Min:
    0x0
  Max:
    0xfffff
  Default:
    0x80000

#### FREQ_CONTROL_CHANNEL_STEP_SIZE

- Group: 0x40
- Indexes: 0x04 ... 0x05

- Summary: EZ Frequency Programming channel step size.
- Purpose:
  - The EZ Frequency Programming method allows the user to control the frequency by selecting a desired channel number, given a base frequency and a channel step size. This property defines the unsigned 16-bit channel step size value.
  - The units of the FREQ_CONTROL_CHANNEL_STEP_SIZE property are in increments of the LSB tuning resolution of the PLL Synthesizer, and are therefore a function of the crystal reference frequency and output frequency band. The formula for calculating the value of the FREQ_CONTROL_CHANNEL_STEP_SIZE property is given by the following equation:

  - The output divider value OUTDIV is automatically configured by WDS as a function of the desired frequency band.
  - The prescaler divider value NPRESC=4
  - The base frequency is specified by the FREQ_CONTROL_INTE and FREQ_CONTROL_FRAC properties.
  - The channel number is specified by the CHANNEL parameter byte passed to the START_TX or START_RX commands.
  - The commanded channel frequency is given by the formula:

- Defaults: 0x00,0x00
- Register View:

| FREQ_CONTROL_CHANNEL_STEP_SIZE
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x04 | CHANNEL_STEP_SIZE[15:8]
0x05 | CHANNEL_STEP_SIZE[7:0]
| Defaults
0x04 | 0x0
0x05 | 0x0

- Field Details:

  ###### FREQ_CONTROL_CHANNEL_STEP_SIZE

  CHANNEL_STEP_SIZE[15:0]
  Description:
    Channel step size
  Min:
    0x0
  Max:
    0xffff
  Default:
    0x0

### PTI

#### PTI_CTL

- Group: 0xf0
- Index: 0x00

- Summary: Packet Trace Interface control fields.
- Purpose:
  - The chip contains packet trace interface for debugging network protocols. This property controls the behavior of this interface.
- Default: 0x80
- Register View:

| PTI_CTL
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x00 | PTI_EN | 0 | 0 | 0 | 0 | 0 | 0 | 0
| Default
| 0x1 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0

- Field Details:

  ###### PTI_CTL

  PTI_EN
  Description:
    Controls global enable of the PTI functionality.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENABLE | 1 | Enable PTI signal to GPIO. GPIO must be configured using GPIO_PIN_CFG. |
    DISABLE | 0 | Disable PTI signal to GPIO. GPIO must be configured using GPIO_PIN_CFG. |

#### PTI_BAUD

- Group: 0xf0
- Indexes: 0x01 ... 0x02

- Summary: Desired baud rate for the PTI interface.
- Purpose:
  - The chip contains a packet trace interface for network debugging. This data is transmitted to host debugger using a UART connection on a GPIO pin (selected using GPIO_PIN_CFG). This property sets the
    baud rate of the packet trace data in 100 baud steps.
- Defaults: 0x13,0x88
- Register View:

| PTI_BAUD
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x01 | 00000000
0x02 | 00000000
| Defaults
0x01 | 0x13
0x02 | 0x88

- Field Details:

  ###### PTI_BAUD

#### PTI_LOG_EN

- Group: 0xf0
- Index: 0x03

- Summary: Enables what the PTI logs.
- Purpose:
  - The chip contains packet trace interface for debugging network protocols. This property controls messages that
    get logged by this interface.
- Default: 0x00
- Register View:

| PTI_LOG_EN
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x03 | 0 | RX_EN | TX_EN | 0 | 0 | 0 | 0 | 0
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0

- Field Details:

  ###### PTI_LOG_EN

  RX_EN
  Description:
    Controls logging of data packets received over the air. Note that status information about each received packet is always logged regardless of this setting.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENABLE | 1 | Enable Logging to the packet trace interface. |
    DISABLE | 0 | Disable Logging to the packet trace interface. |

  TX_EN
  Description:
    Controls logging of data packets sent over the air. Note that status information about each sent packet is always logged regardless of this setting.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENABLE | 1 | Enable Logging to the packet trace interface. |
    DISABLE | 0 | Disable Logging to the packet trace interface. |