# Si4060 revC2A Command/Property API Documentation

#### Interface Version: 1.0

#### Document Version: 2.0.5

#### Generated: 2015-03-18T10:15:42-05:00

## Introduction

This document provides API descriptions for the commands and properties used to control and configure the part. The interface version tracks any functional changes to the API (command, property, field, enumeration, etc.). The documentation version tracks any text changes to the summary or description text of the API components.
The commands are listed in a summary table with links to command details. The properties are listed in a summary table with links to property details. The feature available column in the summary tables lists the firmware revision which first implemented the command or property.
An entry in the summary table will link to a details section, which contains a register view with fields. Clicking a field in the register view will auto-expand the corresponding field details. An up button in the field detail links back to the register view. Each register view title links back to the summary table entry. These hyper-links provide two-click access from top to bottom.

## Command Summary

| BOOT_COMMANDS
--- | ---
| Number | Name | Summary | Feature Available
| 0x02 | POWER_UP | Command to power-up the device and select the operational mode and functionality. |

| COMMON_COMMANDS
--- | ---
| Number | Name | Summary | Feature Available
| 0x00 | NOP | No Operation command. |
| 0x01 | PART_INFO | Reports basic information about the device. |
| 0x10 | FUNC_INFO | Returns the Function revision information of the device. |
| 0x11 | SET_PROPERTY | Sets the value of one or more properties. |
| 0x12 | GET_PROPERTY | Retrieves the value of one or more properties |
| 0x13 | GPIO_PIN_CFG | Configures the GPIO pins. |
| 0x15 | FIFO_INFO | Access the current byte counts in the TX and RX FIFOs, and provide for resetting the FIFOs. |
| 0x20 | GET_INT_STATUS | Returns the interrupt status of ALL the possible interrupt events (both STATUS and PENDING). Optionally, it may be used to clear latched (PENDING) interrupt events. |
| 0x33 | REQUEST_DEVICE_STATE | Request current device state and channel. |
| 0x34 | CHANGE_STATE | Manually switch the chip to a desired operating state. |
| 0x44 | READ_CMD_BUFF | Used to read CTS and the command response. |
| 0x50 | FRR_A_READ | Reads the fast response registers (FRR) starting with FRR_A. |
| 0x51 | FRR_B_READ | Reads the fast response registers (FRR) starting with FRR_B. |
| 0x53 | FRR_C_READ | Reads the fast response registers (FRR) starting with FRR_C. |
| 0x57 | FRR_D_READ | Reads the fast response registers (FRR) starting with FRR_D. |

| TX_COMMANDS
--- | ---
| Number | Name | Summary | Feature Available
| 0x31 | START_TX | Switches to TX state and starts transmission of a packet. |
| 0x66 | WRITE_TX_FIFO | Writes data byte(s) to the TX FIFO. |

| ADVANCED_COMMANDS
--- | ---
| Number | Name | Summary | Feature Available
| 0x14 | GET_ADC_READING | Performs conversions using the Auxiliary ADC and returns the results of those conversions. |
| 0x21 | GET_PH_STATUS | Returns the interrupt status of the Packet Handler Interrupt Group (both STATUS and PENDING). Optionally, it may be used to clear latched (PENDING) interrupt events. |
| 0x23 | GET_CHIP_STATUS | Returns the interrupt status of the Chip Interrupt Group (both STATUS and PENDING). Optionally, it may be used to clear latched (PENDING) interrupt events. |

## Property Summary

| GLOBAL (0x00)
--- | ---
| Group | Number | Name | Default | Summary | Feature Available
| 0x00 | 0x00 | GLOBAL_XO_TUNE | 0x40 | Configure the internal capacitor frequency tuning bank for the crystal oscillator. |
| 0x00 | 0x01 | GLOBAL_CLK_CFG | 0x00 | Clock configuration options. |
| 0x00 | 0x02 | GLOBAL_LOW_BATT_THRESH | 0x18 | Configures the threshold voltage for low-battery detection. |
| 0x00 | 0x03 | GLOBAL_CONFIG | 0x20 | Global configuration settings. |
| 0x00 | 0x04 | GLOBAL_WUT_CONFIG | 0x00 | General Wakeup Timer feature configuration. |
| 0x00 | 0x05 0x06 | GLOBAL_WUT_M | 0x00 0x01 | Configure the mantissa of the Wake-Up Timer (WUT) value. |
| 0x00 | 0x07 | GLOBAL_WUT_R | 0x60 | Configure the exponent of the Wake-Up Timer (WUT) value. |
| 0x00 | 0x08 | GLOBAL_WUT_LDC | 0x00 | Configures the period of time the chip remains active after automatic wake-up in LDC mode. |
| 0x00 | 0x09 | GLOBAL_WUT_CAL | 0x00 | Controls if calibration of the 32K R-C Oscillator will be performed on intervals of the WUT. |

| INT_CTL (0x01)
--- | ---
| Group | Number | Name | Default | Summary | Feature Available
| 0x01 | 0x00 | INT_CTL_ENABLE | 0x04 | This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin. |
| 0x01 | 0x01 | INT_CTL_PH_ENABLE | 0x00 | Enable individual interrupt sources within the Packet Handler Interrupt Group to generate a HW interrupt on the NIRQ output pin. |
| 0x01 | 0x03 | INT_CTL_CHIP_ENABLE | 0x04 | Enable individual interrupt sources within the Chip Interrupt Group to generate a HW interrupt on the NIRQ output pin. |

| FRR_CTL (0x02)
--- | ---
| Group | Number | Name | Default | Summary | Feature Available
| 0x02 | 0x00 | FRR_CTL_A_MODE | 0x01 | Fast Response Register A Configuration. |
| 0x02 | 0x01 | FRR_CTL_B_MODE | 0x02 | Fast Response Register B Configuration. |
| 0x02 | 0x02 | FRR_CTL_C_MODE | 0x09 | Fast Response Register C Configuration. |
| 0x02 | 0x03 | FRR_CTL_D_MODE | 0x00 | Fast Response Register D Configuration. |

| PREAMBLE (0x10)
--- | ---
| Group | Number | Name | Default | Summary | Feature Available
| 0x10 | 0x00 | PREAMBLE_TX_LENGTH | 0x08 | Configure length of TX Preamble. |
| 0x10 | 0x01 | PREAMBLE_CONFIG_STD_1 | 0x14 | Configuration of reception of a packet with a Standard Preamble pattern. |
| 0x10 | 0x02 | PREAMBLE_CONFIG_NSTD | 0x00 | Configuration of transmission/reception of a packet with a Non-Standard Preamble pattern. |
| 0x10 | 0x04 | PREAMBLE_CONFIG | 0x21 | General configuration bits for the Preamble field. |
| 0x10 | 0x05 0x06 0x07 0x08 | PREAMBLE_PATTERN | 0x00 0x00 0x00 0x00 | Configuration of the bit values describing a Non-Standard Preamble pattern. |

| SYNC (0x11)
--- | ---
| Group | Number | Name | Default | Summary | Feature Available
| 0x11 | 0x00 | SYNC_CONFIG | 0x01 | Sync Word configuration bits. |
| 0x11 | 0x01 0x02 0x03 0x04 | SYNC_BITS | 0x2d 0xd4 0x2d 0xd4 | Sync word. |
| 0x11 | 0x05 | SYNC_CONFIG2 | 0x00 | Sync Word configuration bits. |

| PKT (0x12)
--- | ---
| Group | Number | Name | Default | Summary | Feature Available
| 0x12 | 0x00 | PKT_CRC_CONFIG | 0x00 | Select a CRC polynomial and seed. |
| 0x12 | 0x01 0x02 | PKT_WHT_POLY | 0x01 0x08 | 16-bit polynomial value for the PN Generator (e.g., for Data Whitening) |
| 0x12 | 0x03 0x04 | PKT_WHT_SEED | 0xff 0xff | 16-bit seed value for the PN Generator (e.g., for Data Whitening) |
| 0x12 | 0x05 | PKT_WHT_BIT_NUM | 0x00 | Selects which bit of the LFSR (used to generate the PN / data whitening sequence) is used as the output bit for data scrambling. |
| 0x12 | 0x06 | PKT_CONFIG1 | 0x00 | General configuration bits for transmission or reception of a packet. |
| 0x12 | 0x07 | PKT_CONFIG2 | 0x00 | General packet configuration bits. |
| 0x12 | 0x0b | PKT_TX_THRESHOLD | 0x30 | TX FIFO almost empty threshold. |
| 0x12 | 0x0d 0x0e | PKT_FIELD_1_LENGTH | 0x00 0x00 | Unsigned 13-bit Field 1 length value. |
| 0x12 | 0x0f | PKT_FIELD_1_CONFIG | 0x00 | General data processing and packet configuration bits for Field 1. |
| 0x12 | 0x10 | PKT_FIELD_1_CRC_CONFIG | 0x00 | Configuration of CRC control bits across Field 1. |
| 0x12 | 0x11 0x12 | PKT_FIELD_2_LENGTH | 0x00 0x00 | Unsigned 13-bit Field 2 length value. |
| 0x12 | 0x13 | PKT_FIELD_2_CONFIG | 0x00 | General data processing and packet configuration bits for Field 2. |
| 0x12 | 0x14 | PKT_FIELD_2_CRC_CONFIG | 0x00 | Configuration of CRC control bits across Field 2. |
| 0x12 | 0x15 0x16 | PKT_FIELD_3_LENGTH | 0x00 0x00 | Unsigned 13-bit Field 3 length value. |
| 0x12 | 0x17 | PKT_FIELD_3_CONFIG | 0x00 | General data processing and packet configuration bits for Field 3. |
| 0x12 | 0x18 | PKT_FIELD_3_CRC_CONFIG | 0x00 | Configuration of CRC control bits across Field 3. |
| 0x12 | 0x19 0x1a | PKT_FIELD_4_LENGTH | 0x00 0x00 | Unsigned 13-bit Field 4 length value. |
| 0x12 | 0x1b | PKT_FIELD_4_CONFIG | 0x00 | General data processing and packet configuration bits for Field 4. |
| 0x12 | 0x1c | PKT_FIELD_4_CRC_CONFIG | 0x00 | Configuration of CRC control bits across Field 4. |
| 0x12 | 0x1d 0x1e | PKT_FIELD_5_LENGTH | 0x00 0x00 | Unsigned 13-bit Field 5 length value. |
| 0x12 | 0x1f | PKT_FIELD_5_CONFIG | 0x00 | General data processing and packet configuration bits for Field 5. |
| 0x12 | 0x20 | PKT_FIELD_5_CRC_CONFIG | 0x00 | Configuration of CRC control bits across Field 5. |

| MODEM (0x20)
--- | ---
| Group | Number | Name | Default | Summary | Feature Available
| 0x20 | 0x00 | MODEM_MOD_TYPE | 0x02 | Selects the type of modulation. In TX mode, additionally selects the source of the modulation. |
| 0x20 | 0x01 | MODEM_MAP_CONTROL | 0x80 | Controls polarity and mapping of transmit and receive bits. |
| 0x20 | 0x02 | MODEM_DSM_CTRL | 0x07 | Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer. |
| 0x20 | 0x03 0x04 0x05 | MODEM_DATA_RATE | 0x0f 0x42 0x40 | Unsigned 24-bit value used to determine the TX data rate |
| 0x20 | 0x06 0x07 0x08 0x09 | MODEM_TX_NCO_MODE | 0x01 0xc9 0xc3 0x80 | TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus. |
| 0x20 | 0x0a 0x0b 0x0c | MODEM_FREQ_DEV | 0x00 0x06 0xd3 | 17-bit unsigned TX frequency deviation word. |
| 0x20 | 0x0d 0x0e | MODEM_FREQ_OFFSET | 0x00 0x00 | Frequency offset adjustment (a 16-bit signed number). |
| 0x20 | 0x0f | MODEM_TX_FILTER_COEFF_8 | 0x67 | The 8th coefficient of TX spectral shaping filter. |
| 0x20 | 0x10 | MODEM_TX_FILTER_COEFF_7 | 0x60 | The 7th coefficient of TX spectral shaping filter. |
| 0x20 | 0x11 | MODEM_TX_FILTER_COEFF_6 | 0x4d | The 6th coefficient of TX spectral shaping filter. |
| 0x20 | 0x12 | MODEM_TX_FILTER_COEFF_5 | 0x36 | The 5th coefficient of TX spectral shaping filter. |
| 0x20 | 0x13 | MODEM_TX_FILTER_COEFF_4 | 0x21 | The 4th coefficient of TX spectral shaping filter. |
| 0x20 | 0x14 | MODEM_TX_FILTER_COEFF_3 | 0x11 | The 3rd coefficient of TX spectral shaping filter. |
| 0x20 | 0x15 | MODEM_TX_FILTER_COEFF_2 | 0x08 | The 2nd coefficient of TX spectral shaping filter. |
| 0x20 | 0x16 | MODEM_TX_FILTER_COEFF_1 | 0x03 | The 1st coefficient of TX spectral shaping filter. |
| 0x20 | 0x17 | MODEM_TX_FILTER_COEFF_0 | 0x01 | The 0th coefficient of TX spectral shaping filter. |
| 0x20 | 0x18 | MODEM_TX_RAMP_DELAY | 0x01 | TX ramp-down delay setting. |
| 0x20 | 0x19 | MODEM_MDM_CTRL | 0x00 | MDM control. |
| 0x20 | 0x1a | MODEM_IF_CONTROL | 0x08 | Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation. |
| 0x20 | 0x1b 0x1c 0x1d | MODEM_IF_FREQ | 0x03 0xc0 0x00 | the IF frequency setting (an 18-bit signed number). |
| 0x20 | 0x1e | MODEM_DECIMATION_CFG1 | 0x10 | Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter. |
| 0x20 | 0x1f | MODEM_DECIMATION_CFG0 | 0x20 | Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter. |
| 0x20 | 0x20 | MODEM_DECIMATION_CFG2 | 0x00 | Specifies miscellaneous decimator filter selections. |
| 0x20 | 0x21 | MODEM_IFPKD_THRESHOLDS | 0xe8 |  |
| 0x20 | 0x22 0x23 | MODEM_BCR_OSR | 0x00 0x4b | RX BCR/Slicer oversampling rate (12-bit unsigned number). |
| 0x20 | 0x24 0x25 0x26 | MODEM_BCR_NCO_OFFSET | 0x06 0xd3 0xa0 | RX BCR NCO offset value (an unsigned 22-bit number). |
| 0x20 | 0x27 0x28 | MODEM_BCR_GAIN | 0x06 0xd3 | The unsigned 11-bit RX BCR loop gain value. |
| 0x20 | 0x29 | MODEM_BCR_GEAR | 0x02 | RX BCR loop gear control. |
| 0x20 | 0x2a | MODEM_BCR_MISC1 | 0xc0 | Miscellaneous control bits for the RX BCR loop. |
| 0x20 | 0x2b | MODEM_BCR_MISC0 | 0x00 | Miscellaneous RX BCR loop controls. |
| 0x20 | 0x2c | MODEM_AFC_GEAR | 0x00 | RX AFC loop gear control. |
| 0x20 | 0x2d | MODEM_AFC_WAIT | 0x23 | RX AFC loop wait time control. |
| 0x20 | 0x2e 0x2f | MODEM_AFC_GAIN | 0x83 0x69 | Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. |
| 0x20 | 0x30 0x31 | MODEM_AFC_LIMITER | 0x00 0x40 | Set the AFC limiter value. |
| 0x20 | 0x32 | MODEM_AFC_MISC | 0xa0 | Specifies miscellaneous AFC control bits. |
| 0x20 | 0x33 | MODEM_AFC_ZIFOFF | 0x00 | AFC fixed frequency offset in zero IF mode. |
| 0x20 | 0x34 | MODEM_ADC_CTRL | 0x00 | Sigma Delta ADC controls. |
| 0x20 | 0x35 | MODEM_AGC_CONTROL | 0xe0 | Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain. |
| 0x20 | 0x38 | MODEM_AGC_WINDOW_SIZE | 0x11 | Specifies the size of the measurement and settling windows for the AGC algorithm. |
| 0x20 | 0x39 | MODEM_AGC_RFPD_DECAY | 0x10 | Sets the decay time of the RF peak detectors. |
| 0x20 | 0x3a | MODEM_AGC_IFPD_DECAY | 0x10 | Sets the decay time of the IF peak detectors. |
| 0x20 | 0x3b | MODEM_FSK4_GAIN1 | 0x0b | Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression. |
| 0x20 | 0x3c | MODEM_FSK4_GAIN0 | 0x1c | Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression. |
| 0x20 | 0x3d 0x3e | MODEM_FSK4_TH | 0x40 0x00 | 16 bit 4(G)FSK slicer threshold. |
| 0x20 | 0x3f | MODEM_FSK4_MAP | 0x00 | 4(G)FSK symbol mapping code. |
| 0x20 | 0x40 | MODEM_OOK_PDTC | 0x2b | Configures the attack and decay times of the OOK Peak Detector. |
| 0x20 | 0x41 | MODEM_OOK_BLOPK | 0x0c | Configures the slicing reference level of the OOK Peak Detector. |
| 0x20 | 0x42 | MODEM_OOK_CNT1 | 0xa4 | OOK control. |
| 0x20 | 0x43 | MODEM_OOK_MISC | 0x03 | Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator. |
| 0x20 | 0x45 | MODEM_RAW_CONTROL | 0x02 | Defines gain and enable controls for raw / nonstandard mode. |
| 0x20 | 0x46 0x47 | MODEM_RAW_EYE | 0x00 0xa3 | 11 bit eye-open detector threshold. |
| 0x20 | 0x50 | MODEM_RAW_SEARCH2 | 0x00 | Defines and controls the search period length for the Moving Average and Min-Max detectors. |
| 0x20 | 0x51 | MODEM_CLKGEN_BAND | 0x08 | Select PLL Synthesizer output divider ratio as a function of frequency band. |
| 0x20 | 0x54 | MODEM_SPIKE_DET | 0x00 | Configures the threshold for (G)FSK Spike Detection. |

| PA (0x22)
--- | ---
| Group | Number | Name | Default | Summary | Feature Available
| 0x22 | 0x00 | PA_MODE | 0x08 | Selects the PA operating mode, and selects resolution of PA power adjustment (i.e., step size). |
| 0x22 | 0x01 | PA_PWR_LVL | 0x7f | Configuration of PA output power level. |
| 0x22 | 0x02 | PA_BIAS_CLKDUTY | 0x00 | Configuration of the PA Bias and duty cycle of the TX clock source. |
| 0x22 | 0x03 | PA_TC | 0x5d | Configuration of PA ramping parameters. |
| 0x22 | 0x04 | PA_RAMP_EX | 0x80 | Select the time constant of the external PA ramp signal. |
| 0x22 | 0x05 | PA_RAMP_DOWN_DELAY | 0x23 | Delay from the start of the PA ramp down to disabling of the PA output. |

| SYNTH (0x23)
--- | ---
| Group | Number | Name | Default | Summary | Feature Available
| 0x23 | 0x00 | SYNTH_PFDCP_CPFF | 0x2c | Feed forward charge pump current selection. |
| 0x23 | 0x01 | SYNTH_PFDCP_CPINT | 0x0e | Integration charge pump current selection. |
| 0x23 | 0x02 | SYNTH_VCO_KV | 0x0b | Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path. |
| 0x23 | 0x03 | SYNTH_LPFILT3 | 0x04 | Value of resistor R2 in feed-forward path of loop filter. |
| 0x23 | 0x04 | SYNTH_LPFILT2 | 0x0c | Value of capacitor C2 in feed-forward path of loop filter. |
| 0x23 | 0x05 | SYNTH_LPFILT1 | 0x73 | Value of capacitors C1 and C3 in feed-forward path of loop filter. |
| 0x23 | 0x06 | SYNTH_LPFILT0 | 0x03 | Bias current of the active amplifier in the feed-forward loop filter. |
| 0x23 | 0x07 | SYNTH_VCO_KVCAL | 0x05 | Scaling entire KV of VCO. |

| FREQ_CONTROL (0x40)
--- | ---
| Group | Number | Name | Default | Summary | Feature Available
| 0x40 | 0x00 | FREQ_CONTROL_INTE | 0x3c | Frac-N PLL Synthesizer integer divide number. |
| 0x40 | 0x01 0x02 0x03 | FREQ_CONTROL_FRAC | 0x08 0x00 0x00 | Frac-N PLL fraction number. |
| 0x40 | 0x04 0x05 | FREQ_CONTROL_CHANNEL_STEP_SIZE | 0x00 0x00 | EZ Frequency Programming channel step size. |
| 0x40 | 0x06 | FREQ_CONTROL_W_SIZE | 0x20 | Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. |

| PTI (0xf0)
--- | ---
| Group | Number | Name | Default | Summary | Feature Available
| 0xf0 | 0x00 | PTI_CTL | 0x80 | Packet Trace Interface control fields. |
| 0xf0 | 0x01 0x02 | PTI_BAUD | 0x13 0x88 | Desired baud rate for the PTI interface. |
| 0xf0 | 0x03 | PTI_LOG_EN | 0x00 | Enables what the PTI logs. |

## Command Details

### BOOT_COMMANDS

#### POWER_UP

- Number: 0x02
- Summary: Command to power-up the device and select the operational mode and functionality.
- Purpose:
  - This command MUST be issued to complete the power-up sequence for the device. The POWER_UP command is issued after the POR sequence has completed AND CTS is high. CTS can be polled using READ_CMD_BUFF.
  - In the event that a patch is downloaded to the chip, the patch must be downloaded before the POWER_UP command is issued.
  - Power-up is complete when the CTS is high. This command may take longer to complete than other commands, as the chip also performs several internal calibrations.
  - These calibrations include calibration of the boot clock oscillator and the 32kHz R-C oscillator against the crystal oscillator; it is therefore necessary to specify the frequency of the crystal oscillator through the XO_FREQ parameter.
- Argument Stream:

  POWER_UP Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x02
  | 0x01 | BOOT_OPTIONS | PATCH | 0 | FUNC
  | 0x02 | XTAL_OPTIONS | 0 | 0 | 0 | 0 | 0 | 0 | 0 | TCXO
  | 0x03 | XO_FREQ | XO_FREQ[31:24]
  0x04 | XO_FREQ[23:16]
  0x05 | XO_FREQ[15:8]
  0x06 | XO_FREQ[7:0]

- Reply Stream:

  POWER_UP Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CTS | CTS

- Argument Fields:

  ###### BOOT_OPTIONS

  PATCH
  Description:
    Select patch mode or normal boot mode.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    NO_PATCH | 0 | Power up into functional mode specified by FUNC parameter. |
    PATCH | 1 | Indicates a patch has been applied. Validate patch matches the function selected (indicated by the FUNC parameter) and boot the device. |

  FUNC[5:0]
  Description:
    Selects the functionality of the device by specifying the firmware image to be loaded upon boot-up.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    PRO | 1 | Power the chip up into EZRadio PRO functional mode. |

  ###### XTAL_OPTIONS

  TCXO
  Description:
    Selects if the reference oscillator signal is derived from an external TCXO (connected to the XIN pin), or from the internal crystal oscillator in conjunction with a crystal blank (connected across the XIN/XOUT pins).
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    XTAL | 0 | Reference signal is derived from the internal crystal oscillator. |
    TCXO | 1 | Reference signal is derived from an external TCXO. |

  ###### XO_FREQ

  XO_FREQ[31:0]
  Description:
    - Specifies the frequency of the internal crystal oscillator or external TCXO in Hz. The nominal value is 30000000 (30 MHz) = 0x01C9C380.
    - This parameter is used during calibration of the Boot Clock Oscillator and 32kHz R-C Oscillator, but is NOT used for calibration or tuning of the PLL Synthesizer.
  Type:
    U32
  Min:
    0x17d7840
  Max:
    0x1e84800
- Reply Fields:

  ###### CTS

  CTS[7:0]
  Description:
    Clear to Send. Indicates that the previous command has completed execution and the response byte stream (if any) is valid. The next command may be sent.
  Type:
    U8

### COMMON_COMMANDS

#### NOP

- Number: 0x00
- Summary: No Operation command.
- Purpose:
  - This command may be used to ensure that communication with the device has been established. Upon receipt of this command, the chip performs no action except to return CTS.
- Argument Stream:

  NOP Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x00

- Reply Stream:

  NOP Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CTS | CTS

- Argument Fields:
- Reply Fields:

  ###### CTS

  CTS[7:0]
  Description:
    Clear to Send. Indicates that the previous command has completed execution and the response byte stream (if any) is valid. The next command may be sent.
  Type:
    U8

#### PART_INFO

- Number: 0x01
- Summary: Reports basic information about the device.
- Purpose:
  - Returns Part Number, Part Version, ROM ID, etc.
- Argument Stream:

  PART_INFO Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x01

- Reply Stream:

  PART_INFO Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CTS | CTS
  | 0x01 | CHIPREV | CHIPREV
  | 0x02 | PART | PART[15:8]
  0x03 | PART[7:0]
  | 0x04 | PBUILD | PBUILD
  | 0x05 | ID | ID[15:8]
  0x06 | ID[7:0]
  | 0x07 | CUSTOMER | CUSTOMER
  | 0x08 | ROMID | ROMID

- Argument Fields:
- Reply Fields:

  ###### CTS

  CTS[7:0]
  Description:
    Clear to Send. Indicates that the previous command has completed execution and the response byte stream (if any) is valid. The next command may be sent.
  Type:
    U8

  ###### CHIPREV

  CHIPREV[7:0]
  Description:
    Chip Mask Revision.
  Type:
    U8

  ###### PART

  PART[15:0]
  Description:
    Part Number (e.g., si4461 will return - 0x4461).
  Type:
    U16

  ###### PBUILD

  PBUILD[7:0]
  Description:
    Part Build.
  Type:
    U8

  ###### ID

  ID[15:0]
  Description:
    Id.
  Type:
    U16

  ###### CUSTOMER

  CUSTOMER[7:0]
  Description:
    Customer ID.
  Type:
    U8

  ###### ROMID

  ROMID[7:0]
  Description:
    ROM Id.
  Type:
    U8

#### FUNC_INFO

- Number: 0x10
- Summary: Returns the Function revision information of the device.
- Purpose:
  - Return Function revision numbers for currently loaded functional mode. Contrast with PART_INFO.
- Argument Stream:

  FUNC_INFO Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x10

- Reply Stream:

  FUNC_INFO Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CTS | CTS
  | 0x01 | REVEXT | REVEXT
  | 0x02 | REVBRANCH | REVBRANCH
  | 0x03 | REVINT | REVINT
  | 0x04 | PATCH | PATCH[15:8]
  0x05 | PATCH[7:0]
  | 0x06 | FUNC | FUNC

- Argument Fields:
- Reply Fields:

  ###### CTS

  CTS[7:0]
  Description:
    Clear to Send. Indicates that the previous command has completed execution and the response byte stream (if any) is valid. The next command may be sent.
  Type:
    U8

  ###### REVEXT

  REVEXT[7:0]
  Description:
    External revision number.
  Type:
    U8
  Min:
    0x0
  Max:
    0xff

  ###### REVBRANCH

  REVBRANCH[7:0]
  Description:
    Branch revision number.
  Type:
    U8
  Min:
    0x0
  Max:
    0xff

  ###### REVINT

  REVINT[7:0]
  Description:
    Internal revision number.
  Type:
    U8
  Min:
    0x0
  Max:
    0xff

  ###### PATCH

  PATCH[15:0]
  Description:
    - ID of applied patch. This is also the last 2 bytes in the associated patch file (*.csg).
    - 0x0000 = No patch applied.
  Type:
    U16

  ###### FUNC

  FUNC[7:0]
  Description:
    Current functional mode.
  Type:
    U8

#### SET_PROPERTY

- Number: 0x11
- Summary: Sets the value of one or more properties.
- Purpose:
  - This command sets the value of one or more properties. Properties are similar to parameters passed to an API command, but are not expected to change frequently. They are typically used to configure the operation of various internal circuit blocks.
  - Properties may be controlled by higher layers of the user's software. Setting some properties may not cause the device to take immediate action; however, the property will take effect once a command which uses that property is issued.
  - Properties that affect similar circuit blocks or functions (e.g., MODEM or PA or SYNTH properties) are grouped together and share the same GROUP parameter value. Each property within that GROUP has a different offset number or index.
  - A single property may be configured by setting the NUM_PROPS parameter = 0x01, setting the START_PROP parameter to the offset number of that particular property, followed by a single data byte representing the desired value of the property.
  - Multiple contiguous properties may be configured by setting the NUM_PROPS parameter equal to the number of desired properties, setting the START_PROP parameter to the offset number of the first property within that contiguous block of properties, followed by a string of data bytes representing the desired values of the properties.
  - The maximum number of properties that may be set with a single SET_PROPERTY command is 12.
- Argument Stream:

  SET_PROPERTY Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x11
  | 0x01 | GROUP | GROUP
  | 0x02 | NUM_PROPS | NUM_PROPS
  | 0x03 | START_PROP | START_PROP
  | 0x04 | DATA[0] | DATA
  | ... | ... | ...
  | 0x0f | DATA[11] | DATA

- Reply Stream:

  SET_PROPERTY Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CTS | CTS

- Argument Fields:

  ###### GROUP

  GROUP[7:0]
  Description:
    Selects the property group to be configured.
  Type:
    U8

  ###### NUM_PROPS

  NUM_PROPS[7:0]
  Description:
    Selects the number of contiguous properties to be written, starting at START_PROP.
  Type:
    U8
  Min:
    0x1
  Max:
    0xc

  ###### START_PROP

  START_PROP[7:0]
  Description:
    Selects the offset number or index of the property within the specified group. The available properties are determined by the part number and the POWER_UP:FUNC selection.
  Type:
    U8

  ###### DATA[0...11]

  DATA[7:0]
  Description:
    Value to be written to the property located at START_PROP + N. this parameter is not relevant if NUM_PROPS < N + 1. (where N is the Data index)
  Type:
    U8
- Reply Fields:

  ###### CTS

  CTS[7:0]
  Description:
    Clear to Send. Indicates that the previous command has completed execution and the response byte stream (if any) is valid. The next command may be sent.
  Type:
    U8

#### GET_PROPERTY

- Number: 0x12
- Summary: Retrieves the value of one or more properties
- Purpose:
  - This command retrieves the value of one or more properties. Properties are similar to parameters passed to an API command, but are not expected to change frequently. They are typically used to configure the operation of various internal circuit blocks. The returned value represents the default property value upon POWER_UP or the value set previously with a SET_PROPERTY command.
  - Properties that affect similar circuit blocks or functions (e.g., MODEM or PA or SYNTH properties) are grouped together and share the same GROUP parameter value. Each property within that GROUP has a different offset number or index.
  - A single property may be retrieved by setting the NUM_PROPS parameter = 0x01 and setting the START_PROP parameter to the offset number of that particular property. The first data byte of the reply stream represents the value of that property.
  - Multiple contiguous properties may be retrieved by setting the NUM_PROPS parameter equal to the number of desired properties and setting the START_PROP parameter to the offset number of the first property within that contiguous block of properties. The data bytes of the reply stream represent the values of the contiguous properties in sequential order of their offset number.
  - The maximum number of properties that may be retrieved with a single GET_PROPERTY command is 16.
- Argument Stream:

  GET_PROPERTY Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x12
  | 0x01 | GROUP | GROUP
  | 0x02 | NUM_PROPS | NUM_PROPS
  | 0x03 | START_PROP | START_PROP

- Reply Stream:

  GET_PROPERTY Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CTS | CTS
  | 0x01 | DATA[0] | DATA
  | ... | ... | ...
  | 0x10 | DATA[15] | DATA

- Argument Fields:

  ###### GROUP

  GROUP[7:0]
  Description:
    Selects the property group to be retrieved.
  Type:
    U8

  ###### NUM_PROPS

  NUM_PROPS[7:0]
  Description:
    Selects the number of contiguous properties to be retrieved, starting at START_PROP.
  Type:
    U8
  Min:
    0x1
  Max:
    0x10

  ###### START_PROP

  START_PROP[7:0]
  Description:
    Selects the offset number or index of the property within the specified group. the available properties are determined by the part number and the POWER_UP:FUNC selection
  Type:
    U8
- Reply Fields:

  ###### CTS

  CTS[7:0]
  Description:
    Clear to Send. Indicates that the previous command has completed execution and the response byte stream (if any) is valid. The next command may be sent.
  Type:
    U8

  ###### DATA[0...15]

  DATA[7:0]
  Description:
    Retrieved value of the properties located starting at START_PROP. Response bytes in this field are not relevant starting at DATA[NUM_PROPS] and contiuing to the end of the DATA response field.
  Type:
    U8

#### GPIO_PIN_CFG

- Number: 0x13
- Summary: Configures the GPIO pins.
- Purpose:
  - The chip provides General Purpose Input/Output (GPIO) pins for handling a variety of signals. This command is used to select the desired signal for each GPIO pin from an enumerated list of available signals.
  - The drive strength is selectable for those pins configured as outputs. The selected drive strength is applied simultaneously to all outputs; it is currently not possible to individually configure each GPIO pin for different drive strengths.
  - Each pin provides a weak pull-up resistor (~1 Megohm) that may be individually enabled or disabled. It is recommended to disable the pull-up resistor when the pin is configured as an input and driven from an external source (other than an open-drain source).
  - The pins referenced by this command share similar hardware characteristics (i.e., drive strength, pull-up resistors, input/output configurability) but may provide access to different sets of signals. Specifically, the NIRQ and SDO pins are not "signal equivalent" to the GPIO pins.
- Argument Stream:

  GPIO_PIN_CFG Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x13
  | 0x01 | GPIO[0] | 0 | PULL_CTL | GPIO_MODE
  | ... | ... | ... | ... | ...
  | 0x04 | GPIO[3] | 0 | PULL_CTL | GPIO_MODE
  | 0x05 | NIRQ | 0 | PULL_CTL | NIRQ_MODE
  | 0x06 | SDO | 0 | PULL_CTL | SDO_MODE
  | 0x07 | GEN_CONFIG | 0 | DRV_STRENGTH | 0 | 0 | 0 | 0 | 0

- Reply Stream:

  GPIO_PIN_CFG Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CTS | CTS
  | 0x01 | GPIO[0] | GPIO_STATE | X | GPIO_MODE
  | ... | ... | ... | ... | ...
  | 0x04 | GPIO[3] | GPIO_STATE | X | GPIO_MODE
  | 0x05 | NIRQ | NIRQ_STATE | X | NIRQ_MODE
  | 0x06 | SDO | SDO_STATE | X | SDO_MODE
  | 0x07 | GEN_CONFIG | X | DRV_STRENGTH | X | X | X | X | X

- Argument Fields:

  ###### GPIO[0...3]

  PULL_CTL
  Description:
    The pin pull-up control.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    PULL_DIS | 0 | Disable pull-up resistor (recommended setting if the pin is driven from an external source, other than an open-drain source). | revB1A
    PULL_EN | 1 | Enable pull-up resistor. | revB1A

  GPIO_MODE[5:0]
  Description:
    The pin mode.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DONOTHING | 0 | Behavior of this pin is not modified. | revB1A
    TRISTATE | 1 | Input and output drivers disabled. | revB1A
    DRIVE0 | 2 | Pin is configured as a CMOS output and driven low. | revB1A
    DRIVE1 | 3 | Pin is configured as a CMOS output and driven high. | revB1A
    INPUT | 4 | Pin is configured as a CMOS input. This is used for all GPIO functions that require the pin to be an input (e.g., TXDATA input for TX Direct Mode). However, configuration of this pin as an input does NOT additionally select which internal circuit receives that input; that functionality is controlled by other properties, as appropriate. | revB1A
    32K_CLK | 5 | Outputs 32 kHz clock selected using GLOBAL_CLK_CFG:CLK_32K_SEL. Output low if the 32 kHz clock is not enabled. | revB1A
    BOOT_CLK | 6 | Outputs the boot clock signal. This signal will only be present when the chip is in the SPI_ACTIVE state as that is the only state in which the boot clock is active. | revB1A
    DIV_CLK | 7 | Outputs the divided clock signal (or the divided boot clock signal in SPI ACTIVE state). This output is low while the chip is in SLEEP state as the source (e.g., the Xtal Oscillator) for the divided clock signal is not running, and outputs the divided XtalOsc signal in all other states. The divider is configured using the GLOBAL_CLK_CFG:DIVIDED_CLK_SEL. | revB1A
    CTS | 8 | Clear To Send signal. This output goes high when the command handler is able to receive a new command, and is low otherwise. | revB1A
    INV_CTS | 9 | Inverted Clear To Send signal. This output goes low when clear to send a new command, and is high otherwise. | revB1A
    CMD_OVERLAP | 10 | This output is low unless a command overlap occurs (i.e., another command is sent before the command handler completes processing a previous command). When command overlap occurs, this output goes high until the rising edge of CTS. | revB1A
    SDO | 11 | Outputs the Serial Data Out (SDO) signal for the SPI bus. | revB1A
    POR | 12 | This output goes low during Power-On Reset and goes high upon completion of POR. | revB1A
    CAL_WUT | 13 | This output is normally low, and pulses high for one cycle of the 32 kHz clock upon expiration of the Calibration Timer. The 32 kHz clock must be enabled in order to use the Calibration Timer. The Calibration Timer period is configured using GLOBAL_WUT_CONFIG:WUT_CAL_PERIOD and enabled by GLOBAL_WUT_CONFIG:CAL_EN. | revB1A
    WUT | 14 | This output is normally low, and pulses high for 2(WUT_R+1) cycles of the 32 kHz clock upon expiration of the Wake-Up Timer (WUT). The 32 kHz clock must be enabled in order to use the WUT. The period of the WUT is configured using GLOBAL_WUT_M, and GLOBAL_WUT_R and enabled by GLOBAL_WUT_CONFIG:WUT_EN. | revB1A
    EN_PA | 15 | This output goes high when the internal PA is enabled. | revB1A
    TX_DATA_CLK | 16 | Outputs the TX Data Clock signal. This signal is a square wave at the selected TX data rate, and is intended for use in TX Direct Synchronous Mode (i.e., in conjunction with a pin configured for TX Data Input). | revB1A
    TX_DATA | 19 | Outputs the TX data bits pulled from the TX FIFO and sent to the TX modulator. This is an output signal (primarily for diagnostic purposes) and is NOT used as an input for TX Direct Sync/Async mode. | revB1A
    IN_SLEEP | 28 | This output goes high when the chip is NOT in SLEEP state, and goes low when in SLEEP state. | revB1A
    PKT_TRACE | 29 | Outputs packet trace data when not in sleep state. Output low when in sleep state. |
    TX_STATE | 32 | This output is set high while in TX state and is low otherwise. The TX_STATE and RX_STATE signals are typically used for control of peripheral circuits (e.g., a T/R Switch). | revB1A
    TX_FIFO_EMPTY | 35 | This output is high while the number of bytes of empty space in the TX FIFO exceeds the threshold value set by the PKT_TX_THRESHOLD property, and is low otherwise. | revB1A
    LOW_BATT | 36 | This output is high while the battery voltage drops below the threshold value set by the GLOBAL_LOW_BATT_THRESH property, and is low otherwise. |

  ###### NIRQ

  PULL_CTL
  Description:
    The pin pull-up control.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    PULL_DIS | 0 | Disable pull-up resistor (recommended setting if the pin is driven from an external source, other than an open-drain source). | revB1A
    PULL_EN | 1 | Enable pull-up resistor. | revB1A

  NIRQ_MODE[5:0]
  Description:
    The pin mode.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DONOTHING | 0 | Behavior of this pin is not modified. | revB1A
    TRISTATE | 1 | Input and output drivers disabled. | revB1A
    DRIVE0 | 2 | Pin is configured as a CMOS output and driven low. | revB1A
    DRIVE1 | 3 | Pin is configured as a CMOS output and driven high. | revB1A
    INPUT | 4 | Pin is configured as a CMOS input. This is used for all GPIO functions that require the pin to be an input (e.g., TXDATA input for TX Direct Mode). However, configuration of this pin as an input does NOT additionally select which internal circuit receives that input; that functionality is controlled by other properties, as appropriate. | revB1A
    DIV_CLK | 7 | Outputs the divided clock signal (or the divided boot clock signal in SPI ACTIVE state). This output is low while the chip is in SLEEP state as the source (e.g., the Xtal Oscillator) for the divided clock signal is not running, and outputs the divided XtalOsc signal in all other states. The divider is configured using the GLOBAL_CLK_CFG:DIVIDED_CLK_SEL. | revB1A
    CTS | 8 | Clear To Send signal. This output goes high when the command handler is able to receive a new command, and is low otherwise. | revB1A
    SDO | 11 | Outputs the Serial Data Out (SDO) signal for the SPI bus. | revB1A
    POR | 12 | This output goes low during Power-On Reset and goes high upon completion of POR. | revB1A
    EN_PA | 15 | This output goes high when the internal PA is enabled. | revB1A
    TX_DATA_CLK | 16 | Outputs the TX Data Clock signal. This signal is a square wave at the selected TX data rate, and is intended for use in TX Direct Synchronous Mode (i.e., in conjunction with a pin configured for TX Data Input). | revB1A
    TX_DATA | 19 | Outputs the TX data bits pulled from the TX FIFO and sent to the TX modulator. This is an output signal (primarily for diagnostic purposes) and is NOT used as an input for TX Direct Sync/Async mode. | revB1A
    PKT_TRACE | 29 | Outputs packet trace data when not in sleep state. Output low when in sleep state. |
    NIRQ | 39 | Active low interrupt signal. | revBlA

  ###### SDO

  PULL_CTL
  Description:
    The pin pull-up control.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    PULL_DIS | 0 | Disable pull-up resistor (recommended setting if the pin is driven from an external source, other than an open-drain source). | revB1A
    PULL_EN | 1 | Enable pull-up resistor. | revB1A

  SDO_MODE[5:0]
  Description:
    The pin mode.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DONOTHING | 0 | Behavior of this pin is not modified. | revB1A
    TRISTATE | 1 | Input and output drivers disabled. | revB1A
    DRIVE0 | 2 | Pin is configured as a CMOS output and driven low. | revB1A
    DRIVE1 | 3 | Pin is configured as a CMOS output and driven high. | revB1A
    INPUT | 4 | Pin is configured as a CMOS input. This is used for all GPIO functions that require the pin to be an input (e.g., TXDATA input for TX Direct Mode). However, configuration of this pin as an input does NOT additionally select which internal circuit receives that input; that functionality is controlled by other properties, as appropriate. | revB1A
    32K_CLK | 5 | Outputs 32 kHz clock selected using GLOBAL_CLK_CFG:CLK_32K_SEL. Output low if the 32 kHz clock is not enabled. | revB1A
    DIV_CLK | 7 | Outputs the divided clock signal (or the divided boot clock signal in SPI ACTIVE state). This output is low while the chip is in SLEEP state as the source (e.g., the Xtal Oscillator) for the divided clock signal is not running, and outputs the divided XtalOsc signal in all other states. The divider is configured using the GLOBAL_CLK_CFG:DIVIDED_CLK_SEL. | revB1A
    CTS | 8 | Clear To Send signal. This output goes high when the command handler is able to receive a new command, and is low otherwise. | revB1A
    SDO | 11 | Outputs the Serial Data Out (SDO) signal for the SPI bus. | revB1A
    POR | 12 | This output goes low during Power-On Reset and goes high upon completion of POR. | revB1A
    WUT | 14 | This output is normally low, and pulses high for 2(WUT_R+1) cycles of the 32 kHz clock upon expiration of the Wake-Up Timer (WUT). The 32 kHz clock must be enabled in order to use the WUT. The period of the WUT is configured using GLOBAL_WUT_M, and GLOBAL_WUT_R and enabled by GLOBAL_WUT_CONFIG:WUT_EN. | revB1A
    EN_PA | 15 | This output goes high when the internal PA is enabled. | revB1A
    TX_DATA_CLK | 16 | Outputs the TX Data Clock signal. This signal is a square wave at the selected TX data rate, and is intended for use in TX Direct Synchronous Mode (i.e., in conjunction with a pin configured for TX Data Input). | revB1A
    TX_DATA | 19 | Outputs the TX data bits pulled from the TX FIFO and sent to the TX modulator. This is an output signal (primarily for diagnostic purposes) and is NOT used as an input for TX Direct Sync/Async mode. | revB1A

  ###### GEN_CONFIG

  DRV_STRENGTH[1:0]
  Description:
    - Selects the level of drive strength for those GPIO/NIRQ/SDO pins configured as outputs.
    - The selected level of drive strength is applied simultaneously to all output pins, with the following exception: GPIO0 will exhibit a weaker drive strength than the other GPIO pins but only in the lowest drive strength setting; its drive strength is the same for all other settings.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    HIGH | 0 | GPIOs configured as outputs will have the highest drive strength. | revB1A
    MED_HIGH | 1 | GPIOs configured as outputs will have a medium drive strength. | revB1A
    MED_LOW | 2 | GPIOs configured as outputs will have a medium drive strength. | revB1A
    LOW | 3 | GPIOs configured as outputs will have the lowest drive strength. | revB1A

- Reply Fields:

  ###### CTS

  CTS[7:0]
  Description:
    Clear to Send. Indicates that the previous command has completed execution and the response byte stream (if any) is valid. The next command may be sent.
  Type:
    U8

  ###### GPIO[0...3]

  GPIO_STATE
  Description:
    Reads back the logic level on the pin.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    INACTIVE | 0 | Pin was read back as a 0. | revB1A
    ACTIVE | 1 | Pin was read back as a 1. | revB1A

  GPIO_MODE[5:0]
  Description:
    Reads back the enumeration of the currently selected function for the pin.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DONOTHING | 0 | Behavior of this pin is not modified. | revB1A
    TRISTATE | 1 | Input and output drivers disabled. | revB1A
    DRIVE0 | 2 | Pin is configured as a CMOS output and driven low. | revB1A
    DRIVE1 | 3 | Pin is configured as a CMOS output and driven high. | revB1A
    INPUT | 4 | Pin is configured as a CMOS input. This is used for all GPIO functions that require the pin to be an input (e.g., TXDATA input for TX Direct Mode). However, configuration of this pin as an input does NOT additionally select which internal circuit receives that input; that functionality is controlled by other properties, as appropriate. | revB1A
    32K_CLK | 5 | Outputs 32 kHz clock selected using GLOBAL_CLK_CFG:CLK_32K_SEL. Output low if the 32 kHz clock is not enabled. | revB1A
    BOOT_CLK | 6 | Outputs the boot clock signal. This signal will only be present when the chip is in the SPI_ACTIVE state as that is the only state in which the boot clock is active. | revB1A
    DIV_CLK | 7 | Outputs the divided clock signal (or the divided boot clock signal in SPI ACTIVE state). This output is low while the chip is in SLEEP state as the source (e.g., the Xtal Oscillator) for the divided clock signal is not running, and outputs the divided XtalOsc signal in all other states. The divider is configured using the GLOBAL_CLK_CFG:DIVIDED_CLK_SEL. | revB1A
    CTS | 8 | Clear To Send signal. This output goes high when the command handler is able to receive a new command, and is low otherwise. | revB1A
    INV_CTS | 9 | Inverted Clear To Send signal. This output goes low when clear to send a new command, and is high otherwise. | revB1A
    CMD_OVERLAP | 10 | This output is low unless a command overlap occurs (i.e., another command is sent before the command handler completes processing a previous command). When command overlap occurs, this output goes high until the rising edge of CTS. | revB1A
    SDO | 11 | Outputs the Serial Data Out (SDO) signal for the SPI bus. | revB1A
    POR | 12 | This output goes low during Power-On Reset and goes high upon completion of POR. | revB1A
    CAL_WUT | 13 | This output is normally low, and pulses high for one cycle of the 32 kHz clock upon expiration of the Calibration Timer. The 32 kHz clock must be enabled in order to use the Calibration Timer. The Calibration Timer period is configured using GLOBAL_WUT_CONFIG:WUT_CAL_PERIOD and enabled by GLOBAL_WUT_CONFIG:CAL_EN. | revB1A
    WUT | 14 | This output is normally low, and pulses high for 2(WUT_R+1) cycles of the 32 kHz clock upon expiration of the Wake-Up Timer (WUT). The 32 kHz clock must be enabled in order to use the WUT. The period of the WUT is configured using GLOBAL_WUT_M, and GLOBAL_WUT_R and enabled by GLOBAL_WUT_CONFIG:WUT_EN. | revB1A
    EN_PA | 15 | This output goes high when the internal PA is enabled. | revB1A
    TX_DATA_CLK | 16 | Outputs the TX Data Clock signal. This signal is a square wave at the selected TX data rate, and is intended for use in TX Direct Synchronous Mode (i.e., in conjunction with a pin configured for TX Data Input). | revB1A
    TX_DATA | 19 | Outputs the TX data bits pulled from the TX FIFO and sent to the TX modulator. This is an output signal (primarily for diagnostic purposes) and is NOT used as an input for TX Direct Sync/Async mode. | revB1A
    IN_SLEEP | 28 | This output goes high when the chip is NOT in SLEEP state, and goes low when in SLEEP state. | revB1A
    PKT_TRACE | 29 | Outputs packet trace data when not in sleep state. Output low when in sleep state. |
    TX_STATE | 32 | This output is set high while in TX state and is low otherwise. The TX_STATE and RX_STATE signals are typically used for control of peripheral circuits (e.g., a T/R Switch). | revB1A
    TX_FIFO_EMPTY | 35 | This output is high while the number of bytes of empty space in the TX FIFO exceeds the threshold value set by the PKT_TX_THRESHOLD property, and is low otherwise. | revB1A
    LOW_BATT | 36 | This output is high while the battery voltage drops below the threshold value set by the GLOBAL_LOW_BATT_THRESH property, and is low otherwise. |

  ###### NIRQ

  NIRQ_STATE
  Description:
    Reads back the logic level on the NIRQ pin.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    INACTIVE | 0 | Pin was read back as a 0. | revB1A
    ACTIVE | 1 | Pin was read back as a 1. | revB1A

  NIRQ_MODE[5:0]
  Description:
    Reads back the enumeration of the currently selected function for the NIRQ pin.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DONOTHING | 0 | Behavior of this pin is not modified. | revB1A
    TRISTATE | 1 | Input and output drivers disabled. | revB1A
    DRIVE0 | 2 | Pin is configured as a CMOS output and driven low. | revB1A
    DRIVE1 | 3 | Pin is configured as a CMOS output and driven high. | revB1A
    INPUT | 4 | Pin is configured as a CMOS input. This is used for all GPIO functions that require the pin to be an input (e.g., TXDATA input for TX Direct Mode). However, configuration of this pin as an input does NOT additionally select which internal circuit receives that input; that functionality is controlled by other properties, as appropriate. | revB1A
    DIV_CLK | 7 | Outputs the divided clock signal (or the divided boot clock signal in SPI ACTIVE state). This output is low while the chip is in SLEEP state as the source (e.g., the Xtal Oscillator) for the divided clock signal is not running, and outputs the divided XtalOsc signal in all other states. The divider is configured using the GLOBAL_CLK_CFG:DIVIDED_CLK_SEL. | revB1A
    CTS | 8 | Clear To Send signal. This output goes high when the command handler is able to receive a new command, and is low otherwise. | revB1A
    SDO | 11 | Outputs the Serial Data Out (SDO) signal for the SPI bus. | revB1A
    POR | 12 | This output goes low during Power-On Reset and goes high upon completion of POR. | revB1A
    EN_PA | 15 | This output goes high when the internal PA is enabled. | revB1A
    TX_DATA_CLK | 16 | Outputs the TX Data Clock signal. This signal is a square wave at the selected TX data rate, and is intended for use in TX Direct Synchronous Mode (i.e., in conjunction with a pin configured for TX Data Input). | revB1A
    TX_DATA | 19 | Outputs the TX data bits pulled from the TX FIFO and sent to the TX modulator. This is an output signal (primarily for diagnostic purposes) and is NOT used as an input for TX Direct Sync/Async mode. | revB1A
    PKT_TRACE | 29 | Outputs packet trace data when not in sleep state. Output low when in sleep state. |
    NIRQ | 39 | Active low interrupt signal. | revBlA

  ###### SDO

  SDO_STATE
  Description:
    Reads back the logic level on the SDO pin.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    INACTIVE | 0 | Pin was read back as a 0. | revB1A
    ACTIVE | 1 | Pin was read back as a 1. | revB1A

  SDO_MODE[5:0]
  Description:
    Reads back the enumeration of the currently selected function for the SDO pin.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DONOTHING | 0 | Behavior of this pin is not modified. | revB1A
    TRISTATE | 1 | Input and output drivers disabled. | revB1A
    DRIVE0 | 2 | Pin is configured as a CMOS output and driven low. | revB1A
    DRIVE1 | 3 | Pin is configured as a CMOS output and driven high. | revB1A
    INPUT | 4 | Pin is configured as a CMOS input. This is used for all GPIO functions that require the pin to be an input (e.g., TXDATA input for TX Direct Mode). However, configuration of this pin as an input does NOT additionally select which internal circuit receives that input; that functionality is controlled by other properties, as appropriate. | revB1A
    32K_CLK | 5 | Outputs 32 kHz clock selected using GLOBAL_CLK_CFG:CLK_32K_SEL. Output low if the 32 kHz clock is not enabled. | revB1A
    DIV_CLK | 7 | Outputs the divided clock signal (or the divided boot clock signal in SPI ACTIVE state). This output is low while the chip is in SLEEP state as the source (e.g., the Xtal Oscillator) for the divided clock signal is not running, and outputs the divided XtalOsc signal in all other states. The divider is configured using the GLOBAL_CLK_CFG:DIVIDED_CLK_SEL. | revB1A
    CTS | 8 | Clear To Send signal. This output goes high when the command handler is able to receive a new command, and is low otherwise. | revB1A
    SDO | 11 | Outputs the Serial Data Out (SDO) signal for the SPI bus. | revB1A
    POR | 12 | This output goes low during Power-On Reset and goes high upon completion of POR. | revB1A
    WUT | 14 | This output is normally low, and pulses high for 2(WUT_R+1) cycles of the 32 kHz clock upon expiration of the Wake-Up Timer (WUT). The 32 kHz clock must be enabled in order to use the WUT. The period of the WUT is configured using GLOBAL_WUT_M, and GLOBAL_WUT_R and enabled by GLOBAL_WUT_CONFIG:WUT_EN. | revB1A
    EN_PA | 15 | This output goes high when the internal PA is enabled. | revB1A
    TX_DATA_CLK | 16 | Outputs the TX Data Clock signal. This signal is a square wave at the selected TX data rate, and is intended for use in TX Direct Synchronous Mode (i.e., in conjunction with a pin configured for TX Data Input). | revB1A
    TX_DATA | 19 | Outputs the TX data bits pulled from the TX FIFO and sent to the TX modulator. This is an output signal (primarily for diagnostic purposes) and is NOT used as an input for TX Direct Sync/Async mode. | revB1A

  ###### GEN_CONFIG

  DRV_STRENGTH[1:0]
  Description:
    Reads back the enumeration of the currently selected drive strength.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    HIGH | 0 | GPIOs configured as outputs will have the highest drive strength. | revB1A
    MED_HIGH | 1 | GPIOs configured as outputs will have a medium drive strength. | revB1A
    MED_LOW | 2 | GPIOs configured as outputs will have a medium drive strength. | revB1A
    LOW | 3 | GPIOs configured as outputs will have the lowest drive strength. | revB1A

#### FIFO_INFO

- Number: 0x15
- Summary: Access the current byte counts in the TX and RX FIFOs, and provide for resetting the FIFOs.
- Purpose:
  - The chip provides for two separate 64-byte FIFO memories for the purpose of storing transmit and receive data. (When the GLOBAL_CONFIG:FIFO_MODE bit is set, these two FIFOs are combined into a single 129-byte shared FIFO.)
  - The reply stream for this command returns the current number of received bytes stored in the RX FIFO, and the number of remaining empty bytes in the TX FIFO.
  - The command may also be used to reset the individual FIFOs. This is typically used for error recovery (e.g., after encountering a CRC error in RX mode). Any valid data that has not yet been retrieved from the RX FIFO will be lost as a result of a reset; it is recommended to read such data prior to a reset. The FIFOs do not need to be reset prior to initial use after power-up.
  - The FIFO reset function (if enabled) is processed prior to returning the byte count in the FIFOs. Thus the reply stream to a FIFO_INFO command that resets the FIFOs will return byte counts that indicate the FIFOs are empty.
  - A FIFO reset command should not be sent while actively receiving or transmitting a packet, as this may corrupt the index pointers into the FIFOs and result in loss of stored information.
  - The FIFO:TX and FIFO:RX bits are self-clearing; that is, there is no need to send the command twice (e.g., with the reset bits set the first time, and cleared the second time).
- Argument Stream:

  FIFO_INFO Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x15
  | 0x01 | FIFO | 0 | 0 | 0 | 0 | 0 | 0 | 0 | TX

- Reply Stream:

  FIFO_INFO Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CTS | CTS
  | 0x01 | RESERVED0 | X | X | X | X | X | X | X | X
  | 0x02 | TX_FIFO_SPACE | TX_FIFO_SPACE

- Argument Fields:

  ###### FIFO

  TX
  Description:
    - Resets the TX FIFO.
    - The TX FIFO mode specified in property GLOBAL_CONFIG:FIFO_MODE will be effective after reset.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    FALSE | 0 | Do not reset the TX data FIFO. | revB1A
    TRUE | 1 | Reset the TX data FIFO. | revB1A

- Reply Fields:

  ###### CTS

  CTS[7:0]
  Description:
    Clear to Send. Indicates that the previous command has completed execution and the response byte stream (if any) is valid. The next command may be sent.
  Type:
    U8

  ###### TX_FIFO_SPACE

  TX_FIFO_SPACE[7:0]
  Description:
    Returns the number of empty bytes (i.e., space) currently available in the TX FIFO.
  Type:
    U8

#### GET_INT_STATUS

- Number: 0x20
- Summary: Returns the interrupt status of ALL the possible interrupt events (both STATUS and PENDING). Optionally, it may be used to clear latched (PENDING) interrupt events.
- Purpose:
  - Returns the current interrupt status of ALL the possible interrupt events (both STATUS and PENDING) and optionally clears PENDING interrupts.
  - STATUS indicates the current state of an internal interrupt event such as preamble/sync word detection, packet sent/received, etc. For example, PREAMBLE_DETECT is low before detection of a valid preamble, but goes high when the preamble arrives and is successfully detected. STATUS is cleared automatically upon termination or cessation of the corresponding internal interrupt event.
  - PENDING simply latches the rising edge of the corresponding STATUS, and does not change until cleared by a GET_INT_STATUS command (or GET_CHIP_STATUS, GET_PH_STATUS, GET_MODEM_STATUS). For example, PREAMBLE_DETECT_PEND is low before detection of a valid preamble, goes high with PREAMBLE_DETECT, and remains high until cleared.
  - It is possible to poll for interrupts by reading the STATUS and PENDING response bytes, as they are always up-to-date. Additionally, PENDING interrupts may generate a HW interrupt on the NIRQ output pin, if the interrupt is enabled via INT_CTL_ENABLE, INT_CTL_PH_ENABLE, INT_CTL_MODEM_ENABLE, and INT_CTL_CHIP_ENABLE properties.
  - Sending the GET_INT_STATUS command with NO input parameters results in clearing all of the PENDING interrupts.
  - When PENDING interrupts are being cleared, the reply stream reflects their status prior to clearing.
- Argument Stream:

  GET_INT_STATUS Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x20
  | 0x01 | PH_CLR_PEND | 0 | 0 | PACKET_SENT_PEND_CLR | 0 | 0 | 0 | TX_FIFO_ALMOST_EMPTY_PEND_CLR | 0
  | 0x02 | RESERVED0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
  | 0x03 | CHIP_CLR_PEND | 0 | CAL_PEND_CLR | FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_CLR | STATE_CHANGE_PEND_CLR | CMD_ERROR_PEND_CLR | CHIP_READY_PEND_CLR | LOW_BATT_PEND_CLR | WUT_PEND_CLR

- Reply Stream:

  GET_INT_STATUS Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CTS | CTS
  | 0x01 | INT_PEND | X | X | X | X | X | CHIP_INT_PEND | MODEM_INT_PEND | PH_INT_PEND
  | 0x02 | INT_STATUS | X | X | X | X | X | CHIP_INT_STATUS | MODEM_INT_STATUS | PH_INT_STATUS
  | 0x03 | PH_PEND | X | X | PACKET_SENT_PEND | X | X | X | TX_FIFO_ALMOST_EMPTY_PEND | X
  | 0x04 | PH_STATUS | X | X | PACKET_SENT | X | X | X | TX_FIFO_ALMOST_EMPTY | X
  | 0x05 | RESERVED0 | X | X | X | X | X | X | X | X
  | 0x06 | RESERVED1 | X | X | X | X | X | X | X | X
  | 0x07 | CHIP_PEND | X | CAL_PEND | FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND | STATE_CHANGE_PEND | CMD_ERROR_PEND | CHIP_READY_PEND | LOW_BATT_PEND | WUT_PEND
  | 0x08 | CHIP_STATUS | X | CAL | FIFO_UNDERFLOW_OVERFLOW_ERROR | STATE_CHANGE | CMD_ERROR | CHIP_READY | LOW_BATT | WUT

- Argument Fields:

  ###### PH_CLR_PEND

  PACKET_SENT_PEND_CLR
  Description:
    If clear, clear any pending PACKET_SENT interrupt. If set, leave interrupt pending.
  Type:
    BOOL
  TX_FIFO_ALMOST_EMPTY_PEND_CLR
  Description:
    If clear, clear any pending TX_FIFO_ALMOST_EMPTY interrupt. If set, leave interrupt pending.
  Type:
    BOOL

  ###### CHIP_CLR_PEND

  CAL_PEND_CLR
  Description:
    If clear, clear any pending CAL interrupt. If set, leave interrupt pending.
  Type:
    BOOL
  FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_CLR
  Description:
    If clear, clear any pending FIFO_UNDERFLOW_OVERFLOW_ERROR interrupt. If set, leave interrupt pending.
  Type:
    BOOL
  STATE_CHANGE_PEND_CLR
  Description:
    If clear, clear any pending STATE_CHANGE interrupt. If set, leave interrupt pending.
  Type:
    BOOL
  CMD_ERROR_PEND_CLR
  Description:
    If clear, clear any pending CMD_ERROR interrupt. If set, leave interrupt pending.
  Type:
    BOOL
  CHIP_READY_PEND_CLR
  Description:
    If clear, clear any pending CHIP_READY interrupt. If set, leave interrupt pending.
  Type:
    BOOL
  LOW_BATT_PEND_CLR
  Description:
    If clear, clear any pending LOW_BATT interrupt. If set, leave interrupt pending.
  Type:
    BOOL
  WUT_PEND_CLR
  Description:
    If clear, clear any pending WUT interrupt. If set, leave interrupt pending.
  Type:
    BOOL
- Reply Fields:

  ###### CTS

  CTS[7:0]
  Description:
    Clear to Send. Indicates that the previous command has completed execution and the response byte stream (if any) is valid. The next command may be sent.
  Type:
    U8

  ###### INT_PEND

  CHIP_INT_PEND
  Description:
    If set, an enabled CHIP_PEND bit is set indicating an interrupt is pending. See the GET_INT_STATUS:CHIP_STATUS field for the triggering events within the Chip Status Interrupt group.
  Type:
    BOOL
  MODEM_INT_PEND
  Description:
    If set, an enabled MODEM_PEND bit is set indicating an interrupt is pending. See the GET_INT_STATUS:MODEM_STATUS field for the triggering events within the Modem Interrupt group.
  Type:
    BOOL
  PH_INT_PEND
  Description:
    If set, an enabled PH_PEND bit is set indicating an interrupt is pending. See the GET_INT_STATUS:PH_STATUS field for the triggering events within the Packet Handler Interrupt group.
  Type:
    BOOL

  ###### INT_STATUS

  CHIP_INT_STATUS
  Description:
    If set, the Chip Status Interrupt group has an interrupt pending. See the GET_INT_STATUS:CHIP_STATUS field for the triggering events within the Chip Status Interrupt group.
  Type:
    BOOL
  MODEM_INT_STATUS
  Description:
    If set, the Modem Interrupt group has an interrupt pending. See the GET_INT_STATUS:MODEM_STATUS field for the triggering events within the Modem Interrupt group.
  Type:
    BOOL
  PH_INT_STATUS
  Description:
    If set, the Packet Handler Interrupt group has an interrupt pending. See the GET_INT_STATUS:PH_STATUS field for the triggering events within the Packet Handler Interrupt group.
  Type:
    BOOL

  ###### PH_PEND

  PACKET_SENT_PEND
  Description:
    If set, a rising edge of the PACKET_SENT status bit has been detected and therefore a PACKET_SENT interrupt is pending. See associated PACKET_SENT status bit for more details.
  Type:
    BOOL
  TX_FIFO_ALMOST_EMPTY_PEND
  Description:
    If set, a rising edge of the TX_FIFO_ALMOST_EMPTY status bit has been detected and therefore a TX_FIFO_ALMOST_EMPTY interrupt is pending. See associated TX_FIFO_ALMOST_EMPTY status bit for more details.
  Type:
    BOOL

  ###### PH_STATUS

  PACKET_SENT
  Description:
    Set to indicate that data bytes in the TX FIFO were transmitted successfully. Cleared upon entry into TX state.
  Type:
    BOOL
  TX_FIFO_ALMOST_EMPTY
  Description:
    Set to indicate that the amount of space in the TX FIFO is equal to or greater than the PKT_TX_THRESHOLD value. This interrupt may be used to signal the host MCU to store more data bytes into the TX FIFO, thus providing a means for handling packets with lengths greater than the size of the TX FIFO (i.e., 64 bytes, or 129 bytes in shared FIFO mode). Cleared if the amount of space in the TX FIFO is more than the PKT_TX_THRESHOLD value.
  Type:
    BOOL

  ###### CHIP_PEND

  CAL_PEND
  Description:
    If set, a rising edge of the CAL status bit has been detected and therefore a CAL interrupt is pending. See associated CAL status bit for more details.
  Type:
    BOOL
  FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND
  Description:
    If set, a rising edge of the FIFO_UNDERFLOW_OVERFLOW_ERROR status bit has been detected and therefore a FIFO_UNDERFLOW_OVERFLOW_ERROR interrupt is pending. See associated FIFO_UNDERFLOW_OVERFLOW_ERROR status bit for more details.
  Type:
    BOOL
  STATE_CHANGE_PEND
  Description:
    If set, a rising edge of the STATE_CHANGE status bit has been detected and therefore a STATE_CHANGE interrupt is pending. See associated STATE_CHANGE status bit for more details.
  Type:
    BOOL
  CMD_ERROR_PEND
  Description:
    If set, a rising edge of the CMD_ERROR status bit has been detected and therefore a CMD_ERROR interrupt is pending. See associated CMD_ERROR status bit for more details.
  Type:
    BOOL
  CHIP_READY_PEND
  Description:
    If set, a rising edge of the CHIP_READY status bit has been detected and therefore a CHIP_READY interrupt is pending. See associated CHIP_READY status bit for more details.
  Type:
    BOOL
  LOW_BATT_PEND
  Description:
    If set, a rising edge of the LOW_BATT status bit has been detected and therefore a LOW_BATT interrupt is pending. See associated LOW_BATT status bit for more details.
  Type:
    BOOL
  WUT_PEND
  Description:
    If set, a rising edge of the WUT status bit has been detected and therefore a WUT interrupt is pending. See associated WUT status bit for more details.
  Type:
    BOOL

  ###### CHIP_STATUS

  CAL
  Description:
    Self clearing signal that pulses high to indicate a RC32K calibration event is pending. If this occurs, the RC32K oscillator will be calibrated on the next transition to Sleep/Standby state.
  Type:
    BOOL
  FIFO_UNDERFLOW_OVERFLOW_ERROR
  Description:
    Set to indicate that the number of received or transmitted bytes exceeds the size of the RX or TX FIFO, respectively (i.e., 64 bytes for each FIFO, or 129 bytes when sharing the FIFO). Upon such an underflow/overflow event, the FIFO(s) will need to be reset. Cleared by issuing a FIFO_INFO command to reset the FIFOs.
  Type:
    BOOL
  STATE_CHANGE
  Description:
    Set to indicate a successful transition from one state to another operating state. Cleared when a state transition is in progress.
  Type:
    BOOL
  CMD_ERROR
  Description:
    Self clearing signal that pulses high to indicate an error has occurred in the processing of a command. For example, an incorrect command/property ID is sent, or an attempt was made to write a property that is outside of the given property group.
  Type:
    BOOL
  CHIP_READY
  Description:
    Set to indicate the chip (upon completion of the POWER_UP sequence) has reached the state where it is ready to accept commands, or when the IR calibration process is completed. Cleared when the chip is shutdown or when IR calibration has begun.
  Type:
    BOOL
  LOW_BATT
  Description:
    Set to indicate the battery voltage is below the threshold set by GLOBAL_LOW_BATT_THRESH. Cleared to indicate the battery voltage is above the threshold set by GLOBAL_LOW_BATT_THRESH.
  Type:
    BOOL
  WUT
  Description:
    Self clearing signal that pulses high to indicate the WUT (Wake-up timer) has expired.
  Type:
    BOOL

#### REQUEST_DEVICE_STATE

- Number: 0x33
- Summary: Request current device state and channel.
- Purpose:
  - This command returns information regarding the current operating state and tuned frequency channel of the device.
  - Returning the current channel number is often useful in automatic frequency hopping applications, to determine the frequency on which the device found a valid signal.
  - It is not possible for this command to return a device state value indicating the chip is in SLEEP or STANDBY mode, as the very act of sending an SPI command while the chip is in SLEEP or STANDBY mode assures that it wakes into SPI_ACTIVE mode.
- Argument Stream:

  REQUEST_DEVICE_STATE Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x33

- Reply Stream:

  REQUEST_DEVICE_STATE Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CTS | CTS
  | 0x01 | CURR_STATE | X | X | X | X | MAIN_STATE
  | 0x02 | CURRENT_CHANNEL | CURRENT_CHANNEL

- Argument Fields:
- Reply Fields:

  ###### CTS

  CTS[7:0]
  Description:
    Clear to Send. Indicates that the previous command has completed execution and the response byte stream (if any) is valid. The next command may be sent.
  Type:
    U8

  ###### CURR_STATE

  MAIN_STATE[3:0]
  Description:
    Returns the current operating state of the device. Please refer to the published datasheet for more details regarding these operational modes.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    SLEEP | 1 | (Not Applicable) | revB1A
    SPI_ACTIVE | 2 | SPI_ACTIVE state. | revB1A
    READY | 3 | READY state. | revB1A
    READY2 | 4 | Another enumeration for READY state. | revB1A
    TX_TUNE | 5 | TX_TUNE state. | revB1A
    TX | 7 | TX state. | revB1A

  ###### CURRENT_CHANNEL

  CURRENT_CHANNEL[7:0]
  Description:
    Returns the current tuned channel.
  Type:
    U8

#### CHANGE_STATE

- Number: 0x34
- Summary: Manually switch the chip to a desired operating state.
- Purpose:
  - The chip normally manages the required steps in transitioning between operating states automatically. For example, transmission of a packet may require: waking the chip from SLEEP mode, enabling the Xtal Oscillator (READY mode), calibrating the VCO and tuning the PLL Synthesizer (TX_TUNE mode), enabling the PA and transmission of the packet (TX mode), and returning to an IDLE state. This sequencing is normally handled by the internal state machine.
  - This command provides for manually switching to a desired operating state.
  - This command may be used to enter TX or RX mode, if desired. However, those modes of operation typically require specification of additional parameters (e.g., channel number, number of packet bytes, etc.) prior to switching mode. For this reason, separate START_TX and START_RX commands are provided that essentially accomplish the CHANGE_STATE = TX or RX functionality, while simultaneously passing the required parameter bytes.
- Argument Stream:

  CHANGE_STATE Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x34
  | 0x01 | NEXT_STATE1 | 0 | 0 | 0 | 0 | NEW_STATE

- Reply Stream:

  CHANGE_STATE Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CTS | CTS

- Argument Fields:

  ###### NEXT_STATE1

  NEW_STATE[3:0]
  Description:
    Operating state to switch to immediately. Please refer to the published datasheet for more details regarding these operational modes.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    NOCHANGE | 0 | No change, remain in current state. | revB1A
    SLEEP | 1 | SLEEP or STANDBY state, according to the mode of operation of the 32K R-C Osc selected by GLOBAL_CLK_CFG:CLK_32K_SEL. | revB1A
    SPI_ACTIVE | 2 | SPI_ACTIVE state. | revB1A
    READY | 3 | READY state. | revB1A
    TX_TUNE | 5 | TX_TUNE state. | revB1A
    TX | 7 | TX state. | revB1A

- Reply Fields:

  ###### CTS

  CTS[7:0]
  Description:
    Clear to Send. Indicates that the previous command has completed execution and the response byte stream (if any) is valid. The next command may be sent.
  Type:
    U8

#### READ_CMD_BUFF

- Number: 0x44
- Summary: Used to read CTS and the command response.
- Purpose:
  - Processing of API commands is handled by the command handler in the chip. A subsequent command may not be sent until the chip has completed processing of the first command. The chip indicates the ability to receive another command and the availability of response data by issuing a Clear To Send (CTS) signal; it is necessary for the host MCU to poll the chip for this CTS signal. The CTS signal may be polled via SPI command, or monitored on a GPIO line or as an interrupt on the nIRQ pin.
  - This command is used to poll the CTS signal via the SPI bus. The NSEL line should be pulled low, followed by sending the READ_CMD_BUFF command on SDI. While NSEL remains asserted low, an additional eight clock pulses are sent on SCLK and the CTS response byte is read on SDO. If the CTS response byte is not 0xFF, the host MCU should pull NSEL high and repeat the polling procedure.
  - If the CTS response byte is 0xFF, the host MCU should keep NSEL asserted low and provide additional clock cycles on SCLK to read out as many response bytes (on SDO) as necessary. The host MCU should pull NSEL high upon completion of reading the response stream.
  - A primary function of this command is to determine when CTS goes high, and thus by definition this command may be sent while CTS is low. This command itself does not cause CTS to go low.
  - Attempting to read response bytes from the command buffer while CTS is not 0xFF will return invalid results. The response bytes are valid only if CTS = 0xFF.
- Argument Stream:

  READ_CMD_BUFF Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x44

- Reply Stream:

  READ_CMD_BUFF Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CTS | CTS
  | 0x01 | BYTE[0] | CMD_BUFF
  | ... | ... | ...
  | 0x10 | BYTE[15] | CMD_BUFF

- Argument Fields:
- Reply Fields:

  ###### CTS

  CTS[7:0]
  Description:
    Clear to Send. Indicates that the previous command has completed execution and the response byte stream (if any) is valid. The next command may be sent.
  Type:
    U8

  ###### BYTE[0...15]

  CMD_BUFF[7:0]
  Description:
    Byte 0-15 of the command response buffer.
  Type:
    U8

#### FRR_A_READ

- Number: 0x50
- Summary: Reads the fast response registers (FRR) starting with FRR_A.
- Purpose:
  - The chip provides four Fast Response Registers (FRR) that may be read immediately without the need to monitor and check CTS, thus improving the speed at which the contents may be retrieved.
  - The FRR registers may be read in a burst fashion through the FRR_X_READ commands. After the initial 16 clock cycles, each additional eight clock cycles will clock out the contents of the next fast response register in a circular fashion. Example: If the FRR_A_READ command is issued, the registers will be read in the order A-B-C-D, while if the FRR_B_READ command is issued, the registers will be read in the order B-C-D-A, etc.
  - This command does not cause CTS to go low, and can be sent and the reply read while CTS is low. The command ID should be clocked in on SDI then the reply should be clocked out on SDO without deasserting NSEL.
  - The FRR_CTL_X_MODE properties are used to select the specific parameter values that will be returned by the FRR_X_READ commands. Please refer to the text description for FRR_CTL_X_MODE for more details regarding selection of the parameter(s) held within the FRR registers.
- Argument Stream:

  FRR_A_READ Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x50

- Reply Stream:

  FRR_A_READ Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | FRR_A_VALUE | FRR_A_VALUE
  | 0x01 | FRR_B_VALUE | FRR_B_VALUE
  | 0x02 | FRR_C_VALUE | FRR_C_VALUE
  | 0x03 | FRR_D_VALUE | FRR_D_VALUE

- Argument Fields:
- Reply Fields:

  ###### FRR_A_VALUE

  FRR_A_VALUE[7:0]
  Description:
    Value in Fast Response Register A.
  Type:
    U8

  ###### FRR_B_VALUE

  FRR_B_VALUE[7:0]
  Description:
    Value in Fast Response Register B.
  Type:
    U8

  ###### FRR_C_VALUE

  FRR_C_VALUE[7:0]
  Description:
    Value in Fast Response Register C.
  Type:
    U8

  ###### FRR_D_VALUE

  FRR_D_VALUE[7:0]
  Description:
    Value in Fast Response Register D.
  Type:
    U8

#### FRR_B_READ

- Number: 0x51
- Summary: Reads the fast response registers (FRR) starting with FRR_B.
- Purpose:
  - The chip provides four Fast Response Registers (FRR) that may be read immediately without the need to monitor and check CTS, thus improving the speed at which the contents may be retrieved.
  - The FRR registers may be read in a burst fashion through the FRR_X_READ commands. After the initial 16 clock cycles, each additional eight clock cycles will clock out the contents of the next fast response register in a circular fashion. Example: If the FRR_A_READ command is issued, the registers will be read in the order A-B-C-D, while if the FRR_B_READ command is issued, the registers will be read in the order B-C-D-A, etc.
  - This command does not cause CTS to go low, and can be sent and the reply read while CTS is low. The command ID should be clocked in on SDI then the reply should be clocked out on SDO without deasserting NSEL.
  - The FRR_CTL_X_MODE properties are used to select the specific parameter values that will be returned by the FRR_X_READ commands. Please refer to the text description for FRR_CTL_X_MODE for more details regarding selection of the parameter(s) held within the FRR registers.
- Argument Stream:

  FRR_B_READ Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x51

- Reply Stream:

  FRR_B_READ Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | FRR_B_VALUE | FRR_B_VALUE
  | 0x01 | FRR_C_VALUE | FRR_C_VALUE
  | 0x02 | FRR_D_VALUE | FRR_D_VALUE
  | 0x03 | FRR_A_VALUE | FRR_A_VALUE

- Argument Fields:
- Reply Fields:

  ###### FRR_B_VALUE

  FRR_B_VALUE[7:0]
  Description:
    Value in Fast Response Register B.
  Type:
    U8

  ###### FRR_C_VALUE

  FRR_C_VALUE[7:0]
  Description:
    Value in Fast Response Register C.
  Type:
    U8

  ###### FRR_D_VALUE

  FRR_D_VALUE[7:0]
  Description:
    Value in Fast Response Register D.
  Type:
    U8

  ###### FRR_A_VALUE

  FRR_A_VALUE[7:0]
  Description:
    Value in Fast Response Register A.
  Type:
    U8

#### FRR_C_READ

- Number: 0x53
- Summary: Reads the fast response registers (FRR) starting with FRR_C.
- Purpose:
  - The chip provides four Fast Response Registers (FRR) that may be read immediately without the need to monitor and check CTS, thus improving the speed at which the contents may be retrieved.
  - The FRR registers may be read in a burst fashion through the FRR_X_READ commands. After the initial 16 clock cycles, each additional eight clock cycles will clock out the contents of the next fast response register in a circular fashion. Example: If the FRR_A_READ command is issued, the registers will be read in the order A-B-C-D, while if the FRR_B_READ command is issued, the registers will be read in the order B-C-D-A, etc.
  - This command does not cause CTS to go low, and can be sent and the reply read while CTS is low. The command ID should be clocked in on SDI then the reply should be clocked out on SDO without deasserting NSEL.
  - The FRR_CTL_X_MODE properties are used to select the specific parameter values that will be returned by the FRR_X_READ commands. Please refer to the text description for FRR_CTL_X_MODE for more details regarding selection of the parameter(s) held within the FRR registers.
- Argument Stream:

  FRR_C_READ Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x53

- Reply Stream:

  FRR_C_READ Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | FRR_C_VALUE | FRR_C_VALUE
  | 0x01 | FRR_D_VALUE | FRR_D_VALUE
  | 0x02 | FRR_A_VALUE | FRR_A_VALUE
  | 0x03 | FRR_B_VALUE | FRR_B_VALUE

- Argument Fields:
- Reply Fields:

  ###### FRR_C_VALUE

  FRR_C_VALUE[7:0]
  Description:
    Value in Fast Response Register C.
  Type:
    U8

  ###### FRR_D_VALUE

  FRR_D_VALUE[7:0]
  Description:
    Value in Fast Response Register D.
  Type:
    U8

  ###### FRR_A_VALUE

  FRR_A_VALUE[7:0]
  Description:
    Value in Fast Response Register A.
  Type:
    U8

  ###### FRR_B_VALUE

  FRR_B_VALUE[7:0]
  Description:
    Value in Fast Response Register B.
  Type:
    U8

#### FRR_D_READ

- Number: 0x57
- Summary: Reads the fast response registers (FRR) starting with FRR_D.
- Purpose:
  - The chip provides four Fast Response Registers (FRR) that may be read immediately without the need to monitor and check CTS, thus improving the speed at which the contents may be retrieved.
  - The FRR registers may be read in a burst fashion through the FRR_X_READ commands. After the initial 16 clock cycles, each additional eight clock cycles will clock out the contents of the next fast response register in a circular fashion. Example: If the FRR_A_READ command is issued, the registers will be read in the order A-B-C-D, while if the FRR_B_READ command is issued, the registers will be read in the order B-C-D-A, etc.
  - This command does not cause CTS to go low, and can be sent and the reply read while CTS is low. The command ID should be clocked in on SDI then the reply should be clocked out on SDO without deasserting NSEL.
  - The FRR_CTL_X_MODE properties are used to select the specific parameter values that will be returned by the FRR_X_READ commands. Please refer to the text description for FRR_CTL_X_MODE for more details regarding selection of the parameter(s) held within the FRR registers.
- Argument Stream:

  FRR_D_READ Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x57

- Reply Stream:

  FRR_D_READ Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | FRR_D_VALUE | FRR_D_VALUE
  | 0x01 | FRR_A_VALUE | FRR_A_VALUE
  | 0x02 | FRR_B_VALUE | FRR_B_VALUE
  | 0x03 | FRR_C_VALUE | FRR_C_VALUE

- Argument Fields:
- Reply Fields:

  ###### FRR_D_VALUE

  FRR_D_VALUE[7:0]
  Description:
    Value in Fast Response Register D.
  Type:
    U8

  ###### FRR_A_VALUE

  FRR_A_VALUE[7:0]
  Description:
    Value in Fast Response Register A.
  Type:
    U8

  ###### FRR_B_VALUE

  FRR_B_VALUE[7:0]
  Description:
    Value in Fast Response Register B.
  Type:
    U8

  ###### FRR_C_VALUE

  FRR_C_VALUE[7:0]
  Description:
    Value in Fast Response Register C.
  Type:
    U8

### TX_COMMANDS

#### START_TX

- Number: 0x31
- Summary: Switches to TX state and starts transmission of a packet.
- Purpose:
  - This command switches the chip to TX state and begins transmission of a packet. Depending upon the value of the START parameter, the start of transmission may be delayed until a certain condition is met.
  - Several optional parameters may be passed with this command. If these parameter values are not sent, their previously configured values remain in use. The parameter values are retained while in SLEEP mode, and thus only need to be written when they change.
  - The chip may be configured to automatically enter a desired operational state after transmission of the packet.
  - The chip will not return CTS high until the chip has entered the TX state.
- Argument Stream:

  START_TX Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x31
  | 0x01 | CHANNEL | CHANNEL
  | 0x02 | CONDITION | TXCOMPLETE_STATE | UPDATE | RETRANSMIT | START
  | 0x03 | TX_LEN | 0 | 0 | 0 | TX_LEN[12:8]
  0x04 | TX_LEN[7:0]
  | 0x05 | TX_DELAY | TX_DELAY

- Reply Stream:

  START_TX Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CTS | CTS

- Argument Fields:

  ###### CHANNEL

  CHANNEL[7:0]
  Description:
    - Selects the channel number on which to transmit. Please refer to FREQ_CONTROL_CHANNEL_STEP_SIZE for more details regarding the channelized approach to frequency tuning of the chip.
    - If the CHANNEL parameter byte is not passed with the command, the chip will tune to the last channel specified in either a START_TX or START_RX command; the internal variable that retains the CHANNEL value is shared by these two commands.
  Type:
    U8
  Min:
    0x0
  Max:
    0xff

  ###### CONDITION

  TXCOMPLETE_STATE[3:0]
  Description:
    - This parameter selects the desired operational state of the chip to automatically enter upon completion of the packet transmission.
    - If this parameter is not passed with the command, the chip continues to use the previously configured value. If no value has been previously configured (i.e., upon POWER_UP), the default value of 3 = READY state is used.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    NOCHANGE | 0 | Do not change from previously sent TXCOMPLETE_STATE. (No Change does not have the effect of remaining in TX mode.) | revB1A
    SLEEP | 1 | SLEEP or STANDBY state, according to the mode of operotion of the 32K R-C Osc selected by GLOBAL_CLK_CFG:CLK_32K_SEL. | revB1A
    SPI_ACTIVE | 2 | SPI ACTIVE state. | revB1A
    READY | 3 | READY state. | revB1A
    READY2 | 4 | Another enumeration for READY state. | revB1A
    TX_TUNE | 5 | TX_TUNE state. | revB1A
    TX | 7 | TX state. | revC2A

  UPDATE
  Description:
    Selects the condition upon which transmission will start.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    UPDATE | 1 | Update TX parameters (to be used by a subsequent packet) but do not enter TX mode. |
    USE | 0 | Use TX parameters to enter TX mode. |

  RETRANSMIT
  Description:
    - Selects whether the current packet will simply be a retransmission of the previous packet, or whether the current packet will transmit new data from the TX FIFO.
    - In the event of a retransmission, new (additional) data should not be written to the TX FIFO prior to the retransmission.
    - The RETRANSMIT bit should be set prior to sending the first packet, as well as on all subsequent retransmissions.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Send data that has been written to the TX FIFO. If the TX FIFO is empty, a FIFO underflow interrupt will occur. | revB1A
    ENUM_1 | 1 | Send last packet again. | revB1A

  START[1:0]
  Description:
    Selects the condition upon which transmission will start.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    IMMEDIATE | 0 | Start TX immediately. | revB1A
    WUT | 1 | Start TX upon expiration of the Wake-Up Timer. | revB1A

  ###### TX_LEN

  TX_LEN[12:0]
  Description:
    - Specifies the number of bytes to transmit in the data field(s) of the packet.
    - If this field is non-zero, the packet will be transmitted with TX_LEN number of data bytes, using the data field configuration options (e.g., CRC, data whitening, Manchester coding, etc.) of only PKT_FIELD_1_X. The Payload length is limited to 8191 bytes in this scenario.
    - If this field is zero, the number of data bytes to be transmitted is specified by the value(s) of the PKT_FIELD_X_LENGTH properties. The Payload length is limited to 5 x 8191 = 40955 bytes in this scenario (as each of the five data fields may be configured for a length of 8191 bytes). This approach is necessary if field-specific processing is desired (e.g., data whitening on one field but not another, Manchester coding on one field but not another, etc).
    - The TX_LEN parameter should still be passed even if the RETRANSMIT bit is set.
  Type:
    U16
  Min:
    0x0
  Max:
    0x1fff

  ###### TX_DELAY

  TX_DELAY[7:0]
  Description:
    Specifies a time delay (in µsec) between transmissions of packets, in the event another transmission is scheduled.
  Type:
    U8
  Min:
    0x0
  Max:
    0x80
- Reply Fields:

  ###### CTS

  CTS[7:0]
  Description:
    Clear to Send. Indicates that the previous command has completed execution and the response byte stream (if any) is valid. The next command may be sent.
  Type:
    U8

#### WRITE_TX_FIFO

- Number: 0x66
- Summary: Writes data byte(s) to the TX FIFO.
- Purpose:
  - The chip provides for two separate 64-byte FIFO memories for the purpose of storing transmit and receive data. (When the GLOBAL_CONFIG:FIFO_MODE bit is set, these two FIFOs are combined into a single 129-byte shared FIFO.)
  - This command is used to write data byte(s) into the TX FIFO. The WRITE_TX_FIFO command should be clocked in on SDI (followed by the data byte(s) to be written) without deasserting NSEL. If you write more data bytes than the TX FIFO can hold it will generate a FIFO Overflow interrupt event.
  - This command does not cause CTS to go low, and can be sent while CTS is low. This command has no response to be read and thus there is no need to monitor CTS after sending this command.
- Argument Stream:

  WRITE_TX_FIFO Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x66
  | 0x01 | DATA[0] | DATA
  | ... | ... | ...
  | M | DATA[N] | DATA

- Argument Fields:

  ###### DATA[0...N]

  (indefinite length array stream)
  DATA[7:0]
  Description:
    Data to write to the TX FIFO
  Type:
    U8

### ADVANCED_COMMANDS

#### GET_ADC_READING

- Number: 0x14
- Summary: Performs conversions using the Auxiliary ADC and returns the results of those conversions.
- Purpose:
  - The chip provides an Auxiliary Analog-to-Digital Converter (ADC) for the purpose of measuring various analog parameters and returning their values in digital form. The ADC utilizes a Successive Approximation Register (SAR) architecture and achieves 11-bit resolution, with a 9-bit Effective Number of Bits (ENOB).
  - The ADC may be configured to measure the internal battery voltage, an internal temperature sensor, or an external voltage applied to a selected GPIO pin. More than one type of measurement may be enabled at the same time; the conversions will be performed sequentially and all converted values returned.
  - The ADC is capable of converting any battery voltage within the chip's operating supply voltage range of 1.8VDC to 3.6VDC.
  - The GPIO pin carrying the external voltage to be measured is selected by the ADC_GPIO_PIN parameter, and must also be configured as an input pin or tri-state pin (through the GPIO_PIN_CFG command).
  - The voltage on the selected GPIO pin may be internally attenuated prior to conversion, thus effectively extending the range of voltages which may be converted. The attenuation factor is configurable through the GPIO_ATT parameter.
- Argument Stream:

  GET_ADC_READING Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x14
  | 0x01 | ADC_EN | 0 | 0 | 0 | TEMPERATURE_EN | BATTERY_VOLTAGE_EN | ADC_GPIO_EN | ADC_GPIO_PIN
  | 0x02 | ADC_CFG | UDTIME | GPIO_ATT

- Reply Stream:

  GET_ADC_READING Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CTS | CTS
  | 0x01 | GPIO_ADC | X | X | X | X | X | GPIO_ADC[10:8]
  0x02 | GPIO_ADC[7:0]
  | 0x03 | BATTERY_ADC | X | X | X | X | X | BATTERY_ADC[10:8]
  0x04 | BATTERY_ADC[7:0]
  | 0x05 | TEMP_ADC | X | X | X | X | X | TEMP_ADC[10:8]
  0x06 | TEMP_ADC[7:0]

- Argument Fields:

  ###### ADC_EN

  TEMPERATURE_EN
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Do not perform ADC conversion of the temperature. The reply value in TEMP_ADC will always be 0x000. |
    ENUM_1 | 1 | Perform ADC conversion of the temperature. The reply value in TEMP_ADC will be TEMP(degC) = (899/4096)*TEMP_ADC - 293. |

  BATTERY_VOLTAGE_EN
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Do not perform ADC conversion of the battery voltage. The reply value in BATTERY_ADC will always be 0x000. | revB1A
    ENUM_1 | 1 | Perform ADC conversion of the battery voltage. The reply value in BATTERY_ADC will be VBAT(V) = 3*BATTERY_ADC/1280. | revB1A

  ADC_GPIO_EN
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Do not perform ADC conversion of the voltage applied to the selected GPIO pin. The reply value in GPIO_ADC will always be 0x000. | revB1A
    ENUM_1 | 1 | Perform ADC conversion of the voltage applied to the selected GPIO pin. The reply value in GPIO_ADC will be VGPIO(V) = GPIO_ADC/GPIO_ADC_DIV, where GPIO_ADC_DIV is an attenuation factor defined by the selection of the GPIO_ATT parameter. | revB1A

  ADC_GPIO_PIN[1:0]
  Description:
    - Select the GPIO pin on which to perform conversion of an externally applied voltage.
    - The selected GPIO pin must also be configured as an input pin or tri-state pin (through use of the GPIO_PIN_CFG command).
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | The voltage on GPIO0 will be converted by the ADC. | revB1A
    ENUM_1 | 1 | The voltage on GPIO1 will be converted by the ADC. | revB1A
    ENUM_2 | 2 | The voltage on GPIO2 will be converted by the ADC. | revB1A
    ENUM_3 | 3 | The voltage on GPIO3 will be converted by the ADC. | revB1A

  ###### ADC_CFG

  UDTIME[3:0]
  Description:
    - Selects the rate of ADC conversion, where ADC_RATE = SYS_CLK / 12 / 2^(UDTIME + 1). Selecting shorter conversion times (i.e., faster conversion rates) will result in lower ADC resolution and longer conversion times will result in higher ADC resolution.
    - An ADC conversion rate of 305 Hz (UDTIME = 0xC) to 1.22 kHz (UDTIME = 0xA) is recommended.
    - If the ADC_CFG parameter byte is not sent, or is set ADC_CFG = 0x00, the UDTIME parameter will assume a default value of 0xC = 305 Hz ADC conversion rate (for nominal SYS_CLK = 30 MHz).
  Type:
    U8
  GPIO_ATT[3:0]
  Description:
    - Selects the attenuation factor to be internally applied to the voltage on the GPIO pin, prior to conversion by the ADC. This effectively extends the range of voltages which may be converted.
    - If the ADC_CFG parameter byte is not sent, or is set ADC_CFG = 0x00, the GPIO_ATT parameter will assume a default value of 0x5 = 0 to 3.2V range.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    0P8 | 0 | ADC measurement range is 0 to 0.8 V. GPIO_ADC_DIV = 2560. | revB1A
    1P6 | 4 | ADC measurement range is 0 to 1.6 V. GPIO_ADC_DIV = 1280. | revB1A
    3P2 | 5 | ADC measurement range is 0 to 3.2 V. GPIO_ADC_DIV = 640. | revB1A
    2P4 | 8 | ADC measurement range is 0 to 2.4 V. GPIO_ADC_DIV = 853.33. | revB1A
    3P6 | 9 | ADC measurement range is 0 to 3.6 V. GPIO_ADC_DIV = 426.66. | revB1A

- Reply Fields:

  ###### CTS

  CTS[7:0]
  Description:
    Clear to Send. Indicates that the previous command has completed execution and the response byte stream (if any) is valid. The next command may be sent.
  Type:
    U8

  ###### GPIO_ADC

  GPIO_ADC[10:0]
  Description:
    - Returns the voltage on the selected GPIO pin, as converted by the Auxiliary ADC.
    - The reply value will be VGPIO(V) = GPIO_ADC/GPIO_ADC_DIV, where GPIO_ADC_DIV is an attenuation factor defined by the selection of the GPIO_ATT parameter.
  Type:
    U16

  ###### BATTERY_ADC

  BATTERY_ADC[10:0]
  Description:
    - Returns the battery voltage, as converted by the Auxiliary ADC.
    - The reply value will be VBAT(V) = 3*BATTERY_ADC/1280.
  Type:
    U16

  ###### TEMP_ADC

  TEMP_ADC[10:0]
  Description:
    Returns the temperature, as converted by the Auxiliary ADC.The reply value will be TEMP(degC) = (899/4096)*TEMP_ADC - 293.
  Type:
    U16

#### GET_PH_STATUS

- Number: 0x21
- Summary: Returns the interrupt status of the Packet Handler Interrupt Group (both STATUS and PENDING). Optionally, it may be used to clear latched (PENDING) interrupt events.
- Purpose:
  - Returns the current interrupt status of Packet Handler interrupt events (both STATUS and PENDING) and optionally clears PENDING interrupts.
  - Please refer to the GET_INT_STATUS command for more details regarding the difference between STATUS and PENDING interrupts.
  - Sending the GET_PH_STATUS command with NO input parameter results in clearing all of the PENDING interrupts.
  - When PENDING interrupts are being cleared, the reply stream reflects their status prior to clearing.
- Argument Stream:

  GET_PH_STATUS Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x21
  | 0x01 | PH_CLR_PEND | 0 | 0 | PACKET_SENT_PEND_CLR | 0 | 0 | 0 | TX_FIFO_ALMOST_EMPTY_PEND_CLR | 0

- Reply Stream:

  GET_PH_STATUS Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CTS | CTS
  | 0x01 | PH_PEND | X | X | PACKET_SENT_PEND | X | X | X | TX_FIFO_ALMOST_EMPTY_PEND | X
  | 0x02 | PH_STATUS | X | X | PACKET_SENT | X | X | X | TX_FIFO_ALMOST_EMPTY | X

- Argument Fields:

  ###### PH_CLR_PEND

  PACKET_SENT_PEND_CLR
  Description:
    If clear, clear any pending PACKET_SENT interrupt. If set, leave interrupt pending.
  Type:
    BOOL
  TX_FIFO_ALMOST_EMPTY_PEND_CLR
  Description:
    If clear, clear any pending TX_FIFO_ALMOST_EMPTY interrupt. If set, leave interrupt pending.
  Type:
    BOOL
- Reply Fields:

  ###### CTS

  CTS[7:0]
  Description:
    Clear to Send. Indicates that the previous command has completed execution and the response byte stream (if any) is valid. The next command may be sent.
  Type:
    U8

  ###### PH_PEND

  PACKET_SENT_PEND
  Description:
    If set, a rising edge of the PACKET_SENT status bit has been detected and therefore a PACKET_SENT interrupt is pending. See associated PACKET_SENT status bit for more details.
  Type:
    BOOL
  TX_FIFO_ALMOST_EMPTY_PEND
  Description:
    If set, a rising edge of the TX_FIFO_ALMOST_EMPTY status bit has been detected and therefore a TX_FIFO_ALMOST_EMPTY interrupt is pending. See associated TX_FIFO_ALMOST_EMPTY status bit for more details.
  Type:
    BOOL

  ###### PH_STATUS

  PACKET_SENT
  Description:
    Set to indicate that data bytes in the TX FIFO were transmitted successfully. Cleared upon entry into TX state.
  Type:
    BOOL
  TX_FIFO_ALMOST_EMPTY
  Description:
    Set to indicate that the amount of space in the TX FIFO is equal to or greater than the PKT_TX_THRESHOLD value. This interrupt may be used to signal the host MCU to store more data bytes into the TX FIFO, thus providing a means for handling packets with lengths greater than the size of the TX FIFO (i.e., 64 bytes, or 129 bytes in shared FIFO mode). Cleared if the amount of space in the TX FIFO is more than the PKT_TX_THRESHOLD value.
  Type:
    BOOL

#### GET_CHIP_STATUS

- Number: 0x23
- Summary: Returns the interrupt status of the Chip Interrupt Group (both STATUS and PENDING). Optionally, it may be used to clear latched (PENDING) interrupt events.
- Purpose:
  - Returns the current interrupt status of Chip interrupt events (both STATUS and PENDING) and optionally clears PENDING interrupts.
  - Please refer to the GET_INT_STATUS command for more details regarding the difference between STATUS and PENDING interrupts.
  - Sending the GET_CHIP_STATUS command with NO input parameter results in clearing all of the PENDING interrupts.
  - When PENDING interrupts are being cleared, the reply stream reflects their status prior to clearing.
- Argument Stream:

  GET_CHIP_STATUS Argument Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CMD | 0x23
  | 0x01 | CHIP_CLR_PEND | 0 | CAL_PEND_CLR | FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_CLR | STATE_CHANGE_PEND_CLR | CMD_ERROR_PEND_CLR | CHIP_READY_PEND_CLR | LOW_BATT_PEND_CLR | WUT_PEND_CLR

- Reply Stream:

  GET_CHIP_STATUS Reply Stream
  | Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
  | 0x00 | CTS | CTS
  | 0x01 | CHIP_PEND | X | CAL_PEND | FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND | STATE_CHANGE_PEND | CMD_ERROR_PEND | CHIP_READY_PEND | LOW_BATT_PEND | WUT_PEND
  | 0x02 | CHIP_STATUS | X | CAL | FIFO_UNDERFLOW_OVERFLOW_ERROR | STATE_CHANGE | CMD_ERROR | CHIP_READY | LOW_BATT | WUT
  | 0x03 | CMD_ERR_STATUS | CMD_ERR_STATUS
  | 0x04 | CMD_ERR_CMD_ID | CMD_ERR_CMD_ID

- Argument Fields:

  ###### CHIP_CLR_PEND

  CAL_PEND_CLR
  Description:
    If clear, clear any pending CAL interrupt. If set, leave interrupt pending.
  Type:
    BOOL
  FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_CLR
  Description:
    If clear, clear any pending FIFO_UNDERFLOW_OVERFLOW_ERROR interrupt. If set, leave interrupt pending.
  Type:
    BOOL
  STATE_CHANGE_PEND_CLR
  Description:
    If clear, clear any pending STATE_CHANGE interrupt. If set, leave interrupt pending.
  Type:
    BOOL
  CMD_ERROR_PEND_CLR
  Description:
    If clear, clear any pending CMD_ERROR interrupt. If set, leave interrupt pending.
  Type:
    BOOL
  CHIP_READY_PEND_CLR
  Description:
    If clear, clear any pending CHIP_READY interrupt. If set, leave interrupt pending.
  Type:
    BOOL
  LOW_BATT_PEND_CLR
  Description:
    If clear, clear any pending LOW_BATT interrupt. If set, leave interrupt pending.
  Type:
    BOOL
  WUT_PEND_CLR
  Description:
    If clear, clear any pending WUT interrupt. If set, leave interrupt pending.
  Type:
    BOOL
- Reply Fields:

  ###### CTS

  CTS[7:0]
  Description:
    Clear to Send. Indicates that the previous command has completed execution and the response byte stream (if any) is valid. The next command may be sent.
  Type:
    U8

  ###### CHIP_PEND

  CAL_PEND
  Description:
    If set, a rising edge of the CAL status bit has been detected and therefore a CAL interrupt is pending. See associated CAL status bit for more details.
  Type:
    BOOL
  FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND
  Description:
    If set, a rising edge of the FIFO_UNDERFLOW_OVERFLOW_ERROR status bit has been detected and therefore a FIFO_UNDERFLOW_OVERFLOW_ERROR interrupt is pending. See associated FIFO_UNDERFLOW_OVERFLOW_ERROR status bit for more details.
  Type:
    BOOL
  STATE_CHANGE_PEND
  Description:
    If set, a rising edge of the STATE_CHANGE status bit has been detected and therefore a STATE_CHANGE interrupt is pending. See associated STATE_CHANGE status bit for more details.
  Type:
    BOOL
  CMD_ERROR_PEND
  Description:
    If set, a rising edge of the CMD_ERROR status bit has been detected and therefore a CMD_ERROR interrupt is pending. See associated CMD_ERROR status bit for more details.
  Type:
    BOOL
  CHIP_READY_PEND
  Description:
    If set, a rising edge of the CHIP_READY status bit has been detected and therefore a CHIP_READY interrupt is pending. See associated CHIP_READY status bit for more details.
  Type:
    BOOL
  LOW_BATT_PEND
  Description:
    If set, a rising edge of the LOW_BATT status bit has been detected and therefore a LOW_BATT interrupt is pending. See associated LOW_BATT status bit for more details.
  Type:
    BOOL
  WUT_PEND
  Description:
    If set, a rising edge of the WUT status bit has been detected and therefore a WUT interrupt is pending. See associated WUT status bit for more details.
  Type:
    BOOL

  ###### CHIP_STATUS

  CAL
  Description:
    Self clearing signal that pulses high to indicate a RC32K calibration event is pending. If this occurs, the RC32K oscillator will be calibrated on the next transition to Sleep/Standby state.
  Type:
    BOOL
  FIFO_UNDERFLOW_OVERFLOW_ERROR
  Description:
    Set to indicate that the number of received or transmitted bytes exceeds the size of the RX or TX FIFO, respectively (i.e., 64 bytes for each FIFO, or 129 bytes when sharing the FIFO). Upon such an underflow/overflow event, the FIFO(s) will need to be reset. Cleared by issuing a FIFO_INFO command to reset the FIFOs.
  Type:
    BOOL
  STATE_CHANGE
  Description:
    Set to indicate a successful transition from one state to another operating state. Cleared when a state transition is in progress.
  Type:
    BOOL
  CMD_ERROR
  Description:
    Self clearing signal that pulses high to indicate an error has occurred in the processing of a command. For example, an incorrect command/property ID is sent, or an attempt was made to write a property that is outside of the given property group.
  Type:
    BOOL
  CHIP_READY
  Description:
    Set to indicate the chip (upon completion of the POWER_UP sequence) has reached the state where it is ready to accept commands, or when the IR calibration process is completed. Cleared when the chip is shutdown or when IR calibration has begun.
  Type:
    BOOL
  LOW_BATT
  Description:
    Set to indicate the battery voltage is below the threshold set by GLOBAL_LOW_BATT_THRESH. Cleared to indicate the battery voltage is above the threshold set by GLOBAL_LOW_BATT_THRESH.
  Type:
    BOOL
  WUT
  Description:
    Self clearing signal that pulses high to indicate the WUT (Wake-up timer) has expired.
  Type:
    BOOL

  ###### CMD_ERR_STATUS

  CMD_ERR_STATUS[7:0]
  Description:
    Last command error cause. Only valid if CMD_ERROR status bit is set.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    CMD_ERROR_NONE | 0 | No error. |
    CMD_ERROR_BAD_COMMAND | 16 | Bad command issued. |
    CMD_ERROR_BAD_ARG | 17 | Argment(s) in issued command were invalid. |
    CMD_ERROR_COMMAND_BUSY | 18 | Command was issued before previous command was completed. |
    CMD_ERROR_INVALID_STATE | 19 | Command issued was not allowed while in the current device state. |
    CMD_ERROR_BAD_BOOTMODE | 49 | Invalid bootmode supplied. |
    CMD_ERROR_BAD_PROPERTY | 64 | Bad Property ID was provided. |

  ###### CMD_ERR_CMD_ID

  CMD_ERR_CMD_ID[7:0]
  Description:
    Command ID that was being proccessed at the time of the last command error.
  Type:
    ENUM

## Property Details

### GLOBAL

#### GLOBAL_XO_TUNE

- Group: 0x00
- Index: 0x00

- Summary: Configure the internal capacitor frequency tuning bank for the crystal oscillator.
- Purpose:
  - The chip provides internal adjustable capacitor banks for the purpose of tuning the frequency of the crystal oscillator. These capacitances effectively appear in shunt from the XIN and XOUT pins to GND.
  - TUNE_VALUE = 0x00 corresponds to the lowest tuning capacitance value and thus the highest frequency of oscillation, while TUNE_VALUE = 0x7F corresponds to the highest tuning capacitance value and the lowest frequency of oscillation. Each LSB code corresponds to ~70 fF change in capacitance.
  - The total frequency adjustment range (for a typical 30 MHz crystal blank) is approximately ±100 ppm.
- Default: 0x40
- Register View:

| GLOBAL_XO_TUNE
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x00 | 0 | TUNE_VALUE
| Default
| 0x0 | 0x40

- Field Details:

  ###### GLOBAL_XO_TUNE

  TUNE_VALUE[6:0]
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    FASTEST_FREQUENCY | 0 | Lowest capacitance (i.e., highest oscillation frequency) |
    SLOWEST_FREQUENCY | 127 | Highest capacitance (i.e., lowest oscillation frequency) |

#### GLOBAL_CLK_CFG

- Group: 0x00
- Index: 0x01

- Summary: Clock configuration options.
- Purpose:
  - The chip provides for outputting a variety of clock signals on selected GPIO pins. It is necessary to configure these clock signals prior to using the Wake-Up Timer (WUT) or GPIO clock output.
  - The source of the clock signal(s) may be derived from the system clock (i.e., crystal oscillator or external reference source) or from the 32K R-C / Xtal oscillator.
  - The clock signal derived from the system clock (i.e., crystal oscillator or external reference source) may be further divided by a configurable divide ratio, as selected by the DIVIDED_CLK_SEL field. During SPI_ACTIVE mode (i.e., when the crystal oscillator is disabled) the output signal is derived from the divided Boot Clock signal.
  - The 32K clock source may be obtained from an internal 32K R-C Oscillator, or from an internal Crystal Oscillator operating with an external 32K crystal blank.
  - In the event the 32K Xtal Osc is used, the crystal blank must be placed across the GPIO0 and GPIO1 pins, thus rendering these pins unavailable for any other purpose. Additionally, the GPIO0 and GPIO1 pins must be defined as input pins or tri-state pins (through use of the GPIO_PIN_CFG command) in order to support the mode of oscillation.
- Default: 0x00
- Register View:

| GLOBAL_CLK_CFG
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x01 | 0 | DIVIDED_CLK_EN | DIVIDED_CLK_SEL | 0 | CLK_32K_SEL
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0x0

- Field Details:

  ###### GLOBAL_CLK_CFG

  DIVIDED_CLK_EN
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DISABLE | 0 | Divided system clock output is disabled. |
    ENABLE | 1 | Divided system clock output is enabled. |

  DIVIDED_CLK_SEL[2:0]
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DIV_1 | 0 | Clock output is system clock divided by 1. |
    DIV_2 | 1 | Clock output is system clock divided by 2. |
    DIV_3 | 2 | Clock output is system clock divided by 3. |
    DIV_7_5 | 3 | Clock output is system clock divided by 7.5. |
    DIV_10 | 4 | Clock output is system clock divided by 10. |
    DIV_15 | 5 | Clock output is system clock divided by 15. |
    DIV_30 | 6 | Clock output is system clock divided by 30. |

  CLK_32K_SEL[1:0]
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    OFF | 0 | 32 kHz clock is disabled. |
    RC | 1 | 32 kHz clock is driven by internal RC oscillator. |
    CRYSTAL | 2 | 32 kHz clock is driven by internal crystal oscillator operating with external 32K crystal blank across GPIO0 and GPIO1 pins. |

#### GLOBAL_LOW_BATT_THRESH

- Group: 0x00
- Index: 0x02

- Summary: Configures the threshold voltage for low-battery detection.
- Purpose:
  - The chip provides low-battery detection (LBD) capability. The battery voltage is compared against the threshold voltage configured in this property, using a dedicated internal voltage comparator.
  - The result of the LBD function may be viewed in real-time on a GPIO pin, or may be used to generate an interrupt event.
  - The LBD functionality must be enabled in the GLOBAL_WUT_CONFIG property. The battery voltage is measured at time intervals defined by the Wake-Up Timer (WUT), and thus is only available when the WUT is additionally enabled. (Of course, the host MCU may initiate a measurement of the battery voltage at any time through the GET_ADC_READING command.)
  - The low battery threshold is configurable from 1.5V to 3.05V in increments of 50mV, and is given by the following formula:

- Default: 0x18
- Register View:

| GLOBAL_LOW_BATT_THRESH
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x02 | 0 | 0 | 0 | THRESHOLD
| Default
| 0x0 | 0x0 | 0x0 | 0x18

- Field Details:

  ###### GLOBAL_LOW_BATT_THRESH

  THRESHOLD[4:0]
  Min:
    0x0
  Max:
    0x1f
  Default:
    0x18

#### GLOBAL_CONFIG

- Group: 0x00
- Index: 0x03

- Summary: Global configuration settings.
- Purpose:
  - Description: This is a reserved field that should always be written to 1. Note that the recommended setting does not match the current default (wake-up) value of this bit.
- Default: 0x20
- Register View:

| GLOBAL_CONFIG
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x03 | 0 | RESERVED | SEQUENCER_MODE | FIFO_MODE | PROTOCOL | POWER_MODE
| Default
| 0x0 | 0x0 | 0x1 | 0x0 | 0x0 | 0x0

- Field Details:

  ###### GLOBAL_CONFIG

  RESERVED
  Description:
    Description: This is a reserved field that should always be written to 1. Note that the recommended setting does not match the current default (wake-up) value of this bit.
  Default:
    0x0
  SEQUENCER_MODE
  Description:
    - Processing of API commands (e.g., START_TX) is handled by the command handler in the chip. Due to processing overhead and "housekeeping" functions (e.g., interrupt service routines), the time required to process an API command may not be fixed. As a result, the time delay between issuing a START_TX command and the point in time where the chip actually enters TX mode may be slightly variable, in normal operation.
    - The default operation of the chip is to process the START_TX command and enter TX mode as quickly as possible. However, the chip may be configured to enter TX mode only after expiration of a fixed (longer) time period, measured from issuance of the START_TX command. In this fashion, the time delay between the command and the TX packet is fixed and consistent, but slightly longer than normal.
    - The time period is a function of the initial state of the chip prior to entering TX mode. The timer counts 'X' cycles of a clock operating at Fxtal/30 MHz (i.e., 1 µsec clock ticks for the nominal crystal Fxtal=30 MHz).
    - SLEEP / SPI_ACTIVE to TX = 0x1F4 = 500 cycles
    - TX_TUNE to TX = 0x4B = 75 cycles
    - READY to TX = 0x96 = 150 cycles
    - RX to TX = 0x96 = 150 cycles
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    GUARANTEED | 0 | Enter TX mode upon expiration of a guaranteed time period after nSEL (associated with a START_TX command) goes high. The time period depends on the current chip state. |
    FAST | 1 | Enter TX mode as quickly as possible after receipt of a START_TX command. |

  FIFO_MODE
  Description:
    - The chip normally provides for two separate 64-byte FIFO memories for the purpose of storing transmit and receive data.
    - When this bit is set, these two FIFOs are combined into a single 129-byte shared FIFO. The user must ensure that all data is transmitted or retrieved from the shared FIFO space prior to switching TX/RX modes, else stored data may be lost.
    - Shared FIFO mode will not take effect until after performing a reset of the FIFOs (through the FIFO_INFO command).
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    SPLIT_FIFO | 0 | TX and RX FIFO are independent, 64-byte size for each other. |
    HALF_DUPLEX_FIFO | 1 | TX/RX FIFO are sharing with 129-byte size buffer. |

  PROTOCOL[2:0]
  Description:
    - Certain protocols (e.g., IEEE 802.15.4g) require dynamic re-configuration of how the packet is processed.
    - The default mode of operation is to receive a generic packet format; the desired processing of the packet is configured prior to packet reception and remains in effect for the duration of the packet.
    - If this field is set, the chip becomes "protocol-aware" and dynamically alters its packet processing as a function of received Header byte(s).
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    GENERIC | 0 | Packet format is generic, no dynamic reprogramming of packet handler properties. |
    IE154G | 1 | Packet format is IEEE802.15.4g compliant. The following properties are overriden: PKT_CRC_CONFIG, CRC_ENDIAN/BIT_ORDER in PKT_CONFG1 for TX and RX, PKT_FIELD_1_CRC_CONFIG for RX. Other applicable properties in the packet handler group still need to be programmed. Field 1 should have the length of 16 bits to contain the PHR with PKT_LEN_FIELD_SOURCE set to 1 for RX. PSDU field shall use Field 2 with variable length. Field 2 length should be set to the maximum allowed including the anticipated FCS length. It is anticipated that the FCS will be calculated by the host and transmitted over the air. PHR and FCS will be put in the FIFO for the host to retrieve and check. Therefore, CRC shouldn't be enabled. |

  POWER_MODE
  Description:
    - The chip may be placed into either a High Performance or Low Power mode of operation.
    - This bit primarily affects RX and TUNE modes, and trades off RX performance (i.e., sensitivity and linearity) for current consumption. The difference in current consumption in TX mode is negligible.
    - Please refer to the published datasheet for expected values of current consumption in each mode.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    HIGH_PERF | 0 | High performance mode for RX and TX. |
    LOW_POWER | 1 | Low power mode for RX and TX. |

#### GLOBAL_WUT_CONFIG

- Group: 0x00
- Index: 0x04

- Summary: General Wakeup Timer feature configuration.
- Purpose:
  - The chip contains an integrated timer that may be used to wake the chip at periodic intervals. This property is used to enable and configure various functions related to the Wake-Up timer (WUT), such as Low-Battery Detection (LBD) and Low Duty Cycle (LDC) operation.
  - The WUT counts cycles of the 32K clock signal, and thus a 32K clock source (either internal 32K R-C Oscillator or internal Crystal Oscillator with external 32K crystal blank) must also be enabled through the GLOBAL_CLK_CFG property in order to obtain WUT functionality.
  - The frequency of the 32K R-C Oscillator will change with temperature and thus periodic re-calibration is required. The 32K R-C Oscillator is initially calibrated during the POWER_UP command after exit from the SDN state.
  - There are two different methods by which re-calibration of the 32K R-C Oscillator may be configured. One method is to enable the re-calibration by setting the GLOBAL_WUT_CONFIG:CAL_EN bit and selecting the desired calibration period through the GLOBAL_WUT_CONFIG:WUT_CAL_PERIOD parameter. The other method is to leave the GLOBAL_WUT_CONFIG:CAL_EN bit cleared but to configure a non-zero value in the GLOBAL_WUT_CAL property, resulting in calibration on multiples of the WUT period. In both methods, the 32K R-C Oscillator must be enabled to provide a clock signal to the timer(s).
  - Calibration of the 32K R-C Oscillator is performed by comparing its frequency to that of the 30 MHz Xtal Oscillator. Therefore, the 30 MHz Xtal Oscillator is automatically started during calibration, resulting in an increase in average current consumption. Selecting a longer value of GLOBAL_WUT_CAL or GLOBAL_WUT_CONFIG:WUT_CAL_PERIOD is recommended to lower the average current consumption.
  - LDC mode is provided to automatically wake-up the receiver to check if a valid signal is available (LDC RX mode), or to enable the transmitter to send a packet (LDC TX mode).
- Default: 0x00
- Register View:

| GLOBAL_WUT_CONFIG
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x04 | WUT_LDC_EN | WUT_CAL_PERIOD | WUT_LBD_EN | WUT_EN | CAL_EN
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0x0

- Field Details:

  ###### GLOBAL_WUT_CONFIG

  WUT_LDC_EN[1:0]
  Description:
    Enables or disables LDC operation, and selects the mode of LDC operation.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DISABLE_LDC | 0 | Disable LDC operation. |
    TX_LDC | 2 | LDC TX Mode. |

  WUT_CAL_PERIOD[2:0]
  Description:
    - Selects the time interval for periodic re-calibration of the 32K R-C Oscillator.
    - Calibration must additionally be enabled by setting the WUT_CONFIG:CAL_EN bit, else this field has no effect.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    1_SEC | 0 | 1 sec. |
    2_SEC | 1 | 2 sec. |
    4_SEC | 2 | 4 sec. |
    8_SEC | 3 | 8 sec. |
    16_SEC | 4 | 16 sec. |
    32_SEC | 5 | 32 sec. |
    64_SEC | 6 | 64 sec. |
    128_SEC | 7 | 128 sec. |

  WUT_LBD_EN
  Description:
    - "When high, enables the Low Battery Detect (LBD) function.
    - A comparison of the battery voltage with the GLOBAL_LOW_BATT_THRESH value (through use of a dedicated internal voltage comparator) is performed upon expiration of the WUT interval.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DISABLE_LBD | 0 | Disable the LBD functionality. |
    ENABLE_LBD | 1 | Enable the LBD functionality. |

  WUT_EN
  Description:
    Description: Enables or disables the WUT. No other functionality derived from the WUT (e.g., LBD or LDC) may be obtained without first enabling the WUT. It remains additionally necessary to enable a 32K clock source for the WUT. Note that the 32K clock source needs to be stable in order to guarantee WUT timing. If using the internal 32K RC oscillator, wait at least 300 microseconds or 10 clock cycles between enabling the internal oscillator and enabling the WUT. If using an external 32K XTAL, wait at least 1.5 seconds or 49,152 clock cycles between enabling the external XTAL and enabling the WUT.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DISABLE_WUT | 0 | Disable wake up timer. |
    ENABLE_WUT | 1 | Enable wake up timer. |

  CAL_EN
  Description:
    - "Selects whether the chip will wake up at periodic intervals and perform calibration of the 32K R-C Oscillator.
    - When enabled, the calibration interval is controlled by the GLOBAL_WUT_CONFIG:WUT_CAL_PERIOD parameter.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DISABLE_CAL | 0 | Disable the 32K R-C Oscillator calibration timer. |
    ENABLE_CAL | 1 | Enable the 32K R-C Oscillator calibration timer. |

#### GLOBAL_WUT_M

- Group: 0x00
- Indexes: 0x05 ... 0x06

- Summary: Configure the mantissa of the Wake-Up Timer (WUT) value.
- Purpose:
  - The chip contains an integrated timer that may be used to wake the chip at periodic intervals. The WUT is enabled by the GLOBAL_WUT_CONFIG:WUT_EN bit.
  - The WUT_M and WUT_R values should be configured prior to enabling the WUT_EN bit. In the event it is desired to modify the WUT_M/R values, the WUT_EN bit should first be disabled and then re-enabled after the timer values are modified.
  - The clock source for the WUT is taken from either the internal 32 kHz RC Oscillator or from the internal 32 kHz crystal oscillator (operating in conjunction with a 32 kHz crystal blank placed between the GPIO0 and GPIO1 pins). Therefore, a 32K clock source must be enabled (through the GLOBAL_CLK_CFG property) in order for the timer to have a clock signal to count.
  - The period of the WUT is given by the following formula:

  - This property sets the mantissa value WUT_M. A value of WUT_M = 0 is a legal value but will have the same effect as WUT_M = 1.
  - The WUT_M value is only used in defining the period of the WUT, and (unlike the WUT_R value) is not shared in defining the Low Duty Cycle (LDC) duration.
  - The chip may be configured to generate an interrupt event upon expiration of the WUT.
  - Additionally, a GPIO pin may be configured to output a real-time signal with the programmed WUT period. The duty cycle of this signal may be other than 50%, with the output pulsing high for 2(WUT_R+1) cycles of the 32K clock.
- Defaults: 0x00,0x01
- Register View:

| GLOBAL_WUT_M
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x05 | WUT_M[15:8]
0x06 | WUT_M[7:0]
| Defaults
0x05 | 0x0
0x06 | 0x1

- Field Details:

  ###### GLOBAL_WUT_M

  WUT_M[15:0]
  Description:
    Configures the mantissa in the formula for the period.
  Min:
    0x1
  Max:
    0xffff
  Default:
    0x1

#### GLOBAL_WUT_R

- Group: 0x00
- Index: 0x07

- Summary: Configure the exponent of the Wake-Up Timer (WUT) value.
- Purpose:
  - The chip contains an integrated timer that may be used to wake the chip at periodic intervals. Please refer to the text description for GLOBAL_WUT_M for more details regarding setting the period of the WUT.
  - This property sets the value of the exponent WUT_R. A value of WUT_R = 0 is a legal value but has the same effect as WUT_R = 1. The maximum permissible value is WUT_R = 0x14 = 20d.
  - The WUT_R value is shared between defining the period of the WUT and the LDC mode duration, in contrast with the WUT_M value which is used only in defining the period of the WUT.
  - In most applications the WUT is used to wake from a low-current state such as SLEEP mode. The WUT_SLEEP bit is used to select whether the chip returns to SLEEP mode after expiration of the WUT, or remains in SPI_ACTIVE mode. If the chip was already in a higher-current operational state (e.g., TUNE or RX mode) when the WUT expired, it will not drop back to SLEEP or SPI_ACTIVE mode but will remain in the commanded operational state.
- Default: 0x60
- Register View:

| GLOBAL_WUT_R
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x07 | LDC_MAX_PERIODS | WUT_SLEEP | WUT_R
| Default
| 0x1 | 0x1 | 0x0

- Field Details:

  ###### GLOBAL_WUT_R

  LDC_MAX_PERIODS[1:0]
  Description:
    Configures how many LDC periods to wait for a incoming packet to be received after preamble or sync has been detected.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    FOREVER | 0 | Wait forever for an incoming packet. User must abort reception if desired. |
    TWO | 1 | Wait for a max of 2 LDC periods after preamble or sync is received. |
    FOUR | 2 | Wait for a max of 4 LDC periods after preamble or sync is received. |
    EIGHT | 3 | Wait for a max of 8 LDC periods after preamble or sync is received. |

  WUT_SLEEP
  Description:
    selects the operating state after expiration of the WUT.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    READY | 0 | Go to SPI_ACTIVE state after WUT. |
    SLEEP | 1 | Go to Sleep state after WUT. |

  WUT_R[4:0]
  Description:
    Configures the value of the exponent in the formula for the period of the WUT.
  Min:
    0x0
  Max:
    0x14
  Default:
    0x0

#### GLOBAL_WUT_LDC

- Group: 0x00
- Index: 0x08

- Summary: Configures the period of time the chip remains active after automatic wake-up in LDC mode.
- Purpose:
  - The chip contains an integrated timer used to determine the length of time the chip remains active after automatic wake-up in LDC mode.
  - The LDC active period is given by the following formula:

  - This property sets the mantissa value WUT_LDC. A value of WUT_LDC = 0 is a legal value but will have the same effect as WUT_LDC = 1. The WUT_R (exponent) value is shared in defining the period of the WUT.
  - The clock source for the WUT is taken from either the internal 32 kHz RC Oscillator or from the internal 32 kHz crystal oscillator (operating in conjunction with a 32 kHz crystal blank placed between the GPIO0 and GPIO1 pins). Therefore, a 32K clock source must be enabled (through the GLOBAL_CLK_CFG property) in order for the timer to have a clock signal to count.
  - The LDC period determines the length of time the chip remains in active mode, while the WUT period determines the length of time the chip remains inactive. Therefore the total amount of time between successive wake-up cycles is LDC_PERIOD + WUT_PERIOD.
  - The period of time spent in active mode may be less than the defined LDC_PERIOD. Example: if a valid RX packet is detected within the LDC_PERIOD and completely received prior to the expiration of LDC_PERIOD, the chip will return to the WUT state immediately upon the end of the packet.
- Default: 0x00
- Register View:

| GLOBAL_WUT_LDC
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x08 | WUT_LDC
| Default
| 0x0

- Field Details:

  ###### GLOBAL_WUT_LDC

  WUT_LDC[7:0]
  Description:
    - Configures the mantissa in the formula for the period of active time in LDC mode.
    - An LDC mode of operation must be enabled (through the GLOBAL_WUT_CONFIG:WUT_LDC_EN field) for this parameter to take effect.
  Min:
    0x1
  Max:
    0xff
  Default:
    0x0

#### GLOBAL_WUT_CAL

- Group: 0x00
- Index: 0x09

- Summary: Controls if calibration of the 32K R-C Oscillator will be performed on intervals of the WUT.
- Purpose:
  - The chip provides for two different methods of configuring the period between re-calibration of the 32K R-C Oscillator. One method involves enabling a Calibration Timer and selecting a calibration interval in various multiples of 1 second (see the GLOBAL_WUT_CONFIG property); the other method involves performing calibration on configurable integer multiples of the programmed WUT interval.
  - The GLOBAL_WUT_CAL property configures the desired integer multiple of the WUT interval on which to perform calibration (i.e., the second method mentioned above). A value of WUT_CAL = 0x00 disables this feature. Any non-zero value will result in calibration of the 32K R-C Oscillator on that integer multiple of the WUT interval. Example: WUT_CAL = 0x01 will calibrate on every WUT interval, WUT_CAL = 0x02 will calibrate on every second WUT interval, etc.
  - The GLOBAL_WUT_CONFIG:CAL_EN bit must also be cleared for this method of calibration timing to be enabled.
- Default: 0x00
- Register View:

| GLOBAL_WUT_CAL
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x09 | WUT_CAL
| Default
| 0x0

- Field Details:

  ###### GLOBAL_WUT_CAL

  WUT_CAL[7:0]
  Description:
    - Selects the multiple of the WUT period on which to perform calibration of the 32K R-C Oscillator.
    - The GLOBAL_WUT_CONFIG:CAL_EN bit must also be cleared for this method of calibration timing to be enabled.
  Min:
    0x0
  Max:
    0xff
  Default:
    0x0

### INT_CTL

#### INT_CTL_ENABLE

- Group: 0x01
- Index: 0x00

- Summary: This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin.
- Purpose:
  - Enables top-level interrupt sources to generate HW interrupts at the NIRQ pin.
  - The three interrupt groups are Chip, Modem and Packet Handler. Each of them contains multiple possible interrupt sources that must be individually enabled via the INT_CTL_PH_ENABLE, INT_CTL_MODEM_ENABLE, INT_CTL_CHIP_ENABLE properties.
  - Note that this property only provides for global enabling/disabling of the HW interrupt indication on the NIRQ output pin. An internal interrupt event may still be generated even if the indication on the NIRQ output pin is disabled. The interrupt event may always be monitored by polling a GPIO pin, or via GET_INT_STATUS, GET_CHIP_STATUS, GET_PH_STATUS, or GET_MODEM_STATUS commands.
- Default: 0x04
- Register View:

| INT_CTL_ENABLE
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x00 | 0 | 0 | 0 | 0 | 0 | CHIP_INT_STATUS_EN | 0 | PH_INT_STATUS_EN
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x1 | 0x0 | 0x0

- Field Details:

  ###### INT_CTL_ENABLE

  CHIP_INT_STATUS_EN
  Description:
    Enables chip interrupts to assert NIRQ.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DISABLED | 0 | Disable pending interrupts in the Chip Status group from asserting nNIRQ. | revB1A
    ENABLED | 1 | Enable pending interrupts in the Chip Status group to assert nNIRQ. | revB1A

  PH_INT_STATUS_EN
  Description:
    Enables packet handler interrupts to assert NIRQ.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DISABLED | 0 | Disable pending interrupts in tx mode group from asserting nNIRQ. |
    ENABLED | 1 | Enable pending interrupts in tx mode group to assert nNIRQ. |

#### INT_CTL_PH_ENABLE

- Group: 0x01
- Index: 0x01

- Summary: Enable individual interrupt sources within the Packet Handler Interrupt Group to generate a HW interrupt on the NIRQ output pin.
- Purpose:
  - Enable individual interrupt sources within the Packet Handler Interrupt Group in order to generate a HW interrupt at the NIRQ output pin.
  - In order to fully enable a HW interrupt, it is necessary to enable both the individual interrupt source (within this property) as well as the corresponding interrupt group (e.g., set INT_CTL_ENABLE:PH_INT_STATUS_EN).
  - Note that even if an interrupt source is not enabled to generate a HW NIRQ interrupt, the given interrupt event still may occur inside the chip and may be monitored by polling a GPIO pin, or via the GET_INT_STATUS or GET_PH_STATUS commands.
- Default: 0x00
- Register View:

| INT_CTL_PH_ENABLE
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x01 | 0 | 0 | PACKET_SENT_EN | 0 | 0 | 0 | TX_FIFO_ALMOST_EMPTY_EN | 0
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0

- Field Details:

  ###### INT_CTL_PH_ENABLE

  PACKET_SENT_EN
  Description:
    If set, Enables PACKET_SENT interrupt on rising edge of PACKET_SENT status bit. See the status bits in GET_INT_STATUS for more details on the interrupt sources.
  Default:
    0x0
  TX_FIFO_ALMOST_EMPTY_EN
  Description:
    If set, Enables TX_FIFO_ALMOST_EMPTY interrupt on rising edge of TX_FIFO_ALMOST_EMPTY status bit. See the status bits in GET_INT_STATUS for more details on the interrupt sources.
  Default:
    0x0

#### INT_CTL_CHIP_ENABLE

- Group: 0x01
- Index: 0x03

- Summary: Enable individual interrupt sources within the Chip Interrupt Group to generate a HW interrupt on the NIRQ output pin.
- Purpose:
  - Enable individual interrupt sources within the Chip Interrupt Group in order to generate a HW interrupt at the NIRQ output pin.
  - In order to fully enable a HW interrupt, it is necessary to enable both the individual interrupt source (within this property) as well as the corresponding interrupt group (e.g., set INT_CTL_ENABLE:CHIP_INT_STATUS_EN).
  - Note that even if an interrupt source is not enabled to generate a HW NIRQ interrupt, the given interrupt event still may occur inside the chip and may be monitored by polling a GPIO pin, or via the GET_INT_STATUS or GET_CHIP_STATUS commands.
- Default: 0x04
- Register View:

| INT_CTL_CHIP_ENABLE
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x03 | 0 | CAL_EN | FIFO_UNDERFLOW_OVERFLOW_ERROR_EN | STATE_CHANGE_EN | CMD_ERROR_EN | CHIP_READY_EN | LOW_BATT_EN | WUT_EN
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x1 | 0x0 | 0x0

- Field Details:

  ###### INT_CTL_CHIP_ENABLE

  CAL_EN
  Description:
    If set, Enables CAL interrupt on rising edge of CAL status bit. See the status bits in GET_INT_STATUS for more details on the interrupt sources.
  Default:
    0x0
  FIFO_UNDERFLOW_OVERFLOW_ERROR_EN
  Description:
    If set, Enables FIFO_UNDERFLOW_OVERFLOW_ERROR interrupt on rising edge of FIFO_UNDERFLOW_OVERFLOW_ERROR status bit. See the status bits in GET_INT_STATUS for more details on the interrupt sources.
  Default:
    0x0
  STATE_CHANGE_EN
  Description:
    If set, Enables STATE_CHANGE interrupt on rising edge of STATE_CHANGE status bit. See the status bits in GET_INT_STATUS for more details on the interrupt sources.
  Default:
    0x0
  CMD_ERROR_EN
  Description:
    If set, Enables CMD_ERROR interrupt on rising edge of CMD_ERROR status bit. See the status bits in GET_INT_STATUS for more details on the interrupt sources.
  Default:
    0x0
  CHIP_READY_EN
  Description:
    If set, Enables CHIP_READY interrupt on rising edge of CHIP_READY status bit. See the status bits in GET_INT_STATUS for more details on the interrupt sources.
  Default:
    0x1
  LOW_BATT_EN
  Description:
    If set, Enables LOW_BATT interrupt on rising edge of LOW_BATT status bit. See the status bits in GET_INT_STATUS for more details on the interrupt sources.
  Default:
    0x0
  WUT_EN
  Description:
    If set, Enables WUT interrupt on rising edge of WUT status bit. See the status bits in GET_INT_STATUS for more details on the interrupt sources.
  Default:
    0x0

### FRR_CTL

#### FRR_CTL_A_MODE

- Group: 0x02
- Index: 0x00

- Summary: Fast Response Register A Configuration.
- Purpose:
  - The chip provides four Fast Response Registers (FRR) that may be read immediately without the need to monitor and check CTS, thus improving the speed at which the contents may be retrieved.
  - The FRR_CTL_X_MODE properties are used to select the specific parameter values (selected from the enumeration list below) that will be returned by the FRR_X_READ commands. This property selects the parameter held in FRR_A and returned by the FRR_A_READ command.
  - The FRR registers may be read in a burst fashion through the FRR_X_READ commands. After the initial 16 clock cycles, each additional eight clock cycles will clock out the contents of the next fast response register in a circular fashion. Example: If the FRR_A_READ command is issued, the registers will be read in the order A-B-C-D, while if the FRR_B_READ command is issued, the registers will be read in the order B-C-D-A, etc.
- Default: 0x01
- Register View:

| FRR_CTL_A_MODE
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x00 | FRR_A_MODE
| Default
| 0x1

- Field Details:

  ###### FRR_CTL_A_MODE

  FRR_A_MODE[7:0]
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DISABLED | 0 | Disabled. Will always read back 0. | revB1A
    INT_STATUS | 1 | Global status. | revB1A
    INT_PEND | 2 | Global interrupt pending. | revB1A
    INT_PH_STATUS | 3 | Packet Handler status. | revB1A
    INT_PH_PEND | 4 | Packet Handler interrupt pending. | revB1A
    INT_CHIP_STATUS | 7 | Chip status. | revB1A
    INT_CHIP_PEND | 8 | Chip status interrupt pending. | revB1A
    CURRENT_STATE | 9 | Current state. | revB1A

#### FRR_CTL_B_MODE

- Group: 0x02
- Index: 0x01

- Summary: Fast Response Register B Configuration.
- Purpose:
  - This property selects the parameter held in FRR_B and returned by the FRR_B_READ command.
  - Please refer to the text description for FRR_CTL_A_MODE for more details regarding the Fast Response Register (FRR) function.
- Default: 0x02
- Register View:

| FRR_CTL_B_MODE
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x01 | FRR_B_MODE
| Default
| 0x2

- Field Details:

  ###### FRR_CTL_B_MODE

  FRR_B_MODE[7:0]
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DISABLED | 0 | Disabled. Will always read back 0. | revB1A
    INT_STATUS | 1 | Global status. | revB1A
    INT_PEND | 2 | Global interrupt pending. | revB1A
    INT_PH_STATUS | 3 | Packet Handler status. | revB1A
    INT_PH_PEND | 4 | Packet Handler interrupt pending. | revB1A
    INT_CHIP_STATUS | 7 | Chip status. | revB1A
    INT_CHIP_PEND | 8 | Chip status interrupt pending. | revB1A
    CURRENT_STATE | 9 | Current state. | revB1A

#### FRR_CTL_C_MODE

- Group: 0x02
- Index: 0x02

- Summary: Fast Response Register C Configuration.
- Purpose:
  - This property selects the parameter held in FRR_C and returned by the FRR_C_READ command.
  - Please refer to the text description for FRR_CTL_A_MODE for more details regarding the Fast Response Register (FRR) function.
- Default: 0x09
- Register View:

| FRR_CTL_C_MODE
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x02 | FRR_C_MODE
| Default
| 0x9

- Field Details:

  ###### FRR_CTL_C_MODE

  FRR_C_MODE[7:0]
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DISABLED | 0 | Disabled. Will always read back 0. | revB1A
    INT_STATUS | 1 | Global status. | revB1A
    INT_PEND | 2 | Global interrupt pending. | revB1A
    INT_PH_STATUS | 3 | Packet Handler status. | revB1A
    INT_PH_PEND | 4 | Packet Handler interrupt pending. | revB1A
    INT_CHIP_STATUS | 7 | Chip status. | revB1A
    INT_CHIP_PEND | 8 | Chip status interrupt pending. | revB1A
    CURRENT_STATE | 9 | Current state. | revB1A

#### FRR_CTL_D_MODE

- Group: 0x02
- Index: 0x03

- Summary: Fast Response Register D Configuration.
- Purpose:
  - This property selects the parameter held in FRR_D and returned by the FRR_D_READ command.
  - Please refer to the text description for FRR_CTL_A_MODE for more details regarding the Fast Response Register (FRR) function.
- Default: 0x00
- Register View:

| FRR_CTL_D_MODE
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x03 | FRR_D_MODE
| Default
| 0x0

- Field Details:

  ###### FRR_CTL_D_MODE

  FRR_D_MODE[7:0]
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DISABLED | 0 | Disabled. Will always read back 0. | revB1A
    INT_STATUS | 1 | Global status. | revB1A
    INT_PEND | 2 | Global interrupt pending. | revB1A
    INT_PH_STATUS | 3 | Packet Handler status. | revB1A
    INT_PH_PEND | 4 | Packet Handler interrupt pending. | revB1A
    INT_CHIP_STATUS | 7 | Chip status. | revB1A
    INT_CHIP_PEND | 8 | Chip status interrupt pending. | revB1A
    CURRENT_STATE | 9 | Current state. | revB1A

### PREAMBLE

#### PREAMBLE_TX_LENGTH

- Group: 0x10
- Index: 0x00

- Summary: Configure length of TX Preamble.
- Purpose:
  - This property is used to configure the length of the Preamble field in TX mode for both Standard and Non-Standard Preambles.
  - This property is not used by the chip in RX mode except when receiving a Non-Standard Preamble. In such a case, this property must be configured with the expected Preamble length (to provide an upper timeout limit on the Sync Word search algorithm).
  - This property is only applicable in TX Packet Handler FIFO mode; if TX Direct Synchronous or TX Direct Asynchronous mode is selected (see MODEM_MOD_TYPE property), the entire transmission is obtained from a real-time TXDATA input stream on a GPIO pin and no automatic field construction is possible.
  - The units of this property are in either nibbles or bytes, depending upon the value of PREAMBLE_CONFIG:LENGTH_CONFIG.
  - Setting PREAMBLE_TX_LENGTH = 0x00 is a valid value, and will result in skipping transmission of the Preamble field; in such a case, the Sync Word will be the first transmitted field.
- Default: 0x08
- Register View:

| PREAMBLE_TX_LENGTH
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x00 | TX_LENGTH
| Default
| 0x8

- Field Details:

  ###### PREAMBLE_TX_LENGTH

  TX_LENGTH[7:0]
  Description:
    Length of the TX Preamble to send, in units of nibbles or bytes (depending upon the value of PREAMBLE_CONFIG:LENGTH_CONFIG).
  Min:
    0x0
  Max:
    0xff
  Default:
    0x8

#### PREAMBLE_CONFIG_STD_1

- Group: 0x10
- Index: 0x01

- Summary: Configuration of reception of a packet with a Standard Preamble pattern.
- Purpose:
  - The fields in this property are applicable only in RX mode, and apply primarily to reception of Standard Preamble patterns (e.g., 1010 or 0101 patterns).
  - However, see note on required configuration of RX_THRESH during reception of Non-Standard Preamble patterns.
- Default: 0x14
- Register View:

| PREAMBLE_CONFIG_STD_1
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x01 | SKIP_SYNC_TIMEOUT | RX_THRESH
| Default
| 0x0 | 0x14

- Field Details:

  ###### PREAMBLE_CONFIG_STD_1

  SKIP_SYNC_TIMEOUT
  Description:
    - During reception of a Standard Preamble pattern, the chip recognizes the start of the Sync Word field as a sequence of bits that does not match a ...1010... pattern. Detection of the Sync Word is expected to occur soon thereafter (within the programmed length of the Sync Word field).
    - This bit affects the timeout function only during reception of a Standard Preamble; it is not possible to skip the Sync Word timeout function during reception of a Non-Standard Preamble.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DISABLE | 0 | If Sync Word is not found the system will timeout and return to searching for Preamble. |
    ENABLE | 1 | Sync Word search timeout is ignored and the chip remains continuously searching for Sync Word. |

  RX_THRESH[6:0]
  Description:
    - Configures the number of standard preamble bits (e.g., 1010 or 0101) that must be consecutively received to detect a valid preamble. Bit errors are not allowed during qualification of a Standard Preamble.
    - This field does NOT determine the detection threshold during reception of a Non-Standard Preamble (this is set by PREAMBLE_CONFIG_NSTD:PATTERN_LENGTH). However, when receiving a Non-Standard Preamble this field should be configured to a moderate value (e.g., 0x14 to 0x20) else premature timeout of the search for Sync Word may occur.
    - Detection of a PREAMBLE_VALID signal is typically used by the chip as a trigger event for gear-switching of internal clock timing loops or AFC functionality.
    - Setting RX_THRESH = 0x00 is a valid value and will result in skipping checking/qualification of the preamble; the PREAMBLE_VALID signal will be asserted HIGH immediately upon entering RX mode.
  Min:
    0x0
  Max:
    0x7f
  Default:
    0x14

#### PREAMBLE_CONFIG_NSTD

- Group: 0x10
- Index: 0x02

- Summary: Configuration of transmission/reception of a packet with a Non-Standard Preamble pattern.
- Purpose:
  - The fields in this property apply only to transmission and reception of packets with Non-Standard Preamble patterns (e.g., other than 1010 or 0101 patterns).
- Default: 0x00
- Register View:

| PREAMBLE_CONFIG_NSTD
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x02 | RX_ERRORS | PATTERN_LENGTH
| Default
| 0x0 | 0x0

- Field Details:

  ###### PREAMBLE_CONFIG_NSTD

  RX_ERRORS[2:0]
  Description:
    - Number of bit errors that are allowed during reception and qualification of a Non-Standard Preamble pattern.
    - No bit errors are allowed when configured to receive a Standard Preamble pattern; however, it is possible to configure the chip to receive a Non-Standard Preamble but define the pattern to match that of a Standard Preamble, thus providing a means for tolerating bit errors.
  Min:
    0x0
  Max:
    0x7
  Default:
    0x0
  PATTERN_LENGTH[4:0]
  Description:
    - This value (plus 1) specifies the length (in bits) of the repeating pattern that defines the Non-Standard Preamble. The actual values of the bits in the pattern are specified within the PREAMBLE_PATTERN_XX properties; the PATTERN_LENGTH field simply determines how many of those specified bit values are transmitted as a repeating pattern.
    - In TX mode, if the total length of the TX preamble (as defined by the PREAMBLE_TX_LENGTH property) is longer than PATTERN_LENGTH, the pattern will be transmitted repeatedly as necessary.
    - In RX mode during reception of a Non-Standard Preamble, this field determines the number of preamble bits that must be received to detect a valid preamble. That is, the PATTERN_LENGTH field provides a similar Detection Threshold functionality for a Non-Standard Preamble as PREAMBLE_CONFIG_STD_1:RX_THRESH provides for a Standard Preamble.
  Min:
    0x0
  Max:
    0x1f
  Default:
    0x0

#### PREAMBLE_CONFIG

- Group: 0x10
- Index: 0x04

- Summary: General configuration bits for the Preamble field.
- Purpose:
  - Miscellaneous preamble configuration bits.
- Default: 0x21
- Register View:

| PREAMBLE_CONFIG
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x04 | RX_PREAM_SRC | 0 | PREAM_FIRST_1_OR_0 | LENGTH_CONFIG | MAN_CONST | MAN_ENABLE | STANDARD_PREAM
| Default
| 0x0 | 0x0 | 0x1 | 0x0 | 0x0 | 0x0 | 0x1

- Field Details:

  ###### PREAMBLE_CONFIG

  RX_PREAM_SRC
  Description:
    Determines the source of preamble detection in RX.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    STANDARD_PREAM | 0 | The preamble detection source is determined by PREAMBLE_CONFIG:STANDARD_PREAM. If MODEM_DSA_CTRL1:DSA_EN is enabled, the signal arrival block will help qualify preamble detect. |
    DSA_ONLY | 1 | Signal Arrival Detector is used for preamble detection in RX. Ignores setting in PREAMBLE_CONFIG:STANDARD_PREAM. |

  PREAM_FIRST_1_OR_0
  Description:
    This bit should be set to match the polarity of the first bit of the transmitted packet. The WDS Calculator should configure this bit correctly as a function of the selected Preamble type (i.e. Standard or Non-Standard) and first defined bit (e.g., Standard 0101 or Standard 1010).
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    FIRST_0 | 0 | First transmitted bit in the packet is 0. |
    FIRST_1 | 1 | First transmitted bit in the packet is 1. |

  LENGTH_CONFIG
  Description:
    This bit specifies whether the units of the PREAMBLE_TX_LENGTH property are in increments of nibbles or bytes.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    NIBBLE | 0 | The units of the PREAMBLE_TX_LENGTH property are in nibbles. |
    BYTE | 1 | The units of the PREAMBLE_TX_LENGTH property are in bytes. |

  MAN_CONST
  Description:
    Manchester encoding normally operates by replacing each 0 bit with a 10 chip pattern, and each 1 bit with a 01 bit pattern (or vice versa).
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    NO_CON | 0 | When Manchester encoding is enabled across the Preamble field by setting the MAN_ENABLE bit and STANDARD_PREAM=0x2 (i.e., standard preamble pattern is 0101), the post-Manchester transmitted bits will be 10011001. If STANDARD_PREAM=0x1 (i.e., standard preamble pattern is 1010), the post-Manchester transmitted bits will be 01100110. |
    CONST | 1 | When Manchester encoding is enabled across the Preamble field by setting the MAN_ENABLE bit and STANDARD_PREAM=0x2, the pre-Manchester preamble pattern will be replaced with a pattern of constant 1's, and the post-Manchester transmitted bits will be 01010101. If STANDARD_PREAM=0x1, the pre-Manchester pattern will be replaced with a pattern of constant 0's, and the post-Manchester transmitted bits will be 10101010. |

  MAN_ENABLE
  Description:
    This bit enables or disables Manchester encoding/decoding across only the Preamble field. This bit is applicable in both TX and RX mode.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    NO_MAN | 0 | Preamble field is not Manchester encoded/decoded. |
    EN_MAN | 1 | Preamble field is Manchester encoded/decoded. |

  STANDARD_PREAM[1:0]
  Description:
    This field is applicable to both TX and RX modes, but has slightly different meaning in both modes.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    PRE_NS | 0 | TX Mode: Transmit the Non-Standard Preamble (defined in PREAMBLE_PATTERN_XX) as a repetitive pattern until reaching the number of nibbles/bytes defined in PREAMBLE_TX_LENGTH. RX Mode: Expects to receive the Non-Standard Preamble pattern (defined in PREAMBLE_PATTERN_XX) at least once, and generates a PREAMBLE_VALID signal/interrupt upon the first detection of the number of pattern bits specified by PATTERN_LENGTH. |
    PRE_1010 | 1 | TX Mode: Transmit a Standard 1010 preamble until reaching the number of nibbles/bytes defined in PREAMBLE_TX_LENGTH. RX Mode: Expects to receive a Standard 1010 or 0101 preamble. In RX mode, a value of 0x1 or 0x2 in this field results in identical operation. |
    PRE_0101 | 2 | TX Mode: Transmit a Standard 0101 preamble until reaching the number of nibbles/bytes defined in PREAMBLE_TX_LENGTH. RX Mode: Expects to receive a Standard 1010 or 0101 preamble. In RX mode, a value of 0x1 or 0x2 in this field results in identical operation. |

#### PREAMBLE_PATTERN

- Group: 0x10
- Indexes: 0x05 ... 0x08

- Summary: Configuration of the bit values describing a Non-Standard Preamble pattern.
- Purpose:
  - The PREAMBLE_PATTERN property defines the pattern to be transmitted in TX mode and the pattern expected to be received in RX mode, but only when PREAMBLE_CONFIG:STANDARD_PREAM has been set to 0x0 (i.e., use Non-Standard Preamble).
  - The PREAMBLE_PATTERN property is used to define the actual bit values describing the Non-Standard Preamble pattern; PREAMBLE_CONFIG_NSTD:PATTERN_LENGTH is used to define how many bits of the PREAMBLE_PATTERN value is used.
  - In TX mode, if the value of PREAMBLE_TX_LENGTH is larger than PREAMBLE_CONFIG_NSTD:PATTERN_LENGTH, the PREAMBLE_PATTERN will be transmitted repeatedly until the full number of bits has been sent.
  - In RX mode, the full number of bits defined by PREAMBLE_CONFIG_NSTD:PATTERN_LENGTH must be received once before the PREAMBLE_VALID signal/interrupt is generated.
  - If Manchester encoding/decoding is enabled, the values of the PREAMBLE_PATTERN property is expressed in chips (i.e., after Manchester encoding in TX mode, or before Manchester decoding in RX mode).
  - The bits of the PREAMBLE_PATTERN are always sent bits 0-31 time-wise (e.g. bit 0 is sent first).
- Defaults: 0x00,0x00,0x00,0x00
- Register View:

| PREAMBLE_PATTERN
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x05 | PATTERN[31:24]
0x06 | PATTERN[23:16]
0x07 | PATTERN[15:8]
0x08 | PATTERN[7:0]
| Defaults
0x05 | 0x0
0x06 | 0x0
0x07 | 0x0
0x08 | 0x0

- Field Details:

  ###### PREAMBLE_PATTERN

  PATTERN[31:0]
  Description:
    Bits of the Non-Standard Preamble pattern to be transmitted or expected to be received.
  Min:
    0x0
  Max:
    0xffffffff
  Default:
    0x0

### SYNC

#### SYNC_CONFIG

- Group: 0x11
- Index: 0x00

- Summary: Sync Word configuration bits.
- Purpose:
  - Configuration of miscellaneous Sync Word bits. NOTE: each byte of the Sync Word is transmitted/received in little-endian fashion (i.e., least significant bit first). Byte(s) of the Sync Word are transmitted/received in descending order (i.e., Byte 3 first, followed by Byte 2, etc.)
- Default: 0x01
- Register View:

| SYNC_CONFIG
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x00 | SKIP_TX | 000 | 4FSK | MANCH | LENGTH
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0x1

- Field Details:

  ###### SYNC_CONFIG

  SKIP_TX
  Description:
    This property allows the user to choose if the sync word is transmitted. Note: This field only affects TX operation and does not affect reception of the Sync Word.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    SYNC_XMIT | 0 | Sync Word is transmitted. The number of bytes comprising the Sync Word is defined by the LENGTH field within this same property. | revB1A
    NO_SYNC_XMIT | 1 | Sync Word is not transmitted. NOTE: the SKIP_TX bit only affects TX operation, and does not affect reception of the Sync Word. | revB1A

  4FSK
  Description:
    Configures 4FSK modulation for the Sync Word for TX and RX.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Disable 4(G)FSK data processing on this field. |
    ENUM_1 | 1 | Enable 4(G)FSK data processing on this field. |

  MANCH
  Description:
    If Manchester decoding of the Sync Word in RX mode is enabled, MODEM_MAP_CONTROL:ENMANCH should also be set; this results in an extended search timeout period for the Sync Word to allow for the increased number of bits/chips.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DISABLED | 0 | Sync word is not manchester encoded. | revB1A
    ENABLED | 1 | Sync word is manchester encoded. | revB1A

  LENGTH[1:0]
  Description:
    Determines the length of the Sync Word in bytes. The Sync Word is defined in SYNC_BITS and SYNC_BITS2. This length can be modified by ref_prop_field SYNC_CONFIG2 LENGTH_SUB] to allow 2 bit granularity.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    LEN_1_BYTES | 0 | Sync Word is 1-byte (8 bits) in length. Sync Word byte 3 [31:24] is used, with its value defined in the SYNC_BITS property. | revB1A
    LEN_2_BYTES | 1 | Sync Word is 2-bytes (16 bits) in length. Sync Word bytes 3 and 2 [31:16] are used (in descending order), with their values defined in the SYNC_BITS property. | revB1A
    LEN_3_BYTES | 2 | Sync Word is 3-bytes (24 bits) in length. Sync Word bytes 3, 2, and 1 [31:8] are used (in descending order), with their values defined in the SYNC_BITS property. | revB1A
    LEN_4_BYTES | 3 | Sync Word is 4-bytes (32 bits) in length. Sync Word bytes 3, 2, 1, and 0 [31:0] are used (in descending order), with their values defined in the SYNC_BITS property. | revB1A

#### SYNC_BITS

- Group: 0x11
- Indexes: 0x01 ... 0x04

- Summary: Sync word.
- Purpose:
  - Define the value of the Sync Word for both TX and RX operation. NOTE: Although the Sync Word byte(s) are transmitted/received in descending order (i.e., Byte 3 first, followed by Byte 2, etc.), each byte is transmitted/received in little-endian fashion (i.e., least significant bit first).
- Defaults: 0x2d,0xd4,0x2d,0xd4
- Register View:

| SYNC_BITS
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x01 | BITS[31:24]
0x02 | BITS[23:16]
0x03 | BITS[15:8]
0x04 | BITS[7:0]
| Defaults
0x01 | 0x2d
0x02 | 0xd4
0x03 | 0x2d
0x04 | 0xd4

- Field Details:

  ###### SYNC_BITS

  BITS[31:0]
  Description:
    bits
  Min:
    0x0
  Max:
    0xffffffff
  Default:
    0x2dd42dd4

#### SYNC_CONFIG2

- Group: 0x11
- Index: 0x05

- Summary: Sync Word configuration bits.
- Purpose:
  - Advanced Sync Configuration Bits.
- Default: 0x00
- Register View:

| SYNC_CONFIG2
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x05 | SYNC_ERROR_ONLY_BEGIN | 0 | 0 | 0 | 0 | 0 | 00
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0

- Field Details:

  ###### SYNC_CONFIG2

  SYNC_ERROR_ONLY_BEGIN
  Description:
    When this bit is set, the errors that are allowed in the sync match can only occur at the beginning of the Sync. For example, if 5 errors are allowed, these 5 errors must occur in the first 5 bits of the Sync for a Sync to be detected. If there are one or more errors outside of these first 5 bits, Sync is not detected.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    SYNC_ERROR_RAND | 0 | Allow errors to be randomly distributed throughout the Sync. |
    SYNC_ERROR_BEGIN | 1 | Allow errors to only be at the beginning of the sync word. |

### PKT

#### PKT_CRC_CONFIG

- Group: 0x12
- Index: 0x00

- Summary: Select a CRC polynomial and seed.
- Purpose:
  - The chip contains a 32-bit CRC engine for the purpose of generating and comparing a checksum across selected data fields. This property is used to select the desired CRC polynomial and CRC seed value.
  - If a 8-bit CRC polynomial is selected, the length of the resulting checksum is 1-bytes. If a 16-bit CRC polynomial is selected, the length of the resulting checksum is 2-bytes. If a 32-bit CRC polynomial is selected, the length of the resulting checksum is 4-bytes.
  - The configuration bits in this property are common to both TX and RX modes; however, this property is only applicable when automatic Packet Handling is enabled (e.g., when using the TX FIFO as the modulation source in TX mode, or when PKT_CONFIG1:PH_RX_DISABLE is cleared in RX mode).
- Default: 0x00
- Register View:

| PKT_CRC_CONFIG
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x00 | CRC_SEED | ALT_CRC_POLYNOMIAL | CRC_POLYNOMIAL
| Default
| 0x0 | 0x0 | 0x0

- Field Details:

  ###### PKT_CRC_CONFIG

  CRC_SEED
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    CRC_SEED_0 | 0 | Use all 0's for the CRC Seed. |
    CRC_SEED_1 | 1 | Use all 1's for the CRC Seed. |

  ALT_CRC_POLYNOMIAL[2:0]
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    NO_CRC | 0 | None |
    ITU_T_CRC8 | 1 | ITU-T CRC8: X8+X2+X+1. |
    IEC_16 | 2 | IEC-16: X16+X14+X12+X11+X9+X8+X7+X4+X+1. |
    BAICHEVA_16 | 3 | Baicheva-16: X16+X15+X12+X7+X6+X4+X3+1. |
    CRC_16_IBM | 4 | CRC-16 (IBM): X16+X15+X2+1. |
    CCITT_16 | 5 | CCIT-16: X16+X12+X5+1. |
    CRC_16_DNP | 6 | CRC-16-DNP: X16+X13+X12+X11+X10+X8+X6+X5+X2+1. |

  CRC_POLYNOMIAL[3:0]
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    NO_CRC | 0 | None |
    ITU_T_CRC8 | 1 | ITU-T CRC8: X8+X2+X+1. |
    IEC_16 | 2 | IEC-16: X16+X14+X12+X11+X9+X8+X7+X4+X+1. |
    BAICHEVA_16 | 3 | Baicheva-16: X16+X15+X12+X7+X6+X4+X3+1. |
    CRC_16_IBM | 4 | CRC-16 (IBM): X16+X15+X2+1. |
    CCITT_16 | 5 | CCIT-16: X16+X12+X5+1. |
    KOOPMAN | 6 | Koopman: X32+X30+X29+X28+X26+X20+X19+X17+X16+X15+X11+X10+X7+X6+X4+X2+X+1. |
    IEEE_802_3 | 7 | IEEE 802.3: X32+X26+X23+X22+X16+X12+X11+X10+X8+X7+X5+X4+X2+X+1. |
    CASTAGNOLI | 8 | Castagnoli: X32+X28+X27+X26+X25+X23+X22+X20+X19+X18+X14+X13+X11+X10+X9+X8+X6+1. |
    CRC_16_DNP | 9 | CRC-16-DNP: X16+X13+X12+X11+X10+X8+X6+X5+X2+1. |

#### PKT_WHT_POLY

- Group: 0x12
- Indexes: 0x01 ... 0x02

- Summary: 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
- Purpose:
  - The chip contains a 16-bit linear feedback shift register (LFSR) for the purpose of generating a pseudo-random number (PN). The resulting PN sequence may be used for data whitening/de-whitening by XOR-ing the output with the data bits of specified fields.
  - The PN sequence may also be used a modulation source for the TXDATA stream through configuration of the MODEM_MOD_TYPE property. This is often useful for test purposes (e.g., BER tests).
  - The PN sequence generated by the LFSR is determined by the selected 16-bit polynomial and starting seed value. This property defines the polynomial.
  - In general, it is desired to select a polynomial value that results in a maximal length run sequence, where the PN pattern length = 2^N - 1 (e.g., pattern length = 511 bits for a PN9 sequence). There may be more than one polynomial value that will result in a PN sequence of a desired length; the following polynomial values are provided as examples for a variety of popular PN sequence lengths.
  - - PN6: PKT_WHT_POLY = 0x0030.
  - - PN9: PKT_WHT_POLY = 0x0108.
  - - PN11: PKT_WHT_POLY = 0x0500.
  - - PN13: PKT_WHT_POLY = 0x1B00.
  - - PN15: PKT_WHT_POLY = 0x6000.
  - Additional properties related to the generation of the PN sequence are PKT_WHT_SEED and PKT_WHT_BIT_NUM.
- Defaults: 0x01,0x08
- Register View:

| PKT_WHT_POLY
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x01 | WHT_POLY[15:8]
0x02 | WHT_POLY[7:0]
| Defaults
0x01 | 0x1
0x02 | 0x8

- Field Details:

  ###### PKT_WHT_POLY

  WHT_POLY[15:0]
  Description:
    Defines the 16-bit PN polynomial value.
  Min:
    0x0
  Max:
    0xffff
  Default:
    0x108

#### PKT_WHT_SEED

- Group: 0x12
- Indexes: 0x03 ... 0x04

- Summary: 16-bit seed value for the PN Generator (e.g., for Data Whitening)
- Purpose:
  - Defines the 16-bit PN seed value.
- Defaults: 0xff,0xff
- Register View:

| PKT_WHT_SEED
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x03 | WHT_SEED[15:8]
0x04 | WHT_SEED[7:0]
| Defaults
0x03 | 0xff
0x04 | 0xff

- Field Details:

  ###### PKT_WHT_SEED

  WHT_SEED[15:0]
  Description:
    Defines the 16-bit PN seed value.
  Min:
    0x0
  Max:
    0xffff
  Default:
    0xffff

#### PKT_WHT_BIT_NUM

- Group: 0x12
- Index: 0x05

- Summary: Selects which bit of the LFSR (used to generate the PN / data whitening sequence) is used as the output bit for data scrambling.
- Purpose:
  - Enables software whitening over the packet.
- Default: 0x00
- Register View:

| PKT_WHT_BIT_NUM
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x05 | SW_WHT_CTRL | SW_CRC_CTRL | PN_DIRECTION | 0 | WHT_BIT_NUM
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0x0

- Field Details:

  ###### PKT_WHT_BIT_NUM

  SW_WHT_CTRL
  Description:
    Enables software whitening over the packet.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DISABLE | 0 | Disable the software based data whitening algorithm. |
    ENABLE | 1 | Enable the software based data whitening algorithm. |

  SW_CRC_CTRL
  Description:
    Enables software-based CRC calculation over the packet, and is only applicable when also using software-based data whitening by setting the SW_WHT_CTRL bit. If not using software-based whitening, CRC functionality must be configured in the Packet Handler (see PKT_CRC_CONFIG).
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DISABLE | 0 | Disable the software based CRC engine. |
    ENABLE | 1 | Enable the software based CRC engine. |

  PN_DIRECTION
  Description:
    This bit controls the direction data bits are shifted during the whitening operation.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    FORWARD | 0 | Data bits are shifted from bit 7 down to bit 0, in the same direction the polynomial bits are shifted from bit 8 down to bit 0. |
    REVERSED | 1 | Data bits are shifted from bit 0 up to bit 7, in the opposite direction the polynomial bits are shifted from bit 8 down to bit 0. |

  WHT_BIT_NUM[3:0]
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Bit 0 is selected as the output bit for data whitening. |
    ENUM_1 | 1 | Bit 1 is selected as the output bit for data whitening. |
    ENUM_2 | 2 | Bit 2 is selected as the output bit for data whitening. |
    ENUM_3 | 3 | Bit 3 is selected as the output bit for data whitening. |
    ENUM_4 | 4 | Bit 4 is selected as the output bit for data whitening. |
    ENUM_5 | 5 | Bit 5 is selected as the output bit for data whitening. |
    ENUM_6 | 6 | Bit 6 is selected as the output bit for data whitening. |
    ENUM_7 | 7 | Bit 7 is selected as the output bit for data whitening. |
    ENUM_8 | 8 | Bit 8 is selected as the output bit for data whitening. |
    ENUM_9 | 9 | Bit 9 is selected as the output bit for data whitening. |
    ENUM_10 | 10 | Bit 10 is selected as the output bit for data whitening. |
    ENUM_11 | 11 | Bit 11 is selected as the output bit for data whitening. |
    ENUM_12 | 12 | Bit 12 is selected as the output bit for data whitening. |
    ENUM_13 | 13 | Bit 13 is selected as the output bit for data whitening. |
    ENUM_14 | 14 | Bit 14 is selected as the output bit for data whitening. |
    ENUM_15 | 15 | Bit 15 is selected as the output bit for data whitening. |

#### PKT_CONFIG1

- Group: 0x12
- Index: 0x06

- Summary: General configuration bits for transmission or reception of a packet.
- Purpose:
  - In many links, the flow of information is primarily in one direction with only brief acknowledgement (ACK) packets sent in the reverse direction. In such a case, it is inconvenient to re-define the field-level properties (e.g., field length, data whitening, etc.) in between each TX-to-RX-to-TX transition.
  - The chip provides for "splitting" the definitions of field-level properties in TX and RX mode. That is, the chip is capable of using one shared set of field-level properties for both TX and RX, or separate sets of field-level properties in TX and RX.
- Default: 0x00
- Register View:

| PKT_CONFIG1
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x06 | PH_FIELD_SPLIT | 0 | 4FSK_EN | 0 | MANCH_POL | CRC_INVERT | CRC_ENDIAN | BIT_ORDER
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0

- Field Details:

  ###### PKT_CONFIG1

  PH_FIELD_SPLIT
  Description:
    - In many links, the flow of information is primarily in one direction with only brief acknowledgement (ACK) packets sent in the reverse direction. In such a case, it is inconvenient to re-define the field-level properties (e.g., field length, data whitening, etc.) in between each TX-to-RX-to-TX transition.
    - The chip provides for "splitting" the definitions of field-level properties in TX and RX mode. That is, the chip is capable of using one shared set of field-level properties for both TX and RX, or separate sets of field-level properties in TX and RX.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    FIELD_SHARED | 0 | Field level properties are shared between TX and RX modes (defined in property addresses 0x120D to 0x1220). |
    FIELD_SPLIT | 1 | Field level properties are split between TX and RX modes. TX field-level properties are defined from property address 0x120D to 0x1220, RX field-level properties from 0x1221 to 0x1234. |

  4FSK_EN
  Description:
    If set, enables 4(G)FSK processing across the selected field. The Modem must be additionally configured for 4(G)FSK demodulation through appropriate setting of the MODEM_MOD_TYPE property; the 4FSK bit simply configures the PH to process the data stream to the RX FIFO as bit pairs (instead of as single bits for 2(G)FSK mode).
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DISABLE | 0 | The modem is not in 4(G)FSK mode. |
    ENABLE | 1 | The modem is in 4(G)FSK mode. |

  MANCH_POL
  Description:
    - Manchester encoding operates by replacing each bit with a two-chip pattern. This bit selects the polarity of Manchester encoding/decoding.
    - The selected coding polarity is applied to all fields in the packet; it is not possible to select the coding polarity on a field-by-field basis.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    PATTERN_10 | 0 | 0 is encoded to/decoded from a 10 Manchester pattern, and a 1 is encoded to/decoded from a 01 Manchester pattern. |
    PATTERN_01 | 1 | 0 is encoded to/decoded from a 01 Manchester pattern, and a 1 is encoded to/decoded from a 10 Manchester pattern. |

  CRC_INVERT
  Description:
    This bit determines whether each bit in the transmitted or received CRC checksum is inverted in polarity.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    NO_INVERT | 0 | Transmit/receive each CRC checksum bit with non-inverted polarity. |
    INVERT_CRC | 1 | In TX mode, calculate the CRC checksum and then invert the polarity of each checksum bit before transmission. In RX mode, invert the polarity of each received CRC checksum bit prior to comparison. In both modes, the data in the FIFOs remains unaltered. |

  CRC_ENDIAN
  Description:
    - This bit selects the order in which the bytes of the CRC checksum are transmitted or received.
    - Note: if a 16-bit CRC polynomial is selected (in PKT_CRC_CONFIG), the length of the resulting checksum is 2-bytes. If a 32-bit CRC polynomial is selected, the length of the resulting checksum is 4-bytes.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    LSBYTE_FIRST | 0 | The CRC bytes are received/transmitted in the order: lowest byte to highest byte. |
    MSBYTE_FIRST | 1 | The CRC bytes are received/transmitted in the order: highest byte to lowest byte. |

  BIT_ORDER
  Description:
    - This bit selects the transmission/reception order for the bits in all data fields. Note: The Preamble and Sync Word fields are always transmitted or received LSB first (little-endian), regardless of the state of this bit.
    - This bit does not affect the transmission/reception order of the bytes. Example: the transmission of bytes will match the order in which they are stored in the TX FIFO. However, this bit selects whether each byte is transmitted or received in big-endian or little-endian fashion.
    - In RX mode, received data bits observed in real-time (on a GPIO pin) always reflect their true time-wise sequence on the air interface; bit order inversion is performed only on bits stored in the RX FIFO.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    MSBIT_FIRST | 0 | MSB first for all bytes in data fields (big-endian). Bit 7 is transmitted/received first, time-wise. |
    LSBIT_FIRST | 1 | LSB first for all bytes in data fields (little-endian). Bit 0 is transmitted/received first, time-wise. |

#### PKT_CONFIG2

- Group: 0x12
- Index: 0x07

- Summary: General packet configuration bits.
- Purpose:
  - Enables 3 of 6 encoding/decoding. The encoding/decoding is not applied to preamble and sync fields but for all five fields and the CRC.
- Default: 0x00
- Register View:

| PKT_CONFIG2
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x07 | CRC_BIT_ENDIAN | CRC_PADDING | ALT_CRC_SEED | EN_3_OF_6 | 0 | 0 | 0 | 0
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0

- Field Details:

  ###### PKT_CONFIG2

  CRC_BIT_ENDIAN
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    MSBIT_FIRST | 0 | CRC is transmitted most significant bit first. Bit 7 transmitted first timewise. |
    LSBIT_FIRST | 1 | CRC is transmitted least significant bit first. Bit 0 transmitted first timewise. |

  CRC_PADDING
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    NO_PADDING | 0 | CRC engine does not pad if message length is less than 32 bits. |
    PAD_ZEROS | 1 | CRC engine pads zeros if the message length is less than 32 bits. |

  ALT_CRC_SEED
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ALT_CRC_SEED_0 | 0 | Use all 0's for the CRC Seed. |
    ALT_CRC_SEED_1 | 1 | Use all 1's for the CRC Seed. |

  EN_3_OF_6
  Description:
    Enables 3 of 6 encoding/decoding. The encoding/decoding is not applied to preamble and sync fields but for all five fields and the CRC.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DISABLED | 0 | Data encoding 3 of 6 is disabled. |
    ENABLED | 1 | Data encoding 3 of 6 is enabled. |

#### PKT_TX_THRESHOLD

- Group: 0x12
- Index: 0x0b

- Summary: TX FIFO almost empty threshold.
- Purpose:
  - The chip provides for two separate 64-byte FIFO memories for the purpose of storing transmit and receive data. (When the GLOBAL_CONFIG:FIFO_MODE bit is set, these two FIFOs are combined into a single 129-byte shared FIFO.)
  - This property is used to set a threshold value for the TX FIFO. An interrupt event is generated when the amount of empty space in the TX FIFO is equal to or greater than this threshold.
  - The TX_FIFO_ALMOST_EMPTY interrupt may be used to signal the host MCU to store more data bytes into the TX FIFO, thus providing a means for handling packets with lengths greater than the size of the TX FIFO (i.e., 64 bytes, or 129 bytes in shared FIFO mode).
- Default: 0x30
- Register View:

| PKT_TX_THRESHOLD
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x0b | TX_THRESHOLD
| Default
| 0x30

- Field Details:

  ###### PKT_TX_THRESHOLD

  TX_THRESHOLD[7:0]
  Description:
    Sets the TX FIFO Almost Empty threshold, in number of bytes.
  Min:
    0x0
  Max:
    0x40
  Default:
    0x30

#### PKT_FIELD_1_LENGTH

- Group: 0x12
- Indexes: 0x0d ... 0x0e

- Summary: Unsigned 13-bit Field 1 length value.
- Purpose:
  - The PKT_FIELD_1_LENGTH properties specify the length of Field 1 in bytes. The field length is an unsigned 13-bit value.
  - Partitioning of the Payload into separate fields is provided to support variable length packets, and to allow different forms of data processing (e.g., Manchester encoding, data whitening, etc) across different fields.
  - These properties are applicable in TX mode only if the START_TX command is sent with the parameter TX_LEN=0.
  - A value of zero in this property means that the field is not used. During TX mode, data will be retrieved from the TX FIFO until encountering the first field whose length has been set to zero. It is possible (although not common) to set the length of Field 1 = 0 bytes, as this would indicate transmission/reception of a packet with no Payload data at all.
- Defaults: 0x00,0x00
- Register View:

| PKT_FIELD_1_LENGTH
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x0d | 0 | 0 | 0 | FIELD_1_LENGTH[12:8]
0x0e | FIELD_1_LENGTH[7:0]
| Defaults
0x0d | 0x0 | 0x0 | 0x0 | 0x0
0x0e | 0x0

- Field Details:

  ###### PKT_FIELD_1_LENGTH

  FIELD_1_LENGTH[12:0]
  Description:
    Bits 12 to 0 of the field length.
  Min:
    0x0
  Max:
    0x1fff
  Default:
    0x0

#### PKT_FIELD_1_CONFIG

- Group: 0x12
- Index: 0x0f

- Summary: General data processing and packet configuration bits for Field 1.
- Purpose:
  - Partitioning of the Payload into separate fields is provided to support features such as variable length packets and field-specific data processing (e.g., Manchester encoding, data whitening, etc). This property provides configuration bits for field-specific processing on Field 1.
  - The configuration bits in this property are common to both TX and RX modes dependent on PKT_CONFIG1:PH_FIELD_SPLIT; however, this property is only applicable when automatic Packet Handling is enabled (e.g., when using the TX FIFO as the modulation source in TX mode, or when PKT_CONFIG1:PH_RX_DISABLE is cleared in RX mode).
- Default: 0x00
- Register View:

| PKT_FIELD_1_CONFIG
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x0f | 0 | 0 | 0 | 4FSK | 0 | PN_START | WHITEN | MANCH
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0

- Field Details:

  ###### PKT_FIELD_1_CONFIG

  4FSK
  Description:
    - The chip supports field-specific configuration of (G)FSK modulation modes, i.e., 2(G)FSK across certain fields and 4(G)FSK across other fields. In such a case, the Modem must be configured for 4(G)FSK operation across the entire packet (by setting the MODEM_MOD_TYPE property), and the Packet Handler is then configured on a field-by-field basis to process the data stream from the FIFO as bit pairs (for 4(G)FSK) or single bits (for 2(G)FSK).
    - When 4(G)FSK is enabled across a field, the PH pulls two bits from the FIFO and sends them to the TX Modulator to be transmitted as one-of-four deviation levels.
    - When 4(G)FSK is disabled across a field, the PH pulls one bit from the FIFO and replaces it with the appropriate two bits that map to the outer two deviation levels. Although the TX Modulator remains configured for four levels of deviation (by the MODEM_MOD_TYPE property), using only the outer two deviation levels effectively results in 2(G)FSK modulation across that field.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Disable 4(G)FSK data processing on this field. |
    ENUM_1 | 1 | Enable 4(G)FSK data processing on this field. |

  PN_START
  Description:
    - The chip contains a linear feedback shift register (LFSR) for the purpose of generating a pseudo-random number (PN). Data whitening/de-whitening may be obtained by XOR-ing the output from the resulting PN sequence with the data bits of specified fields.
    - This bit controls whether the PN engine is freshly loaded with its seed value (specified in PKT_WHT_SEED_XX) at the start of this field, or whether the PN engine continues calculation from its last state (i.e., from the previous packet). Note: the seed value for the PN engine may only be loaded at the start of Field 1; it is not possible to re-load the seed value at any other place in the packet.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 1 | Continue PN generation using last state from previous packet. |
    ENUM_1 | 1 | Load PN engine with the seed value at the start of Field 1. |

  WHITEN
  Description:
    - The data whitening/de-whitening function is only available when automatic Packet Handling is enabled (e.g., when using the TX FIFO as the modulation source in TX mode, or when the PH_RX_DISABLE bit in the PKT_CONFIG1 property is cleared in RX mode).
    - In RX mode, the data de-whitening function is performed only on bits stored in the RX FIFO; received data bits observed in real-time (on a GPIO pin) are output prior to de-whitening.
    - Enabling data whitening does not affect the over-the-air data rate.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Disable data whitening/de-whitening on this field. |
    ENUM_1 | 1 | Enable data whitening/de-whitening on this field. |

  MANCH
  Description:
    - Manchester encoding operates by replacing each bit with a two-chip pattern (e.g., each '0' bit with a '10' pattern and each '1' bit with a '01' bit pattern, or vice versa). The desired encoding polarity is selected by PKT_CONFIG1:MANCH_POL.
    - Enabling Manchester encoding in one or more fields does not affect the over-the-air data rate; each bit/chip within the entire packet is transmitted at the same data rate (specified by the MODEM_DATA_RATE_X properties). Manchester encoding simply affects the number of bits/chips that are sent (e.g., by replacing one bit with two chips).
    - In RX mode, the Manchester decoding function is performed only on bits stored in the RX FIFO; received data bits observed in real-time (on a GPIO pin) are output prior to decoding.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Disable manchester encoding/decoding on this field. |
    ENUM_1 | 1 | Enable manchester encoding/decoding on this field. |

#### PKT_FIELD_1_CRC_CONFIG

- Group: 0x12
- Index: 0x10

- Summary: Configuration of CRC control bits across Field 1.
- Purpose:
  - This property is use to control the calculation, transmission, and checking of CRC across Field 1.
- Default: 0x00
- Register View:

| PKT_FIELD_1_CRC_CONFIG
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x10 | CRC_START | ALT_CRC_START | SEND_CRC | SEND_ALT_CRC | 0 | 0 | CRC_ENABLE | ALT_CRC_ENABLE
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0

- Field Details:

  ###### PKT_FIELD_1_CRC_CONFIG

  CRC_START
  Description:
    - The chip contains a 32-bit CRC engine that may be configured for a variety of polynomials and seed values (refer to the PKT_CRC_CONFIG property). This bit controls whether the CRC engine is freshly loaded with its seed value (PKT_CRC_CONFIG:CRC_SEED) at the start of this field, or whether the CRC engine continues calculation from its last state (i.e., from the previous packet). Note: the seed value for the CRC engine may only be loaded at the start of Field 1; it is not possible to re-load the seed value at any other place in the packet.
    - This bit is applicable in both TX and RX modes.
    - If in RX mode and PKT_CONFIG1:PH_FIELD_SPLIT is set, this bit is ignored and the CRC_START functionality is obtained from the appropriate PKT_RX_FIELD_X_CRC_CONFIG property.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Continue CRC calculation using the last state from the previous packet. |
    ENUM_1 | 1 | Load the CRC engine with the seed value at the start of this field using PKT_CRC_CONFIG:CRC_SEED. |

  ALT_CRC_START
  Description:
    - The chip contains a 16-bit CRC engine that may be configured for a variety of polynomials and seed values (refer to the PKT_CRC_CONFIG property). This bit controls whether the CRC engine is freshly loaded with its seed value (PKT_CRC_CONFIG:CRC_SEED) at the start of this field, or whether the CRC engine continues calculation from its last state (i.e., from the previous packet). Note: the seed value for the ALT CRC engine may only be loaded at the start of Field 1; it is not possible to re-load the seed value at any other place in the packet.
    - This bit is applicable in both TX and RX modes.
    - If in RX mode and PKT_CONFIG1:PH_FIELD_SPLIT bit is set, this bit is ignored and the ALT_CRC_START functionality is obtained from the appropriate PKT_RX_FIELD_X_CRC_CONFIG property.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    CONTINUE | 0 | Continue 16-bit CRC calculation using the last state from the previous packet. |
    LOAD | 1 | Load 16-bit CRC engine with seed value at the start of this field using PKT_CRC_CONFIG:CRC_SEED. |

  SEND_CRC
  Description:
    This bit is applicable only in TX mode, and determines whether the accumulated CRC checksum will be transmitted at the end of this field.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Do not Transmit CRC at the end of this field. |
    ENUM_1 | 1 | Transmit CRC at the end of this field. |

  SEND_ALT_CRC
  Description:
    This bit is applicable only in TX mode, and determines whether the accumulated ALT CRC checksum will be transmitted at the end of this field.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Do not Transmit ALT CRC at the end of this field. |
    ENUM_1 | 1 | Transmit ALT CRC at the end of this field. |

  CRC_ENABLE
  Description:
    - This bit is applicable in both TX and RX modes, and enables CRC checksum calculation over this field. Note: enabling CRC calculation across a field does not automatically result in transmission/checking of the CRC checksum at the end of the field.
    - If in RX mode and PKT_CONFIG1:PH_FIELD_SPLIT is set, this bit is ignored and the CRC_ENABLE functionality is obtained from the appropriate PKT_RX_FIELD_X_CRC_CONFIG property.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Disable CRC calculation over this field. |
    ENUM_1 | 1 | Enable CRC calculation over this field. |

  ALT_CRC_ENABLE
  Description:
    - This bit is applicable in both TX and RX modes, and enables ALT CRC checksum calculation over this field. Note: enabling ALT CRC calculation across a field does not automatically result in transmission/checking of the ALT CRC checksum at the end of the field.
    - If in RX mode and PKT_CONFIG1:PH_FIELD_SPLIT is set, this bit is ignored and the ALT_CRC_ENABLE functionality is obtained from the appropriate PKT_RX_FIELD_X_CRC_CONFIG property.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Disable ALT CRC calculation over this field. |
    ENUM_1 | 1 | Enable ALT CRC calculation over this field. |

#### PKT_FIELD_2_LENGTH

- Group: 0x12
- Indexes: 0x11 ... 0x12

- Summary: Unsigned 13-bit Field 2 length value.
- Purpose:
  - The PKT_FIELD_2_LENGTH properties specify the length of Field 2 in bytes. The field length is an unsigned 13-bit value.
  - Please refer to the text description for PKT_FIELD_1_LENGTH for more details regarding field length configuration.
- Defaults: 0x00,0x00
- Register View:

| PKT_FIELD_2_LENGTH
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x11 | 0 | 0 | 0 | FIELD_2_LENGTH[12:8]
0x12 | FIELD_2_LENGTH[7:0]
| Defaults
0x11 | 0x0 | 0x0 | 0x0 | 0x0
0x12 | 0x0

- Field Details:

  ###### PKT_FIELD_2_LENGTH

  FIELD_2_LENGTH[12:0]
  Description:
    Bits 12 to 0 of the field length.
  Min:
    0x0
  Max:
    0x1fff
  Default:
    0x0

#### PKT_FIELD_2_CONFIG

- Group: 0x12
- Index: 0x13

- Summary: General data processing and packet configuration bits for Field 2.
- Purpose:
  - Partitioning of the Payload into separate fields is provided to support features such as variable length packets and field-specific data processing (e.g., Manchester encoding, data whitening, etc). This property provides configuration bits for field-specific processing on Field 2.
  - The configuration bits in this property are common to both TX and RX modes dependent on PKT_CONFIG1:PH_FIELD_SPLIT; however, this property is only applicable when automatic Packet Handling is enabled (e.g., when using the TX FIFO as the modulation source in TX mode, or when PKT_CONFIG1:PH_RX_DISABLE is cleared in RX mode).
- Default: 0x00
- Register View:

| PKT_FIELD_2_CONFIG
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x13 | 0 | 0 | 0 | 4FSK | 0 | 0 | WHITEN | MANCH
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0

- Field Details:

  ###### PKT_FIELD_2_CONFIG

  4FSK
  Description:
    - The chip supports field-specific configuration of (G)FSK modulation modes, i.e., 2(G)FSK across certain fields and 4(G)FSK across other fields. In such a case, the Modem must be configured for 4(G)FSK operation across the entire packet (by setting the MODEM_MOD_TYPE property), and the Packet Handler is then configured on a field-by-field basis to process the data stream from the FIFO as bit pairs (for 4(G)FSK) or single bits (for 2(G)FSK).
    - When 4(G)FSK is enabled across a field, the PH pulls two bits from the FIFO and sends them to the TX Modulator to be transmitted as one-of-four deviation levels.
    - When 4(G)FSK is disabled across a field, the PH pulls one bit from the FIFO and replaces it with the appropriate two bits that map to the outer two deviation levels. Although the TX Modulator remains configured for four levels of deviation (by the MODEM_MOD_TYPE property), using only the outer two deviation levels effectively results in 2(G)FSK modulation across that field.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Disable 4(G)FSK data processing on this field. |
    ENUM_1 | 1 | Enable 4(G)FSK data processing on this field. |

  WHITEN
  Description:
    - The data whitening/de-whitening function is only available when automatic Packet Handling is enabled (e.g., when using the TX FIFO as the modulation source in TX mode, or when the PH_RX_DISABLE bit in the PKT_CONFIG1 property is cleared in RX mode).
    - In RX mode, the data de-whitening function is performed only on bits stored in the RX FIFO; received data bits observed in real-time (on a GPIO pin) are output prior to de-whitening.
    - Enabling data whitening does not affect the over-the-air data rate.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Disable data whitening/de-whitening on this field. |
    ENUM_1 | 1 | Enable data whitening/de-whitening on this field. |

  MANCH
  Description:
    - Manchester encoding operates by replacing each bit with a two-chip pattern (e.g., each '0' bit with a '10' pattern and each '1' bit with a '01' bit pattern, or vice versa). The desired encoding polarity is selected by PKT_CONFIG1:MANCH_POL.
    - Enabling Manchester encoding in one or more fields does not affect the over-the-air data rate; each bit/chip within the entire packet is transmitted at the same data rate (specified by the MODEM_DATA_RATE_X properties). Manchester encoding simply affects the number of bits/chips that are sent (e.g., by replacing one bit with two chips).
    - In RX mode, the Manchester decoding function is performed only on bits stored in the RX FIFO; received data bits observed in real-time (on a GPIO pin) are output prior to decoding.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Disable manchester encoding/decoding on this field. |
    ENUM_1 | 1 | Enable manchester encoding/decoding on this field. |

#### PKT_FIELD_2_CRC_CONFIG

- Group: 0x12
- Index: 0x14

- Summary: Configuration of CRC control bits across Field 2.
- Purpose:
  - This property is use to control the calculation, transmission, and checking of CRC across Field 2.
- Default: 0x00
- Register View:

| PKT_FIELD_2_CRC_CONFIG
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x14 | 0 | 0 | SEND_CRC | SEND_ALT_CRC | 0 | 0 | CRC_ENABLE | ALT_CRC_ENABLE
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0

- Field Details:

  ###### PKT_FIELD_2_CRC_CONFIG

  SEND_CRC
  Description:
    This bit is applicable only in TX mode, and determines whether the accumulated CRC checksum will be transmitted at the end of this field.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Do not Transmit CRC at the end of this field. |
    ENUM_1 | 1 | Transmit CRC at the end of this field. |

  SEND_ALT_CRC
  Description:
    This bit is applicable only in TX mode, and determines whether the accumulated ALT CRC checksum will be transmitted at the end of this field.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Do not Transmit ALT CRC at the end of this field. |
    ENUM_1 | 1 | Transmit ALT CRC at the end of this field. |

  CRC_ENABLE
  Description:
    - This bit is applicable in both TX and RX modes, and enables CRC checksum calculation over this field. Note: enabling CRC calculation across a field does not automatically result in transmission/checking of the CRC checksum at the end of the field.
    - If in RX mode and PKT_CONFIG1:PH_FIELD_SPLIT is set, this bit is ignored and the CRC_ENABLE functionality is obtained from the appropriate PKT_RX_FIELD_X_CRC_CONFIG property.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Disable CRC calculation over this field. |
    ENUM_1 | 1 | Enable CRC calculation over this field. |

  ALT_CRC_ENABLE
  Description:
    - This bit is applicable in both TX and RX modes, and enables ALT CRC checksum calculation over this field. Note: enabling ALT CRC calculation across a field does not automatically result in transmission/checking of the ALT CRC checksum at the end of the field.
    - If in RX mode and PKT_CONFIG1:PH_FIELD_SPLIT is set, this bit is ignored and the ALT_CRC_ENABLE functionality is obtained from the appropriate PKT_RX_FIELD_X_CRC_CONFIG property.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Disable ALT CRC calculation over this field. |
    ENUM_1 | 1 | Enable ALT CRC calculation over this field. |

#### PKT_FIELD_3_LENGTH

- Group: 0x12
- Indexes: 0x15 ... 0x16

- Summary: Unsigned 13-bit Field 3 length value.
- Purpose:
  - The PKT_FIELD_3_LENGTH properties specify the length of Field 3 in bytes. The field length is an unsigned 13-bit value.
  - Please refer to the text description for PKT_FIELD_1_LENGTH for more details regarding field length configuration.
- Defaults: 0x00,0x00
- Register View:

| PKT_FIELD_3_LENGTH
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x15 | 0 | 0 | 0 | FIELD_3_LENGTH[12:8]
0x16 | FIELD_3_LENGTH[7:0]
| Defaults
0x15 | 0x0 | 0x0 | 0x0 | 0x0
0x16 | 0x0

- Field Details:

  ###### PKT_FIELD_3_LENGTH

  FIELD_3_LENGTH[12:0]
  Description:
    Bits 12 to 0 of the field length.
  Min:
    0x0
  Max:
    0x1fff
  Default:
    0x0

#### PKT_FIELD_3_CONFIG

- Group: 0x12
- Index: 0x17

- Summary: General data processing and packet configuration bits for Field 3.
- Purpose:
  - Partitioning of the Payload into separate fields is provided to support features such as variable length packets and field-specific data processing (e.g., Manchester encoding, data whitening, etc). This property provides configuration bits for field-specific processing on Field 3.
  - The configuration bits in this property are common to both TX and RX modes dependent on PKT_CONFIG1:PH_FIELD_SPLIT; however, this property is only applicable when automatic Packet Handling is enabled (e.g., when using the TX FIFO as the modulation source in TX mode, or when PKT_CONFIG1:PH_RX_DISABLE is cleared in RX mode).
- Default: 0x00
- Register View:

| PKT_FIELD_3_CONFIG
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x17 | 0 | 0 | 0 | 4FSK | 0 | 0 | WHITEN | MANCH
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0

- Field Details:

  ###### PKT_FIELD_3_CONFIG

  4FSK
  Description:
    - The chip supports field-specific configuration of (G)FSK modulation modes, i.e., 2(G)FSK across certain fields and 4(G)FSK across other fields. In such a case, the Modem must be configured for 4(G)FSK operation across the entire packet (by setting the MODEM_MOD_TYPE property), and the Packet Handler is then configured on a field-by-field basis to process the data stream from the FIFO as bit pairs (for 4(G)FSK) or single bits (for 2(G)FSK).
    - When 4(G)FSK is enabled across a field, the PH pulls two bits from the FIFO and sends them to the TX Modulator to be transmitted as one-of-four deviation levels.
    - When 4(G)FSK is disabled across a field, the PH pulls one bit from the FIFO and replaces it with the appropriate two bits that map to the outer two deviation levels. Although the TX Modulator remains configured for four levels of deviation (by the MODEM_MOD_TYPE property), using only the outer two deviation levels effectively results in 2(G)FSK modulation across that field.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Disable 4(G)FSK data processing on this field. |
    ENUM_1 | 1 | Enable 4(G)FSK data processing on this field. |

  WHITEN
  Description:
    - The data whitening/de-whitening function is only available when automatic Packet Handling is enabled (e.g., when using the TX FIFO as the modulation source in TX mode, or when the PH_RX_DISABLE bit in the PKT_CONFIG1 property is cleared in RX mode).
    - In RX mode, the data de-whitening function is performed only on bits stored in the RX FIFO; received data bits observed in real-time (on a GPIO pin) are output prior to de-whitening.
    - Enabling data whitening does not affect the over-the-air data rate.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Disable data whitening/de-whitening on this field. |
    ENUM_1 | 1 | Enable data whitening/de-whitening on this field. |

  MANCH
  Description:
    - Manchester encoding operates by replacing each bit with a two-chip pattern (e.g., each '0' bit with a '10' pattern and each '1' bit with a '01' bit pattern, or vice versa). The desired encoding polarity is selected by PKT_CONFIG1:MANCH_POL.
    - Enabling Manchester encoding in one or more fields does not affect the over-the-air data rate; each bit/chip within the entire packet is transmitted at the same data rate (specified by the MODEM_DATA_RATE_X properties). Manchester encoding simply affects the number of bits/chips that are sent (e.g., by replacing one bit with two chips).
    - In RX mode, the Manchester decoding function is performed only on bits stored in the RX FIFO; received data bits observed in real-time (on a GPIO pin) are output prior to decoding.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Disable manchester encoding/decoding on this field. |
    ENUM_1 | 1 | Enable manchester encoding/decoding on this field. |

#### PKT_FIELD_3_CRC_CONFIG

- Group: 0x12
- Index: 0x18

- Summary: Configuration of CRC control bits across Field 3.
- Purpose:
  - This property is use to control the calculation, transmission, and checking of CRC across Field 3.
- Default: 0x00
- Register View:

| PKT_FIELD_3_CRC_CONFIG
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x18 | 0 | 0 | SEND_CRC | SEND_ALT_CRC | 0 | 0 | CRC_ENABLE | ALT_CRC_ENABLE
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0

- Field Details:

  ###### PKT_FIELD_3_CRC_CONFIG

  SEND_CRC
  Description:
    This bit is applicable only in TX mode, and determines whether the accumulated CRC checksum will be transmitted at the end of this field.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Do not Transmit CRC at the end of this field. |
    ENUM_1 | 1 | Transmit CRC at the end of this field. |

  SEND_ALT_CRC
  Description:
    This bit is applicable only in TX mode, and determines whether the accumulated ALT CRC checksum will be transmitted at the end of this field.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Do not Transmit ALT CRC at the end of this field. |
    ENUM_1 | 1 | Transmit ALT CRC at the end of this field. |

  CRC_ENABLE
  Description:
    - This bit is applicable in both TX and RX modes, and enables CRC checksum calculation over this field. Note: enabling CRC calculation across a field does not automatically result in transmission/checking of the CRC checksum at the end of the field.
    - If in RX mode and PKT_CONFIG1:PH_FIELD_SPLIT is set, this bit is ignored and the CRC_ENABLE functionality is obtained from the appropriate PKT_RX_FIELD_X_CRC_CONFIG property.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Disable CRC calculation over this field. |
    ENUM_1 | 1 | Enable CRC calculation over this field. |

  ALT_CRC_ENABLE
  Description:
    - This bit is applicable in both TX and RX modes, and enables ALT CRC checksum calculation over this field. Note: enabling ALT CRC calculation across a field does not automatically result in transmission/checking of the ALT CRC checksum at the end of the field.
    - If in RX mode and PKT_CONFIG1:PH_FIELD_SPLIT is set, this bit is ignored and the ALT_CRC_ENABLE functionality is obtained from the appropriate PKT_RX_FIELD_X_CRC_CONFIG property.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Disable ALT CRC calculation over this field. |
    ENUM_1 | 1 | Enable ALT CRC calculation over this field. |

#### PKT_FIELD_4_LENGTH

- Group: 0x12
- Indexes: 0x19 ... 0x1a

- Summary: Unsigned 13-bit Field 4 length value.
- Purpose:
  - The PKT_FIELD_4_LENGTH properties specify the length of Field 4 in bytes. The field length is an unsigned 13-bit value.
  - Please refer to the text description for PKT_FIELD_1_LENGTH for more details regarding field length configuration.
- Defaults: 0x00,0x00
- Register View:

| PKT_FIELD_4_LENGTH
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x19 | 0 | 0 | 0 | FIELD_4_LENGTH[12:8]
0x1a | FIELD_4_LENGTH[7:0]
| Defaults
0x19 | 0x0 | 0x0 | 0x0 | 0x0
0x1a | 0x0

- Field Details:

  ###### PKT_FIELD_4_LENGTH

  FIELD_4_LENGTH[12:0]
  Description:
    Bits 12 to 0 of the field length.
  Min:
    0x0
  Max:
    0x1fff
  Default:
    0x0

#### PKT_FIELD_4_CONFIG

- Group: 0x12
- Index: 0x1b

- Summary: General data processing and packet configuration bits for Field 4.
- Purpose:
  - Partitioning of the Payload into separate fields is provided to support features such as variable length packets and field-specific data processing (e.g., Manchester encoding, data whitening, etc). This property provides configuration bits for field-specific processing on Field 4.
  - The configuration bits in this property are common to both TX and RX modes dependent on PKT_CONFIG1:PH_FIELD_SPLIT; however, this property is only applicable when automatic Packet Handling is enabled (e.g., when using the TX FIFO as the modulation source in TX mode, or when PKT_CONFIG1:PH_RX_DISABLE is cleared in RX mode).
- Default: 0x00
- Register View:

| PKT_FIELD_4_CONFIG
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x1b | 0 | 0 | 0 | 4FSK | 0 | 0 | WHITEN | MANCH
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0

- Field Details:

  ###### PKT_FIELD_4_CONFIG

  4FSK
  Description:
    - The chip supports field-specific configuration of (G)FSK modulation modes, i.e., 2(G)FSK across certain fields and 4(G)FSK across other fields. In such a case, the Modem must be configured for 4(G)FSK operation across the entire packet (by setting the MODEM_MOD_TYPE property), and the Packet Handler is then configured on a field-by-field basis to process the data stream from the FIFO as bit pairs (for 4(G)FSK) or single bits (for 2(G)FSK).
    - When 4(G)FSK is enabled across a field, the PH pulls two bits from the FIFO and sends them to the TX Modulator to be transmitted as one-of-four deviation levels.
    - When 4(G)FSK is disabled across a field, the PH pulls one bit from the FIFO and replaces it with the appropriate two bits that map to the outer two deviation levels. Although the TX Modulator remains configured for four levels of deviation (by the MODEM_MOD_TYPE property), using only the outer two deviation levels effectively results in 2(G)FSK modulation across that field.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Disable 4(G)FSK data processing on this field. |
    ENUM_1 | 1 | Enable 4(G)FSK data processing on this field. |

  WHITEN
  Description:
    - The data whitening/de-whitening function is only available when automatic Packet Handling is enabled (e.g., when using the TX FIFO as the modulation source in TX mode, or when the PH_RX_DISABLE bit in the PKT_CONFIG1 property is cleared in RX mode).
    - In RX mode, the data de-whitening function is performed only on bits stored in the RX FIFO; received data bits observed in real-time (on a GPIO pin) are output prior to de-whitening.
    - Enabling data whitening does not affect the over-the-air data rate.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Disable data whitening/de-whitening on this field. |
    ENUM_1 | 1 | Enable data whitening/de-whitening on this field. |

  MANCH
  Description:
    - Manchester encoding operates by replacing each bit with a two-chip pattern (e.g., each '0' bit with a '10' pattern and each '1' bit with a '01' bit pattern, or vice versa). The desired encoding polarity is selected by PKT_CONFIG1:MANCH_POL.
    - Enabling Manchester encoding in one or more fields does not affect the over-the-air data rate; each bit/chip within the entire packet is transmitted at the same data rate (specified by the MODEM_DATA_RATE_X properties). Manchester encoding simply affects the number of bits/chips that are sent (e.g., by replacing one bit with two chips).
    - In RX mode, the Manchester decoding function is performed only on bits stored in the RX FIFO; received data bits observed in real-time (on a GPIO pin) are output prior to decoding.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Disable manchester encoding/decoding on this field. |
    ENUM_1 | 1 | Enable manchester encoding/decoding on this field. |

#### PKT_FIELD_4_CRC_CONFIG

- Group: 0x12
- Index: 0x1c

- Summary: Configuration of CRC control bits across Field 4.
- Purpose:
  - This property is use to control the calculation, transmission, and checking of CRC across Field 4.
- Default: 0x00
- Register View:

| PKT_FIELD_4_CRC_CONFIG
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x1c | 0 | 0 | SEND_CRC | SEND_ALT_CRC | 0 | 0 | CRC_ENABLE | ALT_CRC_ENABLE
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0

- Field Details:

  ###### PKT_FIELD_4_CRC_CONFIG

  SEND_CRC
  Description:
    This bit is applicable only in TX mode, and determines whether the accumulated CRC checksum will be transmitted at the end of this field.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Do not Transmit CRC at the end of this field. |
    ENUM_1 | 1 | Transmit CRC at the end of this field. |

  SEND_ALT_CRC
  Description:
    This bit is applicable only in TX mode, and determines whether the accumulated ALT CRC checksum will be transmitted at the end of this field.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Do not Transmit ALT CRC at the end of this field. |
    ENUM_1 | 1 | Transmit ALT CRC at the end of this field. |

  CRC_ENABLE
  Description:
    - This bit is applicable in both TX and RX modes, and enables CRC checksum calculation over this field. Note: enabling CRC calculation across a field does not automatically result in transmission/checking of the CRC checksum at the end of the field.
    - If in RX mode and PKT_CONFIG1:PH_FIELD_SPLIT is set, this bit is ignored and the CRC_ENABLE functionality is obtained from the appropriate PKT_RX_FIELD_X_CRC_CONFIG property.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Disable CRC calculation over this field. |
    ENUM_1 | 1 | Enable CRC calculation over this field. |

  ALT_CRC_ENABLE
  Description:
    - This bit is applicable in both TX and RX modes, and enables ALT CRC checksum calculation over this field. Note: enabling ALT CRC calculation across a field does not automatically result in transmission/checking of the ALT CRC checksum at the end of the field.
    - If in RX mode and PKT_CONFIG1:PH_FIELD_SPLIT is set, this bit is ignored and the ALT_CRC_ENABLE functionality is obtained from the appropriate PKT_RX_FIELD_X_CRC_CONFIG property.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Disable ALT CRC calculation over this field. |
    ENUM_1 | 1 | Enable ALT CRC calculation over this field. |

#### PKT_FIELD_5_LENGTH

- Group: 0x12
- Indexes: 0x1d ... 0x1e

- Summary: Unsigned 13-bit Field 5 length value.
- Purpose:
  - The PKT_FIELD_5_LENGTH properties specify the length of Field 5 in bytes. The field length is an unsigned 13-bit value.
  - Please refer to the text description for PKT_FIELD_1_LENGTH for more details regarding field length configuration.
- Defaults: 0x00,0x00
- Register View:

| PKT_FIELD_5_LENGTH
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x1d | 0 | 0 | 0 | FIELD_5_LENGTH[12:8]
0x1e | FIELD_5_LENGTH[7:0]
| Defaults
0x1d | 0x0 | 0x0 | 0x0 | 0x0
0x1e | 0x0

- Field Details:

  ###### PKT_FIELD_5_LENGTH

  FIELD_5_LENGTH[12:0]
  Description:
    Bits 12 to 0 of the field length.
  Min:
    0x0
  Max:
    0x1fff
  Default:
    0x0

#### PKT_FIELD_5_CONFIG

- Group: 0x12
- Index: 0x1f

- Summary: General data processing and packet configuration bits for Field 5.
- Purpose:
  - Partitioning of the Payload into separate fields is provided to support features such as variable length packets and field-specific data processing (e.g., Manchester encoding, data whitening, etc). This property provides configuration bits for field-specific processing on Field 5.
  - The configuration bits in this property are common to both TX and RX modes dependent on PKT_CONFIG1:PH_FIELD_SPLIT; however, this property is only applicable when automatic Packet Handling is enabled (e.g., when using the TX FIFO as the modulation source in TX mode, or when PKT_CONFIG1:PH_RX_DISABLE is cleared in RX mode).
- Default: 0x00
- Register View:

| PKT_FIELD_5_CONFIG
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x1f | 0 | 0 | 0 | 4FSK | 0 | 0 | WHITEN | MANCH
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0

- Field Details:

  ###### PKT_FIELD_5_CONFIG

  4FSK
  Description:
    - The chip supports field-specific configuration of (G)FSK modulation modes, i.e., 2(G)FSK across certain fields and 4(G)FSK across other fields. In such a case, the Modem must be configured for 4(G)FSK operation across the entire packet (by setting the MODEM_MOD_TYPE property), and the Packet Handler is then configured on a field-by-field basis to process the data stream from the FIFO as bit pairs (for 4(G)FSK) or single bits (for 2(G)FSK).
    - When 4(G)FSK is enabled across a field, the PH pulls two bits from the FIFO and sends them to the TX Modulator to be transmitted as one-of-four deviation levels.
    - When 4(G)FSK is disabled across a field, the PH pulls one bit from the FIFO and replaces it with the appropriate two bits that map to the outer two deviation levels. Although the TX Modulator remains configured for four levels of deviation (by the MODEM_MOD_TYPE property), using only the outer two deviation levels effectively results in 2(G)FSK modulation across that field.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Disable 4(G)FSK data processing on this field. |
    ENUM_1 | 1 | Enable 4(G)FSK data processing on this field. |

  WHITEN
  Description:
    - The data whitening/de-whitening function is only available when automatic Packet Handling is enabled (e.g., when using the TX FIFO as the modulation source in TX mode, or when the PH_RX_DISABLE bit in the PKT_CONFIG1 property is cleared in RX mode).
    - In RX mode, the data de-whitening function is performed only on bits stored in the RX FIFO; received data bits observed in real-time (on a GPIO pin) are output prior to de-whitening.
    - Enabling data whitening does not affect the over-the-air data rate.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Disable data whitening/de-whitening on this field. |
    ENUM_1 | 1 | Enable data whitening/de-whitening on this field. |

  MANCH
  Description:
    - Manchester encoding operates by replacing each bit with a two-chip pattern (e.g., each '0' bit with a '10' pattern and each '1' bit with a '01' bit pattern, or vice versa). The desired encoding polarity is selected by PKT_CONFIG1:MANCH_POL.
    - Enabling Manchester encoding in one or more fields does not affect the over-the-air data rate; each bit/chip within the entire packet is transmitted at the same data rate (specified by the MODEM_DATA_RATE_X properties). Manchester encoding simply affects the number of bits/chips that are sent (e.g., by replacing one bit with two chips).
    - In RX mode, the Manchester decoding function is performed only on bits stored in the RX FIFO; received data bits observed in real-time (on a GPIO pin) are output prior to decoding.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Disable manchester encoding/decoding on this field. |
    ENUM_1 | 1 | Enable manchester encoding/decoding on this field. |

#### PKT_FIELD_5_CRC_CONFIG

- Group: 0x12
- Index: 0x20

- Summary: Configuration of CRC control bits across Field 5.
- Purpose:
  - This property is use to control the calculation, transmission, and checking of CRC across Field 5.
- Default: 0x00
- Register View:

| PKT_FIELD_5_CRC_CONFIG
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x20 | 0 | 0 | SEND_CRC | SEND_ALT_CRC | 0 | 0 | CRC_ENABLE | ALT_CRC_ENABLE
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0

- Field Details:

  ###### PKT_FIELD_5_CRC_CONFIG

  SEND_CRC
  Description:
    This bit is applicable only in TX mode, and determines whether the accumulated CRC checksum will be transmitted at the end of this field.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Do not Transmit CRC at the end of this field. |
    ENUM_1 | 1 | Transmit CRC at the end of this field. |

  SEND_ALT_CRC
  Description:
    This bit is applicable only in TX mode, and determines whether the accumulated ALT CRC checksum will be transmitted at the end of this field.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Do not Transmit ALT CRC at the end of this field. |
    ENUM_1 | 1 | Transmit ALT CRC at the end of this field. |

  CRC_ENABLE
  Description:
    - This bit is applicable in both TX and RX modes, and enables CRC checksum calculation over this field. Note: enabling CRC calculation across a field does not automatically result in transmission/checking of the CRC checksum at the end of the field.
    - If in RX mode and PKT_CONFIG1:PH_FIELD_SPLIT is set, this bit is ignored and the CRC_ENABLE functionality is obtained from the appropriate PKT_RX_FIELD_X_CRC_CONFIG property.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Disable CRC calculation over this field. |
    ENUM_1 | 1 | Enable CRC calculation over this field. |

  ALT_CRC_ENABLE
  Description:
    - This bit is applicable in both TX and RX modes, and enables ALT CRC checksum calculation over this field. Note: enabling ALT CRC calculation across a field does not automatically result in transmission/checking of the ALT CRC checksum at the end of the field.
    - If in RX mode and PKT_CONFIG1:PH_FIELD_SPLIT is set, this bit is ignored and the ALT_CRC_ENABLE functionality is obtained from the appropriate PKT_RX_FIELD_X_CRC_CONFIG property.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Disable ALT CRC calculation over this field. |
    ENUM_1 | 1 | Enable ALT CRC calculation over this field. |

### MODEM

#### MODEM_MOD_TYPE

- Group: 0x20
- Index: 0x00

- Summary: Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
- Purpose:
  - This property configures the Modem in the chip for transmission/reception of the following modulation types: OOK, 2(G)FSK, and 4(G)FSK (if supported) modulation.
  - In TX mode, this property is additionally used to select the source of the TX data stream, and whether that TX data stream is from a synchronous or asynchronous source (in Direct mode only).
  - The Modem must be configured for transmission/reception of only one type of modulation throughout the entire packet; it is not possible (for example) to use OOK modulation over certain fields and (G)FSK modulation over other fields. If 4(G)FSK is supported, it is possible to switch between 2(G)FSK and 4(G)FSK on a field-specific basis; however, this is accomplished by configuring the Modem to 4(G)FSK mode for the entire packet and then performing special data processing in the Packet Handler.
- Default: 0x02
- Register View:

| MODEM_MOD_TYPE
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x00 | TX_DIRECT_MODE_TYPE | TX_DIRECT_MODE_GPIO | MOD_SOURCE | MOD_TYPE
| Default
| 0x0 | 0x0 | 0x0 | 0x2

- Field Details:

  ###### MODEM_MOD_TYPE

  TX_DIRECT_MODE_TYPE
  Description:
    - This bit determines whether a real-time TX data stream (applied to the chip on a selected GPIO input pin) is processed in synchronous or asynchronous fashion. This bit is applicable only in TX mode, and only when the MOD_SOURCE field is also set for TX Direct mode.
    - In TX Direct Synchronous mode, the chip controls the transmit data rate by outputting a TX bit clock (GPIO_PIN_CFG=0x10). The host MCU receives the rising edge of the TX clock and responds by outputting one bit for each clock tick; the chip clocks in this new data bit on the subsequent falling edge of the TX clock. All 2-level modulation modes (OOK, 2FSK, 2GFSK) are supported.
    - In TX Direct Asynchronous mode, the host MCU controls the transmit data rate; the RFIC has no knowledge of the rate of the incoming TX data stream but simply oversamples the data as fast as possible to determine the bit edge transitions. OOK and 2FSK are supported, but 2GFSK is not supported in this mode.
    - 4(G)FSK is not supported in either TX Direct Synchronous or TX Direct Asynchronous modes.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    SYNC | 0 | Direct mode operates in synchronous mode, applies to TX only. |
    ASYNC | 1 | Direct mode operates in asynchronous mode, applies to TX only. GFSK is not supported. |

  TX_DIRECT_MODE_GPIO[1:0]
  Description:
    - This field determines which GPIO pin is selected by the Modem as the modulation data source during TX Direct mode. This bit is applicable only in TX mode, and only when the MOD_SOURCE field is also set for TX Direct mode.
    - This field does not automatically configure the selected GPIO pin as a digital input pin; it remains necessary to additionally configure the desired GPIO pin as a CMOS-compatible input pin by setting GPIO_PIN_CFG=0x04.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    GPIO0 | 0 | TX direct mode uses GPIO0 as data source. |
    GPIO1 | 1 | TX direct mode uses GPIO1 as data source. |
    GPIO2 | 2 | TX direct mode uses GPIO2 as data source. |
    GPIO3 | 3 | TX direct mode uses GPIO3 as data source. |

  MOD_SOURCE[1:0]
  Description:
    This bit selects the source of modulation during TX mode. It is applicable only in TX mode.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    PACKET | 0 | The modulation is sourced from the TX FIFO in the packet handler. | revB1A
    DIRECT | 1 | The modulation is sourced in real-time (i.e., TX Direct Mode) from a GPIO pin, as selected by the TX_DIRECT_MODE_GPIO field. | revB1A
    PSEUDO | 2 | The modulation is sourced from the internal pseudo-random generator. | revB1A

  MOD_TYPE[2:0]
  Description:
    - This field configures the Modem for transmission or reception of the desired type of modulation.
    - With the exception of CW mode (a TX-only function), this bit is applicable in both TX and RX modes.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    CW | 0 | CW. |
    OOK | 1 | OOK. |
    2FSK | 2 | 2FSK. |
    2GFSK | 3 | 2GFSK. |
    4FSK | 4 | 4FSK. |
    4GFSK | 5 | 4GFSK. |

#### MODEM_MAP_CONTROL

- Group: 0x20
- Index: 0x01

- Summary: Controls polarity and mapping of transmit and receive bits.
- Purpose:
  - The chip provides the ability to invert the polarity of the TX and RX data bits. This flexibility is provided to ensure compatibility of the chip with other legacy systems that may have a different definition of data bit polarity.
  - The ENMANCH bit signals the chip to adjust the "search for Sync Word" timeout period in the event that the Sync Word is configured for simultaneous Manchester coding and 4(G)FSK coding. This configuration is currently not supported and thus the setting of the ENMANCH bit is internally ignored.
- Default: 0x80
- Register View:

| MODEM_MAP_CONTROL
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x01 | ENMANCH | 0 | ENINV_TXBIT | ENINV_FD | 0 | 0 | 0 | 0
| Default
| 0x1 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0

- Field Details:

  ###### MODEM_MAP_CONTROL

  ENMANCH
  Description:
    - When set, signals the chip adjust the "search for Sync Word" timeout period in the event that the Sync Word field is simultaneously configured for Manchester coding and 4(G)FSK coding.
    - This configuration is currently not supported; the setting of the ENMANCH bit is internally ignored.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Do not adjust Sync Word timeout for Manchester coding. |
    ENUM_1 | 1 | Adjust Sync Word timeout for Manchester coding. |

  ENINV_TXBIT
  Description:
    - Enables/disables inversion of the entire TX data bit stream, occurring at the circuit point just prior to injection into the Modulator. The inversion of the data bit stream applies to all three possible sources of TX modulation (FIFO, Direct from GPIO pin, or PN generator).
    - In OOK mode, this has the obvious effect of changing a TX-ON bit to a TX-OFF bit, and vice versa.
    - In 2(G)FSK mode, this has the obvious effect of changing a +Fdev bit to a -Fdev bit, and vice versa.
    - The default setting of this bit (i.e., non-inversion) results in a '1' TX data bit mapping to the +Fdev deviation level.
    - In 4(G)FSK mode, the resulting effect depends upon the selected symbol mapping; that is, inverting a pair of TX data bits (that previously mapped to one 4(G)FSK deviation level) may not result in transmission of the opposite deviation level.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Do not invert TX data bits. |
    ENUM_1 | 1 | Invert TX data bits. |

  ENINV_FD
  Description:
    - Enables/disables inversion of the polarity of frequency deviation in TX 2(G)FSK or 4(G)FSK mode. This bit has no effect in TX OOK mode or RX mode.
    - In 2(G)FSK mode, this bit has the same effect as inverting the TX data bit stream through the ENINV_TXBIT.
    - In 4(G)FSK mode, this bit results in inversion of the modulation waveform; this may differ from inverting the TX data bit stream (through the ENINV_TXBIT), depending upon the selected symbol mapping.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Do not invert the polarity of the frequency deviation. |
    ENUM_1 | 1 | Invert the polarity of the frequency deviation. |

#### MODEM_DSM_CTRL

- Group: 0x20
- Index: 0x02

- Summary: Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
- Purpose:
  - This property provides several miscellaneous control bits for DSM functions such as clock source, dithering, and modulator order. These control bits are primarily intended for engineering diagnostic purposes, and Silicon Labs does not recommend altering the values suggested by the WDS Calculator (with the possible exception of the DSM_LSB bit).
  - Some DSM Fractional-N PLL Synthesizers may exhibit discrete tones or pattern-related spurs for certain fractional values of the frequency control word. A common method of breaking up these tones or patterns is to add a noise-like (pseudo-random) bit sequence to the LSB of the frequency control word; this is known as "dithering". The chip provides for enabling dithering and selection of two different types of dithering; however, Silicon Labs has not observed a need to enable this functionality and recommends that dithering remain disabled.
  - The fractional frequency values that commonly give rise to pattern-related spurs in many DSMs are exact powers-of-2 (e.g., 0.5, 0.25, 0.125, etc). In addition to dithering, another common method of eliminating pattern-related spurs is to simply ensure that the frequency control word is always an odd value, and thus can never be an exact power-of-2. The chip provides for internally forcing the LSB of the frequency control word to always be set high, thus resulting in an odd value (regardless of the frequency control word programmed by the user). This functionality is controlled by the DSM_LSB bit. The downside of obtaining only odd values of the frequency control word is that the frequency tuning resolution is effectively degraded by a factor of 2x (e.g., 57.22 Hz tuning resolution in the 915M band instead of 28.61 Hz tuning resolution). Silicon Labs is not aware of a need for enabling this functionality as no significant pattern-related spurs have been observed; however, the WDS Calculator currently suggests setting this bit and absent a need for extremely fine frequency tuning resolution, Silicon Labs recommends not altering this setting.
- Default: 0x07
- Register View:

| MODEM_DSM_CTRL
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x02 | DSMCLK_SEL | DSM_MODE | DSMDT_EN | DSMDTTP | DSM_RST | DSM_LSB | DSM_ORDER
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x1 | 0x3

- Field Details:

  ###### MODEM_DSM_CTRL

  DSMCLK_SEL
  Description:
    Selects the clock source for the DSM.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | DSM clock comes from 30 MHz PLL feedback clock. |
    ENUM_1 | 1 | DSM clock comes from 30 MHz crystal clock. |

  DSM_MODE
  Description:
    Selects the type of DSM used in the PLL Synthesizer.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | MASH 1-1-1 DSM will be selected. |
    ENUM_1 | 1 | A single loop DSM will be selected. |

  DSMDT_EN
  Description:
    - Selects whether dithering is enabled in the DSM.
    - When enabled, the type of dithering is controlled by the DSMDTTP bit.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | DSM dithering is disabled. |
    ENUM_1 | 1 | DSM dithering is enabled. |

  DSMDTTP
  Description:
    - Selects the type of dithering added to the DSM.
    - The bits of the pseudo-random dithering sequence may be viewed as +1/0 bits or as +1/-1 bits; the latter method is DC-balanced while the former method effectively adds ½ LSB of frequency offset to the frequency control word.
    - This bit has no effect unless dithering is enabled by setting the DSMDT_EN bit.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | +1/0 is added to DSM input LSB. |
    ENUM_1 | 1 | +1/-1 is added to DSM input LSB. |

  DSM_RST
  Description:
    Provides a method of resetting the DSM.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENABLE | 0 | DSM is in operational state (reset is not active). |
    RESET | 1 | DSM will be in reset state until it is clear. |

  DSM_LSB
  Description:
    - Selects whether the LSB of the DSM frequency control word is always forced high, resulting in odd values of the frequency control word.
    - If enabled, the effective frequency tuning resolution is degraded.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | The LSB of the DSM input is unaltered |
    ENUM_1 | 1 | The LSB of the DSM input is internally forced high (i.e., the frequency control word is forced to always be an odd value). |

  DSM_ORDER[1:0]
  Description:
    Selects the order of the DSM.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | 0 order, with 0 output continuously. |
    ENUM_1 | 1 | 1st order, with no noise shaping. |
    ENUM_2 | 2 | 2nd order, MASH 1-1. |
    ENUM_3 | 3 | 3rd order, MASH 1-1-1. |

#### MODEM_DATA_RATE

- Group: 0x20
- Indexes: 0x03 ... 0x05

- Summary: Unsigned 24-bit value used to determine the TX data rate
- Purpose:
  - The TX data rate is derived from an internal clock signal from the TX Numerically Controlled Oscillator (NCO).
  - The TX NCO provides a clock signal at a configurable multiple of the final desired TX data rate; the exact oversampling ratio depends upon the modulation mode (OOK / FSK / GFSK) and selected data rate.
  - The value of the MODEM_DATA_RATE property works in conjunction with the MODEM_TX_NCO_MODE property and TXOSR field to provide the desired data rate. As a result, the units of the MODEM_DATA_RATE property are not fixed. However, as a general guideline, the value of the MODEM_DATA_RATE property will be either 1x, 2x, 4x, 10x, 20x, or 40x the desired data rate (in bits per second).
  - Please refer to the text description for MODEM_TX_NCO_MODE for more details regarding the TX Numerically Controlled Oscillator (NCO), and the roles of the MODEM_TX_NCO_MODE and MODEM_DATA_RATE properties in setting the TX data rate.
  - The default values of the MODEM_DATA_RATE and MODEM_TX_NCO_MODE properties result in a data rate of 100 kbps.
- Defaults: 0x0f,0x42,0x40
- Register View:

| MODEM_DATA_RATE
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x03 | DATA_RATE[23:16]
0x04 | DATA_RATE[15:8]
0x05 | DATA_RATE[7:0]
| Defaults
0x03 | 0xf
0x04 | 0x42
0x05 | 0x40

- Field Details:

  ###### MODEM_DATA_RATE

  DATA_RATE[23:0]
  Description:
    Data rate
  Min:
    0x0
  Max:
    0xffffff
  Default:
    0xf4240

#### MODEM_TX_NCO_MODE

- Group: 0x20
- Indexes: 0x06 ... 0x09

- Summary: TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
- Purpose:
  - The chip contains a TX Numerically Controlled Oscillator (NCO) for the purpose of creating an internal clock signal at a configurable multiple of the desired data rate.
  - For 2GFSK and 4GFSK modes of operation, the oversampling ratio is configured by the TXOSR field and is selectable between 10x, 20x, and 40x. The oversampled NCO clock signal is used to synthesize the individual deviation steps of the Gaussian filtered modulation waveform, and thus necessarily must be at a higher multiple of the desired data rate.
  - For OOK, 2FSK, and 4FSK modes of operation, there is no inherent need to create an oversampled clock; the only required signal is the TXCLK signal at the desired data rate. However, it is convenient to use the same NCO clock circuitry and thus the TXCLK data rate signal is obtained by first generating an NCO clock signal at an oversampling ratio of 10x and then subsequently dividing-by-10.
  - The NCO is comprised of an accumulator that is clocked by the crystal oscillator frequency (Fxtal), has a maximum count limit (modulus) equal to the value of the MODEM_TX_NCO_MODE property, and on each clock tick accumulates a value set by the MODEM_DATA_RATE property. Thus the accumulator wraps over its maximum count limit at a rate given by the formula:

    The overflow pulses generated by the accumulator are the TX NCO clock signal.
  - The actual TX data rate (and frequency of the TXCLK signal) is given by the formula:

  - In 2GFSK or 4GFSK mode, the TXOSR value may be increased to 20x or 40x (from its nominal value of 10x). This increase in oversampling rate results in a Gaussian filtered modulation waveform with finer deviation steps, and thus reduces the modulation sideband artifacts. The 20x or 40x oversampling rate options are only available at lower data rates; the WDS Calculator will automatically suggest the highest possible value of TXOSR for the selected data rate. If an oversampling rate of 20x or 40x is selected, the value entered for the MODEM_DATA_RATE property should also be scaled by 2x or 4x (respectively), in order to maintain the desired TX data rate.
  - The value entered for the MODEM_TX_NCO_MODE property is recommended to be either Fxtal or Fxtal/10 (e.g., 0x1C9C380 = 30M decimal, or 0x02DC6C0 =3M decimal, assuming the crystal frequency is 30 MHz). The WDS Calculator will automatically suggest the appropriate value as a function of data rate (Fxtal for DR > 200kbps, and Fxtal/10 for DR ≥ 200kbps). This provides a different adjustment resolution of the data rate.
  - The MODEM_TX_NCO_MODE and MODEM_DATA_RATE properties affect only the TX data rate, and have no effect in configuring the data rate in RX mode.
  - The default values of the MODEM_DATA_RATE and MODEM_TX_NCO_MODE properties result in a data rate of 100 kbps.
- Defaults: 0x01,0xc9,0xc3,0x80
- Register View:

| MODEM_TX_NCO_MODE
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x06 | 0 | 0 | 0 | 0 | TXOSR[1:0] | NCOMOD[25:24]
0x07 | NCOMOD[23:16]
0x08 | NCOMOD[15:8]
0x09 | NCOMOD[7:0]
| Defaults
0x06 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x1
0x07 | 0xc9
0x08 | 0xc3
0x09 | 0x80

- Field Details:

  ###### MODEM_TX_NCO_MODE

  TXOSR[1:0]
  Description:
    Sets the oversampling ratio of the internal NCO clock signal used to synthesize the Gaussian filtered modulation waveform. This field is only effective in GFSK mode.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | TX Gaussian filter oversampling ratio is 10x. |
    ENUM_1 | 1 | TX Gaussian filter oversampling ratio is 40x. |
    ENUM_2 | 2 | TX Gaussian filter oversampling ratio is 20x. |
    ENUM_3 | 3 | Reserved, do not use. |

  NCOMOD[25:0]
  Description:
    Sets the modulus (maximum count value) of the accumulator used in the TX NCO clock generation circuitry.
  Min:
    0x0
  Max:
    0x3ffffff
  Default:
    0x1c9c380

#### MODEM_FREQ_DEV

- Group: 0x20
- Indexes: 0x0a ... 0x0c

- Summary: 17-bit unsigned TX frequency deviation word.
- Purpose:
  - The TX frequency deviation is specified by an unsigned 17-bit value. This property defines the frequency deviation value.
  - The units of the MODEM_FREQ_DEV property are in increments of the LSB tuning resolution of the PLL Synthesizer, and are therefore a function of the crystal frequency and output frequency band. The formula for calculating the value of the MODEM_FREQ_DEV property is given by the following equation:

  - The output divider value OUTDIV is configured as a function of the desired frequency band, and is specified in property MODEM_CLKGEN_BAND:BAND.
  - The prescaler divider value NPRESC is configured as a function of the selected synthesizer performance mode and may take on the values NPRESC=2 or NPRESC=4, as specified in property MODEM_CLKGEN_BAND:SY_SEL.
  - For 2(G)FSK mode, the specified value is the peak deviation. For 4(G)FSK mode (if supported), the specified value is the inner deviation (i.e., between channel center frequency and the nearest symbol deviation level).
  - The MODEM_FREQ_DEV property are only used in TX mode.
- Defaults: 0x00,0x06,0xd3
- Register View:

| MODEM_FREQ_DEV
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x0a | 0 | 0 | 0 | 0 | 0 | 0 | 0 | FREQDEV
0x0b | FREQDEV[15:8]
0x0c | FREQDEV[7:0]
| Defaults
0x0a | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0
0x0b | 0x6
0x0c | 0xd3

- Field Details:

  ###### MODEM_FREQ_DEV

  FREQDEV[16:0]
  Default:
    0x6d3

#### MODEM_FREQ_OFFSET

- Group: 0x20
- Indexes: 0x0d ... 0x0e

- Summary: Frequency offset adjustment (a 16-bit signed number).
- Purpose:
  - In TX mode, the MODEM_FREQ_OFFSET value is used to provide an offset to the programmed TX frequency. This allows fine tuning of the TX frequency to account for the variability of the TX reference frequency (e.g., crystal oscillator frequency error).
  - In RX mode when PLL AFC is disabled, the MODEM_FREQ_OFFSET value is used to provide an offset for the programmed RX frequency. This property has no function in RX mode with PLL AFC enabled. Specifically, reading this property does NOT return the estimated AFC frequency error in RX mode; that frequency error value may be obtained from the GET_MODEM_STATUS command.
  - The frequency offset adjustment is a signed 16-bit value. This property defines the frequency offset value.
  - The units of the MODEM_FREQ_OFFSET property are in increments of the LSB tuning resolution of the PLL Synthesizer, and are therefore a function of the crystal reference frequency and output frequency band. The formula for calculating the value of the MODEM_FREQ_OFFSET property is given by the following equation:

  - Please refer to the text description for FREQ_CONTROL_INTE for more details regarding frequency calculation.
  - The absolute range of this property expressed in Hz is a function of the crystal reference frequency and output frequency band, but ranges from +/-937.5 kHz in the 915M band to +/-468.7 kHz in the 450M band, etc.
- Defaults: 0x00,0x00
- Register View:

| MODEM_FREQ_OFFSET
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x0d | FREQOFFSET[15:8]
0x0e | FREQOFFSET[7:0]
| Defaults
0x0d | 0x0
0x0e | 0x0

- Field Details:

  ###### MODEM_FREQ_OFFSET

  FREQOFFSET[15:0]
  Default:
    0x0

#### MODEM_TX_FILTER_COEFF_8

- Group: 0x20
- Index: 0x0f

- Summary: The 8th coefficient of TX spectral shaping filter.
- Purpose:
  - The chip can apply a spectral shaping filter function (e.g., Gaussian filtering) to the TX data stream. The filter is implemented as a 17-tap digital FIR filter, and thus internally there are a total of 17 filter coefficients. However, the values of the tap coefficients are symmetrical: Coeff16=Coeff0, Coeff15=Coeff1, etc. Thus it is only necessary to store a total of 9 coefficients (Coeff8 thru Coeff0); the internal circuitry obtains the remaining coefficients through symmetry.
  - This property specifies the 8th coefficient of the TX shaping filter.
  - The filtering function provided by the default suggested coefficient values is Gaussian filtering with B*T=0.5. Other filtering functions are possible; please contact Silicon Labs for filter coefficient values.
  - The spectral shaping filter function is used only in TX mode, and is not available when using TX Direct Asynchronous mode.
- Default: 0x67
- Register View:

| MODEM_TX_FILTER_COEFF_8
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x0f | TXCOE8
| Default
| 0x67

- Field Details:

  ###### MODEM_TX_FILTER_COEFF_8

  TXCOE8[7:0]
  Default:
    0x67

#### MODEM_TX_FILTER_COEFF_7

- Group: 0x20
- Index: 0x10

- Summary: The 7th coefficient of TX spectral shaping filter.
- Purpose:
  - This property specifies the 7th coefficient of the TX shaping filter.
  - Please refer to the text description for MODEM_TX_FILTER_COEFF_8 for more details regarding TX spectral shaping filtering.
- Default: 0x60
- Register View:

| MODEM_TX_FILTER_COEFF_7
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x10 | TXCOE7
| Default
| 0x60

- Field Details:

  ###### MODEM_TX_FILTER_COEFF_7

  TXCOE7[7:0]
  Default:
    0x60

#### MODEM_TX_FILTER_COEFF_6

- Group: 0x20
- Index: 0x11

- Summary: The 6th coefficient of TX spectral shaping filter.
- Purpose:
  - This property specifies the 6th coefficient of the TX shaping filter.
  - Please refer to the text description for MODEM_TX_FILTER_COEFF_8 for more details regarding TX spectral shaping filtering.
- Default: 0x4d
- Register View:

| MODEM_TX_FILTER_COEFF_6
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x11 | TXCOE6
| Default
| 0x4d

- Field Details:

  ###### MODEM_TX_FILTER_COEFF_6

  TXCOE6[7:0]
  Default:
    0x4d

#### MODEM_TX_FILTER_COEFF_5

- Group: 0x20
- Index: 0x12

- Summary: The 5th coefficient of TX spectral shaping filter.
- Purpose:
  - This property specifies the 5th coefficient of the TX shaping filter.
  - Please refer to the text description for MODEM_TX_FILTER_COEFF_8 for more details regarding TX spectral shaping filtering.
- Default: 0x36
- Register View:

| MODEM_TX_FILTER_COEFF_5
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x12 | TXCOE5
| Default
| 0x36

- Field Details:

  ###### MODEM_TX_FILTER_COEFF_5

  TXCOE5[7:0]
  Default:
    0x36

#### MODEM_TX_FILTER_COEFF_4

- Group: 0x20
- Index: 0x13

- Summary: The 4th coefficient of TX spectral shaping filter.
- Purpose:
  - This property specifies the 4th coefficient of the TX shaping filter.
  - Please refer to the text description for MODEM_TX_FILTER_COEFF_8 for more details regarding TX spectral shaping filtering.
- Default: 0x21
- Register View:

| MODEM_TX_FILTER_COEFF_4
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x13 | TXCOE4
| Default
| 0x21

- Field Details:

  ###### MODEM_TX_FILTER_COEFF_4

  TXCOE4[7:0]
  Default:
    0x21

#### MODEM_TX_FILTER_COEFF_3

- Group: 0x20
- Index: 0x14

- Summary: The 3rd coefficient of TX spectral shaping filter.
- Purpose:
  - This property specifies the 3rd coefficient of the TX shaping filter.
  - Please refer to the text description for MODEM_TX_FILTER_COEFF_8 for more details regarding TX spectral shaping filtering.
- Default: 0x11
- Register View:

| MODEM_TX_FILTER_COEFF_3
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x14 | TXCOE3
| Default
| 0x11

- Field Details:

  ###### MODEM_TX_FILTER_COEFF_3

  TXCOE3[7:0]
  Default:
    0x11

#### MODEM_TX_FILTER_COEFF_2

- Group: 0x20
- Index: 0x15

- Summary: The 2nd coefficient of TX spectral shaping filter.
- Purpose:
  - This property specifies the 2nd coefficient of the TX shaping filter.
  - Please refer to the text description for MODEM_TX_FILTER_COEFF_8 for more details regarding TX spectral shaping filtering.
- Default: 0x08
- Register View:

| MODEM_TX_FILTER_COEFF_2
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x15 | TXCOE2
| Default
| 0x8

- Field Details:

  ###### MODEM_TX_FILTER_COEFF_2

  TXCOE2[7:0]
  Default:
    0x8

#### MODEM_TX_FILTER_COEFF_1

- Group: 0x20
- Index: 0x16

- Summary: The 1st coefficient of TX spectral shaping filter.
- Purpose:
  - This property specifies the 1st coefficient of the TX shaping filter.
  - Please refer to the text description for MODEM_TX_FILTER_COEFF_8 for more details regarding TX spectral shaping filtering.
- Default: 0x03
- Register View:

| MODEM_TX_FILTER_COEFF_1
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x16 | TXCOE1
| Default
| 0x3

- Field Details:

  ###### MODEM_TX_FILTER_COEFF_1

  TXCOE1[7:0]
  Default:
    0x3

#### MODEM_TX_FILTER_COEFF_0

- Group: 0x20
- Index: 0x17

- Summary: The 0th coefficient of TX spectral shaping filter.
- Purpose:
  - This property specifies the 0th coefficient of the TX shaping filter.
  - Please refer to the text description for MODEM_TX_FILTER_COEFF_8 for more details regarding TX spectral shaping filtering.
- Default: 0x01
- Register View:

| MODEM_TX_FILTER_COEFF_0
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x17 | TXCOE0
| Default
| 0x1

- Field Details:

  ###### MODEM_TX_FILTER_COEFF_0

  TXCOE0[7:0]
  Default:
    0x1

#### MODEM_TX_RAMP_DELAY

- Group: 0x20
- Index: 0x18

- Summary: TX ramp-down delay setting.
- Purpose:
  - This property specifies the delay time between transmission of the final symbol of a 2(G)FSK or 4(G)FSK packet and the start of the ramp-down of the PA output power. This configurable delay time ensures that all symbols have been fully transmitted before any reduction in output power occurs.
  - This property applies only in TX mode, and has no effect when using OOK modulation.
  - Units of the delay are in bit/symbol periods. The WDS Calculator suggests an appropriate delay value as a function of the selected modulation type and data rate.
- Default: 0x01
- Register View:

| MODEM_TX_RAMP_DELAY
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x18 | 0 | 0 | 0 | 0 | 0 | RAMP_DLY
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x1

- Field Details:

  ###### MODEM_TX_RAMP_DELAY

  RAMP_DLY[2:0]
  Min:
    0x1
  Max:
    0x7
  Default:
    0x1

#### MODEM_MDM_CTRL

- Group: 0x20
- Index: 0x19

- Summary: MDM control.
- Purpose:
  - Detector selection and PM pattern configuration.
- Default: 0x00
- Register View:

| MODEM_MDM_CTRL
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x19 | PH_SRC_SEL | 0 | 0 | 0 | 0 | 0 | 0 | 0
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0

- Field Details:

  ###### MODEM_MDM_CTRL

  PH_SRC_SEL
  Description:
    BCR/Slicer phase source selection.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Input from phase computer output. |
    ENUM_1 | 1 | Input from detector's output. |

#### MODEM_IF_CONTROL

- Group: 0x20
- Index: 0x1a

- Summary: Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
- Purpose:
  - The chip normally operates with a fixed IF frequency of Fxtal / 64 (e.g., 30.0 MHz / 64 = 468.75 kHz). As a low-side Mixer injection scheme is used, this places the image response at 2*468.75 kHz = 937.5 kHz below the desired channel.
  - It is possible to configure the chip to operate with a lower IF frequency, given by the formula: Fif = Fxtal / (64 * N). As this value is related to the fixed IF frequency by the scale factor 'N', it is referred to as Scaled-IF mode.
  - The scale factor 'N' (and thus also the resulting scaled IF frequency) is automatically suggested by the WDS Calculator as a function of the selected data rate, with lower IF frequencies resulting for lower data rates. The scale factor 'N' is always an integer value, and is usually (but not always) a power of 2 (e.g.,N = 2^M).
  - Scaled-IF mode may be useful when it is desired to position the image response at a frequency other than that normally resulting from the Fixed-IF mode of operation.
  - It is also possible to configure the chip to operate with zero IF frequency, with the benefit that image response frequency is eliminated. However, the RX sensitivity of the chip is somewhat degraded in Zero-IF mode. Also, the RFIC currently does not support reception of an OOK modulated signal in Zero-IF mode.
  - The value of the MODEM_IF_FREQ property should set be in accordance with this property (i.e., to the appropriate value of IF frequency for Fixed-IF or Scaled-IF mode, or to a value of zero for Zero-IF mode).
  - If the ZEROIF bit is set, the FIXIF bit should be cleared.
- Default: 0x08
- Register View:

| MODEM_IF_CONTROL
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x1a | 0 | 0 | 0 | ZEROIF | FIXIF | 0 | 00
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0x1 | 0x0 | 0x0

- Field Details:

  ###### MODEM_IF_CONTROL

  ZEROIF
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    NORMAL | 0 | Non zero-IF mode (i.e., fixed IF or scalable IF mode). |
    ZERO | 1 | Zero-IF mode. |

  FIXIF
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    SCALED | 0 | Scaled-IF mode. |
    FIXED | 1 | Fixed-IF mode. |

#### MODEM_IF_FREQ

- Group: 0x20
- Indexes: 0x1b ... 0x1d

- Summary: the IF frequency setting (an 18-bit signed number).
- Purpose:
  - In RX mode, the chip uses a low-side Mixer injection scheme (except when in Zero-IF mode). The FREQ_CONTROL_INTE and FREQ_CONTROL_FRAC properties define the channel center frequency; in order to receive on this frequency the chip automatically shifts the RX LO frequency downwards by an amount equal to the IF frequency.
  - The MODEM_IF_FREQ property defines the amount by which the RX LO frequency is shifted.
  - This value is a signed 18-bit number. It is summed with the frequency control word for the PLL Synthesizer, and thus must contain a negative value in order to provide a downwards shift in frequency.
  - In Fixed-IF and Scaled-IF mode, the IF frequency is given by the following equation:

    where N=1 for Fixed-IF mode and N=2,3,4... for Scaled-IF mode. Example: in Fixed-IF mode with the nominal crystal frequency of 30.0 MHz, the IF frequency is 30 MHz / 64 = 468.75 kHz. In Scaled-IF mode, the scale factor 'N' is always an integer value and is usually (but not always) a power of 2 (e.g., N = 2M).
  - In Zero-IF mode, the MODEM_IF_FREQ should be set = 0x00000.
  - The units of the MODEM_IF_FREQ property are in increments of the LSB tuning resolution of the PLL Synthesizer, and are therefore a function of the crystal reference frequency and output frequency band. The formula for calculating the positive representation of the MODEM_IF_FREQ property is given by the following equation:

  - The output divider value OUTDIV is configured as a function of the desired frequency band, and is specified in property MODEM_CLKGEN_BAND:BAND.
  - The prescaler divider value NPRESC is configured as a function of the selected synthesizer performance mode and may take on the values NPRESC=2 or NPRESC=4, as specified in property MODEM_CLKGEN_BAND:SY_SEL.
  - Example: for the nominal Fixed-IF mode IF frequency of 468.75kHz when operating in the 915 MHz band (OUTDIV=4) with a 30 MHz crystal, the calculated positive representation of MODEM_IF_FREQ = 16384 = 0x4000.
  - The appropriate value to program into the MODEM_IF_FREQ property is the complement of the calculated positive representation, e.g., 0x3C000.
- Defaults: 0x03,0xc0,0x00
- Register View:

| MODEM_IF_FREQ
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x1b | 0 | 0 | 0 | 0 | 0 | 0 | IF_FREQ[17:16]
0x1c | IF_FREQ[15:8]
0x1d | IF_FREQ[7:0]
| Defaults
0x1b | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x3
0x1c | 0xc0
0x1d | 0x0

- Field Details:

  ###### MODEM_IF_FREQ

  IF_FREQ[17:0]
  Description:
    18-bit IF frequency.
  Default:
    0x3c000

#### MODEM_DECIMATION_CFG1

- Group: 0x20
- Index: 0x1e

- Summary: Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
- Purpose:
  - The RX channel selection bandpass filtering is provided by a digital filter within the RX Modem circuit block. The filter bandwidth is a function of the filter tap coefficients and the clock or sample rate of the filter. That is, using the same set of filter tap coefficients with different filter clock rates will result in different filter bandwidths.
  - The high-speed I/Q data samples from the RX A/D Converters are decimated by a programmable ratio in order to provide the desired sample rate at the input of the digital filter. The decimation ratio is determined by the NDEC0, NDEC1, and NDEC2 values in this property, and thus these values (in conjunction with the filter tap coefficients specified in MODEM_CHFLT_RX1_CHFLT_COEXX) determine the RX channel selection filter bandwidth.
  - The decimation ratio of each decimator circuit block is 2NDEC. In (G)FSK mode the RX data samples pass through two cascaded decimator blocks, and thus the decimation ratio is 2(NDEC1+NDEC2). In OOK mode, the post-demodulated RX data samples pass through an additional decimator block with decimation ratio 2NDEC0. If not in OOK mode, this decimation coefficient should be set NDEC0 = 0.
  - There is an additional polyphase filter and decimator circuit block, located prior to the decimators controlled by the NDEC0/1/2 coefficients. The decimation ratio of this "pre-decimator" block is controlled by bits within the MODEM_DECIMATION_CFG0 property. The total decimation ratio is the product of the ratios of the individual circuit blocks.
- Default: 0x10
- Register View:

| MODEM_DECIMATION_CFG1
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x1e | NDEC2 | NDEC1 | NDEC0 | 0
| Default
| 0x0 | 0x1 | 0x0 | 0x0

- Field Details:

  ###### MODEM_DECIMATION_CFG1

  NDEC2[1:0]
  Description:
    - Decimation coefficient for the second of two cascaded decimation circuit blocks in the CIC filter.
    - Decimating rate is 2NDEC2.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Decimate by 1. |
    ENUM_1 | 1 | Decimate by 2. |
    ENUM_2 | 2 | Decimate by 4. |
    ENUM_3 | 3 | Decimate by 8. |

  NDEC1[1:0]
  Description:
    - Decimation coefficient for the first of two cascading decimation circuit blocks in the CIC filter.
    - Decimating rate is 2NDEC1.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Decimate by 1. |
    ENUM_1 | 1 | Decimate by 2. |
    ENUM_2 | 2 | Decimate by 4. |
    ENUM_3 | 3 | Decimate by 8. |

  NDEC0[2:0]
  Description:
    - Decimation coefficient for the additional decimation circuit block used in the RX Modem during OOK reception.
    - Decimating rate is 2NDEC0.
    - NDEC0 should be set to 0 when not in OOK mode.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Decimate by 1. |
    ENUM_1 | 1 | Decimate by 2. |
    ENUM_2 | 2 | Decimate by 4. |
    ENUM_3 | 3 | Decimate by 8. |
    ENUM_4 | 4 | Decimate by 16. |
    ENUM_5 | 5 | Decimate by 32. |
    ENUM_6 | 6 | Decimate by 64. |
    ENUM_7 | 7 | Decimate by 128. |

#### MODEM_DECIMATION_CFG0

- Group: 0x20
- Index: 0x1f

- Summary: Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
- Purpose:
  - The RX channel selection bandpass filter is a digital filter that is nominally 27 taps in length. By setting the CHFLT_LOPW bit, it is possible to configure the filter with only 15 taps; the advantage of the 15-tap filter is a reduction in current consumption and filter processing delay at the expense of reduced filtering performance (e.g., adjacent channel selectivity). The reduction in current consumption depends upon the selected data rate, but is typically ~100 to 200 uA.
  - As the channel selection bandpass filter is a digital filter, it inherently has a SIN(X)/X response which introduces some slope in amplitude across the passband. The effect is negligible for low bandwidth filters; for higher bandwidth filters the amplitude slope across the passband can approach 1 dB. The chip has a droop compensation filter that provides an inverse SIN(X)/X response; when enabled (by clearing the DROOPFLTBYP bit), this compensation filter effectively flattens the amplitude response across the passband. This bit is cleared by default (compensation filter is enabled), and Silicon Labs does not recommend altering this configuration.
  - The RFIC provides a configurable polyphase filter that is located prior to the decimation circuit blocks and CIC digital filter. This "pre-decimation" filter may be configured (by the DWN3BYP and DWN2BYP) bits to select an additional decimation factor of 2 or 3 (in addition to the decimation factor selected by the NDEC0/1/2 coefficients in the MODEM_DECIMATION_CFG1 property). If no additional decimation factor is desired, both the decimate-by-2 and decimate-by-3 circuits may be bypassed by setting both the DWN2BYP and DWN3BYP bits.
  - At very low data rates, the sensitivity may be improved by increasing the digital gain of the RX Modem. Setting the RXGAINX2 bit accomplishes this by doubling the gain of the fixed decimate-by-8 stage that immediately follows the RX A/D Converters. The WDS Calculator automatically suggests setting this bit when working with data rates below 1 kbps.
- Default: 0x20
- Register View:

| MODEM_DECIMATION_CFG0
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x1f | CHFLT_LOPW | DROOPFLTBYP | DWN3BYP | DWN2BYP | 0 | 0 | 0 | RXGAINX2
| Default
| 0x0 | 0x0 | 0x1 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0

- Field Details:

  ###### MODEM_DECIMATION_CFG0

  CHFLT_LOPW
  Description:
    Selects the operating mode of the channel selection filter (normal mode, or low-power mode with reduced performance).
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Normal mode (27 tap filter) |
    ENUM_1 | 1 | Low power mode with reduced performance (15 tap filter) |

  DROOPFLTBYP
  Description:
    Enables or bypasses the droop compensation filter.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Enables the droop compensation filter. |
    ENUM_1 | 1 | Bypass the droop compensation filter. |

  DWN3BYP
  Description:
    - Selects or bypasses the decimate-by-3 polyphase filter (located prior to the normal decimation stages and CIC filter).
    - The DWN3BYP and DWN2BYP bits may be simultaneously set (both filters bypassed), but the bits should not be simultaneously cleared.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Enables the decimate-by-3 polyphase filter |
    ENUM_1 | 1 | Bypass the decimate-by-3 polyphase filter. |

  DWN2BYP
  Description:
    - Selects or bypasses the decimate-by-2 polyphase filter (located prior to the normal decimation stages and CIC filter).
    - The DWN3BYP and DWN2BYP bits may be simultaneously set (both filters bypassed), but the bits should not be simultaneously cleared.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Select the decimate-by-2 polyphase filter. |
    ENUM_1 | 1 | Bypass the decimate-by-2 polyphase filter. |

  RXGAINX2
  Description:
    Doubles the gain of the fixed decimate-by-8 filter stage (following the RX A/D Converters) for the purpose of improving sensitivity at low data rates.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Normal decimate-by-8 filter gain. |
    ENUM_1 | 1 | Doubel the decimate-by-8 filter gain |

#### MODEM_DECIMATION_CFG2

- Group: 0x20
- Index: 0x20

- Summary: Specifies miscellaneous decimator filter selections.
- Purpose:
  - Need to fill in.
- Default: 0x00
- Register View:

| MODEM_DECIMATION_CFG2
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x20 | 0 | NDEC3 | NDEC2GAIN | NDEC2AGC | 0 | 0
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0

- Field Details:

  ###### MODEM_DECIMATION_CFG2

  NDEC3[1:0]
  Description:
    The third state CIC filter decimation index. Decimation rate is 2^ndec3[1:0]
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    NDEC3_1 | 0 | Decimation Ratio is 1. |
    NDEC3_2 | 1 | Decimation Ratio is 2 |
    NDEC3_4 | 2 | Decimation Ratio is 4. |
    NDEC3_8 | 3 | Decimation Ratio is 8 |

  NDEC2GAIN[1:0]
  Description:
    If ndec2agc is disabled, the second stage CIC filter's gain is manually controlled by this register. Otherwise it defines the second stage CIC filter's max gain.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    NDEC2_GAIN0 | 0 | Second state CIC filter decimation gain is 0dB and AGC filter is disabled. |
    NDEC2_GAIN12 | 1 | Second state CIC filter decimation gain is 12dB. |
    NDEC2_GAIN24 | 2 | Second state CIC filter decimation gain is 24dB |

  NDEC2AGC
  Description:
    If set, the second state CIC filter's gain is automatically controlled
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DISABLED | 0 | Disable automatic control of the second stage CIC filter's gain.. |
    ENABLED | 1 | Enable automatic control of the second stage CIC filter's gain.. |

#### MODEM_IFPKD_THRESHOLDS

- Group: 0x20
- Index: 0x21

- Summary:
- Purpose:
- Default: 0xe8
- Register View:

| MODEM_IFPKD_THRESHOLDS
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x21 | 0000 | 0000
| Default
| 0xe | 0x8

- Field Details:

  ###### MODEM_IFPKD_THRESHOLDS

#### MODEM_BCR_OSR

- Group: 0x20
- Indexes: 0x22 ... 0x23

- Summary: RX BCR/Slicer oversampling rate (12-bit unsigned number).
- Purpose:
  - The RX Modem in the chip contains a Numerically Controlled Oscillator (NCO) for the purpose of synchronizing a local bit clock to the received data stream. The timing of this NCO is maintained by a feedback loop called the Bit Clock Recovery (BCR) loop.
  - The BCR loop is sampled at a rate higher than the RX data rate. The ratio between the sampling rate and the RX data rate is called the BCR oversampling rate (OSR), with typical values of OSR = 8 to 12. The desired value of OSR is calculated as a function of the channel filter bandwidth and RX data rate, and reflects a compromise between low clock jitter (high sample rate) and lower current consumption and improved adjacent channel filter attenuation (low sample rate).
  - The BCR loop sampling clock is derived from the crystal oscillator through a series of decimations, and thus the sampling rate is controlled by the NDEC2, NDEC1, NDEC0, DWN3BYP, and DWN2BYP bits in the MODEM_DECIMATION_CFG properties. In (G)FSK mode, the channel filter and BCR loop use the same sampling clock rate; in OOK mode, the BCR loop uses a lower sampling clock rate by additionally configuring the NDEC0 parameter.
  - The 12-bit value programmed into the MODEM_BCR_OSR properties represents the target value of OSR multiplied by 8x (alternatively, the 12-bit value may be viewed as a 9-bit integer portion and 3-bit fractional portion). Example: for a target value of OSR = 11.75, the value of MODEM_BCR_OSR = 0x5E.
  - This property defines the RX BCR/Slicer oversampling rate.
- Defaults: 0x00,0x4b
- Register View:

| MODEM_BCR_OSR
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x22 | 0 | 0 | 0 | 0 | RXOSR[11:8]
0x23 | RXOSR[7:0]
| Defaults
0x22 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0
0x23 | 0x4b

- Field Details:

  ###### MODEM_BCR_OSR

  RXOSR[11:0]
  Description:
    RX symbol oversampling rate at the BCR/Slicer.
  Default:
    0x4b

#### MODEM_BCR_NCO_OFFSET

- Group: 0x20
- Indexes: 0x24 ... 0x26

- Summary: RX BCR NCO offset value (an unsigned 22-bit number).
- Purpose:
  - The RX Modem in the chip contains a Numerically Controlled Oscillator (NCO) for the purpose of synchronizing a local bit clock to the received data stream. The timing of this NCO is maintained by a feedback loop called the Bit Clock Recovery (BCR) loop.
  - The NCO operates by accumulating a programmed offset value on each tick of the BCR oversampling clock signal (see MODEM_BCR_OSR for more details of the BCR/Slicer oversampling clock). The rate at which the accumulator overflows is therefore a function of the word-width of the accumulator, the programmed offset value, and the BCR oversampling clock rate.
  - The NCO accumulator generates a pulse each time it overflows; the programmed offset value is selected such that the rate of pulses produced by the accumulator equals the desired RX data rate.
  - The 22-bit value programmed into the MODEM_BCR_NCO_OFFSET property represents the target offset value multiplied by 64x (alternatively, the 22-bit value may be viewed as a 16-bit integer portion and 6-bit fractional portion). Example: for a target offset value of OFFSET = 5592.40625, the value of MODEM_BCR_NCO_OFFSET = 0x05761A.
- Defaults: 0x06,0xd3,0xa0
- Register View:

| MODEM_BCR_NCO_OFFSET
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x24 | 0 | 0 | NCOFF[21:16]
0x25 | NCOFF[15:8]
0x26 | NCOFF[7:0]
| Defaults
0x24 | 0x0 | 0x0 | 0x6
0x25 | 0xd3
0x26 | 0xa0

- Field Details:

  ###### MODEM_BCR_NCO_OFFSET

  NCOFF[21:0]
  Description:
    The RX BCR NCO offset value.
  Default:
    0x6d3a0

#### MODEM_BCR_GAIN

- Group: 0x20
- Indexes: 0x27 ... 0x28

- Summary: The unsigned 11-bit RX BCR loop gain value.
- Purpose:
  - The RX Modem in the chip contains a Numerically Controlled Oscillator (NCO) for the purpose of synchronizing a local bit clock to the received data stream. The timing of this NCO is maintained by a feedback loop called the Bit Clock Recovery (BCR) loop. (Please refer to the text description for MODEM_BCR_NCO_OFFSET for more details regarding the BCR NCO.)
  - The BCR NCO provides a local clock signal that is at the desired data rate; however, a method of synchronizing the phase of the local clock signal to that of the received data stream is also required. This phase alignment is accomplished by measuring the phase difference between the local bit clock and the received data stream, and adjusting the phase of the bit clock by means of a feedback loop.
  - This property adjusts the gain of the BCR feedback loop. A large value of gain results in fast acquisition of timing but increased clock jitter, while a low value of gain provides lower clock jitter but slower timing acquisition.
  - The chip provides for switching the loop gain (i.e., "gear shifting") at a configurable point during the packet. This allows the chip to initially use a high loop gain value (resulting in fast acquisition of timing during reception of the Preamble), followed by a lower loop gain value (resulting in low clock jitter during reception of the Payload).
  - The clock recovery gain in MODEM_BCR_GAIN is an unsigned 11-bit value that serves as a common "baseline" gain value; it is further scaled by individually selectable scale factors to determine the effective loop gain values to be used prior to and after gear shifting. These scale factors are specified by MODEM_BCR_GEAR:CRFAST and MODEM_BCR_GEAR:CRSLOW.
- Defaults: 0x06,0xd3
- Register View:

| MODEM_BCR_GAIN
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x27 | 0 | 0 | 0 | 0 | 0 | CRGAIN[10:8]
0x28 | CRGAIN[7:0]
| Defaults
0x27 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x6
0x28 | 0xd3

- Field Details:

  ###### MODEM_BCR_GAIN

  CRGAIN[10:0]
  Description:
    The clock recovery timing loop gain.
  Default:
    0x6d3

#### MODEM_BCR_GEAR

- Group: 0x20
- Index: 0x29

- Summary: RX BCR loop gear control.
- Purpose:
  - RX BCR loop gear control.
  - A reduced value of bit clock recovery gain is often desired after gear shifting (to reduce clock jitter). The BCR loop gain in both gear modes is obtained from a baseline clock recovery gain value (crgain in the MODEM_BCR_GAIN_x properties), scaled by the crfast and crslow values specified in this property. NOTE: larger values of crfast or crslow result in lower values of bit clock recovery gain.
- Default: 0x02
- Register View:

| MODEM_BCR_GEAR
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x29 | 0 | 0 | CRFAST | CRSLOW
| Default
| 0x0 | 0x0 | 0x0 | 0x2

- Field Details:

  ###### MODEM_BCR_GEAR

  CRFAST[2:0]
  Description:
    The fast timing gain applies before gear switching occurs. The effective BCR loop gain is calculated as: crgain/(2^crfast).
  Default:
    0x0
  CRSLOW[2:0]
  Description:
    The slow timing gain applies after gear switching occurs. The effective BCR loop gain is calculated as: crgain/(2^crslow).
  Default:
    0x2

#### MODEM_BCR_MISC1

- Group: 0x20
- Index: 0x2a

- Summary: Miscellaneous control bits for the RX BCR loop.
- Purpose:
  - This property configures miscellaneous options within the RX BCR loop.
- Default: 0xc0
- Register View:

| MODEM_BCR_MISC1
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x2a | BCRFBBYP | SLICEFBBYP | 0 | RXNCOCOMP | RXCOMP_LAT | CRGAINX2 | DIS_MIDPT | ESC_MIDPT
| Default
| 0x1 | 0x1 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0

- Field Details:

  ###### MODEM_BCR_MISC1

  BCRFBBYP
  Description:
    - The frequency of the down-converted signal in the IF may not be perfectly centered in the IF (e.g. PLL-based AFC correction is disabled or settles with some small residual frequency error).
    - If left uncompensated, this residual frequency error may degrade the ability of the BCR and Slicer to track and slice the data bits (respectively).
    - In normal operation, the measured residual frequency error is provided as feedback to the BCR and Slicer to compensate their performance.
    - This bit disables the feedback term to the BCR tracking loop. This is normally used only for diagnostics purposes or during reception of special test signals (e.g., BER tests).
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENABLED | 0 | Feedback of the compensation term to the BCR tracking loop is enabled (normal operation). |
    DISABLED | 1 | Feedback of the compensation term to the BCR tracking loop is bypassed (disabled). |

  SLICEFBBYP
  Description:
    Please refer to the text description for MODEM_BCR_MISC1:BCRFBBYP for further details regarding this functionality.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENABLED | 0 | Feedback of the compensation term to the slicer is enabled (normal operation). |
    DISABLED | 1 | Feedback of the compensation term to the slicer is bypassed (disabled). |

  RXNCOCOMP
  Description:
    - The RX Modem in the chip contains a Numerically Controlled Oscillator (NCO) for the purpose of synchronizing a local bit clock to the received data stream. (Please refer to the text description for MODEM_BCR_NCO_OFFSET for more details regarding the BCR NCO.)
    - The free-running frequency of the NCO is normally set to a fixed value (appropriate for the selected data rate) and used throughout the entire packet.
    - In the event of receiving a packet with a large error in the data rate, the BCR loop may not be able to maintain tracking without first obtaining a more accurate estimate of the actual received data rate.
    - This bit allows the chip to compensate for data rate error by acquiring a new estimate for the NCO frequency from the received data itself. This new NCO frequency estimate is obtained during the Preamble field, and then used for the remainder of the packet.
    - This compensation is typically needed only when the data rate error is greater than 1%.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DISABLED | 0 | Compensation of the BCR NCO frequency is disabled (normal operation). |
    ENABLED | 1 | Compensation of the BCR NCO frequency is enabled. |

  RXCOMP_LAT
  Description:
    - This bit determines the location in the packet at which the new estimation of BCR NCO frequency is taken.
    - This bit has no effect if RXNCOCOMP is not also set; please refer to the text description for RXNCOCOMP for further details.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    SAMP_PREAMBLE_END | 0 | BCR NCO compensation is sampled upon detection of the end of the Preamble (i.e., boundary between Preamble and Sync Word). |
    SAMP_PREAMBLE_VALID | 1 | BCR NCO compensation is sampled upon detection of PREAMBLE_VALID. |

  CRGAINX2
  Description:
    - Selects whether the BCR loop gain will be increased by a factor of 2x.
    - This gain increase applies to all modes of operation (i.e., both high-gear and low-gear modes).
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    NORMAL | 0 | BCR loop gain is not doubled (normal operation). |
    DOUBLED | 1 | BCR loop gain is doubled. |

  DIS_MIDPT
  Description:
    - The BCR loop attempts to synchronize the local RX bit clock to the edge transitions of the received data bits by sampling the phase at 1*Tb intervals.
    - The sensitivity of the phase sampling process may be reduced if the BCR loop accidentally aligns to sampling at the mid-point of the data bits instead of at bit boundaries. In extreme conditions, the sampled phase information may not be sufficient to drive the BCR loop away from the mid-point condition and towards the optimal bit boundary sampling condition.
    - This mid-point sampling condition may be detected and corrected by deliberately "kicking" the BCR loop slightly.
    - This functionality only applies to demodulation of a 2(G)FSK signal with a standard '1010...' Preamble pattern using the Synchronous Demodulator.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENABLED | 0 | Correction of a BCR mid-point phase sampling condition by resetting the NCO is enabled (normal operation). |
    DISABLED | 1 | Correction of a BCR mid-point phase sampling condition by resetting the NCO is disabled. |

  ESC_MIDPT
  Description:
    Selects the method of "kicking" the BCR loop to escape a mid-point phase sampling condition, as described for the DIS_MIDPT bit.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ESCAPE_1CLK | 0 | Upon detection of a BCR mid-point phase sampling condition, the NCO will stop running for one sample clock to escape. |
    ESCAPE_PHASE_ERR | 1 | Upon detection of a BCR mid-point phase sampling condition, the current phase error is added to the NCO to escape. |

#### MODEM_BCR_MISC0

- Group: 0x20
- Index: 0x2b

- Summary: Miscellaneous RX BCR loop controls.
- Purpose:
  - This property configures miscellaneous options within the RX BCR loop.
- Default: 0x00
- Register View:

| MODEM_BCR_MISC0
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x2b | ADCWATCH | ADCRST | DISTOGG | PH0SIZE | 0 | 0 | 0 | 0
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0

- Field Details:

  ###### MODEM_BCR_MISC0

  ADCWATCH
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | ADC watch dog is disabled. |
    ENUM_1 | 1 | ADC watch dog is enabled. If the invalid preamble is detected and no 1010 pattern is detected, ADC reset will be generated. |

  ADCRST
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | ADC watch dog is disabled. |
    ENUM_1 | 1 | Enable ADC reset from AGC loop. If IF-PD's current and previous high threshold exceed, ADC reset will be generated. |

  DISTOGG
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Normal. |
    ENUM_1 | 1 | Enabled. If the phase differential output is zero, the discriminator output will be toggling. |

  PH0SIZE
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | 5 consecutive zeros of phase differential output will cause RX machine reset. |
    ENUM_1 | 1 | 3 consecutive zeros of phase differential output will cause RX machine reset. |

#### MODEM_AFC_GEAR

- Group: 0x20
- Index: 0x2c

- Summary: RX AFC loop gear control.
- Purpose:
  - Selection of gear switching source for both RX AFC and BCR.
  - Control of gain for RX AFC in both FAST and SLOW modes (i.e., before and after gear switching)
- Default: 0x00
- Register View:

| MODEM_AFC_GEAR
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x2c | GEAR_SW | AFC_FAST | AFC_SLOW
| Default
| 0x0 | 0x0 | 0x0

- Field Details:

  ###### MODEM_AFC_GEAR

  GEAR_SW[1:0]
  Description:
    Selects the event upon which gear switching will occur. Gear switching simultaneously affects the BCR tracking loop as well as the PLL-based AFC loop (if enabled).
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Preamble detection - switch gears after detection of Preamble. |
    ENUM_1 | 1 | Sync word detection - switch gears after detection of Sync Word. |
    ENUM_2 | 2 | Mid-Point frequency error detection - switch gears when the estimated frequency error of the Min-Max detector in the Asynchronous Demodulator is less than the half eye-threshold for a consecutive number of search periods. NOTE: The consecutive number of search periods is defined MODEM_RAW_SEARCH:SCH_FRZTH, while the length of each search period (in bits) is defined by MODEM_RAW_SEARCH:SCHPRD_HI. |
    ENUM_3 | 3 | Preamble detection - switch gears after detection of Preamble (same as gear_sw = 0) |

  AFC_FAST[2:0]
  Description:
    - Sets the gain of the PLL-based AFC acquisition loop prior to gear switching (i.e., during Fast tracking mode).
    - The gain of the AFC loop is the product of a baseline gain value and a scale factor that differs according to gear switching. The baseline gain value is specified by MODEM_AFC_GAIN while the scale factors are held by the AFC_FAST and AFC_SLOW parameters.
    - The gain of the AFC loop in Fast tracking mode is MODEM_AFC_GAIN * 2-AFC_FAST, and thus a larger value of AFC_FAST results in slower AFC tracking speed prior to gear switching.
  Min:
    0x0
  Max:
    0x7
  Default:
    0x0
  AFC_SLOW[2:0]
  Description:
    - Sets the gain of the PLL-based AFC acquisition loop after gear switching (i.e., during Slow tracking mode).
    - The gain of the AFC loop is the product of a baseline gain value and a scale factor that differs according to gear switching. The baseline gain value is specified by MODEM_AFC_GAIN while the scale factors are held by the AFC_FAST and AFC_SLOW parameters.
    - The gain of the AFC loop in Slow tracking mode is MODEM_AFC_GAIN * 2-AFC_SLOW, and thus a larger value of AFC_SLOW results in slower AFC tracking speed after gear switching.
  Min:
    0x0
  Max:
    0x7
  Default:
    0x0

#### MODEM_AFC_WAIT

- Group: 0x20
- Index: 0x2d

- Summary: RX AFC loop wait time control.
- Purpose:
  - The chip provides for Automatic Frequency Correction (AFC) in RX mode to improve reception of the signal in the presence of frequency error in the link. The frequency error is measured and corrected during the initial acquisition of the packet (e.g., during the Preamble), allowing optimized reception of the remainder of the packet.
  - One form of AFC provided by the chip operates by adjusting the frequency of the RX LO signal from the PLL Synthesizer, and strives to position the down-converted IF signal in the center of the IF passband. This PLL-based form of AFC thus operates in the analog domain; the chip also provides for other forms of AFC that operate in the digital domain of the RX Modem. The SHWAIT and LGWAIT parameters in the MODEM_AFC_WAIT property affect only PLL-based AFC.
  - Each AFC correction cycle consists of: a) measuring the frequency error, b) adjusting the frequency of the PLL, and c) allowing the PLL to settle prior to taking another measurement of frequency error.
  - The SHWAIT and LGWAIT parameters determine the periods of time allowed for the PLL to settle after each AFC adjustment cycle. Two different waiting periods (short and long) are provided, depending upon whether the AFC algorithm is operating before or after gear switching.
  - The waiting time is in multiples of the symbol period, and thus changes as a function of the data rate. At higher data rates (i.e., shorter symbol periods), the values of the SHWAIT and LGWAIT parameters may need to be increased to provide sufficient time for the PLL to re-settle after correction. The WDS Calculator automatically suggests appropriate values as a function of the selected data rate.
- Default: 0x23
- Register View:

| MODEM_AFC_WAIT
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x2d | SHWAIT | LGWAIT
| Default
| 0x2 | 0x3

- Field Details:

  ###### MODEM_AFC_WAIT

  SHWAIT[3:0]
  Description:
    - This specifies the wait period per PLL AFC correction cycle before gear switching has occurred. The SHWAIT parameter is typically set to a value smaller than the LGWAIT parameter, as fast acquisition speed prior to gear switching is usually desirable.
    - The effective wait time is (SHWAIT+1)*2Tb.
    - When set to '0' then no PLL AFC correction will occur before gear switching, i.e., PLL AFC is disabled before gear switching.
  Min:
    0x0
  Max:
    0xf
  Default:
    0x2
  LGWAIT[3:0]
  Description:
    - This specifies the wait period per PLL AFC correction cycle after gear switching has occurred. The LGWAIT parameter is typically set to a value larger than the SHWAIT parameter, as robust tracking of unbalanced data after gear switching is usually desirable.
    - The effective wait time is (LGWAIT+1)*2Tb.
    - When set to '0' then no PLL AFC correction will occur after gear switching, i.e., PLL AFC is disabled after gear switching.
    - If MODEM_AFC_MISC:ENAFCFRZ is set, there will be no PLL AFC correction after gear switching, regardless of the value of LGWAIT.
  Min:
    0x0
  Max:
    0xf
  Default:
    0x3

#### MODEM_AFC_GAIN

- Group: 0x20
- Indexes: 0x2e ... 0x2f

- Summary: Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
- Purpose:
  - The chip provides for Automatic Frequency Correction (AFC) functionality in which the frequency error of the received signal is measured and used to adjust the PLL Synthesizer to position the down-converted IF signal in the center of the IF bandwidth.
  - The AFC algorithm uses a feedback loop to track the frequency of the incoming signal. The gain of the AFC loop is the product of a baseline gain value and a scale factor that differs according to gear switching. The baseline gain value is specified by this property (an unsigned 13-bit value) while the scale factors are held by the MODEM_AFC_GEAR:AFC_FAST and MODEM_AFC_GEAR:AFC_SLOW parameters.
  - The ENAFC parameter enables the frequency error estimation circuitry.
  - The AFCBD parameter enables dynamic switching of the RX bandwidth during the packet. Please refer to MODEM_CHFLT_RX2_CHFLT_COE for further details regarding the use of adaptive RX bandwidth.
- Defaults: 0x83,0x69
- Register View:

| MODEM_AFC_GAIN
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x2e | ENAFC | AFCBD | AFC_GAIN_DIV | AFCGAIN[12:8]
0x2f | AFCGAIN[7:0]
| Defaults
0x2e | 0x1 | 0x0 | 0x0 | 0x3
0x2f | 0x69

- Field Details:

  ###### MODEM_AFC_GAIN

  ENAFC
  Description:
    - When set, enables estimation of the frequency error.
    - Estimated frequency error is made available to feedback to the Frac-N PLL, BCR and Slicer. NOTE: enabling of each individual AFC function is performed in the MODEM_BCR_MISC1 and MODEM_AFC_MISC properties.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DISABLE | 0 | Estimation of frequency error is disabled. This effectively disables all forms of AFC (both PLL-based AFC as well as Slicer and BCR compensation). |
    ENABLE | 1 | Estimation of frequency error is enabled. |

  AFCBD
  Description:
    If set, enables the use of adaptive RX bandwidth across the packet.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DISABLE | 0 | Adaptive RX bandwidth is disabled. The RX channel filter coefficients specified in MODEM_CHFLT_RX1_CHFLT_COE are used across the entire packet. |
    ENABLE | 1 | Adaptive RX bandwidth is enabled. The RX channel filter coefficients specified in MODEM_CHFLT_RX1_CHFLT_COE are used prior to gear switching, and the coefficients specified in MODEM_CHFLT_RX2_CHFLT_COE are used after gear switching. |

  AFC_GAIN_DIV
  Description:
    Reduces AFC loop gain by half when set.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    NO_REDUCTION | 0 | AFC loop gain is not reduced (normal operation). |
    REDUCTION_BY_HALF | 1 | AFC loop gain is reduced by half. |

  AFCGAIN[12:0]
  Description:
    13-bit AFC loop gain value.
  Min:
    0x0
  Max:
    0x1fff
  Default:
    0x369

#### MODEM_AFC_LIMITER

- Group: 0x20
- Indexes: 0x30 ... 0x31

- Summary: Set the AFC limiter value.
- Purpose:
  - The chip provides for Automatic Frequency Correction (AFC) functionality in which the frequency error of the received signal is measured and used to adjust the PLL Synthesizer to position the down-converted IF signal in the center of the IF bandwidth.
  - This property provides a "watchdog" upper limit on how far the AFC tracking loop may vary from the commanded channel center frequency (i.e., due to tracking on noise). Upon reaching this limit, the AFC algorithm is reset to begin reacquisition from the channel center frequency.
- Defaults: 0x00,0x40
- Register View:

| MODEM_AFC_LIMITER
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x30 | 0 | AFCLIM[14:8]
0x31 | AFCLIM[7:0]
| Defaults
0x30 | 0x0 | 0x0
0x31 | 0x40

- Field Details:

  ###### MODEM_AFC_LIMITER

  AFCLIM[14:0]
  Description:
    - 15-bit AFC limiter value. If the frequency error measured by the AFC correction algorithm exceeds this value, the AFC algorithm is reset to begin reacquisition from channel center frequency.
    - The AFC limiter value should be viewed as a 14-bit value plus an additional bit that enables an 8x scale factor. If AFCLIM[14] = '0', then the AFC limiter value is AFCLIM[13:0]. If AFCLIM[14] = '1', then the AFC limiter value is AFCLIM[13:0]*8.
  Min:
    0x0
  Max:
    0x7fff
  Default:
    0x40

#### MODEM_AFC_MISC

- Group: 0x20
- Index: 0x32

- Summary: Specifies miscellaneous AFC control bits.
- Purpose:
  - Specifies miscellaneous bits for control of AFC functionality.
- Default: 0xa0
- Register View:

| MODEM_AFC_MISC
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x32 | ENAFCFRZ | ENFBPLL | EN2TB_EST | ENFZPMEND | ENAFC_CLKSW | 0 | NON_FRZEN | LARGE_FREQ_ERR
| Default
| 0x1 | 0x0 | 0x1 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0

- Field Details:

  ###### MODEM_AFC_MISC

  ENAFCFRZ
  Description:
    Selects whether the AFC will operate over the entire packet, or will be frozen after gear switching.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    AFC_PKT | 0 | AFC will operate over the entire packet. |
    AFC_FRZN_AFTER_GEAR_SW | 1 | AFC will be frozen after the gear switching. |

  ENFBPLL
  Description:
    Selects whether the estimation of frequency error (i.e., AFC correction value) will be provided as feedback to adjust the PLL Synthesizer frequency.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DISABLE_AFC_COR_PLL | 0 | Disable AFC correction value feedback to the PLL. |
    ENABLE_AFC_COR_PLL | 1 | Enable AFC correction value feedback to the PLL. |

  EN2TB_EST
  Description:
    Selects whether AFC correction uses the estimation of frequency error developed by the Moving Average or Min-Max detector in the Asynchronous Demodulator, or the 2*Tb estimator in the Synchronous Demodulator.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    AFC_COR_MA | 0 | AFC correction uses the frequency estimation developed by the Moving Average or Min-Max detector in the Asynchronous Demodulator. |
    AFC_COR_2TB | 1 | AFC correction uses the frequency estimation developed by the 2*Tb estimator in the Synchronous Demodulator. This bit must be set for proper reception of a standard packet using the Synchronous Demodulator. |

  ENFZPMEND
  Description:
    - Selects whether the AFC will freeze at the end of the '...10101...' Preamble pattern (i.e., boundary between Preamble and Sync Word).
    - This functionality may be useful if a very long Preamble is used and very good frequency error correction is desired. Setting the ENAFCFRZ bit will take precedence over setting this bit (i.e., the AFC may be frozen earlier, as determined by the gear switching source).
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    NO_AFC_FRZN | 0 | AFC will not be frozen at the end of the Preamble. |
    AFC_FRZN_PREAMBLE | 1 | AFC will be frozen at the end of the Preamble. |

  ENAFC_CLKSW
  Description:
    - Selects whether the clock source for the 2*Tb frequency estimator is switched from a free-running bit clock to the BCR's bit clock upon detection of PREAMBLE_VALID.
    - This bit is most useful when used together with the ENFZPMEND bit; that is, when a long Preamble is available and very good frequency error correction is desired.
    - This bit has no effect if the EN2TB_EST bit is not also set (i.e., if the Asynchronous Demodulator is in use.)
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    NO_CLK_SW | 0 | The clock source for the 2*Tb frequency estimator is not switched. |
    CLK_SW_TO_BCR_BCLK | 1 | The clock source for the 2*Tb frequency estimator is switched to the BCR's bit clock upon detection of PREAMBLE_VALID. |

  NON_FRZEN
  Description:
    - Selects whether AFC correction to the PLL is frozen.
    - This bit only has an effect for a very specific chip configuration: a) the Asynchronous Demodulator is in use, b) the modulation type is not OOK, and c) the Min-Max detector is used to develop the slicing threshold level (as configured in the MODEM_OOK_MISC property).
    - When configured in this fashion, the chip will normally freeze AFC correction to the PLL when a sufficient length of consecutive 1's or 0's is encountered, as the chip may not be able to correctly estimate the frequency error within the given search period.
    - The consecutive number of search periods is defined by MODEM_RAW_SEARCH:SCH_FRZTH, while the length of each search period is defined by MODEM_RAW_SEARCH:SCHPRD_HI.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    AFC_FRZN_CONSEC_BITS | 0 | AFC correction of the PLL will be frozen if a consecutive string of 1's or 0's that exceed the search period is encountered. |
    AFC_ALWAYS_EN | 1 | AFC correction of the PLL will remain enabled if a consecutive string of 1's or 0's that exceed the search period is encountered. |

  LARGE_FREQ_ERR
  Description:
    Setting this bit expands the range of the AFC acquisition algorithm. It is recommended to set this bit when the expected frequency error is larger than 12*Symbol_Rate.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DISABLED | 0 | Expected range of frequency error is normal (less than 12*Symbol_Rate) |
    ENABLED | 1 | Expected range of frequency error is large (greater than 12*Symbol_Rate) |

#### MODEM_AFC_ZIFOFF

- Group: 0x20
- Index: 0x33

- Summary: AFC fixed frequency offset in zero IF mode.
- Purpose:
  - AFC fixed frequency offset in zero IF mode.
- Default: 0x00
- Register View:

| MODEM_AFC_ZIFOFF
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x33 | ZEROFF
| Default
| 0x0

- Field Details:

  ###### MODEM_AFC_ZIFOFF

  ZEROFF[7:0]
  Default:
    0x0

#### MODEM_ADC_CTRL

- Group: 0x20
- Index: 0x34

- Summary: Sigma Delta ADC controls.
- Purpose:
  - This property configures various options in the sigma delta ADC.
- Default: 0x00
- Register View:

| MODEM_ADC_CTRL
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x34 | 0 | 0 | 0 | HGAIN | EN_DRST | 0 | REALADC | 0
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0

- Field Details:

  ###### MODEM_ADC_CTRL

  HGAIN
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 1 | Adds 12 dB gain to ADC input for IR calibration. |

  EN_DRST
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DISABLE | 0 | Disable direct reset by modem. |
    ENABLE | 1 | Enable direct reset by modem. |

  REALADC
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    COMPLEX | 0 | ADC complex mode. |
    REAL | 1 | ADC real mode. |

#### MODEM_AGC_CONTROL

- Group: 0x20
- Index: 0x35

- Summary: Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
- Purpose:
  - This property provides several miscellaneous control bits for the AGC functionality. These control bits are primarily intended for engineering diagnostic purposes; Silicon Labs does not recommend altering the values suggested by the WDS Calculator, unless required to accommodate unusual customer applications.
- Default: 0xe0
- Register View:

| MODEM_AGC_CONTROL
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x35 | AGCOVPKT | IFPDSLOW | RFPDSLOW | SGI_N | AGC_SLOW | 0 | ADC_GAIN_COR_EN | RST_PKDT_PERIOD
| Default
| 0x1 | 0x1 | 0x1 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0

- Field Details:

  ###### MODEM_AGC_CONTROL

  AGCOVPKT
  Description:
    - Selects whether the AGC operates over the entire packet, or only during acquisition of the Preamble.
    - Reductions in gain (in the event of signal level increases) are always allowed at any time, regardless of the state of this bit.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | The full AGC operates only during acquisition of the Preamble. Gain increases (in the event of a decrease in signal level) over the remainder of packet are not allowed. |
    ENUM_1 | 1 | AGC function operates over the entire packet. |

  IFPDSLOW
  Description:
    - The chip contains peak detectors in the IF chain for the purpose of sensing the signal level at the outputs of the IF PGAs. The information from these peak detectors is used by the AGC algorithm to adjust the gain of the RX chain (PGA and LNA).
    - In the event the signal level increases abruptly, it is desirable to decrease the gain rapidly else compression may occur in the RX chain. The IFPDSLOW bit controls the step size of gain reductions to the PGA, and thus affects the slope or speed of the AGC attack time.
    - This bit affects only the rate of gain decreases; increases in gain are always performed in 3 dB steps.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | The IF programmable gain loop will perform the first required gain decrease in a -3 dB step, but if further gain reductions are required (due to successive indications of the signal level exceeding the peak detector threshold) will switch to -6 dB steps. |
    ENUM_1 | 1 | The IF programmable gain loop will always perform gain decreases in -3 dB steps. |

  RFPDSLOW
  Description:
    - The chip contains RF peak detectors for the purpose of sensing the signal level at the output of the LNA. The information from these peak detectors is used by the AGC algorithm to adjust the gain of the RX chain (PGA and LNA).
    - In the event the signal level increases abruptly, it is desirable to decrease the gain rapidly else compression may occur in the RX chain. The RFPDSLOW bit controls the step size of gain reductions to the LNA, and thus affects the slope or speed of the AGC attack time.
    - This bit affects only the rate of gain decreases; increases in gain are always performed in 3 dB steps.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | The RF programmable gain loop will perform the first required gain decrease in a -3 dB step, but if further gain reductions are required (due to successive indications of the signal level exceeding the peak detector threshold) will switch to -6 dB steps. |
    ENUM_1 | 1 | The RF programmable gain loop will always perform gain decreases in -3 dB steps. |

  SGI_N
  Description:
    - Selects whether gain increases are allowed due to selection of a weak antenna during the Antenna Diversity algorithm.
    - This bit is effective only in ANT-DIV mode, and only during acquisition of the Preamble (when the signal strength of the two antennas is being evaluated).
    - This functionality is provided to prevent temporary overload of the RX Chain due to final selection of a strong antenna, after first adjusting the gain to a high value as a result of evaluation of a low signal on a weak antenna.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | AGC gain increases during signal reductions are prevented. |
    ENUM_1 | 1 | AGC gain increases during signal reductions are allowed. |

  AGC_SLOW
  Description:
    - The period of the AGC cycle (including both a measurement window period and a gain settling window period) is normally configured by the MODEM_AGC_WINDOW_SIZE property.
    - In the event that the AGC cycle speed cannot be configured to a sufficiently low value, the AGC speed may be reduced by an additional factor of 8x by setting the AGC_SLOW bit.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Normal AGC speed. |
    ENUM_1 | 1 | AGC speed is reduced by a factor of 8. |

  ADC_GAIN_COR_EN
  Description:
    Selects whether the input gain of the RX A/D Converter is reduced when the condition of minimum AGC gain is detected.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ADC_GAIN_DIS | 0 | Adjustment of the ADC input gain is disabled. |
    ADC_GAIN_VIA_AGC | 1 | ADC input gain is reduced by 6 dB, when the condition of minimum AGC gain is detected. |

  RST_PKDT_PERIOD
  Description:
    Selects the period at which the IF and RF peak detectors are reset.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | The peak detectors are reset only when a change in gain is indicated by the peak detector output. |
    ENUM_1 | 1 | The peak detectors are reset on each and every cycle of the AGC algorithm. |

#### MODEM_AGC_WINDOW_SIZE

- Group: 0x20
- Index: 0x38

- Summary: Specifies the size of the measurement and settling windows for the AGC algorithm.
- Purpose:
  - One cycle of the AGC algorithm consists of a measurement window period, a (potential) gain adjustment, and a gain settling window period.
  - During the measurement window period, the signal level is measured by peak detectors located at the outputs of the LNA and PGA gain stages. Gain adjustments (up or down) are performed depending upon whether the measured signal level falls within an amplitude threshold window.
  - The periods of both the measurement window and the gain settling window are adjustable. It is necessary that the measurement window is sufficient in length to allow capture of a peak of the sinusoidal IF signal. As the IF frequency used by the chip is configurable, the measurement window must also be configurable.
  - The units of the MEASWIN and SETTLEWIN fields are in periods of the oversampling clock for the Bit Clock Recovery (BCR) loop (e.g., typically 8 to 12 times the received data rate).
  - In the event that the window times obtained for the maximum values of MEASWIN and SETTLEWIN are not sufficiently long, their effective values may be simultaneously increased by a factor of 8x by setting the AGC_SLOW bit in the MODEM_AGC_CONTROL property. (This need is unlikely to occur.)
- Default: 0x11
- Register View:

| MODEM_AGC_WINDOW_SIZE
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x38 | MEASWIN | SETTLEWIN
| Default
| 0x1 | 0x1

- Field Details:

  ###### MODEM_AGC_WINDOW_SIZE

  MEASWIN[3:0]
  Description:
    - Size of the signal level measurement window for the AGC algorithm.
    - Effective measurement time is:

  Min:
    0x1
  Max:
    0xf
  Default:
    0x1
  SETTLEWIN[3:0]
  Description:
    - Size of the gain settling window for the AGC algorithm.
    - Effective settling time is:

  Min:
    0x1
  Max:
    0xf
  Default:
    0x1

#### MODEM_AGC_RFPD_DECAY

- Group: 0x20
- Index: 0x39

- Summary: Sets the decay time of the RF peak detectors.
- Purpose:
  - The chip contains RF peak detectors in the LNA for the purpose of sensing the signal level at the output of the LNA. The information from these peak detectors is used by the AGC algorithm to adjust the gain of the RX chain (PGA and LNA).
  - It is usually desirable for AGC circuitry to attack quickly (rapidly decrease the gain when the signal level increases) but decay slowly (slowly increase the gain when the signal level decreases).
  - To accomplish the slow decay, the chip requires that the peak detectors indicate a consecutive number of "signal below threshold" conditions before the gain is increased. The requirement for consistent indication for gain increase is advisable to prevent gain chattering. The required number of consecutive indications is set by the RFPD_DECAY value.
  - It is usually recommended to set the MODEM_AGC_IFPD_DECAY and MODEM_AGC_RFPD_DECAY properties to identical values.
- Default: 0x10
- Register View:

| MODEM_AGC_RFPD_DECAY
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x39 | RFPD_DECAY
| Default
| 0x10

- Field Details:

  ###### MODEM_AGC_RFPD_DECAY

  RFPD_DECAY[7:0]
  Description:
    Specifies the consecutive number of AGC cycles for which the RF peak detectors must give a consistent increase gain indication, before the gain increase is allowed.
  Min:
    0x1
  Max:
    0xff
  Default:
    0x10

#### MODEM_AGC_IFPD_DECAY

- Group: 0x20
- Index: 0x3a

- Summary: Sets the decay time of the IF peak detectors.
- Purpose:
  - The chip contains peak detectors in the IF chain for the purpose of sensing the signal level at the outputs of the IF PGAs. The information from these peak detectors is used by the AGC algorithm to adjust the gain of the RX chain (PGA and LNA).
  - It is usually desirable for AGC circuitry to attack quickly (rapidly decrease the gain when the signal level increases) but decay slowly (slowly increase the gain when the signal level decreases).
  - To accomplish the slow decay, the chip requires that the peak detectors indicate a consecutive number of "signal below threshold" conditions before the gain is increased. The requirement for consistent indication for gain increase is advisable to prevent gain chattering. The required number of consecutive indications is set by the IFPD_DECAY value.
  - It is usually recommended to set the MODEM_AGC_IFPD_DECAY and MODEM_AGC_RFPD_DECAY properties to identical values.
- Default: 0x10
- Register View:

| MODEM_AGC_IFPD_DECAY
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x3a | IFPD_DECAY
| Default
| 0x10

- Field Details:

  ###### MODEM_AGC_IFPD_DECAY

  IFPD_DECAY[7:0]
  Description:
    Specifies the consecutive number of AGC cycles for which the IF peak detectors must give a consistent increase gain indication, before the gain increase is allowed.
  Min:
    0x1
  Max:
    0xff
  Default:
    0x10

#### MODEM_FSK4_GAIN1

- Group: 0x20
- Index: 0x3b

- Summary: Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
- Purpose:
  - Controls 4(G)FSK suppression gain.
- Default: 0x0b
- Register View:

| MODEM_FSK4_GAIN1
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x3b | 4FSK_ISIS_DISABLE | 4FSK_GAIN1
| Default
| 0x0 | 0xb

- Field Details:

  ###### MODEM_FSK4_GAIN1

  4FSK_ISIS_DISABLE
  Description:
    Second phase compensation factor for 4(G)FSK.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Normal. |
    ENUM_1 | 1 | Disable 4(G)FSK ISI-suppression. |

  4FSK_GAIN1[6:0]
  Description:
    Gain factor of the secondary branch in 4(G)FSK ISI-suppression.
  Default:
    0xb

#### MODEM_FSK4_GAIN0

- Group: 0x20
- Index: 0x3c

- Summary: Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
- Purpose:
  - Controls 4(G)FSK suppression gain.
- Default: 0x1c
- Register View:

| MODEM_FSK4_GAIN0
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x3c | PHASE_COMP_2FSK | 4FSK_GAIN0
| Default
| 0x0 | 0x1c

- Field Details:

  ###### MODEM_FSK4_GAIN0

  PHASE_COMP_2FSK
  Description:
    If set, phase compensation is enabled.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DISABLED | 0 | Disable phase compenstation for 2fsk.. |
    ENABLED | 1 | Enable phase compenstation for 2fsk.. |

  4FSK_GAIN0[6:0]
  Default:
    0x1c

#### MODEM_FSK4_TH

- Group: 0x20
- Indexes: 0x3d ... 0x3e

- Summary: 16 bit 4(G)FSK slicer threshold.
- Purpose:
  - 16 bit4(G)FSK slicer threshold.
- Defaults: 0x40,0x00
- Register View:

| MODEM_FSK4_TH
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x3d | 4FSKTH[15:8]
0x3e | 4FSKTH[7:0]
| Defaults
0x3d | 0x40
0x3e | 0x0

- Field Details:

  ###### MODEM_FSK4_TH

  4FSKTH[15:0]
  Default:
    0x4000

#### MODEM_FSK4_MAP

- Group: 0x20
- Index: 0x3f

- Summary: 4(G)FSK symbol mapping code.
- Purpose:
  - The chip is capable of transmitting and receiving 4(G)FSK modulation. In this type of modulation, pairs of data bits are encoded/decoded into 1-of-4 possible frequency deviation levels. This property controls the mapping of bit pairs into deviation levels.
  - The four deviation levels are evenly spaced and symmetrical around the channel center frequency. As an example, the deviation levels for a 4(G)FSK modulation protocol with 10kHz spacing between levels would be: -15kHz, -5kHz, +5 kHz, and +15 kHz.
  - By convention, these four deviation levels are often referred to as the -3ΔF, -1ΔF, +1ΔF, and +3ΔF levels. This naming convention arises from the fact that the outer deviation (i.e., the difference between channel center frequency and the outer-most deviation levels) is always 3x the inner deviation.
  - There are 24 unique ways in which pairs of bits may be mapped to the four deviation levels. These methods are enumerated below. The coding of the enumerations is read (left to right) as: -3ΔF, -1ΔF, +1ΔF, and +3ΔF.
  - Using MODEM_FSK4_MAP = 0x00 as an example, the bit pair '00' would be mapped to the -3ΔF level, the bit pair '01' would be mapped to the -1ΔF level, the bit pair '11' to the +1ΔF level, and the '10' bit pair to the +3ΔF level.
  - It is important that the TX and RX sides of the link use the same 4(G)FSK symbol mapping, else establishment of the link may not be possible. Also, test equipment vendors may not all use the same default symbol mapping; settings that work with one piece of lab test equipment may not work with another.
- Default: 0x00
- Register View:

| MODEM_FSK4_MAP
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x3f | 4FSKMAP
| Default
| 0x0

- Field Details:

  ###### MODEM_FSK4_MAP

  4FSKMAP[7:0]
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | `00 `01 `11 `10 |
    ENUM_1 | 1 | `00 `01 `10 `11 |
    ENUM_2 | 2 | `00 `11 `01 `10 |
    ENUM_3 | 3 | `00 `11 `10 `01 |
    ENUM_4 | 4 | `00 `10 `01 `11 |
    ENUM_5 | 5 | `00 `10 `11 `01 |
    ENUM_6 | 6 | `01 `00 `11 `10 |
    ENUM_7 | 7 | `01 `00 `10 `11 |
    ENUM_8 | 8 | `01 `11 `00 `10 |
    ENUM_9 | 9 | `01 `11 `10 `00 |
    ENUM_10 | 10 | `01 `10 `00 `11 |
    ENUM_11 | 11 | `01 `10 `11 `00 |
    ENUM_12 | 12 | `11 `00 `01 `10 |
    ENUM_13 | 13 | `11 `00 `10 `01 |
    ENUM_14 | 14 | `11 `01 `00 `10 |
    ENUM_15 | 15 | `11 `01 `10 `00 |
    ENUM_16 | 16 | `11 `10 `00 `01 |
    ENUM_17 | 17 | `11 `10 `01 `00 |
    ENUM_18 | 18 | `10 `00 `01 `11 |
    ENUM_19 | 19 | `10 `00 `11 `01 |
    ENUM_20 | 20 | `10 `01 `00 `11 |
    ENUM_21 | 21 | `10 `01 `11 `00 |
    ENUM_22 | 22 | `10 `11 `00 `01 |
    ENUM_23 | 23 | `10 `11 `01 `00 |

#### MODEM_OOK_PDTC

- Group: 0x20
- Index: 0x40

- Summary: Configures the attack and decay times of the OOK Peak Detector.
- Purpose:
  - The chip provides two different methods of developing the slicing reference level for demodulation of an OOK signal: Peak Detection, and a Moving Average Filter. This property configures the attack and decay times of the OOK peak detector.
  - The rate at which the peak detector charges or discharges is proportional to 2-ATTACK or 2-DECAY. As a result, larger values of the ATTACK and DECAY parameters result in slower attack and decay times, respectively.
  - Please refer to MODEM_OOK_MISC for more details regarding configuration of the detector(s) used in OOK demodulation.
- Default: 0x2b
- Register View:

| MODEM_OOK_PDTC
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x40 | 0 | ATTACK | DECAY
| Default
| 0x0 | 0x2 | 0xb

- Field Details:

  ###### MODEM_OOK_PDTC

  ATTACK[2:0]
  Description:
    Selection of the attack time of the OOK peak detector. The peak detector charges at a rate proportional to 2-ATTACK.
  Min:
    0x0
  Max:
    0x7
  Default:
    0x2
  DECAY[3:0]
  Description:
    Selection of the decay time of the OOK peak detector. The peak detector discharges at a rate proportional to 2-DECAY.
  Min:
    0x0
  Max:
    0xf
  Default:
    0xb

#### MODEM_OOK_BLOPK

- Group: 0x20
- Index: 0x41

- Summary: Configures the slicing reference level of the OOK Peak Detector.
- Purpose:
  - The chip provides two different methods of developing the slicing reference level for demodulation of an OOK signal: Peak Detection, and a Moving Average Filter. This property configures the slicing reference level of the OOK peak detector.
  - The slicing reference level is defined as a selectable number of dB below the peak measured signal level.
- Default: 0x0c
- Register View:

| MODEM_OOK_BLOPK
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x41 | BW_PK
| Default
| 0xc

- Field Details:

  ###### MODEM_OOK_BLOPK

  BW_PK[7:0]
  Description:
    Sets the slicing reference level of the OOK peak detector at a selectable number of dB below the peak measured level.
  Min:
    0x0
  Max:
    0xff
  Default:
    0xc

#### MODEM_OOK_CNT1

- Group: 0x20
- Index: 0x42

- Summary: OOK control.
- Purpose:
  - OOK control.
- Default: 0xa4
- Register View:

| MODEM_OOK_CNT1
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x42 | S2P_MAP | OOKFRZEN | MA_FREQDWN | RAW_SYN | SLICER_FAST | SQUELCH
| Default
| 0x2 | 0x1 | 0x0 | 0x0 | 0x1 | 0x0

- Field Details:

  ###### MODEM_OOK_CNT1

  S2P_MAP[1:0]
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | S2p_mapping 0. |
    ENUM_1 | 1 | S2p_mapping 1. |
    ENUM_2 | 2 | S2p_mapping 2. |
    ENUM_3 | 3 | S2p_mapping 3. |

  OOKFRZEN
  Description:
    This bit only has an effect after preamble is detected.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Normal. |
    ENUM_1 | 1 | AGC and OOK moving average detector's threshold output will be frozen after the preamble is detected. |

  MA_FREQDWN
  Description:
    - If set, estimated frequency from MA detector will be trunked 4 bits to avoid overflow.
    - AFC gain should be increased 16 times if this bit is set.
    - It is recommended to set this bit for Rb smaller than 1kbps and/or hModInd greater than 50 if MA detector's frequency error estimator is selected.
  Default:
    0x0
  RAW_SYN
  Description:
    If set, raw data output is synchronized to bit clock.
  Default:
    0x0
  SLICER_FAST
  Description:
    This bit effects 2(G)FSK/OOK mode only.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Discriminator's slicer output is de-glitched by bit clock. |
    ENUM_1 | 1 | Discriminator's slicer output is de-glitched by sample clock to reduce turn-around time. |

  SQUELCH[1:0]
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Squelch function is off. |
    ENUM_1 | 1 | When no signal is received, there is no toggling of RX data output. |
    ENUM_2 | 2 | When PM is not detected, there is no toggling of RX data output. |
    ENUM_3 | 3 | When no signal or PM is not detected, there is no toggling of RX data output. |

#### MODEM_OOK_MISC

- Group: 0x20
- Index: 0x43

- Summary: Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
- Purpose:
  - The chip internally implements two different types of demodulator circuits: a synchronous demodulator and an asynchronous demodulator. The synchronous demodulator is typically used for reception of (G)FSK signals with a standard Preamble and packet structure, while the asynchronous demodulator is typically used for reception of (G)FSK signals with non-standard Preamble and packet structures, as well as for all OOK signals.
  - Within the asynchronous demodulator, several different types of detectors may be selected to establish the voltage reference level for slicing the received data bits.
  - This property is used to select among the following types of detectors: a moving average filter, a peak detector, and a min-max detector.
  - The moving average filter detector establishes the slicing threshold level based upon the average of the previous data bits, and thus works best when the data stream is balanced and contains numerous bit transitions (e.g., a Preamble pattern or Manchester-coded data). This type of detector may be used with both OOK and (G)FSK signals.
  - The peak detector establishes the slicing threshold level as a selectable number of dB below the peak measured signal level. This type of detector is applicable only for OOK signals.
  - The min-max detector establishes the slicing threshold level as the mid-point between the maximum and minimum detected frequency deviation levels. This type of detector is applicable only for (G)FSK signals.
- Default: 0x03
- Register View:

| MODEM_OOK_MISC
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x43 | OOKFASTMA | 0 | OOK_LIMIT_DISCHG | OOK_SQUELCH_EN | OOK_DISCHG_DIV | DETECTOR
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x3

- Field Details:

  ###### MODEM_OOK_MISC

  OOKFASTMA
  Description:
    - Selects whether the length of the moving average filter window (used to establish the slicing threshold value from the previous data bits) is as specified directly by the MODEM_RAW_SEARCH property, or the value in MODEM_RAW_SEARCH is effectively increased by 2x.
    - This bit is effective only when demodulating an OOK signal, and allows trading off accuracy of the slicing threshold with response time to the first bit(s) of the OOK packet.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    NORMAL_MA_WINDOW | 0 | Normal. |
    LONG_MA_WINDOW | 1 | Deploy longer MA filter window. |

  OOK_LIMIT_DISCHG
  Description:
    Configures if the peak detector discharge is limited.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ALWAYS_DISCHG | 0 | Peak detector discharges always. |
    LIMIT_DISCHG | 1 | Peak detector discharge is disabled when the detected peak is lower than the input signal for low input levels. |

  OOK_SQUELCH_EN
  Description:
    When set, squelches the RXDATA bit stream output in real-time on a selected GPIO pin until signal arrival is detected. This squelch functionality is only applicable when demodulating an OOK signal.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DISABLED | 0 | Disable OOK Squelch functionality.. |
    ENABLED | 1 | Enable OOK Squelch functionality.. |

  OOK_DISCHG_DIV[1:0]
  Description:
    OOK Peak Detector discharge divider.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    NO_DISCHG_DIV | 0 | Does not affect OOK decay rate specified in decay[3:0] in MODEM_OOK_PDTC. |
    DISCHG_HALF | 1 | OOK PK Detector discharges at half of the OOK decay rate specified in decay[3:0] in MODEM_OOK_PDTC. |
    DISCHG_QUARTER | 2 | OOK PK Detector discharges at a quarter of the OOK decay rate specified in decay[3:0] in MODEM_OOK_PDTC. |
    DISCHG_EIGHTH | 3 | OOK PK Detector discharges at an 8th of the decay rate specified in decay[3:0] in MODEM_OOK_PDTC. |

  DETECTOR[1:0]
  Description:
    Selects the type of detector used to establish the slicing threshold for asynchronous demodulation of the data.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    MA_PK | 0 | Both the peak detector and the moving average filter detector are used; the outputs of the two detectors are logically AND'ed together to provide the final RX data stream. This option is applicable only when demodulating an OOK signal. |
    PK | 1 | PThe peak detector is selected to establish the slicing threshold level. Selection of the peak detector is only applicable when demodulating an OOK signal. The attack and decay times of the peak detector are controlled through the MODEM_OOK_PDTC property. |
    MA | 2 | The moving average filter detector is selected to establish the slicing threshold level. Selection of the MA filter detector is appropriate for demodulation of either an OOK signal or a (G)FSK signal with an unconventional (i.e., "legacy") packet structure. The MA filter window length is configured through the MODEM_RAW_SEARCH property. |
    MEAN | 3 | The min-max detector is selected to establish the slicing threshold level as the mid-point between the measured extreme frequency deviation levels. Selection of the min-max detector is applicable when demodulating a (G)FSK signal with an unconventional (i.e., "legacy") packet structure. The search window length (over which the min-max frequency values are measured) is configured through the MODEM_RAW_SEARCH property. |

#### MODEM_RAW_CONTROL

- Group: 0x20
- Index: 0x45

- Summary: Defines gain and enable controls for raw / nonstandard mode.
- Purpose:
  - Defines gain and enable controls for raw / nonstandard mode.
- Default: 0x02
- Register View:

| MODEM_RAW_CONTROL
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x45 | UNSTDPK | CONSCHK_BYP | 0 | 0 | PM_PATTERN | RAWGAIN
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x2

- Field Details:

  ###### MODEM_RAW_CONTROL

  UNSTDPK
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Standard packet mode. |
    ENUM_1 | 1 | MA or mean frequency error estimator. |

  CONSCHK_BYP
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | If unstdpk is '1', and conschk_byp= '0', the consecutive '1' or '0' of payload data during 'Sch_Period' will stop the mean value being updated. |
    ENUM_1 | 1 | Normal. |

  PM_PATTERN[1:0]
  Description:
    PM pattern configuration. The preamble detection is done inside modem.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    1010 | 0 | If preamble has '1010' pattern, modem is recommended to work on standard packet mode. |
    CONSECUTIVE_ONE | 1 | If preamble has more than 32-bit consecutive '1' pattern, modem is recommended to work on un-standard packet mode. |
    CONSECUTIVE_ZERO | 2 | If preamble has more than 32-bit consecutive '0' pattern, modem is recommended work on un-standard packet mode. |
    RANDOM | 3 | If preamble is random data, modem is recommended to work on un-standard packet mode. |

  RAWGAIN[1:0]
  Description:
    Raw data MA filter gain.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Gain = 8. |
    ENUM_1 | 1 | Gain = 4. |
    ENUM_2 | 2 | Gain = 2. |
    ENUM_3 | 3 | Gain = 1. |

#### MODEM_RAW_EYE

- Group: 0x20
- Indexes: 0x46 ... 0x47

- Summary: 11 bit eye-open detector threshold.
- Purpose:
  - 11 bit eye-open detector threshold.
- Defaults: 0x00,0xa3
- Register View:

| MODEM_RAW_EYE
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x46 | 0 | 0 | 0 | 0 | 0 | RAWEYE[10:8]
0x47 | RAWEYE[7:0]
| Defaults
0x46 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0
0x47 | 0xa3

- Field Details:

  ###### MODEM_RAW_EYE

  RAWEYE[10:0]
  Description:
    Eye-open detector threshold.
  Default:
    0xa3

#### MODEM_RAW_SEARCH2

- Group: 0x20
- Index: 0x50

- Summary: Defines and controls the search period length for the Moving Average and Min-Max detectors.
- Purpose:
  - The chip internally implements two different types of demodulator circuits: a synchronous demodulator and an asynchronous demodulator. The synchronous demodulator is typically used for reception of (G)FSK signals with a standard Preamble and packet structure, while the asynchronous demodulator is typically used for reception of (G)FSK signals with non-standard Preamble and packet structures, as well as for all OOK signals.
  - Within the asynchronous demodulator, several different types of detectors may be selected to establish the voltage reference level for slicing the received data bits, including a moving average filter, a peak detector, and a min-max detector. The type of detector used in the asynchronous demodulator is selected in the MODEM_OOK_MISC property.
    The moving average filter and min-max detectors both establish the slicing threshold level based upon the values of the previous data bits. This property is used to configure the number of previous data bits (i.e., search window length) over which the moving average and min-max detectors establish the slicing threshold level.
  - The search period length may be configured for different values before gear switching and after gear switching. A shorter search period window is typically selected prior to gear switching, as the Preamble field usually contains regular bit transitions and fast acquisition is desirable. A longer search period window is typically selected after gear switching, as the Payload fields may contain highly unbalanced data and irregular bit transitions; as a result, a longer search period may be required to capture both polarities of data bits for accurate establishment of the slicing threshold level.
  - Alternatively, the slicing threshold search engine may be "frozen" upon gear switching, such that no further adjustments to the slicing threshold level are made across the remainder of the packet.
- Default: 0x00
- Register View:

| MODEM_RAW_SEARCH2
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x50 | SCH_FRZEN | RAWFLT_SEL | SCHPRD_HI | SCHPRD_LOW
| Default
| 0x0 | 0x0 | 0x0 | 0x0

- Field Details:

  ###### MODEM_RAW_SEARCH2

  SCH_FRZEN
  Description:
    Selects whether the Moving Average or Min-Max slicing threshold search engine is frozen upon gear switching.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DISABLED | 0 | Do not freeze the Moving Average or Min-Max slicing threshold search engine upon switching to low gear. |
    ENABLED | 1 | Freeze the Moving Average or Min-Max slicing threshold search engine upon switching to low gear. |

  RAWFLT_SEL
  Description:
    If set, enable 4-tap MA for raw data filter.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DISABLED | 0 | Disable raw data filter to use the 4-tap MA filter.. |
    ENABLED | 1 | Enable raw data filter to use the 4-tap MA filter.. |

  SCHPRD_HI[2:0]
  Description:
    Selects the search period window length (in bit periods) over which the Moving Average filter or Min-Max detector establishes the slicing threshold level, prior to gear switching (i.e., during high gear).
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    SEARCH_2TB | 0 | Search window period = 2*TB |
    SEARCH_3TB | 1 | Search window period = 3*TB |
    SEARCH_4TB | 2 | Search window period = 4*TB |
    SEARCH_5TB | 3 | Search window period = 5*TB |
    SEARCH_8TB | 4 | Search window period = 8*TB |
    SEARCH_12TB | 5 | Search window period = 12*TB |
    SEARCH_14TB | 6 | Search window period = 14*TB |
    SEARCH_16TB | 7 | Search window period = 16*TB |

  SCHPRD_LOW[2:0]
  Description:
    Selects the search period window length (in bit periods) over which the Moving Average filter or Min-Max detector establishes the slicing threshold level, after gear switching (i.e., during low gear).
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    SEARCH_2TB | 0 | Search window period = 2*TB |
    SEARCH_3TB | 1 | Search window period = 3*TB |
    SEARCH_4TB | 2 | Search window period = 4*TB |
    SEARCH_5TB | 3 | Search window period = 5*TB |
    SEARCH_8TB | 4 | Search window period = 8*TB |
    SEARCH_12TB | 5 | Search window period = 12*TB |
    SEARCH_14TB | 6 | Search window period = 14*TB |
    SEARCH_16TB | 7 | Search window period = 16*TB |

#### MODEM_CLKGEN_BAND

- Group: 0x20
- Index: 0x51

- Summary: Select PLL Synthesizer output divider ratio as a function of frequency band.
- Purpose:
  - Selects the divide ratio of the configurable divider at the output of the PLL Synthesizer as a function of the desired operating frequency band.
  - Configures the PLL Synthesizer for High Performance or Low Power operating mode, allowing a tradeoff between tuning resolution and current consumption.
- Default: 0x08
- Register View:

| MODEM_CLKGEN_BAND
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x51 | 0 | 0 | 0 | FORCE_SY_RECAL | SY_SEL | BAND
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0x1 | 0x0

- Field Details:

  ###### MODEM_CLKGEN_BAND

  FORCE_SY_RECAL
  Description:
    Controls whether synthesizer recalibration is forced during state transitions if the frequency is not changed. e.g. RX to RX between packets on the same frequency.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    FORCE | 0 | Force Recalibration. |
    SKIP | 1 | Skip recalibration if frequency is not changed. |

  SY_SEL
  Description:
    Selects the value of the fixed prescaler modulus in the PLL divider feedback path, allowing a tradeoff between improved tuning resolution and synthesizer quantization noise at the expense of slightly increased current consumption. The published formula for calculating FREQ_CONTROL_INTE and FREQ_CONTROL_FRAC assumes this bit is set to '1'; contact Silicon Labs for assistance with frequency calculations when clearing this bit.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Low-power mode (fixed prescaler = Div-by-4). Approximately 200 uA less current than High Performance mode, but with coarser tuning resolution of the PLL Synthesizer. |
    ENUM_1 | 1 | High Performance mode (fixed prescaler = Div-by-2). |

  BAND[2:0]
  Description:
    Selects the PLL Synthesizer output divider ratio appropriate for the desired frequency band. The VCO in the PLL Synthesizer operates at approximately 3.6 GHz; operation across a wide range of frequency bands is obtained by switching in a configurable divider (OUTDIV) at the output of the PLL Synthesizer, e.g., OUTDIV = Div-by-4 for 900 MHz band.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    FVCO_DIV_4 | 0 | Output is FVCO/4. |
    FVCO_DIV_6 | 1 | Output is FVCO/6. |
    FVCO_DIV_8 | 2 | Output is FVCO/8. |
    FVCO_DIV_12 | 3 | Output is FVCO/12. |
    FVCO_DIV_16 | 4 | Output is FVCO/16. |
    FVCO_DIV_24 | 5 | Output is FVCO/24. |
    FVCO_DIV_24_2 | 6 | Output is FVCO/24. |
    FVCO_DIV_24_3 | 7 | Output is FVCO/24. |

#### MODEM_SPIKE_DET

- Group: 0x20
- Index: 0x54

- Summary: Configures the threshold for (G)FSK Spike Detection.
- Purpose:
  - Refer to MODEM_DSA_CTRL1 for an overview of the Signal Arrival Detection (DSA) funciton.
  - The DSA circuit contains a block that calculates the difference in phase between adjacent samples in the RX Modem; an excessive difference in the phase of adjacent samples is equivalent to a "spike" in the frequency domain and indicates a noisey or weak signal. This property is used to configure the threshold above which an excessive phase difference is considered a spike.
  - The DSA algorithm counts the number of spikes over a programmable search period of time; the signal is considered to have arrived if the spike count value is less than a programmable tolerance limit. THe tolerance limit is set in MODEM_DSA_CTRL1:ADJ_SAMP_ERR_TOLERANCE, while the length and number of search period windows is set in MODEM_RAW_SEARCH:SCHPRD_HI and MODEM_DSA_CTRL2:ARRIVAL_THD.
  - This property also allows for rmoval of such detected spikes from teh signal path. When enabled, the Modem replaces the "spike" frequency data sample with a value that is interpolated from the frequency samples on either side of the spike.
  - This property is only applicable when receiving a (G)FSK signal and should not be used when receiving an OOK signal.
- Default: 0x00
- Register View:

| MODEM_SPIKE_DET
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x54 | SPIKE_REMOVAL_EN | SPIKE_THRESHOLD
| Default
| 0x0 | 0x0

- Field Details:

  ###### MODEM_SPIKE_DET

  SPIKE_REMOVAL_EN
  Description:
    Enable/Disable bit for the Sike Removal function for (G)FSK signals. When enabled, the RX Modem replaces the frequency sample for the detected "spike" with a value that is interpolated from data samples on either side of the spike.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DISABLED | 0 | Disable (G)FSK Spike Removal Function. |
    ENABLED | 1 | Enable (G)FSK Spike Removal Function. |

  SPIKE_THRESHOLD[6:0]
  Description:
    This parameter sets the threshold of phase difference between adjacent samples in the RX Modem, above which the phase difference is considered excessive and to be a "spike". The required value for this parameter depends heavily on RX Modem parameters such as data rate, deviation, and over-sampling rate; Silicon Laboratories recommends use of the value suggested by WDS.
  Default:
    0x0

### PA

#### PA_MODE

- Group: 0x22
- Index: 0x00

- Summary: Selects the PA operating mode, and selects resolution of PA power adjustment (i.e., step size).
- Purpose:
  - The PA output circuit is designed to operate as either a switching-type amplifier, or as a switched programmable current source.
  - This property selects the operating mode of the PA. A switching-type amplifier (matched for Class-E or Square Wave operation) will typically provide higher output power and better current efficiency, while a switched current amplifier will typically provide more linear control of output power and better power flatness over variations in VDD supply voltage.
  - The output power level is configured through the PA_PWR_LVL property and (when operating in Switched Current mode) the PA_BIAS_CLKDUTY property.
  - The chip provides a signal on the TXRAMP pin for ramping control of an external PA. This signal may be enabled/disabled through the EXT_PA_RAMP bit in this property; configuration of the external ramping signal itself is provided in the PA_RAMP_EX property.
  - The different chips within the Si446x family (e.g., Si4460/61/63/64) contain a variety of sizes and groups of PA output devices. These are selected to obtain the desired output power level and power adjustment step size. This configuration is automatically handled inside the chip according to chip type; the PA_SEL field does not need to be configured to obtain proper operation of the PA. However, there is no harm in continuing to set this parameter to the value(s) suggested by WDS.
- Default: 0x08
- Register View:

| PA_MODE
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x00 | EXT_PA_RAMP | 0 | PA_SEL | 0 | PA_MODE
| Default
| 0x0 | 0x0 | 0x2 | 0x0 | 0x0

- Field Details:

  ###### PA_MODE

  EXT_PA_RAMP
  Description:
    - When set, enables a signal on the TXRAMP pin for ramping control of an external PA.
    - The characteristics of the external ramping signal are configured through the PA_RAMP_EX property.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Disable external TX ramp signal. |
    ENUM_1 | 1 | Enable external TX ramp signal. |

  PA_SEL[3:0]
  Description:
    - Selects the appropriate groups and sizes of PA output devices to obtain the desired output power level and power adjustment step size, according to chip type.
    - Use of enumerations other than those listed below are not recommended.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    HP_FINE | 1 | Si4463/64: lower maximum power but with finer step size (~2x). |
    HP_COARSE | 2 | Si4463/64: higher maximum power but with larger step size. |
    LP | 6 | Si4460: lower-power applications. |
    MP | 8 | Si4461: medium-power applications. |

  PA_MODE
  Description:
    Selects the operating mode of the PA.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    CLE | 0 | Switching-Amplifier Mode (for Class-E or Square Wave match). |
    SWC | 1 | Switched Current Mode. |

#### PA_PWR_LVL

- Group: 0x22
- Index: 0x01

- Summary: Configuration of PA output power level.
- Purpose:
  - The PA circuitry in the chip contains an output device whose size may be adjusted by enabling/disabling different numbers of device fingers. Selection of a higher value results in an increase in TX output power.
  - The relationship between output power and the number of enabled device fingers is not necessarily linear, and is dependent upon the PA mode of operation (e.g., Class-E or Switched Current), the duty cycle of the drive signal to the output circuit, the VDD supply voltage, and the output match. As a result, there is no simple formula to relate the setting of the PA_PWR_LVL property to an absolute value of output power in dBm.
  - The adjustment resolution of the TX output power is very fine (step size < 0.1 dB) when operating near the maximum power setting, but becomes coarser as the output power level is reduced.
- Default: 0x7f
- Register View:

| PA_PWR_LVL
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x01 | 0 | DDAC
| Default
| 0x0 | 0x7f

- Field Details:

  ###### PA_PWR_LVL

  DDAC[6:0]
  Description:
    Selects the number of enabled output device fingers, with a larger value resulting in increased output power.
  Min:
    0x0
  Max:
    0x7f
  Default:
    0x7f

#### PA_BIAS_CLKDUTY

- Group: 0x22
- Index: 0x02

- Summary: Configuration of the PA Bias and duty cycle of the TX clock source.
- Purpose:
  - The PA output circuit is designed to operate as either a switching-type amplifier, or as a switched programmable current source. The PA mode of operation is selected through the PA_MODE property; the bias current (when operated as a switched programmable current source) and the duty cycle of the driving TX clock source are selected through this property.
- Default: 0x00
- Register View:

| PA_BIAS_CLKDUTY
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x02 | CLK_DUTY | OB
| Default
| 0x0 | 0x0

- Field Details:

  ###### PA_BIAS_CLKDUTY

  CLK_DUTY[1:0]
  Description:
    - This parameter adjusts the drive mode (single-ended or complementary) and duty cycle of the TX clock source to the PA output devices.
    - Silicon Labs recommends use of the modes listed below, as they have been optimized for the listed chips and associated output power levels.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    DIFF_50 | 0 | Complementary drive signals, 50% duty cycle. Recommended for use with Si4463/Si4464 high-power (e.g., +20dBm)applications, and as an option for Si4461 medium-power (e.g., +13 to +16 dBm) applications. |
    SINGLE_25 | 3 | Single-ended drive signal, 25% duty cycle. Recommended for use with Si4460 low-power (e.g., +10 to +13 dBm, or lower) applications, and as an option for Si4461 medium-power (e.g., +13 to +16 dBm) applications. |

  OB[5:0]
  Description:
    - When the PA is configured for the Switched Current mode of operation, the output devices act as programmable current sources. The current sources are switched ON and OFF at the RF frequency by the driving signal selected by the CLK_DUTY parameter, thus delivering pulses of programmable current to the load.
    - This parameter selects the amount of bias current per enabled output device finger. The total number of enabled output device fingers is selected by the PA_PWR_LVL property, and thus the total PA bias current is equal to Bias_Current_per_Finger * Number_Enabled_Fingers.
    - The step size of this parameter is in increments of 10 µA. There is a fixed 10 µA bias current added to the value selected by this field (e.g., OB = 0 = 10µA, OB = 1 = 20µA, etc.)
    - This parameter has no effect when PA_MODE = Switching Amplifier.
  Min:
    0x0
  Max:
    0x3f
  Default:
    0x0

#### PA_TC

- Group: 0x22
- Index: 0x03

- Summary: Configuration of PA ramping parameters.
- Purpose:
  - The chip provides for PA power ramping in order to minimize spectral splatter and switching transients.
  - The TC value specifies the time constant for the ramping of both the rising and falling edges of the PA power. This time constant is applicable to both the rising and falling edges of the TX packet in (G)FSK mode, as well as to individual data bits in OOK mode. It is difficult to precisely define the ramp time as different measurement methods may be used (e.g., 10% to 90% rise time, to within 1dB of final value, etc.) However, the approximate ramp time is given by the following table:

  - The FSK_MOD_DLY value specifies an additional delay period from the rising edge of the PA ramp to the first bit of the (G)FSK modulation. It is configurable over the range of 2 to 30 usec in increments of 4 usec, and is added to an intrinsic modulation delay of approximately 3 bits/symbols.
  - The purpose of the FSK_MOD_DLY parameter is to ensure that the (G)FSK modulation does not begin before the PA power ramping has been completed. In (G)FSK mode, the value of FSK_MOD_DLY should be programmed to work well with the selected value of TC. The FSK_MOD_DLY parameter has no effect in OOK mode.
- Default: 0x5d
- Register View:

| PA_TC
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x03 | FSK_MOD_DLY | TC
| Default
| 0x2 | 0x1d

- Field Details:

  ###### PA_TC

  FSK_MOD_DLY[2:0]
  Description:
    In (G)FSK mode this specifies an additional delay from the rising edge of the PA ramp to the start of the (G)FSK modulation.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    2_US | 0 | Start of (G)FSK modulation is delayed by an additional 2µsec |
    6_US | 1 | Start of (G)FSK modulation is delayed by an additional 6µsec |
    10_US | 2 | Start of (G)FSK modulation is delayed by an additional 10µsec |
    14_US | 3 | Start of (G)FSK modulation is delayed by an additional 14µsec |
    18_US | 4 | Start of (G)FSK modulation is delayed by an additional 18µsec |
    22_US | 5 | Start of (G)FSK modulation is delayed by an additional 22µsec |
    26_US | 6 | Start of (G)FSK modulation is delayed by an additional 26µsec |
    30_US | 7 | Start of (G)FSK modulation is delayed by an additional 30µsec |

  TC[4:0]
  Description:
    Specifies the time constant for the ramping of both the rising and falling edges of the PA power.
  Min:
    0x0
  Max:
    0x1f
  Default:
    0x1d

#### PA_RAMP_EX

- Group: 0x22
- Index: 0x04

- Summary: Select the time constant of the external PA ramp signal.
- Purpose:
  - The chip provides a signal on the TXRAMP pin for ramping control of an external PA. This property selects the ramp time constant of the TXRAMP signal. The signal may be enabled/disabled through the EXT_PA_RAMP bit in the PA_MODE property.
  - The time constant of the ramp signal is determined by the following formula:

  - The amplitude range of the TXRAMP signal is fixed at ramping from 0V to 3.0V. In the event the VDD supply voltage to the chip is reduced, the upper voltage limit of the TXRAMP signal will be approximately VDD - 0.1V.
  - This property does not affect the ramp time constant of the internal PA.
- Default: 0x80
- Register View:

| PA_RAMP_EX
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x04 | 0000 | TC
| Default
| 0x8 | 0x0

- Field Details:

  ###### PA_RAMP_EX

  TC[3:0]
  Description:
    - Selects the ramp time (both up and down) of the external PA ramp signal on the TXRAMP pin.
    - The ramp time is determined by the formula:

  Min:
    0x0
  Max:
    0xf
  Default:
    0x0

#### PA_RAMP_DOWN_DELAY

- Group: 0x22
- Index: 0x05

- Summary: Delay from the start of the PA ramp down to disabling of the PA output.
- Purpose:
  - The ramp time constant selected by the PA_TC:TC field controls the ramping of an analog bias voltage applied to the PA output device(s). The RF drive signal to the PA output devices must remain active until the completion of the ramp-down process, else the ramp-down waveform would terminate abruptly. This property delays the complete shut-down of the PA block until the analog ramp-down is complete.
  - The units of this parameter are in µsec. This delay time must be greater than or equal to the ramp time specified by PA_TC:TC, but must not be greater than RAMP_DOWN_DELAY = 0x28 = 40. For most applications, it is acceptable to leave this property at its default value.
  - This property has no effect upon the ramp-up process.
- Default: 0x23
- Register View:

| PA_RAMP_DOWN_DELAY
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x05 | RAMP_DOWN_DELAY
| Default
| 0x23

- Field Details:

  ###### PA_RAMP_DOWN_DELAY

  RAMP_DOWN_DELAY[7:0]
  Description:
    Selects the delay time (in µsec) between the start of the ramp-down process and the disabling of the PA output.
  Min:
    0x1
  Max:
    0x28
  Default:
    0x23

### SYNTH

#### SYNTH_PFDCP_CPFF

- Group: 0x23
- Index: 0x00

- Summary: Feed forward charge pump current selection.
- Purpose:
  - The charge pump and loop filter in the PLL Synthesizer have two paths: an integral path and a feed-forward path. This property adjusts the charge pump gain (i.e., current) for the feed-forward path.
  - The coding of the MSB (bit 5) of the CP_FF_CUR field is inverted. As a result, the minimum charge pump gain setting is obtained for a value of CP_FF_CUR=0x20, while CP_FF_CUR=0x00 corresponds to a mid-range charge pump gain setting and 0x1F corresponds to the maximum charge pump gain setting.
  - The step size or resolution of the charge pump feed-forward current is in increments of 5 uA. Thus the range of values provided by the CP_FF_CUR field is from 0 uA to 315 uA.
  - CP_FF_CUR_TEST is a test bit and is not recommended for general customer applications. The CP_FF_CUR_TEST bit is not binary-weighted with the CP_FF_CUR field but instead provides an additional 160 uA, when set.
  - NOTE: the primary purpose of the SYNTH group of properties is to adjust the PLL loop bandwidth to a value appropriate for the selected data rate. Silicon Labs does not recommend modifying these properties away from the values suggested by the WDS Calculator.
- Default: 0x2c
- Register View:

| SYNTH_PFDCP_CPFF
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x00 | 0 | CP_FF_CUR_TEST | CP_FF_CUR
| Default
| 0x0 | 0x0 | 0x2c

- Field Details:

  ###### SYNTH_PFDCP_CPFF

  CP_FF_CUR_TEST
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Do not increase charge pump current. Use value defined in CP_FF_CUR. |
    ENUM_1 | 1 | Increase charge pump current defined in CP_FF_CUR by 160 uA. |

  CP_FF_CUR[5:0]
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_32 | 32 | 0 uA. |
    ENUM_33 | 33 | 5 uA. |
    ENUM_64 | 63 | 155 uA. |
    ENUM_0 | 0 | 160 uA. |
    ENUM_1 | 1 | 165 uA. |
    ENUM_31 | 31 | 315 uA. |

#### SYNTH_PFDCP_CPINT

- Group: 0x23
- Index: 0x01

- Summary: Integration charge pump current selection.
- Purpose:
  - The charge pump and loop filter in the PLL Synthesizer have two paths: an integral path and a feed-forward path. This property adjusts the charge pump gain (i.e., current) for the integral path.
  - The coding of the MSB (bit 3) of the CP_INT_CUR field is inverted. As a result, the minimum charge pump gain setting is obtained for a value of CP_INT_CUR=0x08, while CP_INT_CUR=0x00 corresponds to a mid-range charge pump gain setting and 0x07 corresponds to the maximum charge pump gain setting.
  - The step size or resolution of the charge pump feed-forward current is in increments of 5 uA. Thus the range of values provided by the CP_INT_CUR field is from 0 uA to 75 uA.
  - NOTE: the primary purpose of the SYNTH group of properties is to adjust the PLL loop bandwidth to a value appropriate for the selected data rate. Silicon Labs does not recommend modifying these properties away from the values suggested by the WDS Calculator.
- Default: 0x0e
- Register View:

| SYNTH_PFDCP_CPINT
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x01 | 0 | 0 | 0 | 0 | CP_INT_CUR
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0xe

- Field Details:

  ###### SYNTH_PFDCP_CPINT

  CP_INT_CUR[3:0]
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_8 | 8 | 0 uA. |
    ENUM_9 | 9 | 5 uA. |
    ENUM_10 | 10 | 10 uA. |
    ENUM_11 | 11 | 15 uA. |
    ENUM_12 | 12 | 20 uA. |
    ENUM_13 | 13 | 25 uA. |
    ENUM_14 | 14 | 30 uA. |
    ENUM_15 | 15 | 35 uA. |
    ENUM_0 | 0 | 40 uA. |
    ENUM_1 | 1 | 45 uA. |
    ENUM_2 | 2 | 50 uA. |
    ENUM_3 | 3 | 55 uA. |
    ENUM_4 | 4 | 60 uA. |
    ENUM_5 | 5 | 65 uA. |
    ENUM_6 | 6 | 70 uA. |
    ENUM_7 | 7 | Maximum 75 uA. |

#### SYNTH_VCO_KV

- Group: 0x23
- Index: 0x02

- Summary: Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
- Purpose:
  - The charge pump, loop filter, and VCO tuning varactors in the PLL Synthesizer have two paths: an integral path and a feed-forward path. This property adjusts the gain scaling factors (Kv) for the tuning varactors in both the integral path and the feed-forward path. The adjustment of the gain factors is accomplished internally by switching in different number of varactor devices.
  - NOTE: the primary purpose of the SYNTH group of properties is to adjust the PLL loop bandwidth to a value appropriate for the selected data rate. Silicon Labs does not recommend modifying these properties away from the values suggested by the WDS Calculator.
- Default: 0x0b
- Register View:

| SYNTH_VCO_KV
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x02 | 0 | 0 | 0 | RESERVED | KV_DIR | KV_INT
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0x2 | 0x3

- Field Details:

  ###### SYNTH_VCO_KV

  RESERVED
  Description:
    Reserved. Always write 0.
  Default:
    0x0
  KV_DIR[1:0]
  Description:
    Sets the scaling factor on the tuning varactor gain (Kv_dir) in the feed-forward path (i.e., direct path).
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    GND | 0 | Sets the feed-forward (i.e., direct) path tuning varactor input port of the VCO to GND (used only for testing purposes). |
    HALF | 1 | Sets kv_dir to 1/2 of its maximum value. |
    MAX | 2 | Sets kv_dir to its maximum value. |
    ENUM_3 | 3 | Sets kv_dir to its maximum value (same as kv_dir = 2). |

  KV_INT[1:0]
  Description:
    Sets the scaling factor on the tuning varactor gain (Kv_int) in the integral path.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    GND | 0 | Sets the integral path tuning varactor input port of the VCO to GND (used only for testing purposes). |
    33PERCENT | 1 | Sets kv_int to 1/3 of its maximum value. |
    66PENCENT | 2 | Sets kv_int to 2/3 of its maximum value. |
    MAX | 3 | Sets kv_int to its maximum value. |

#### SYNTH_LPFILT3

- Group: 0x23
- Index: 0x03

- Summary: Value of resistor R2 in feed-forward path of loop filter.
- Purpose:
  - The loop filter in the feed-forward path contains three lowpass filter poles: R1-C1, R2-C2, and R3-C3.
  - The LPF_FF_R2 field adjusts the value of resistor R2, and thus adjusts the cutoff frequency of the R2-C2 lowpass filter pole.
  - Additionally, the resistor R2 affects the DC gain of the transistor Gm stage in the feed-forward path. Increasing the value of R2 has the effect of increasing the feed-forward path gain.
  - The value of R2 is in increments of 18 kΩ, ranging from a minimum value of 18 kΩ to a maximum of 144 kΩ.
  - NOTE: the primary purpose of the SYNTH group of properties is to adjust the PLL loop bandwidth to a value appropriate for the selected data rate. Silicon Labs does not recommend modifying these properties away from the values suggested by the WDS Calculator.
- Default: 0x04
- Register View:

| SYNTH_LPFILT3
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x03 | 0 | 0 | 0 | 0 | 0 | LPF_FF_R2
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x4

- Field Details:

  ###### SYNTH_LPFILT3

  LPF_FF_R2[2:0]
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | R2 = 18 kΩ |
    ENUM_1 | 1 | R2 = 36 kΩ |
    ENUM_2 | 2 | R2 = 54 kΩ |
    ENUM_3 | 3 | R2 = 72 kΩ |
    ENUM_4 | 4 | R2 = 90 kΩ |
    ENUM_5 | 5 | R2 = 108 kΩ |
    ENUM_6 | 6 | R2 = 126 kΩ |
    ENUM_7 | 7 | R2 = 144 kΩ |

#### SYNTH_LPFILT2

- Group: 0x23
- Index: 0x04

- Summary: Value of capacitor C2 in feed-forward path of loop filter.
- Purpose:
  - The loop filter in the feed-forward path contains three lowpass filter poles: R1-C1, R2-C2, and R3-C3.
  - The LPF_FF_C2 field adjusts the value of capacitor C2, and thus adjusts the cutoff frequency of the R2-C2 lowpass filter pole.
  - The value of C2 is in increments of 335 fF, ranging from a minimum value of 877 fF to a maximum of 11.25 pF.
  - NOTE: the primary purpose of the SYNTH group of properties is to adjust the PLL loop bandwidth to a value appropriate for the selected data rate. Silicon Labs does not recommend modifying these properties away from the values suggested by the WDS Calculator.
- Default: 0x0c
- Register View:

| SYNTH_LPFILT2
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x04 | 0 | 0 | 0 | LPF_FF_C2
| Default
| 0x0 | 0x0 | 0x0 | 0xc

- Field Details:

  ###### SYNTH_LPFILT2

  LPF_FF_C2[4:0]
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | C2 = 877 fF. |
    ENUM_1 | 31 | C2 = 11.25 pF. |

#### SYNTH_LPFILT1

- Group: 0x23
- Index: 0x05

- Summary: Value of capacitors C1 and C3 in feed-forward path of loop filter.
- Purpose:
  - The loop filter in the feed-forward path contains three lowpass filter poles: R1-C1, R2-C2, and R3-C3.
  - The LPF_FF_C3 field adjusts the value of capacitor C3, and thus adjusts the cutoff frequency of the R3-C3 lowpass filter pole. The value of resistor R3 is not adjustable and is fixed at R3=2 kΩ.
  - The value of C3 is in increments of 1 pF, ranging from a minimum value of 9 pF to a maximum of 12 pF.
  - The total value of capacitor C1 is determined by a 3-bit binary-weighted field LPF_FF_C1 in increments of 380 fF, and a 2-bit offset field LPF_FF_C1_CODE in increments of 1 pF, plus an additional fixed capacitance of 4.55 pF. Thus the total value of capacitor C1 may be described by the following equation:
  - C1 = 4.55pF + 380fF*LPF_FF_C1 + 1pF*LPF_FF_C1_CODE
  - The value of resistor R1 is not adjustable and is fixed at R1=9.86 kΩ.
  - NOTE: the primary purpose of the SYNTH group of properties is to adjust the PLL loop bandwidth to a value appropriate for the selected data rate. Silicon Labs does not recommend modifying these properties away from the values suggested by the WDS Calculator.
- Default: 0x73
- Register View:

| SYNTH_LPFILT1
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x05 | 0 | LPF_FF_C1 | LPF_FF_C1_CODE | LPF_FF_C3
| Default
| 0x0 | 0x7 | 0x0 | 0x3

- Field Details:

  ###### SYNTH_LPFILT1

  LPF_FF_C1[2:0]
  Description:
    Sets the fine-tune value of C1 in increments of 380 fF, with a range from 4.55 pF to 7.21 pF.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | C1 = 4.55 pF. |
    ENUM_1 | 1 | C1 = 4.93 pF. |
    ENUM_2 | 2 | C1 = 5.31 pF. |
    ENUM_3 | 3 | C1 = 5.69 pF. |
    ENUM_4 | 4 | C1 = 6.07 pF. |
    ENUM_5 | 5 | C1 = 6.45 pF. |
    ENUM_6 | 6 | C1 = 6.83 pF. |
    ENUM_7 | 7 | C1 = 7.21 pF. |

  LPF_FF_C1_CODE[1:0]
  Description:
    Offsets the value of C1 in increments of 1pF, with a range of 0pF to 3pF.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | delta C1 = 0 pF. |
    ENUM_1 | 1 | delta C1 = 1 pF. |
    ENUM_2 | 2 | delta C1 = 2 pF. |
    ENUM_3 | 3 | delta C1 = 3 pF. |

  LPF_FF_C3[1:0]
  Description:
    Sets the value of C3 in increments of 1pF, with a range of 9pF to 12pF.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | C3 = 9 pF. |
    ENUM_1 | 1 | C3 = 10 pF. |
    ENUM_2 | 2 | C3 = 11 pF. |
    ENUM_3 | 3 | C3 = 12 pF. |

#### SYNTH_LPFILT0

- Group: 0x23
- Index: 0x06

- Summary: Bias current of the active amplifier in the feed-forward loop filter.
- Purpose:
  - The loop filter in the PLL Synthesizer consists of an integrator path and a feed-forward path. The feed-forward path consists of an active amplifier (a single transistor Gm stage) with three lowpass filter poles and one right-half plane zero.
  - This property selects the bias current of the active amplifier. Adjusting the bias current has the additional effect of changing the DC gain of the amplifier which in turn affects the PLL loop bandwidth and loop dynamics. The suggested settings for all other properties within the SYNTH group assume the default value of SYNTH_LPFILT0 = 0x03 = 100µA. In the event a different value of bias current is selected, it would become necessary to modify all other SYNTH properties in order to maintain the desired PLL loop bandwidth. For this reason, Silicon Labs recommends leaving this property at its default value.
- Default: 0x03
- Register View:

| SYNTH_LPFILT0
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x06 | 0 | 0 | 0 | 0 | 0 | 0 | LPF_FF_BIAS
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x3

- Field Details:

  ###### SYNTH_LPFILT0

  LPF_FF_BIAS[1:0]
  Description:
    Selects the bias current of the amplifier in the feed-forward loop filter path.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | 25 uA. |
    ENUM_1 | 1 | 34 uA. |
    ENUM_2 | 2 | 50 uA. |
    ENUM_3 | 3 | 100 uA. |

#### SYNTH_VCO_KVCAL

- Group: 0x23
- Index: 0x07

- Summary: Scaling entire KV of VCO.
- Purpose:
  - Scaling on VCO KV for all parameters.
- Default: 0x05
- Register View:

| SYNTH_VCO_KVCAL
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x07 | 0 | 0 | 0 | LADR_SELECT | KVCAL
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0x5

- Field Details:

  ###### SYNTH_VCO_KVCAL

  LADR_SELECT
  Description:
    Enable VCO ladder.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENUM_0 | 0 | Disable VCO ladder. |
    ENUM_1 | 1 | Enable VCO ladder. |

  KVCAL[3:0]
  Description:
    Sets the scaling on the VCO ladder where 0 is the max voltage setting and 15 is the min voltage setting.
  Min:
    0x0
  Max:
    0xf
  Default:
    0x5

### FREQ_CONTROL

#### FREQ_CONTROL_INTE

- Group: 0x40
- Index: 0x00

- Summary: Frac-N PLL Synthesizer integer divide number.
- Purpose:
  - The total divide ratio for the Fractional-N PLL Synthesizer consists of an integer portion and a fractional portion. This property defines the integer divide number; the fractional divide value is specified in property FREQ_CONTROL_FRAC.
  - The formula for calculating RF channel frequency as a function of integer and fractional divide values is as follows:

  - The output divider value OUTDIV is configured as a function of the desired frequency band, and is specified in property MODEM_CLKGEN_BAND:BAND.
  - The prescaler divider value NPRESC is configured as a function of the selected synthesizer performance mode and may take on the values NPRESC=2 or NPRESC=4, as specified in property MODEM_CLKGEN_BAND:SY_SEL.
  - The entire fcfrac word is 20-bits in length, but the MSB should always be set to 1, and thus the term fcfrac/219 will always be between 1 and 2 in value. As a result, the integer term fcinte should be reduced by 1. Example: a total desired divide ratio of N = 60.135 should be implemented as fcinte = 59, fcfrac/219 = 1.135.
  - Modifying this property will have no effect until the chip exits from TX or RX state, and then re-enters the state.
- Default: 0x3c
- Register View:

| FREQ_CONTROL_INTE
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x00 | 0 | INTE
| Default
| 0x0 | 0x3c

- Field Details:

  ###### FREQ_CONTROL_INTE

  INTE[6:0]
  Min:
    0x0
  Max:
    0x7f
  Default:
    0x3c

#### FREQ_CONTROL_FRAC

- Group: 0x40
- Indexes: 0x01 ... 0x03

- Summary: Frac-N PLL fraction number.
- Purpose:
  - Please refer to the text description for FREQ_CONTROL_INTE for more details regarding frequency calculation.
- Defaults: 0x08,0x00,0x00
- Register View:

| FREQ_CONTROL_FRAC
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x01 | 0 | 0 | 0 | 0 | FRAC[19:16]
0x02 | FRAC[15:8]
0x03 | FRAC[7:0]
| Defaults
0x01 | 0x0 | 0x0 | 0x0 | 0x0 | 0x8
0x02 | 0x0
0x03 | 0x0

- Field Details:

  ###### FREQ_CONTROL_FRAC

  FRAC[19:0]
  Description:
    Frequency control fractional part
  Min:
    0x0
  Max:
    0xfffff
  Default:
    0x80000

#### FREQ_CONTROL_CHANNEL_STEP_SIZE

- Group: 0x40
- Indexes: 0x04 ... 0x05

- Summary: EZ Frequency Programming channel step size.
- Purpose:
  - The EZ Frequency Programming method allows the user to control the frequency by selecting a desired channel number, given a base frequency and a channel step size. This property defines the unsigned 16-bit channel step size value.
  - The units of the FREQ_CONTROL_CHANNEL_STEP_SIZE property are in increments of the LSB tuning resolution of the PLL Synthesizer, and are therefore a function of the crystal reference frequency and output frequency band. The formula for calculating the value of the FREQ_CONTROL_CHANNEL_STEP_SIZE property is given by the following equation:

  - The output divider value OUTDIV is configured as a function of the desired frequency band, and is specified in property MODEM_CLKGEN_BAND:BAND.
  - The prescaler divider value NPRESC is configured as a function of the selected synthesizer performance mode and may take on the values NPRESC=2 or NPRESC=4, as specified in property MODEM_CLKGEN_BAND:SY_SEL.
  - The base frequency is specified by the FREQ_CONTROL_INTE and FREQ_CONTROL_FRAC properties.
  - The channel number is specified by the CHANNEL parameter byte passed to the START_TX command.
  - The commanded channel frequency is given by the formula:

- Defaults: 0x00,0x00
- Register View:

| FREQ_CONTROL_CHANNEL_STEP_SIZE
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x04 | CHANNEL_STEP_SIZE[15:8]
0x05 | CHANNEL_STEP_SIZE[7:0]
| Defaults
0x04 | 0x0
0x05 | 0x0

- Field Details:

  ###### FREQ_CONTROL_CHANNEL_STEP_SIZE

  CHANNEL_STEP_SIZE[15:0]
  Description:
    Channel step size
  Min:
    0x0
  Max:
    0xffff
  Default:
    0x0

#### FREQ_CONTROL_W_SIZE

- Group: 0x40
- Index: 0x06

- Summary: Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
- Purpose:
  - The chip performs a calibration of the VCO at each new commanded frequency. This is accomplished by counting cycles of the VCO frequency and comparing to an expected target count value.
  - The length of the window during which cycles of the VCO frequency are counted is specified by this property. The units are in cycles of the crystal reference frequency (e.g., 30 MHz clock periods).
  - This property does not need to change as a function of crystal reference frequency; the chip automatically calculates the target VCO count value as a function of crystal reference frequency and thus this property may remain constant. Silicon Labs recommends setting this property always to 0x20.
- Default: 0x20
- Register View:

| FREQ_CONTROL_W_SIZE
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x06 | W_SIZE
| Default
| 0x20

- Field Details:

  ###### FREQ_CONTROL_W_SIZE

  W_SIZE[7:0]
  Min:
    0x0
  Max:
    0xff
  Default:
    0x20

### PTI

#### PTI_CTL

- Group: 0xf0
- Index: 0x00

- Summary: Packet Trace Interface control fields.
- Purpose:
  - The chip contains packet trace interface for debugging network protocols. This property controls the behavior of this interface.
- Default: 0x80
- Register View:

| PTI_CTL
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x00 | PTI_EN | 0 | 0 | 0 | 0 | 0 | 0 | 0
| Default
| 0x1 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0

- Field Details:

  ###### PTI_CTL

  PTI_EN
  Description:
    Controls global enable of the PTI functionality.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENABLE | 1 | Enable PTI signal to GPIO. GPIO must be configured using GPIO_PIN_CFG. |
    DISABLE | 0 | Disable PTI signal to GPIO. GPIO must be configured using GPIO_PIN_CFG. |

#### PTI_BAUD

- Group: 0xf0
- Indexes: 0x01 ... 0x02

- Summary: Desired baud rate for the PTI interface.
- Purpose:
  - The chip contains a packet trace interface for network debugging. This data is transmitted to host debugger using a UART connection on a GPIO pin (selected using GPIO_PIN_CFG). This property sets the
    baud rate of the packet trace data in 100 baud steps.
- Defaults: 0x13,0x88
- Register View:

| PTI_BAUD
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x01 | 00000000
0x02 | 00000000
| Defaults
0x01 | 0x13
0x02 | 0x88

- Field Details:

  ###### PTI_BAUD

#### PTI_LOG_EN

- Group: 0xf0
- Index: 0x03

- Summary: Enables what the PTI logs.
- Purpose:
  - The chip contains packet trace interface for debugging network protocols. This property controls messages that
    get logged by this interface.
- Default: 0x00
- Register View:

| PTI_LOG_EN
--- | ---
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0x03 | 0 | 0 | TX_EN | 0 | 0 | 0 | 0 | 0
| Default
| 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0

- Field Details:

  ###### PTI_LOG_EN

  TX_EN
  Description:
    Controls logging of data packets sent over the air. Note that status information about each sent packet is always logged regardless of this setting.
  Format:
    Enumeration

    Name | Value | Description | Feature Available
    --- | --- | --- | ---
    ENABLE | 1 | Enable Logging to the packet trace interface. |
    DISABLE | 0 | Disable Logging to the packet trace interface. |