ClockBuilder™ Utility

Step 1: Specify Requirements    Step 2: Preview Configuration    Step 3: Initiate Request

Specify Custom Part

Specify your custom clock by selecting parameters below. Need help? View the ClockBuilder video tutorial.
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Input

Input Type: 

Block Diagram

Package: 
Optional Control Pins
The Si5350 has programmable input pins that can be factory-
customized to support any of the following functions.
You may choose up to # optional control pin functions:
Output Enable (OEB) Pins: 
Spread Spectrum Clocking  
(SSC): 
Modulation: Down Spread
Percentage:   (-0.1% to -2.5%)
Modulation Rate: 31.5 kHz
Loss of Lock (LOL) Pins: 
Powerdown (PDN) Pins: 
*The FS pins and the backup frequency planning are not available at this time in ClockBuilder. Contact Silicon Laboratories for more information.

Output Clocks

Output Frequency:
Number of device frequency configurations
 (frequency plans):
Frequency Plan #1
Output Frequencies
Name Check to
Enable
Frequency
(MHz)
Bank
VDDO
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
Frequency Plan #2
Output Frequencies ()
Name Check to
Enable
Frequency
(MHz)
Bank
VDDO
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
Frequency Plan #3
Output Frequencies (FS[1:0]=11)
Name Check to
Enable
Frequency
(MHz)
Bank
VDDO
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
Number of device frequency configurations
 (frequency plans):
Device can be configured as a clock generator with 1 to 3 frequency configurations (plans) or a clock buffer with 1 to 3 format/VDDO configurations.
Frequency Plan #1
Output Frequencies
Name Check to
Enable
Frequency
(MHz)
Output VDDO
and Format
CLK0A Check this box to power CLK0A/0B. Leave unchecked to turn off CLK0A/0B.
CLK0B
CLK1A Check this box to power CLK1A/1B. Leave unchecked to turn off CLK0A/0B.
CLK1B
CLK2A Check this box to power CLK2A/2B. Leave unchecked to turn off CLK2A/2B.
CLK2B
CLK3A Check this box to power CLK3A/3B. Leave unchecked to turn off CLK3A/3B.
CLK3B
Output Disable StateIf Output Enable pin(s) are used (see Control Pins section), the settings below configure the output clock disable state. The output disable state also is asserted until the PLL acquires lock or during a power-up sequence.
Tri-State Low High
Output Frequencies
Name Check to
Enable
Frequency
(MHz)
Output VDDO
and Format
CLK0A Check this box to power CLK0A/0B. Leave unchecked to turn off CLK0A/0B.
CLK0B
CLK1A Check this box to power CLK1A/1B. Leave unchecked to turn off CLK1A/1B.
CLK1B
CLK2A Check this box to power CLK2A/2B. Leave unchecked to turn off CLK2A/2B.
CLK2B
CLK3A Check this box to power CLK3A/3B. Leave unchecked to turn off CLK3A/3B.
CLK3B
Output Disable StateIf Output Enable pin(s) are used (see Control Pins section), the settings below configure the output clock disable state. The output disable state also is asserted until the PLL acquires lock or during a power-up sequence.
Tri-State Low High
Output Frequencies (FS1,FS0=11)
Name Check to
Enable
Frequency
(MHz)
Output VDDO
and Format
CLK0A Check this box to power CLK0A/0B. Leave unchecked to turn off CLK0A/0B.
CLK0B
CLK1A Check this box to power CLK1A/1B. Leave unchecked to turn off CLK1A/1B.
CLK1B
CLK2A Check this box to power CLK2A/2B. Leave unchecked to turn off CLK2A/2B.
CLK2B
CLK3A Check this box to power CLK3A/3B. Leave unchecked to turn off CLK3A/3B.
CLK3B
Output Disable StateIf Output Enable pin(s) are used (see Control Pins section), the settings below configure the output clock disable state. The output disable state also is asserted until the PLL acquires lock or during a power-up sequence.
Tri-State Low High
Any Si5350 output clock can be connected to either the crystal or the analog control voltage input.
Any Si5350 output clock can be connected to either the crystal or the reference clock.
Any OE pin can be mapped to control any output clock. Use the table below to assign OE control to
specific output clocks. The device pinout will be assigned based on the selected frequency configuration.
Output Clock Assignment
Automatic   Manual  
Enable
Channel
Output
Frequency
(MHz)
OE Control Pin Reference Enable
SSC
Crystal   CLKIN
Crystal   CLKIN
Crystal   CLKIN
Crystal   CLKIN
Crystal   CLKIN
Crystal   CLKIN
Crystal   CLKIN
Crystal   CLKIN

Control Pins

The Si5355 has 5 programmable input pins that can be factory-customized to support any of the following functions:
Output Enable Master, Output Enable (per bank), Frequency Select (selects active frequency configuration) and Reset.
The Frequency Select and Reset pins are only required on Si5355 devices with 2 or 3 frequency configurations.
You may pick up to # optional control pins
(* denotes a function that requires assignment)
Device Pin #
Function Pin3 Pin12 Pin19 Pin5 Pin6
Reset*
FS0*
FS1*
OE
OEA
OEB
OEC
OED
Device Pin #
Function Pin3 Pin12 Pin19 Pin5 Pin6 Input signals to P5 and P6 cannot exceed 1.2 V unless a resistor network divider is used. See datasheet "P5 and P6 Input Control" section for more information.
OEB_all Master output enable. When low, all output clocks are enabled. When high, this pin disables all output clocks to their assigned output disable state.
OEB0 CLK0A/0B output enable. When low, the clock is enabled (on). When high, this pin disables the clock to its assigned output disable state.
OEB1 CLK1A/1B output enable. When low, the clock is enabled (on). When high, this pin disables the clock to its assigned output disable state.
OEB2 CLK2A/2B output enable. When low, the clock is enabled (on). When high, this pin disables the clock to its assigned output disable state.
OEB3 CLK3A/3B output enable. When low, the clock is enabled (on). When high, this pin disables the clock to its assigned output disable state.
FS0 When specifying a device with 2 (or 3) frequency configurations, one (or two) FS pins is (are) required, and the optional RESET pin may be useful. RESET allows changes to the FS pins (for the purpose of selecting different frequency plans) to be recognized by the device without having to power cycle the device.
FS1 When specifying a device with 2 (or 3) frequency configurations, one (or two) FS pins is (are) required, and the optional RESET pin may be useful. RESET allows changes to the FS pins (for the purpose of selecting different frequency plans) to be recognized by the device without having to power cycle the device.
RESET When specifying a device with 2 (or 3) frequency configurations, one (or two) FS pins is (are) required, and the optional RESET pin may be useful. RESET allows changes to the FS pins (for the purpose of selecting different frequency plans) to be recognized by the device without having to power cycle the device.
SSENB When asserted (driven to ground), this pin applies spread spectrum clocking to reduce EMI to any output clock defined with a 100 MHz frequency. The default spreading profile is for PCIe compliance: 0.5% down spread with a 31.5 kHz modulation rate. If this pin is asserted and there are no 100 MHz clocks defined, there is no impact on any of the output clocks.
Device Pin #
Function Pin Pin Pin Pin Pin