Si5040 10 Gbps XFP transceiver
The Si5040 is a high-performance, protocol-agnostic 10 Gbps XFP transceiver featuring integrated jitter attenuating capability based on Silicon Labs' proven DSPLL technology. The Si5040 provides industry-leading jitter performance for all telecom and datacom protocols between 9.9 and 11.4 Gbps, including OC-192/STM-64, 10GE, 10G Fiber Channel and their associated forward error correction (FEC) data rates.
The device, is packaged in a 5 x 5 mm LGA package and only consumes 575 mW typ. It is designed to perform reshaping, reamplifying and retiming of the bidirectional 10 Gbps serial data by integrating two independent Clock and Data Recovery units (CDRs), two DSPLL-based Clock Multiplier Units (CMUs), and data retimers in both transmit and receive directions.
Si5010 CDR for OC-3/12 and STM-1/4 (2.5 V)
The Si5010 is a fully-integrated, low-power CDR IC designed for high-speed serial communication systems. The Si5010 sets a standard for low jitter, small size and low power for high speed CDR devices. It consumes 293 mW (typ OC-12) from a single 2.5 V supply and comes standard in a 20-pin micro leaded package (MLP).
The Si5010 recovers timing information and data from a serial input at OC-3/12 or STM-1/4 rates. The Si5010 utilizes Silicon Laboratories' proprietary DSPLL technology to provide superior jitter performance that remains constant across the entire industrial temperature range. The Si5010 significantly exceeds all SONET/SDH jitter requirements, providing additional design margin with respect to jitter generation, tolerance and transfer.
Si5013 CDR+LA for OC-3/12 and STM-1/4 (3.3 V)
The Si5013 combines a high sensitivity limiting amplifier and multi-rate CDR unit into a single IC. The Si5013 consumes 560 mW (typ OC-12) from a single 3.3 V supply and comes packaged in a small 5 x 5 mm, 28-pin MLP. The device operates over the industrial temperature range (–20 to 85 °C.) and utilizes Silicon Laboratories' proprietary DSPLL technology to provide superior jitter performance that remains constant across the entire industrial temperature range. In addition, the Si5013 significantly exceeds all SONET/SDH jitter requirements, providing additional design margin with respect to jitter generation, tolerance and transfer.
The Si5013 extracts timing information and data from a serial input at OC-12/3 or STM-4/1 rates. To simplify device application and reduce board space requirements, the Si5013 eliminates the need for an external reference clock by integrating this function into the device. Enhanced analog and digital signal monitoring is also provided with user-programmable alarms to simplify detection of analog loss-of-signal (LOS) and digital bit error rate (BER). To accommodate BER optimization for long haul data links, user-programmable data slicing is available to reduce circuit complexity.
Si5017 CDR+LA for OC-48/STM-16 and 2.7 Gbps FEC (3.3 V)
The Si5017 combines a high-sensitivity limiting amplifier and multi-rate CDR unit into a single IC. The Si5017 consumes 528 mW (typ OC-48) from a single 3.3 V supply and comes packaged in a small 5 x 5 mm, 28-pin MLP. The device utilizes Silicon Laboratories' proprietary DSPLL technology to provide superior jitter performance that remains constant across the entire industrial temperature range (–20 to +85 °C). The Si5017 significantly exceeds all SONET/SDH jitter requirements, providing additional design margin with respect to jitter generation, tolerance and transfer.
The Si5017 extracts timing information and data from a serial input at OC-48 rates. Support for data 2.7 Gbps streams is also provided for OC-48/STM-16 applications that employ FEC. To simplify device application and reduce board space requirements, the Si5017 eliminates the need for an external reference clock by integrating this function into the device. Enhanced analog and digital signal monitoring is also provided with user-programmable alarms to simplify detection of analog LOS and digital BER. To accommodate BER optimization for long-haul data links, user-programmable data slicing is available to reduce circuit complexity.
Si5018 CDR for OC-48/STM-16 and 2.7 Gbps FEC (2.5 V)
The Si5018 is a fully-integrated low-power CDR IC designed for high-speed serial communication systems. The Si5018 sets a standard for low jitter, small size and low power for high-speed CDR ICs. It typically consumes 270 mW (OC-48 typ) from a single 2.5 V supply and comes in a 20-pin MLP. The device utilizes Silicon Laboratories' proprietary DSPLL technology to provide superior jitter performance that remains constant across the entire industrial temperature range. The Si5018 significantly exceeds all SONET/SDH jitter requirements, providing additional design margin with respect to jitter generation, tolerance and transfer.
The Si5018 recovers timing information and data from a serial input at OC-48 or STM-16 rates. Support for data 2.7 Gbps streams is also provided for OC-48/STM-16 applications that employ FEC.
Si5020 CDR for OC-3/12/48, GbE, 2.7 Gbps FEC (2.5 V)
The Si5020 is a fully-integrated low-power CDR IC designed for high-speed serial communication systems. The Si5020 utilizes Silicon Laboratories' proprietary DSPLL technology to provide superior jitter performance that remains constant across the entire industrial temperature range. The device significantly exceeds all SONET/SDH jitter requirements, providing additional design margin with respect to jitter generation, tolerance and transfer. The Si5020 sets a standard for low jitter, small size and low power for high-speed CDR ICs. It consumes 270 mW (OC-48 typ) from a single 2.5 V supply and comes in a 20-pin MLP.
The Si5020 recovers timing information and data from a serial input at OC-3/12/48, STM-1/4/16 or Gigabit Ethernet (GbE) rates. Support for 2.7 Gbps data streams is also provided for OC-48/STM-16 applications that employ FEC.
Si5023 CDR+LA for OC-3/12/48, GbE, 2.7 Gbps FEC (3.3 V)
The Si5023 combines a high-sensitivity limiting amplifier and multi-rate CDR unit into a single IC. The device consumes 500 mW (typ OC-48) from a single 3.3 V supply and comes packaged in a small 5 x 5 mm, 28-pin MLP. The Si5023 utilizes Silicon Laboratories' proprietary DSPLL technology to provide superior jitter performance that remains constant across the entire industrial temperature range (–20 to 85 °C). The Si5023 Provides additional design margin with respect to jitter generation, tolerance and transfer, by significantly exceeding all SONET/SDH jitter requirements.
The Si5023 extracts timing information and data from a serial input at OC-48/12/3, STM-16/4/1, GbE and 2.7 Gbps FEC rates. To simplify device application and reduce board space requirements, the Si5023 eliminates the need for an external reference clock by integrating this function into the device. Enhanced analog and digital signal monitoring is also provided with user-programmable alarms to simplify detection of analog LOS and digital BER. To accommodate BER optimization for long haul data links, user-programmable data slicing is available to reduce circuit complexity.
The receive path consists of a fully-integrated limiting amplifier, CDR and a 1:16 deserializer. The transmit path combines an eight-word FIFO with flow control, low-jitter clock multiplier unit (CMU) and a 16:1 serializer. The CMU uses Silicon Laboratories' DSPLL technology to provide superior jitter performance while reducing design complexity by eliminating external loop filter components. In addition, DSPLL supports programmable loop filter bandwidths, eliminating the need for expensive external VCXO's and clean-up PLL's for jitter attenuation. To simplify BER optimization in long-haul applications, programmable slicing and sample phase adjustment are supported.
Si5110 OC-48/STM-16 SONET/SDH transceiver (4-bit)
The Si5110 is a complete low-power transceiver for high-speed serial communication systems operating between 2.5 Gbps and 2.7 Gbps, making it suitable for OC-48/STM-16 and OC-48/STM-16 applications that use 15/14 FEC. The Si5110 provides a 4-bit, 622 MHz LVDS interface and is packaged in a 99-pin 11 x 11 mm CBGA package. The device operates from a single 1.8 V supply.
The receive path consists of a fully-integrated limiting amplifier, CDR and a 1:4 deserializer. The transmit path combines an eight-word FIFO with flow control, low jitter CMU and a 4:1 serializer. The CMU uses Silicon Laboratories' DSPLL technology to provide superior jitter performance while reducing design complexity by eliminating external loop filter components. In addition, DSPLL supports programmable loop filter bandwidths, eliminating the need for expensive external VCXOs and clean-up PLL's for jitter attenuation. To simplify BER optimization in long-haul applications, programmable slicing and sample phase adjustment are supported.
OC-192/STM-64 and OC-48/STM-16 Transceivers
Based on Silicon Labs' proprietary DSPLL® technology, these devices offer superior jitter performance while integrating all PLL circuitry, including loop filter components. This makes the device less sensitive to board-level noise sources, resulting in improved jitter performance and simplified board layout. In addition, the DSPLL functions as a narrow-band PLL in the Si5040 and Si5110/5100 transceivers, eliminating the need for external jitter-attenuating PLLs or costly VCXOs.
Si5100 OC-48/STM-16 SONET/SDH transceiver (16-bit)
The Si5100 is a complete low-power transceiver for high-speed serial communication systems operating between 2.5 Gbps and 2.7 Gbps, making it suitable for OC-48/STM-16 and OC-48/STM-16 applications that use 15/14 FEC. The Si5100 provides a 16-bit, 155 MHz LVDS interface and is packaged in a 195-pin 15 x 15 mm ceramic ball grid array (CBGA) package. The device operates from a single 1.8 V supply.