LVCMOS Clocks (<4 outputs)

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Si51211 Block Diagram

Silicon Labs LVCMOS clock generators:

  • Highly flexible, pin, factory and I2C programmability
  • Industry-leading performance in jitter, customization, power and size
  • Generate multiple frequencies simultaneously and/or using FSEL
  • Programmable EMI reduction, edge rates, skew and slew, output impedance, and spread spectrum percentages
  • Samples available in < 2 weeks

The Tiny Clock Si5121x is the industry’s smallest, lowest power, frequency flexible programmable clock generator. Perfect for consumer electronics, industrial, and embedded applications where space, low power, low cost, and high volume reliable supply are fundamental.

The Si5350/51 offers multiple, non-integer-related frequencies at lower jitter, lower power and smaller size than competing solutions. Perfect for performance oriented consumer electronics, industrial, and embedded applications

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Using Configurable Tiny Clocks to Reduce Space, Power and EMI

Features

  • Si51210/11/14/19
    • 6TDFN Tiny Clock  2 outputs = 1.4 x 1.2 = 1.7 mm2
    • 8TDFN Tiny Clock 3 outputs = 1.4 x 1.6 = 2.2 mm2
    • Ultra-low power dissipation (6 mA Typ for 3 outputs)
    • < 2 week lead time for factory-customized parts
    • Accepts crystal or reference clock input
    • Generates up to 3 CMOS outputs (3 to 200 MHz)
    • Programmable FSEL, SSEL, SSON, PD and OE
    • 1.8, 2.5-3.3 V voltage supply range
    • Contact Silicon Labs to build a custom clock (PPR)
  • Si5350/51 (10-MSOP option)
    • Generates any frequency on any output, 8 kHz to 133 MHz
    • Exact clock synthesis: 0 ppm error
    • Similar frequency flexibility as 8 independent PLLs
    • Crystal or clock input
    • < 100 ps pk-pk period jitter for any configuration
    • Glitchless switching between output frequencies
    • I2C programmable or pin-controlled
    • Excellent PSRR: no discrete components required
    • Customizable drive strength
    • Customizable crystal load capacitance at XIN/XOUT pins
    • Factory and field-programmable versions available
    • Two-week sample lead time for any custom clock
  • SL15xxx, SL160xx
    • Low power: 2.1 mA typ at 38 MHz, CL=0 and VDD=3.3 V
    • On-chip, programmable crystal capacitive load (CL): 8 to 20 pF
    • Spread spectrum clock generation
    • Down or center spread, spread percentage: 01. to 5%
    • Spread modulation frequency from 16 to 128 kHz
    • User-definable control pins: power down, output enable, spread enable or frequency select, spread select
    • 7 drive strength (programmable tr/tf) options
    • Custom solutions available (contact Silicon Labs)
     

    Applications

    Documentation    Expand All   Collapse All

     
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    Data Sheet (15)

    Document NameDescriptionVersionLast Updated
    Si51210.pdf
    Si51210 Data Sheet0.71/27/2012
    Si51211.pdf
    Si51211 Data Sheet0.71/27/2012
    Si51214.pdf
    Si51214 Data Sheet0.71/27/2012
    Si51219.pdf
    Si51219 Data Sheet0.71/27/2012
    Si5350A.pdf
    Si5350A Data Sheet0.95/25/2011
    Si5350A_SC.pdf
    Si5350A Data Sheet (Chinese)0.917/8/2011
    Si5350A_JA.pdf
    Si5350A Data Sheet (Japanese)0.96/22/2011
    Si5350C.pdf
    Si5350C Data Sheet0.95/25/2011
    Si5351.pdf
    Si5351 Data Sheet0.958/2/2011
    SL15100.pdf
    SL15100 Data Sheet1.83/8/2011
    SL15100-38AH.pdf
    SL15100-38AH Data Sheet1.04/5/2012
    SL15300.pdf
    SL15300 Data Sheet2.03/8/2011
    SL15303.pdf
    SL15303 Data Sheet2.03/8/2011
    SL16010.pdf
    SL16010 Data Sheet2.63/8/2011
    SL16020.pdf
    SL16020 Data Sheet2.23/8/2011

    Data Short (1)

    Document NameDescriptionVersionLast Updated
    Si5350-51_short.pdf
    Si5350/51 Data Short10.20.1011/3/2010

    User Guides (5)

    Document NameDescriptionVersionLast Updated
    Si51210-14-EVB.pdf
    Si51210/14-EVB Tiny Clock User's Guide0.11/26/2012
    Si51211-EVB.pdf
    Si51211-EVB User's Guide0.11/26/2012
    Si51219-EVB.pdf
    Si51219-EVB User's Guide0.11/26/2012
    Si535x-20QFN-EVB.pdf
    Si535x-20QFN-EVB User's Guide0.111/2/2010
    Si535x-24QSOP-EVB.pdf
    Si535x-24QSOP-EVB User's Guide0.211/2/2010

    Application Notes (5)

    Document NameDescriptionVersionLast Updated
    AN551.pdf
    AN551: Crystal Selection Guide for Si5350/51 Devices0.33/13/2012
    AN554.pdf
    AN554: Si5350/51 PCB Layout Guide0.111/2/2010
    an56.pdf
    AN56: Calculating Total Output Jitter for PLLs0.35/4/2012
    AN581.pdf
    AN581: Meeting SerDes Jitter Requirements Simplified with Silicon Labs Clocks and Oscillators0.19/2/2011
    AN619.pdf
    AN619: Manually Generating an Si5351 Register Map0.112/19/2011

    White Papers (5)

    Document NameDescriptionVersionLast Updated
    Configurable-Tiny-Clocks-Reduce-Space-Power-and-EMI.pdf
    Configurable Tiny Clocks Reduce Space, Power and EMI in Consumer Electronics Designs1.01/27/2012
    Reducing-EMI_WP.pdf
    Reducing EMI and Improving Signal Integrity Using Spread Spectrum Clocking1.05/31/2011
    PCIe-Clock-Source-Selection.pdf
    Selecting the Optimum PCIe Clock Source1.01/10/2012
    Si5350-51 Frequency Shifting_WP.pdf
    Si5350-51 Frequency Shifting White Paper0.111/2/2010
    Timing-ICs-Keep-Beat-with-Needs-of-Todays-Embedded-Market.pdf
    Timing ICs Keep Beat with Needs of Today’s Embedded Market1.011/21/2011

    Miscellaneous (7)

    Document NameDescriptionVersionLast Updated
    ppr-programmable-product-request-form.docx
    Programmable Product Request Form (PPR)3.03/23/2012
    Si5350-TMSTK_QS_Guide.pdf
    Si5350 Timing ToolStick Quick-Start Guide0.111/2/2010
    Silicon-Labs-Timing-Cross-Reference.pdf
    Silicon Labs Timing Cross-Reference to Xilinx, Altera and Lattice FPGA Devices3.05/3/2012
    timing-solutions-for-cavium-processors.pdf
    Silicon Labs' Timing Solutions for Cavium Processors1.27/15/2011
    timing-solutions-for-freescale-processors.pdf
    Silicon Labs' Timing Solutions for Freescale Processors1.02/10/2012
    Timing-Solutions-for-Altera.pdf
    Timing Solutions for Altera0.312/7/2011
    timing-solutions-for-plx-technology.pdf
    Timing Solutions for PLX Technology1.011/8/2011

    PCN (4)

    Document NameDescriptionVersionLast Updated
    11090810 Test to UTL std.pdf
    11090810 Test to UTL std
    1109084_SL Assembly Transfer to UTAC Thailand std reissue.pdf
    1109084 SL Assembly Transfer to UTAC Thailand std reissue
    1110101B_Bulletin to expand OFC for ship OSEP parts.pdf
    1110101B_Bulletin to expand OFC for ship OSEP parts
    1204091B_ClockBuilder Desktop Software v5.0.0 Availability-Silicon_Labs.pdf
    1204091B_ClockBuilder Desktop Software v5.0.0 Availability-Silicon_Labs

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    Software (2)

    Document NameDescriptionVersionUpdated
    release_notes_clockbuilder.txt
    Release Notes for ClockBuilder Desktop6/27/2011
    ClockBuilderDesktopSwInstall.zip
    Si5335/38/51/56 ClockBuilder Desktop Software Version 5.05.03/17/2012

    Models (3)

    Document NameDescriptionVersionUpdated
    si5350a-a-gt.ibs
    Si5350A-A-GT IBIS Model3.08/23/2011
    si5350c-a-gt.ibs
    Si5350C-A-GT IBIS Model3.08/23/2011
    si5351a-a-gt.ibs
    Si5351A-A-GT IBIS Model3.18/23/2011

    Product Matrix


    Part Number Available DocumentsControlPackageReference InputsClock OutputsInput FrequencyOutput FrequencyPhase Jitter (RMS)Output Format(s)VDDVDDO
    Si51210Data Sheet
    Pin6-pin TDFN123 - 166 MHz (Clock), 8 - 48 MHz (Xtal)3 - 200 MHzLVCMOS2.5 - 3.3 V
    Si51211Data Sheet
    Pin8-pin TDFN233 - 166 MHz (Clock), 8 - 48 MHz (Xtal)3 - 200 MHzLVCMOS2.5 - 3.3 V1.8 V, 2.5 V, 3.3 V
    Si51214Data Sheet
    Pin6-pin TDFN123 - 166 MHz (Clock), 8 - 48 MHz (Xtal)3 - 200 MHzLVCMOS1.8 V
    Si51219Data Sheet
    Pin8-pin TSSOP233 - 166 MHz (Clock), 8 - 48 MHz (Xtal)3 - 200 MHzLVCMOS2.5 - 3.3 V1.8 V, 2.5 V, 3.3 V
    Si5350A-A-GTSample
    Buy
    Data Sheet
    Data Sheet
    Data Short
    Pin10-pin MSOP1325/27 MHz (Xtal)0.008 - 133 MHz3.5 psLVCMOS 2.5 V, 3.3 V2.5 V, 3.3 V
    Si5350C-A-GTData Sheet
    Data Sheet
    Data Short
    Pin10-pin MSOP2310 - 100 MHz (Clock), 25/27 MHz (Xtal)0.008 - 133 MHz3.5 psLVCMOS 2.5 V, 3.3 V2.5 V, 3.3 V
    Si5351A-A-GTData Sheet
    Data Short
    I2C10-pin MSOP13 25/27 MHz (Xtal)0.008 - 133 MHz3.5 psLVCMOS 2.5 V, 3.3 V2.5 V, 3.3 V
    SL15100Data Sheet
    Pin8-pin TSSOP123 - 166 MHz (Clock), 8 - 48 MHz (Xtal)3 - 200 MHz> 1.0 psLVCMOS 2.5 V, 3.3 V
    SL15300Data Sheet
    Pin8-pin TSSOP143 - 166 MHz (Clock), 8 - 48 MHz (Xtal)3 - 200 MHz> 1.0 psLVCMOS 1.8 V, 2.5 V, 3.3 V
    SL15303Data Sheet
    Pin8-pin TSSOP133 - 166 MHz (Clock), 8 - 48 MHz (Xtal)3 - 200 MHz> 1.0 psLVCMOS 1.8 V, 2.5 V, 3.3 V
    SL16010DCData Sheet
    I2C/Pin10-pin TDFN1227 MHz100 MHz, 27 MHz> 1.0 psLVCMOS 3.3 V
    SL16020DCData Sheet
    I2C/Pin10-pin TDFN1227 MHz100 MHz, 27 MHz> 1.0 psLVCMOS 3.3 V

    Si5350/51 devices in the 10-MSOP packaging option supports generation of up to 3 LVCMOS clocks. The device can be customized to generate multiple independent non-integer-related frequencies with equivalent frequency synthesis capability of 3 PLLs, with exact frequency synthesis (0 ppm error), at significantly lower jitter, lower power and smaller size than competing solutions. Integrated VCXO functionality is also provided.

    The factory programmable Si5121x is industry’s lowest power, smallest footprint and frequency flexible programmable clock generator targeting low power, low cost and high volume consumer and embedded applications. The device operates from a single crystal or an external clock source and generate 1 to 2 or 1 to 3 outputs up to 200 MHz They are factory programmed to provide customized output frequencies, control inputs and AC parameter tuning like output drive strength that are optimized for customer board condition and application requirements.

    SL15100/300/303 clocks generate frequencies from 3 to 200 MHz in configurations that support 2 to 4 LVCMOS outputs. A simple integer output divider is integrated so that integer-related outputs can be easily generated. To minimize electromagnetic interference, AC parameters like rise/fall time can be customized. 

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    Training & Resources

    Featured Videos

    See How to Build a Custom Clock
    See How to Build a Custom Clock
    Minimizing Noise and Interference with PSRR
    Minimizing Noise and Interference with PSRR

    Featured Utilities

    Clock Tree Design Service

    Silicon Labs clock tree design and consulting services help hardware designers simplify design and layout. Fill out the web form or upload files, and Silicon Labs will return a custom clock tree proposal within 3 business days based on your design.

    ClockBuilder™ Wizard

    The simple, easy-to-use ClockBuilder™ utility can be used to quickly develop custom, application-specific clock generators that support any combination of user-specified input/output frequencies.

    Build Custom XO/VCXO

    Specify a custom silicon or crystal oscillator and build a part number in minutes. Need to reorder? Look up a currently existing product by part number.

    Parametric Search

    Use this utility to search the selection of available clock generators and buffers, low jitter and jitter attenuating clock multipliers, synchronous ethernet, SONET/SDH clocks, crystal oscillators, and voltage-controlled crystal oscillators. Samples ship in less than two weeks!

    Cross-Reference Search

    Enter the part number from another company into the utility to find a list of Silicon Labs' products that can replace those parts. Once you find the products you need, you can click on the part number to see more details about the Silicon Labs' device, download the data sheet and export the results to Excel.


    Featured White Papers

    Selecting the Optimum PCIe Clock Source

    To ensure proper compliance with the PCIe standard, systems require careful attention to the timing subsystem and architecture. This article explores some of the standard clocking architectures for PCIe and considers their benefits for typical system applications, including: clock architecture selection (Common Refclk, Separate Refclk or Data Clocked Refclk), requirements in applications that use FPGAs, jitter performance of the reference clock, use of spread spectrum clocking, and more.

    SyncE and IEEE 1588: Sync Distribution for a Unified Network

    Since Ethernet or packet based networks operate asynchronously, many of the traditional applications that depend on synchronization are not supported. Designers increasingly need to combine services supplied by data efficient packet networks with the ones served by the large installed base of traditional SONET/SDH networks. Both Synchronous Ethernet (SyncE) and packet timing using the IEEE 1588 protocol offer viable solutions in unifying service delivery over both networks. Download this new app note from Silicon Labs to discover methods for transporting synchronization and potential synchronized timing implementations.

    Prototyping with Frequency-Flexible Crystal Oscillators

    Developers of new systems ideally should make decisions regarding clocking requirements early in the design process. Although clocking rates are critical parameters that should be known in advance, determining these rates sometimes requires experimentation and re-evaluation. The use of frequency-flexible, programmable crystal oscillators (XOs) as prototyping tools can facilitate the process of validating system performance and help streamline the overall product development cycle.

    View all Clock and Oscillator Training & Resources...

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