Clock + VCXO Solutions

Silicon Labs' highly-integrated clock + VCXO solutions feature an integrated voltage controlled oscillator (VCXO). Free-running and VCXO clocks can be generated by one device, making them ideal for cost-sensitive consumer applications.

Si5350/51 clock generators feature an integrated VCXO that does not require pullable crystals. These devices come in both 3 and 8 output configurations.

The SL38000 series of clock generators offer both VCXO and spread spectrum clock generation (SSCG) options, with LVCMOS outputs from 1-200 MHz.

Features

Si5350/51

Integrated high linearity VCXO
Pullable crystal not required
Generates any frequency on any output, 8 kHz to 133 MHz
Exact clock synthesis: 0 ppm error
Similar frequency flexibility as 8 independent PLLs
Crystal or clock input
<100 ps pk-pk period jitter for any configuration
Glitchless switching between output frequencies
I²C programmable or pin-controlled
Excellent PSRR: no discrete components required
Factory and field-progammable versions available
Two-week sample lead time for any custom clock

SL38xxx

Integrated VCXO functionality with 150 ppm pull range
4-PLL architecture capable of generating up to 11 LVCMOS outputs
Programmable/configurable output frequencies from 1 to 200 MHz
8 to 48 MHz external crystals supported
8 to 166 MHz external clock input supported
Customizable PD#/OE/SSON#/FS functions
Customizable/programmable rise/fall times (7 settings per output)
Programmable/configurable center or down spread spectrum with up to 16 dB of EMI reduction
Spread spectrum modulation from 0.25 to 5.0% with both linear and non-linear profiles
Programmable/configurable crystal load capacitors (CL=10 to 20 pF)
Low noise PLL by-pass mode for reference clock generation
4 independent output supply pins (VDDO)
I²C control interface
Packages: 28-pin TSSOP
Custom solutions available (contact Silicon Labs)

Applications

Printers & MFP
Digital Copiers
PC/NBPC
LCD Monitors
HDTV
Storage
Servers & Routers
Embedded

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Data Sheet (7)

Document Name	Description	Version	Last Updated
Si5350B.pdf	Si5350B Data Sheet	0.9	5/25/2011
Si5351.pdf	Si5351 Data Sheet	0.95	8/2/2011
SL38000.pdf	SL38000 Data Sheet	1.1	3/9/2011
SL38000-15AH.pdf	SL38000-15AH Data Sheet	2.3	3/9/2011
SL38160.pdf	SL38160 Data Sheet	1.1	3/9/2011
SL38160-17.pdf	SL38160-17 Data Sheet	AB	3/9/2011
SL38160-18.pdf	SL38160-18 Data Sheet	AB	3/9/2011

Data Short (1)

Document Name	Description	Version	Last Updated
Si5350-51_short.pdf	Si5350/51 Data Short	10.20.10	11/3/2010

User Guides (2)

Document Name	Description	Version	Last Updated
Si535x-20QFN-EVB.pdf	Si535x-20QFN-EVB User's Guide	0.1	11/2/2010
Si535x-24QSOP-EVB.pdf	Si535x-24QSOP-EVB User's Guide	0.2	11/2/2010

Application Notes (5)

Document Name	Description	Version	Last Updated
AN551.pdf	AN551: Crystal Selection Guide for Si5350/51 Devices	0.3	3/13/2012
AN554.pdf	AN554: Si5350/51 PCB Layout Guide	0.1	11/2/2010
an56.pdf	AN56: Calculating Total Output Jitter for PLLs	0.3	5/4/2012
AN581.pdf	AN581: Meeting SerDes Jitter Requirements Simplified with Silicon Labs Clocks and Oscillators	0.1	9/2/2011
AN619.pdf	AN619: Manually Generating an Si5351 Register Map	0.1	12/19/2011

White Papers (5)

Document Name	Description	Version	Last Updated
Configurable-Tiny-Clocks-Reduce-Space-Power-and-EMI.pdf	Configurable Tiny Clocks Reduce Space, Power and EMI in Consumer Electronics Designs	1.0	1/27/2012
Reducing-EMI_WP.pdf	Reducing EMI and Improving Signal Integrity Using Spread Spectrum Clocking	1.0	5/31/2011
PCIe-Clock-Source-Selection.pdf	Selecting the Optimum PCIe Clock Source	1.0	1/10/2012
Si5350-51 Frequency Shifting_WP.pdf	Si5350-51 Frequency Shifting White Paper	0.1	11/2/2010
Timing-ICs-Keep-Beat-with-Needs-of-Todays-Embedded-Market.pdf	Timing ICs Keep Beat with Needs of Today’s Embedded Market	1.0	11/21/2011

Miscellaneous (7)

Document Name	Description	Version	Last Updated
ppr-programmable-product-request-form.docx	Programmable Product Request Form (PPR)	3.0	3/23/2012
Si5350-TMSTK_QS_Guide.pdf	Si5350 Timing ToolStick Quick-Start Guide	0.1	11/2/2010
Silicon-Labs-Timing-Cross-Reference.pdf	Silicon Labs Timing Cross-Reference to Xilinx, Altera and Lattice FPGA Devices	3.0	5/3/2012
timing-solutions-for-cavium-processors.pdf	Silicon Labs' Timing Solutions for Cavium Processors	1.2	7/15/2011
timing-solutions-for-freescale-processors.pdf	Silicon Labs' Timing Solutions for Freescale Processors	1.0	2/10/2012
Timing-Solutions-for-Altera.pdf	Timing Solutions for Altera	0.3	12/7/2011
timing-solutions-for-plx-technology.pdf	Timing Solutions for PLX Technology	1.0	11/8/2011

PCN (5)

Document Name	Description	Version	Last Updated
11090810 Test to UTL std.pdf	11090810 Test to UTL std
1109084_SL Assembly Transfer to UTAC Thailand std reissue.pdf	1109084 SL Assembly Transfer to UTAC Thailand std reissue
1110101B_Bulletin to expand OFC for ship OSEP parts.pdf	1110101B_Bulletin to expand OFC for ship OSEP parts
1203231B_LPP_Reel1.pdf	1203231B_LPP_Reel1
1204091B_ClockBuilder Desktop Software v5.0.0 Availability-Silicon_Labs.pdf	1204091B_ClockBuilder Desktop Software v5.0.0 Availability-Silicon_Labs

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Software (2)

Document Name	Description	Version	Updated
release_notes_clockbuilder.txt	Release Notes for ClockBuilder Desktop		6/27/2011
ClockBuilderDesktopSwInstall.zip	Si5335/38/51/56 ClockBuilder Desktop Software Version 5.0	5.0	3/17/2012

Models (5)

Document Name	Description	Version	Updated
si5350b-a-gm.ibs	Si5350B-A-GM IBIS Model	3.0	8/23/2011
si5350b-a-gt.ibs	Si5350B-A-GT IBIS Model	3.0	8/23/2011
si5350b-a-gu.ibs	Si5350B-A-GU IBIS Model	3.0	8/23/2011
si5351b-a-gm.ibs	Si5351B-A-GM IBIS Model	3.1	8/23/2011
si5351b-a-gu.ibs	Si5351B-A-GU IBIS Model	3.1	8/23/2011

Product Matrix

Part Number	Available Documents	Control	Package	Reference Inputs	Clock Outputs	Input Frequency	Output Frequency	Phase Jitter (RMS)	Output Format(s)	VDD	VDDO
Si5350B-A-GM	Data Sheet Data Sheet Data Short	Pin	4x4 mm 20-QFN	1	8	25/27 MHz (Xtal)	0.008 - 133 MHz	3.5 ps	LVCMOS	2.5 V, 3.3 V	2.5 V, 3.3 V
Si5350B-A-GT	Data Sheet Data Sheet Data Short	Pin	10-pin MSOP	1	3	25/27 MHz (Xtal)	0.008 - 133 MHz	3.5 ps	LVCMOS	2.5 V, 3.3 V	2.5 V, 3.3 V
Si5350B-A-GU	Data Sheet Data Sheet Data Short	Pin	24-pin QSOP	1	8	25/27 MHz (Xtal)	0.008 - 133 MHz	3.5 ps	LVCMOS	2.5 V, 3.3 V	2.5 V, 3.3 V
Si5351B-A-GM	Data Sheet Data Short	I2C	4x4 mm 20-QFN	1	8	25/27 MHz (Xtal)	0.008 - 133 MHz	3.5 ps	LVCMOS	2.5 V, 3.3 V	2.5 V, 3.3 V
Si5351B-A-GU	Data Sheet Data Short	I2C	24-pin QSOP	1	8	25/27 MHz (Xtal)	0.008 - 133 MHz	3.5 ps	LVCMOS	2.5 V, 3.3 V	2.5 V, 3.3 V
SL38000	Data Sheet	I2C/Pin	28-pin TSSOP	1	12	3 - 166 MHz (Clock), 8 - 48 MHz (Xtal)	3 - 200 MHz	> 1.0 ps	LVCMOS	1.8 V, 2.5 V, 3.3 V	1.8/2.5/3.3 V, VDDO<=VDD
SL38000ZI-15H	Data Sheet	Pin	28-pin TSSOP	1	5	25 MHz	12 MHz, 125 MHz, 133 MHz, 25 MHz, 50 MHz	> 1.0 ps	LVCMOS	3.3 V	3.3 V
SL38160	Data Sheet	I2C/Pin	16-pin TSSOP	1	8	3 - 166 MHz (Clock), 8 - 48 MHz (Xtal)	3 - 200 MHz	> 1.0 ps	LVCMOS	1.8 V, 2.5 V, 3.3 V	1.8/2.5/3.3 V, VDDO<=VDD
SL38160-17AH	Data Sheet	I2C	16-pin TSSOP	1	4	27 MHz	13.5 - 148.5 MHz, 27 MHz, 8.19 - 49.15 MHz	> 1.0 ps	LVCMOS	3.3 V	3.3 V
SL38160-18AH	Data Sheet	I2C/Pin	16-pin TSSOP	2	2	27 MHz	25 - 202 MHz, 27 MHz	> 1.0 ps	LVCMOS	3.3 V	3.3 V

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Featured White Papers

Selecting the Optimum PCIe Clock Source

To ensure proper compliance with the PCIe standard, systems require careful attention to the timing subsystem and architecture. This article explores some of the standard clocking architectures for PCIe and considers their benefits for typical system applications, including: clock architecture selection (Common Refclk, Separate Refclk or Data Clocked Refclk), requirements in applications that use FPGAs, jitter performance of the reference clock, use of spread spectrum clocking, and more.

SyncE and IEEE 1588: Sync Distribution for a Unified Network

Since Ethernet or packet based networks operate asynchronously, many of the traditional applications that depend on synchronization are not supported. Designers increasingly need to combine services supplied by data efficient packet networks with the ones served by the large installed base of traditional SONET/SDH networks. Both Synchronous Ethernet (SyncE) and packet timing using the IEEE 1588 protocol offer viable solutions in unifying service delivery over both networks. Download this new app note from Silicon Labs to discover methods for transporting synchronization and potential synchronized timing implementations.

Prototyping with Frequency-Flexible Crystal Oscillators

Developers of new systems ideally should make decisions regarding clocking requirements early in the design process. Although clocking rates are critical parameters that should be known in advance, determining these rates sometimes requires experimentation and re-evaluation. The use of frequency-flexible, programmable crystal oscillators (XOs) as prototyping tools can facilitate the process of validating system performance and help streamline the overall product development cycle.

Clocks and Oscillators

Title Content
Integrated Clock + VCXO Solutions

Features

Applications