Differential + LVCMOS Clock Generators

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Si5338 Programmable Clock Generator IC Block Diagram

Silicon Labs’ Si533x family of programmable clock generator IC solutions provide any rate, any output frequency synthesis. All combinations of output frequencies can be generated exactly with 0 ppm error.

  • The Si5334/35/38 clock generator devices provide LVPECL/CML/LVDS/HCSL/CMOS clock generation up to 710 MHz with 1 ps rms phase jitter.
  • The SL28PCIe10/30/50 clock generator devices accept 14 or 25 MHz input, and generate up to 6 PCI Express (PCIe) outputs.

 

Product Matrix Highlights

​Device Control​ Max Output Freq(MHz)​ Inputs​ Outputs​ Output Formats​ Jitter(rms)​
Si5338 I2C​ 710​ 1​ 4 or 8​ LVPECL, LVDS, HCSL, CML, LVCMOS, SSTL, HSTL​ <1 ps​
Si5334 Pin​ 710​ 1​ 4 or 8​ LVPECL, LVDS, HCSL, CML, LVCMOS, SSTL, HSTL​​ <1 ps​
Si5335 Pin​ 350​ 1​ 4 or 8​ LVPECL, LVDS, HCSL, CML, LVCMOS, SSTL, HSTL​​ 1 ps​
SL28PCIe1x/5x I2C/Pin​ 100 MHz, 25 MHz, 27 MHz, Programmable SE ​ 1​ Upto 10​ LVCMOS, HCSL​ 3 ps​

See all product matrix details

 

Features

  • Si5334/35/38
    • Generates any frequency on any output: 160 kHz to 710 MHz (Si5334/38), or 1 to 350 MHz (Si5335)
    • Exact clock synthesis (0 ppm error)
    • Low phase jitter: 1 ps rms (12 kHz to 20 MHz)
    • Crystal (8 to 30 MHz) or clock (5 to 710 MHz) input
    • 4 differential outputs or 8 single-ended outputs
    • Any format, any output: LVPECL, CML, LVDS, HCSL, LVCMOS, HSTL, SSTL
    • Independent VDDO per output eliminates external level translators (1.5, 1.8, 2.5, 3.3 V)
    • Excellent PSRR; no discrete components required
    • I2C programmable (Si5338), pin-controlled (Si5334), or ClockBuilder customized (Si5335)
    • Configurable spread spectrum clock generation
    • Easy connection to Si5317 for jitter attenuation
 

Applications

 

Technologies

Documentation    Expand All   Collapse All

 
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Data Sheet (6)

Document NameDescriptionVersionLast Updated
Si5334.pdf
Si5334 Data Sheet0.166/28/2010
Si5335.pdf
Si5335 Data Sheet1.04/9/2012
Si5338.pdf
Si5338 Data Sheet1.13/28/2012
SL28PCIe10.pdf
SL28PCIe10 Data Sheet1.13/7/2011
SL28PCIe30.pdf
SL28PCIe30 Data SheetAA3/7/2011
SL28PCIe50.pdf
SL28PCIe50 Data SheetsAA3/7/2011

User Guides (2)

Document NameDescriptionVersionLast Updated
Si5338-56-PROG-EVB.pdf
Si5338/56-PROG-EVB Users Guide0.46/25/2010
Si5338-EVB.pdf
Si5338-EVB User Guide1.411/16/2011

Application Notes (11)

Document NameDescriptionVersionLast Updated
AN360.pdf
AN360: Crystal Selection Guide for Si533x and Si5355/56 Devices0.53/28/2012
AN377.pdf
AN377: Timing and Synchronization in Broadcast Video0.19/9/2009
AN408.pdf
AN408: Termination Options for Any-Frequency, Any Output Clock Generators and Clock Buffers0.411/23/2010
AN428.pdf
AN428: Jump Start: In-System, Flash-Based Programming for Silicon Labs’ Timing Products0.610/5/2010
AN473.pdf
AN473: Configuring the Si5338 Evaluation Board in Zero Delay Mode0.112/10/2009
AN491.pdf
AN491: Power Supply Rejection for Low Jitter Clocks0.14/2/2010
an56.pdf
AN56: Calculating Total Output Jitter for PLLs0.35/4/2012
AN562.pdf
AN562: PCI Express 3.0 Jitter Requirements0.11/5/2011
AN581.pdf
AN581: Meeting SerDes Jitter Requirements Simplified with Silicon Labs Clocks and Oscillators0.19/2/2011
AN623.pdf
AN623: Customizing the Si5335 with ClockBuilder1.011/17/2011
AN624.pdf
AN624: Si5335 Solves Timing Challenges in PCI Express, Computing, Communications and FPGA-Based Systems1.011/17/2011

White Papers (5)

Document NameDescriptionVersionLast Updated
Configurable-Tiny-Clocks-Reduce-Space-Power-and-EMI.pdf
Configurable Tiny Clocks Reduce Space, Power and EMI in Consumer Electronics Designs1.01/27/2012
MultiSynthWhitePaper.pdf
MultiSynth White Paper0415104/15/2010
Reducing-EMI_WP.pdf
Reducing EMI and Improving Signal Integrity Using Spread Spectrum Clocking1.05/31/2011
PCIe-Clock-Source-Selection.pdf
Selecting the Optimum PCIe Clock Source1.01/10/2012
Timing-ICs-Keep-Beat-with-Needs-of-Todays-Embedded-Market.pdf
Timing ICs Keep Beat with Needs of Today’s Embedded Market1.011/21/2011

Miscellaneous (7)

Document NameDescriptionVersionLast Updated
ppr-programmable-product-request-form.docx
Programmable Product Request Form (PPR)3.03/23/2012
Si5338-RM.pdf
Si5338 Reference Manual: Configuring the Si5338 without ClockBuilder Desktop (replaces AN411)1.03/28/2012
Silicon-Labs-Timing-Cross-Reference.pdf
Silicon Labs Timing Cross-Reference to Xilinx, Altera and Lattice FPGA Devices3.05/3/2012
timing-solutions-for-cavium-processors.pdf
Silicon Labs' Timing Solutions for Cavium Processors1.27/15/2011
timing-solutions-for-freescale-processors.pdf
Silicon Labs' Timing Solutions for Freescale Processors1.02/10/2012
Timing-Solutions-for-Altera.pdf
Timing Solutions for Altera0.312/7/2011
timing-solutions-for-plx-technology.pdf
Timing Solutions for PLX Technology1.011/8/2011

PCN (4)

Document NameDescriptionVersionLast Updated
1107132 Si5330, Si5334, Si5338, Si5355, Si5356 Shipment Media Change std.pdf
1107132 Si5330, Si5334, Si5338, Si5355, Si5356 Shipment Media Change std
1203281B_Si5338_DocumentationUpdate_Bulletin_std.pdf
1203281B_Si5338_DocumentationUpdate_Bulletin_std
1204091B_ClockBuilder Desktop Software v5.0.0 Availability-Silicon_Labs.pdf
1204091B_ClockBuilder Desktop Software v5.0.0 Availability-Silicon_Labs
1204101B_Si5335_Datasheet_v1.0_availability_Bulletin.pdf
1204101B_Si5335_Datasheet_v1.0_availability_Bulletin

Design Tools    Expand All   Collapse All

 
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Software (3)

Document NameDescriptionVersionUpdated
AN428SW.zip
AN428 Jumpstart Software Ver 1.31.38/23/2010
release_notes_clockbuilder.txt
Release Notes for ClockBuilder Desktop6/27/2011
ClockBuilderDesktopSwInstall.zip
Si5335/38/51/56 ClockBuilder Desktop Software Version 5.05.03/17/2012

Models (31)

Document NameDescriptionVersionUpdated
si5334a-axxxxx-gm.ibs
Si5334A axxxxx IBIS Model3.111/9/2010
si5334b-axxxxx-gm.ibs
Si5334B axxxxx IBIS Model3.111/9/2010
si5334c-axxxxx-gm.ibs
Si5334C axxxxx IBIS Model3.111/9/2010
si5334d-axxxxx-gm.ibs
Si5334D axxxxx IBIS Model3.111/9/2010
si5334e-axxxxx-gm.ibs
Si5334E axxxxx IBIS Model3.111/9/2010
si5334f-axxxxx-gm.ibs
Si5334F axxxxx IBIS Model3.111/9/2010
si5334g-axxxxx-gm.ibs
Si5334G axxxxx IBIS Model3.111/9/2010
si5334h-axxxxx-gm.ibs
Si5334H axxxxx IBIS Model3.111/9/2010
si5334j-axxxxx-gm.ibs
Si5334J axxxxx IBIS Model3.111/9/2010
si5334k-axxxxx-gm.ibs
Si5334K axxxxx IBIS Model3.111/9/2010
si5334l-axxxxx-gm.ibs
Si5334L axxxxx IBIS Model3.111/9/2010
si5334m-axxxxx-gm.ibs
Si5334M axxxxx IBIS Model3.111/9/2010
si5335A-axxxxx-gmr.ibs
Si5335A IBIS Model3.211/30/2011
si5335B-axxxxx-gmr.ibs
Si5335B IBIS Model3.211/30/2011
si5335C-axxxxx-gmr.ibs
Si5335C IBIS Model3.211/30/2011
si5335D-axxxxx-gmr.ibs
Si5335D IBIS Model3.211/30/2011
si5338a-axxxxx-gm.ibs
Si5338A axxxxx IBIS Model3.66/14/2011
si5338b-axxxxx-gm.ibs
Si5338B axxxxx IBIS Model3.66/14/2011
si5338c-axxxxx-gm.ibs
Si5338C axxxxx IBIS Model3.66/14/2011
si5338d-axxxxx-gm.ibs
Si5338D axxxxx IBIS Model3.66/14/2011
si5338e-axxxxx-gm.ibs
Si5338E axxxxx IBIS Model3.66/14/2011
si5338f-axxxxx-gm.ibs
Si5338F axxxxx IBIS Model3.66/14/2011
si5338g-axxxxx-gm.ibs
Si5338G axxxxx IBIS Model3.66/14/2011
si5338h-axxxxx-gm.ibs
Si5338H axxxxx IBIS Model3.66/14/2011
si5338j-axxxxx-gm.ibs
Si5338J axxxxx IBIS Model3.66/14/2011
si5338k-axxxxx-gm.ibs
Si5338K axxxxx IBIS Model3.66/14/2011
si5338l-axxxxx-gm.ibs
Si5338L axxxxx IBIS Model3.66/14/2011
si5338m-axxxxx-gm.ibs
Si5338M axxxxx IBIS Model3.66/14/2011
si5338n-axxxxx-gm.ibs
Si5338N axxxxx IBIS Model3.66/14/2011
si5338p-axxxxx-gm.ibs
Si5338P axxxxx IBIS Model3.66/14/2011
si5338q-axxxxx-gm.ibs
Si5338Q axxxxx IBIS Model3.66/14/2011

Product Matrix


Part Number Available DocumentsControlPackageReference InputsClock OutputsInput FrequencyOutput FrequencyPhase Jitter (RMS)Output Format(s)VDDVDDO
Si5334AData Sheet
Pin4x4 mm 24-QFN148 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)0.16 - 710 MHz1.0 psLVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL 1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5334BData Sheet
Pin4x4 mm 24-QFN148 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)0.16 - 200 MHz1.0 psLVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL 1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5334CData Sheet
Pin4x4 mm 24-QFN148 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)0.16 - 200 MHz1.0 psLVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL 1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5334DData Sheet
Pin4x4 mm 24-QFN148 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)0.16 - 710 MHz1.0 psLVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL 1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5334EData Sheet
Pin4x4 mm 24-QFN148 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)0.16 - 200 MHz1.0 psLVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL 1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5334FData Sheet
Pin4x4 mm 24-QFN148 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)0.16 - 200 MHz1.0 psLVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL 1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5334GData Sheet
Pin4x4 mm 24-QFN148 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)0.16 - 710 MHz1.0 psLVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL 1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5334JData Sheet
Pin4x4 mm 24-QFN148 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)0.16 - 200 MHz1.0 psLVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL 1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5334KData Sheet
Pin4x4 mm 24-QFN148 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)0.16 - 710 MHz1.0 psLVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL 1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5334LData Sheet
Pin4x4 mm 24-QFN148 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)0.16 - 200 MHz1.0 psLVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL 1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5334MData Sheet
Pin4x4 mm 24-QFN148 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)0.16 - 200 MHz1.0 psLVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL 1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5335AData Sheet
Pin24-pin QFN1410 - 350 (Clock) 25 or 27 (Xtal)1 - 350 MHz1.0 psLVCMOS, LVDS, LVPECL, HCSL, SSTL, HSTL, CML1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5335BData Sheet
Pin24-pin QFN1410 - 350 (Clock) 25/27 (Xtal)1 - 350 MHz1.0 psLVCMOS, LVDS, LVPECL, HCSL, SSTL, HSTL, CML1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5335CData Sheet
Pin24-pin QFN1410 - 350 (Clock) 25/27 (Xtal)1 - 350 MHz1.0 psLVCMOS, LVDS, LVPECL, HCSL, SSTL, HSTL, CML1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5335DData Sheet
Pin24-pin QFN1410 - 350 (Clock) 25/27 (Xtal)1 - 350 MHz1.0 psLVCMOS, LVDS, LVPECL, HCSL, SSTL, HSTL, CML1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5338AData Sheet
I2C4x4 mm 24-QFN148 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)0.16 - 710 MHz1.0 psLVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL 1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5338BData Sheet
I2C4x4 mm 24-QFN148 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)0.16 - 200 MHz1.0 psLVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL 1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5338CData Sheet
I2C4x4 mm 24-QFN148 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)0.16 - 200 MHz1.0 psLVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL 1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5338DData Sheet
I2C4x4 mm 24-QFN148 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)0.16 - 710 MHz1.0 psLVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL 1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5338EData Sheet
I2C4x4 mm 24-QFN148 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)0.16 - 200 MHz1.0 psLVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL 1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5338FData Sheet
I2C4x4 mm 24-QFN148 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)0.16 - 200 MHz1.0 psLVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL 1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5338GData Sheet
I2C4x4 mm 24-QFN148 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)0.16 - 710 MHz1.0 psLVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL 1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5338HData Sheet
I2C4x4 mm 24-QFN148 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)0.16 - 200 MHz1.0 psLVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL 1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5338JData Sheet
I2C4x4 mm 24-QFN148 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)0.16 - 200 MHz1.0 psLVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL 1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5338KData Sheet
I2C4x4 mm 24-QFN148 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)0.16 - 710 MHz1.0 psLVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL 1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5338LData Sheet
I2C4x4 mm 24-QFN148 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)0.16 - 200 MHz1.0 psLVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL 1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5338MData Sheet
I2C4x4 mm 24-QFN148 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)0.16 - 200 MHz1.0 psLVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL 1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5338NData Sheet
I2C4x4 mm 24-QFN448 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)0.16 - 710 MHz1.0 psLVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL 1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5338PData Sheet
I2C4x4 mm 24-QFN448 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)0.16 - 200 MHz1.0 psLVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL 1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5338QData Sheet
I2C4x4 mm 24-QFN448 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)0.16 - 200 MHz1.0 psLVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL 1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
SL28PCIe10Data Sheet
I2C/Pin32-pin QFN1810 - 45 MHz100 MHz, 25 MHz, 27 MHz, Programmable SE3.1 psLVCMOS, HCSL 3.3 V3.3 - 1.05 V
SL28PCIe50Data Sheet
I2C/Pin48-pin QFN11010 - 45 MHz100 MHz, 25 MHz, Programmable SE3.1 psLVCMOS, HCSL 3.3 V3.3 - 1.05 V

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To ensure proper compliance with the PCIe standard, systems require careful attention to the timing subsystem and architecture. This article explores some of the standard clocking architectures for PCIe and considers their benefits for typical system applications, including: clock architecture selection (Common Refclk, Separate Refclk or Data Clocked Refclk), requirements in applications that use FPGAs, jitter performance of the reference clock, use of spread spectrum clocking, and more.

SyncE and IEEE 1588: Sync Distribution for a Unified Network

Since Ethernet or packet based networks operate asynchronously, many of the traditional applications that depend on synchronization are not supported. Designers increasingly need to combine services supplied by data efficient packet networks with the ones served by the large installed base of traditional SONET/SDH networks. Both Synchronous Ethernet (SyncE) and packet timing using the IEEE 1588 protocol offer viable solutions in unifying service delivery over both networks. Download this new app note from Silicon Labs to discover methods for transporting synchronization and potential synchronized timing implementations.

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