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PCI Express (PCIe) Gen 1/2/3 Clocks

Silicon Labs' PCI Express clocks provide industry-leading jitter performance, compliance with PCI Express (PCIe) Gen 1/2/3 requirements, outstanding frequency flexibility and configurable AC parameters for signal integrity optimization.

The PCIe Clock family addresses the specific clock requirements of PCIe Generation 1, 2 or 3 system interfaces. This interface standard has become the industry choice as a high speed interconnect between devices and system I/Os and is used in consumer, server, storage, IP gateways, multi-function printers (MFPs) and industrial applications.

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Selecting the Optimum PCIe Clock Source

Features

Si5334/35/38—4 Differential Output Clock Generator

Lowest jitter PCIe Gen 3 clock
Complies with all PCIe Gen 1/2/3 jitter specifications with margin
PCIe compliant spread spectrum clock generation
Any frequency on any output (0.16–350 MHz)
Integrated level/format translation (HCSL, LVDS, LVCMOS, LVPECL, CML)
ClockBuilder web-configurable (Si5335)
Pin-programmable (Si5334)
I²C programmable (Si5338)
24-pin QFN package

Si52142/43/44/46/47—2, 4, 6 and 9 PCIe Output Clock Generator

Extremely low power consumption (<6 mA) HCSL output drivers
Supports 2, 4, 6 or 9 PCIe outputs
Integrated termination and I_REF resistors
I²C control interface for AC parameter, signal integrity and EMI tuning
Operate from 25 MHz RCLK or widely available, low cost 25 MHz crystals
Supports industrial grade (-40 to + 85 ˚C)
24-, 32- and 48-pin QFN packages
Contact Silicon Labs to build a custom clock (PPR)

Applications

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Data Sheet (20)

Document Name	Description	Version	Last Updated
CY28400.pdf	CY28400 Data Sheet	A	3/9/2011
CY28400-2.pdf	CY28400-2 Data Sheet	C	3/9/2011
CY28800.pdf	CY28800 Data Sheet	B	3/9/2011
Si52142.pdf	Si52142 Data Sheet	0.1	1/9/2012
Si52143.pdf	Si52143 Data Sheet	0.1	1/9/2012
Si52144.pdf	Si52144 Data Sheet	0.1	1/9/2012
Si52146.pdf	Si52146 Data Sheet	1.0	1/9/2012
Si52147.pdf	Si52147 Data Sheet	1.0	4/26/2012
Si5334.pdf	Si5334 Data Sheet	0.16	6/28/2010
Si5335.pdf	Si5335 Data Sheet	1.0	4/9/2012
Si5338.pdf	Si5338 Data Sheet	1.1	3/28/2012
Si5356.pdf	Si5356A Data Sheet	1.0	5/1/2012
SL28DB200.pdf	SL28DB200 Data Sheet	C	3/9/2011
SL28PCIe14.pdf	SL28PCIe14 Data Sheet	AA	3/9/2011
SL28PCIe16.pdf	SL28PCIe16 Data Sheet	AB	3/10/2011
SL28PCIe25.pdf	SL28PCIe25 Data Sheet	AA	3/10/2011
SL28PCIe26.pdf	SL28PCIe26 Data Sheet	AA	3/10/2011
SL28SRC01.pdf	SL28SRC01 Data Sheet	AA	3/8/2011
SL28SRC02.pdf	SL28SRC02 Data Sheet	AA	3/8/2011
SL28SRC04.pdf	SL28SRC04 Data Sheet	AA	3/8/2011

User Guides (5)

Document Name	Description	Version	Last Updated
Si52144-EVB.pdf	Si52144-EVB User's Guide	0.1	1/9/2012
Si52147-EVB.pdf	Si52147-EVB User's Guide	0.1	1/9/2012
Si5338-56-PROG-EVB.pdf	Si5338/56-PROG-EVB Users Guide	0.4	6/25/2010
Si5338-EVB.pdf	Si5338-EVB User Guide	1.4	11/16/2011
Si5356EVB.pdf	Si5356-EVB User Guide	0.2	6/25/2010

Application Notes (13)

Document Name	Description	Version	Last Updated
AN360.pdf	AN360: Crystal Selection Guide for Si533x and Si5355/56 Devices	0.5	3/28/2012
AN377.pdf	AN377: Timing and Synchronization in Broadcast Video	0.1	9/9/2009
AN408.pdf	AN408: Termination Options for Any-Frequency, Any Output Clock Generators and Clock Buffers	0.4	11/23/2010
AN428.pdf	AN428: Jump Start: In-System, Flash-Based Programming for Silicon Labs’ Timing Products	0.6	10/5/2010
AN473.pdf	AN473: Configuring the Si5338 Evaluation Board in Zero Delay Mode	0.1	12/10/2009
AN491.pdf	AN491: Power Supply Rejection for Low Jitter Clocks	0.1	4/2/2010
an56.pdf	AN56: Calculating Total Output Jitter for PLLs	0.3	5/4/2012
AN562.pdf	AN562: PCI Express 3.0 Jitter Requirements	0.1	1/5/2011
AN581.pdf	AN581: Meeting SerDes Jitter Requirements Simplified with Silicon Labs Clocks and Oscillators	0.1	9/2/2011
AN623.pdf	AN623: Customizing the Si5335 with ClockBuilder	1.0	11/17/2011
AN624.pdf	AN624: Si5335 Solves Timing Challenges in PCI Express, Computing, Communications and FPGA-Based Systems	1.0	11/17/2011
AN636.pdf	AN636: Si5214x and Si5315x Signal Integrity Tuning to Improve Connectivity	0.1	1/12/2012
AN565.pdf	Configuring the Si5356A	0.1	4/25/2011

White Papers (5)

Document Name	Description	Version	Last Updated
Configurable-Tiny-Clocks-Reduce-Space-Power-and-EMI.pdf	Configurable Tiny Clocks Reduce Space, Power and EMI in Consumer Electronics Designs	1.0	1/27/2012
MultiSynthWhitePaper.pdf	MultiSynth White Paper	041510	4/15/2010
Reducing-EMI_WP.pdf	Reducing EMI and Improving Signal Integrity Using Spread Spectrum Clocking	1.0	5/31/2011
PCIe-Clock-Source-Selection.pdf	Selecting the Optimum PCIe Clock Source	1.0	1/10/2012
Timing-ICs-Keep-Beat-with-Needs-of-Todays-Embedded-Market.pdf	Timing ICs Keep Beat with Needs of Today’s Embedded Market	1.0	11/21/2011

Miscellaneous (7)

Document Name	Description	Version	Last Updated
ppr-programmable-product-request-form.docx	Programmable Product Request Form (PPR)	3.0	3/23/2012
Si5338-RM.pdf	Si5338 Reference Manual: Configuring the Si5338 without ClockBuilder Desktop (replaces AN411)	1.0	3/28/2012
Silicon-Labs-Timing-Cross-Reference.pdf	Silicon Labs Timing Cross-Reference to Xilinx, Altera and Lattice FPGA Devices	3.0	5/3/2012
timing-solutions-for-cavium-processors.pdf	Silicon Labs' Timing Solutions for Cavium Processors	1.2	7/15/2011
timing-solutions-for-freescale-processors.pdf	Silicon Labs' Timing Solutions for Freescale Processors	1.0	2/10/2012
Timing-Solutions-for-Altera.pdf	Timing Solutions for Altera	0.3	12/7/2011
timing-solutions-for-plx-technology.pdf	Timing Solutions for PLX Technology	1.0	11/8/2011

PCN (10)

Document Name	Description	Version	Last Updated
1107132 Si5330, Si5334, Si5338, Si5355, Si5356 Shipment Media Change std.pdf	1107132 Si5330, Si5334, Si5338, Si5355, Si5356 Shipment Media Change std
1109081 SPEL Assy PCN std.pdf	1109081 SPEL Assy PCN std
11090810 Test to UTL std.pdf	11090810 Test to UTL std
1109084_SL Assembly Transfer to UTAC Thailand std reissue.pdf	1109084 SL Assembly Transfer to UTAC Thailand std reissue
1110101B_Bulletin to expand OFC for ship OSEP parts.pdf	1110101B_Bulletin to expand OFC for ship OSEP parts
1203231B_LPP_Reel1.pdf	1203231B_LPP_Reel1
1203281B_Si5338_DocumentationUpdate_Bulletin_std.pdf	1203281B_Si5338_DocumentationUpdate_Bulletin_std
1204091B_ClockBuilder Desktop Software v5.0.0 Availability-Silicon_Labs.pdf	1204091B_ClockBuilder Desktop Software v5.0.0 Availability-Silicon_Labs
1204101B_Si5335_Datasheet_v1.0_availability_Bulletin.pdf	1204101B_Si5335_Datasheet_v1.0_availability_Bulletin
1205011B_Si5356A_Si5355_Datasheet_v1.0_Availability_Bulletin.pdf	1205011B_Si5356A_Si5355_Datasheet_v1.0_Availability_Bulletin

Development Tools

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Software (3)

Document Name	Description	Version	Updated
AN428SW.zip	AN428 Jumpstart Software Ver 1.3	1.3	8/23/2010
release_notes_clockbuilder.txt	Release Notes for ClockBuilder Desktop		6/27/2011
ClockBuilderDesktopSwInstall.zip	Si5335/38/51/56 ClockBuilder Desktop Software Version 5.0	5.0	3/17/2012

Models (23)

Document Name	Description	Version	Updated
si5334k-axxxxx-gm.ibs	Si5334K axxxxx IBIS Model	3.1	11/9/2010
si5334l-axxxxx-gm.ibs	Si5334L axxxxx IBIS Model	3.1	11/9/2010
si5334m-axxxxx-gm.ibs	Si5334M axxxxx IBIS Model	3.1	11/9/2010
si5335A-axxxxx-gmr.ibs	Si5335A IBIS Model	3.2	11/30/2011
si5335B-axxxxx-gmr.ibs	Si5335B IBIS Model	3.2	11/30/2011
si5335C-axxxxx-gmr.ibs	Si5335C IBIS Model	3.2	11/30/2011
si5335D-axxxxx-gmr.ibs	Si5335D IBIS Model	3.2	11/30/2011
si5338a-axxxxx-gm.ibs	Si5338A axxxxx IBIS Model	3.6	6/14/2011
si5338b-axxxxx-gm.ibs	Si5338B axxxxx IBIS Model	3.6	6/14/2011
si5338c-axxxxx-gm.ibs	Si5338C axxxxx IBIS Model	3.6	6/14/2011
si5338d-axxxxx-gm.ibs	Si5338D axxxxx IBIS Model	3.6	6/14/2011
si5338e-axxxxx-gm.ibs	Si5338E axxxxx IBIS Model	3.6	6/14/2011
si5338f-axxxxx-gm.ibs	Si5338F axxxxx IBIS Model	3.6	6/14/2011
si5338g-axxxxx-gm.ibs	Si5338G axxxxx IBIS Model	3.6	6/14/2011
si5338h-axxxxx-gm.ibs	Si5338H axxxxx IBIS Model	3.6	6/14/2011
si5338j-axxxxx-gm.ibs	Si5338J axxxxx IBIS Model	3.6	6/14/2011
si5338k-axxxxx-gm.ibs	Si5338K axxxxx IBIS Model	3.6	6/14/2011
si5338l-axxxxx-gm.ibs	Si5338L axxxxx IBIS Model	3.6	6/14/2011
si5338m-axxxxx-gm.ibs	Si5338M axxxxx IBIS Model	3.6	6/14/2011
si5338n-axxxxx-gm.ibs	Si5338N axxxxx IBIS Model	3.6	6/14/2011
si5338p-axxxxx-gm.ibs	Si5338P axxxxx IBIS Model	3.6	6/14/2011
si5338q-axxxxx-gm.ibs	Si5338Q axxxxx IBIS Model	3.6	6/14/2011
si5356a-axxxxx-gm.ibs	Si5356A axxxxx IBIS Model	3.2	11/30/2010

Product Matrix

Part Number	Available Documents	Control	Package	Reference Inputs	Clock Outputs	Input Frequency	Output Frequency	Phase Jitter (RMS)	Output Format(s)	VDD	VDDO
CY28400	Data Sheet	I2C/Pin	28-pin SSOP	1	4	100 MHz	100 MHz	> 1.0 ps	HCSL	3.3 V	3.3 V
CY28400-2	Data Sheet	I2C/Pin	28-pin SSOP/TSSOP	1	4	100 MHz	100 MHz	> 1.0 ps	HCSL	3.3 V	3.3 V
CY28800	Data Sheet	I2C/Pin	48-pin SSOP	1	8	100 MHz	100 MHz	> 1.0 ps	HCSL	3.3 V	3.3 V
Si52142	Data Sheet	I2C/Pin	24-pin QFN	1	3	25 MHz	100 MHz, 25 MHz	1.0 ps	HSCL, LVCMOS	3.3 V	3.3 V
Si52143	Data Sheet	I2C/Pin	24-pin QFN	1	5	25 MHz	100 MHz, 25 MHz	1.0 ps	HSCL, LVCMOS	3.3 V	3.3 V
Si52144	Data Sheet	I2C/Pin	24-pin QFN	1	4	25 MHz	100 MHz	1.0 ps	HSCL	3.3 V	3.3 V
Si52146	Data Sheet	I2C/Pin	32-pin QFN	1	6	25 MHz	100 MHz	1.0 ps	HSCL	3.3 V	3.3 V
Si52147	Data Sheet	I2C/Pin	32-pin QFN	1	9	25 MHz	100 MHz	1.0 ps	HSCL	3.3 V	3.3 V
Si5334K	Data Sheet	Pin	4x4 mm 24-QFN	1	4	8 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)	0.16 - 710 MHz	1.0 ps	LVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL	1.8 V, 2.5 V, 3.3 V	1.8 V, 2.5 V, 3.3 V
Si5334L	Data Sheet	Pin	4x4 mm 24-QFN	1	4	8 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)	0.16 - 200 MHz	1.0 ps	LVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL	1.8 V, 2.5 V, 3.3 V	1.8 V, 2.5 V, 3.3 V
Si5334M	Data Sheet	Pin	4x4 mm 24-QFN	1	4	8 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)	0.16 - 200 MHz	1.0 ps	LVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL	1.8 V, 2.5 V, 3.3 V	1.8 V, 2.5 V, 3.3 V
Si5335A	Data Sheet	Pin	24-pin QFN	1	4	10 - 350 (Clock) 25 or 27 (Xtal)	1 - 350 MHz	1.0 ps	LVCMOS, LVDS, LVPECL, HCSL, SSTL, HSTL, CML	1.8 V, 2.5 V, 3.3 V	1.8 V, 2.5 V, 3.3 V
Si5335B	Data Sheet	Pin	24-pin QFN	1	4	10 - 350 (Clock) 25/27 (Xtal)	1 - 350 MHz	1.0 ps	LVCMOS, LVDS, LVPECL, HCSL, SSTL, HSTL, CML	1.8 V, 2.5 V, 3.3 V	1.8 V, 2.5 V, 3.3 V
Si5335C	Data Sheet	Pin	24-pin QFN	1	4	10 - 350 (Clock) 25/27 (Xtal)	1 - 350 MHz	1.0 ps	LVCMOS, LVDS, LVPECL, HCSL, SSTL, HSTL, CML	1.8 V, 2.5 V, 3.3 V	1.8 V, 2.5 V, 3.3 V
Si5335D	Data Sheet	Pin	24-pin QFN	1	4	10 - 350 (Clock) 25/27 (Xtal)	1 - 350 MHz	1.0 ps	LVCMOS, LVDS, LVPECL, HCSL, SSTL, HSTL, CML	1.8 V, 2.5 V, 3.3 V	1.8 V, 2.5 V, 3.3 V
Si5338A	Data Sheet	I2C	4x4 mm 24-QFN	1	4	8 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)	0.16 - 710 MHz	1.0 ps	LVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL	1.8 V, 2.5 V, 3.3 V	1.8 V, 2.5 V, 3.3 V
Si5338B	Data Sheet	I2C	4x4 mm 24-QFN	1	4	8 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)	0.16 - 200 MHz	1.0 ps	LVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL	1.8 V, 2.5 V, 3.3 V	1.8 V, 2.5 V, 3.3 V
Si5338C	Data Sheet	I2C	4x4 mm 24-QFN	1	4	8 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)	0.16 - 200 MHz	1.0 ps	LVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL	1.8 V, 2.5 V, 3.3 V	1.8 V, 2.5 V, 3.3 V
Si5338D	Data Sheet	I2C	4x4 mm 24-QFN	1	4	8 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)	0.16 - 710 MHz	1.0 ps	LVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL	1.8 V, 2.5 V, 3.3 V	1.8 V, 2.5 V, 3.3 V
Si5338E	Data Sheet	I2C	4x4 mm 24-QFN	1	4	8 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)	0.16 - 200 MHz	1.0 ps	LVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL	1.8 V, 2.5 V, 3.3 V	1.8 V, 2.5 V, 3.3 V
Si5338F	Data Sheet	I2C	4x4 mm 24-QFN	1	4	8 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)	0.16 - 200 MHz	1.0 ps	LVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL	1.8 V, 2.5 V, 3.3 V	1.8 V, 2.5 V, 3.3 V
Si5338G	Data Sheet	I2C	4x4 mm 24-QFN	1	4	8 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)	0.16 - 710 MHz	1.0 ps	LVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL	1.8 V, 2.5 V, 3.3 V	1.8 V, 2.5 V, 3.3 V
Si5338H	Data Sheet	I2C	4x4 mm 24-QFN	1	4	8 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)	0.16 - 200 MHz	1.0 ps	LVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL	1.8 V, 2.5 V, 3.3 V	1.8 V, 2.5 V, 3.3 V
Si5338J	Data Sheet	I2C	4x4 mm 24-QFN	1	4	8 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)	0.16 - 200 MHz	1.0 ps	LVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL	1.8 V, 2.5 V, 3.3 V	1.8 V, 2.5 V, 3.3 V
Si5338K	Data Sheet	I2C	4x4 mm 24-QFN	1	4	8 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)	0.16 - 710 MHz	1.0 ps	LVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL	1.8 V, 2.5 V, 3.3 V	1.8 V, 2.5 V, 3.3 V
Si5338L	Data Sheet	I2C	4x4 mm 24-QFN	1	4	8 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)	0.16 - 200 MHz	1.0 ps	LVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL	1.8 V, 2.5 V, 3.3 V	1.8 V, 2.5 V, 3.3 V
Si5338M	Data Sheet	I2C	4x4 mm 24-QFN	1	4	8 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)	0.16 - 200 MHz	1.0 ps	LVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL	1.8 V, 2.5 V, 3.3 V	1.8 V, 2.5 V, 3.3 V
Si5338N	Data Sheet	I2C	4x4 mm 24-QFN	4	4	8 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)	0.16 - 710 MHz	1.0 ps	LVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL	1.8 V, 2.5 V, 3.3 V	1.8 V, 2.5 V, 3.3 V
Si5338P	Data Sheet	I2C	4x4 mm 24-QFN	4	4	8 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)	0.16 - 200 MHz	1.0 ps	LVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL	1.8 V, 2.5 V, 3.3 V	1.8 V, 2.5 V, 3.3 V
Si5338Q	Data Sheet	I2C	4x4 mm 24-QFN	4	4	8 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)	0.16 - 200 MHz	1.0 ps	LVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL	1.8 V, 2.5 V, 3.3 V	1.8 V, 2.5 V, 3.3 V
Si5356	Data Sheet	I2C	4x4 mm 24-QFN	1	8	25/27 MHz (Xtal) or 5 - 200 MHz (Clock)	1 - 200 MHz	2.0 ps	LVCMOS	1.8 V, 2.5 V, 3.3 V	1.8 V, 2.5 V, 3.3 V
SL28DB200	Data Sheet	Pin	16-pin TSSOP	1	2	100 MHz	100 MHz	> 1.0 ps	HCSL	3.3 V	3.3 V
SL28PCIe14	Data Sheet	I2C/Pin	32-pin QFN	2	4	25/100 MHz	100 MHz	1.0 ps	HCSL	3.3 V	3.3 V
SL28PCIe16	Data Sheet	I2C/Pin	32-pin QFN	1	6	10 - 45 MHz	100 MHz	1.0 ps	HCSL	3.3 V	3.3 V
SL28PCIe25	Data Sheet	I2C/Pin	32-pin QFN	1	4	25 MHz	100 MHz, 25 MHz	3.1 ps	LVCMOS, HCSL	3.3 V	3.3 V
SL28PCIe26	Data Sheet	I2C/Pin	32-pin QFN	1	4	25 MHz	100 MHz	3.1 ps	HCSL	3.3 V	3.3 V
SL28SRC01	Data Sheet	Pin	16-pin TSSOP	1	1	14.318 MHz	100 MHz	1.0 ps	HCSL	3.3 V	3.3 V
SL28SRC02	Data Sheet	Pin	20-pin TSSOP	1	2	14.318 MHz	100 MHz	1.0 ps	HCSL	3.3 V	3.3 V
SL28SRC04	Data Sheet	Pin	24-pin TSSOP	1	4	14.318 MHz	100 MHz	1.0 ps	HCSL	3.3 V	3.3 V

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The Si5334/35/38 provides the ability to generate a mix of up to four differential LVDS, LVPECL and HCSL clocks. Each output clock is PCIe Gen 3 compliant and can be a unique frequency up to 350 MHz with a unique output format and supply rail.

The SL28PCIe10/30/50 highly integrated, customizable clock generator family is capable of generating PCIe compliant differential clocks, standard frequency LVCMOS system clocks and user programmable clocks. This family can be factory customized to provide a mix HCSL and LVCMOS outputs. These outputs can be programmed to produce frequencies that range from 1 to 400 MHz. Programmable AC parameters (output drive strength, rise/fall times and differential signal cross point), spread spectrum support and programmable output impedance are available to prevent electromagnetic interference (EMI) issues. All devices in this family are factory configured to a default customer specification that can later be modified via the I²C interface.

The SL28PCIe25/26/14/16 and SL28SRCxx off-the-shelf PCIe clock generators are simple to use and low power. To reduce electromagnetic interference, the spread spectrum function is easily enabled through a control pin interface. The SL28PCIe25/26/14/16 devices also have an I²C interface that allows cross point adjustment for lower common mode energy dissipation as well as the ability to disable unused output signals. Spread spectrum can also be controlled through the I²C bus.

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Selecting the Optimum PCIe Clock Source

To ensure proper compliance with the PCIe standard, systems require careful attention to the timing subsystem and architecture. This article explores some of the standard clocking architectures for PCIe and considers their benefits for typical system applications, including: clock architecture selection (Common Refclk, Separate Refclk or Data Clocked Refclk), requirements in applications that use FPGAs, jitter performance of the reference clock, use of spread spectrum clocking, and more.

SyncE and IEEE 1588: Sync Distribution for a Unified Network

Since Ethernet or packet based networks operate asynchronously, many of the traditional applications that depend on synchronization are not supported. Designers increasingly need to combine services supplied by data efficient packet networks with the ones served by the large installed base of traditional SONET/SDH networks. Both Synchronous Ethernet (SyncE) and packet timing using the IEEE 1588 protocol offer viable solutions in unifying service delivery over both networks. Download this new app note from Silicon Labs to discover methods for transporting synchronization and potential synchronized timing implementations.

Prototyping with Frequency-Flexible Crystal Oscillators

Developers of new systems ideally should make decisions regarding clocking requirements early in the design process. Although clocking rates are critical parameters that should be known in advance, determining these rates sometimes requires experimentation and re-evaluation. The use of frequency-flexible, programmable crystal oscillators (XOs) as prototyping tools can facilitate the process of validating system performance and help streamline the overall product development cycle.

Clock Generators and Buffers

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PCI Express (PCIe) Gen 1/2/3 Clocks

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