​Zero Delay Buffers

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SL23EP05 Zero Delay Buffer Block Diagram

Silicon Labs' zero delay clock buffer products are used in applications that require zero propagation delay between the input and output clocks. Silicon Labs' zero delay buffers are based on Silicon Labs’ low power, high performance PLL technology and provide low power consumption and allow spread spectrum modulation to propagate through the system for EMI reduction.

Primarily used in high performance systems for clock distribution, these products provide very low skew, jitter and propagation delay, meet very tight setup and hold time requirements, and improve system timing margins. These low delay and skew zero delay buffers offer improved performance, power, and wider frequency range than the competition.

 

Features

  • PLL-based clock distribution
  • Low propagation delay
  • Low output-to-output skew
  • Low device-to-device skew
  • Low output jitter
  • Multiple drive strength options
  • Wide operation frequency range: 10 to 220MHz
  • 3.3V to 2.5V power supply range
  • Low power dissipation
  • 4, 5, 8 and 9 output devices available
  • Programmable skew rise/fall times in output drivers
 

Applications

Documentation    Expand All   Collapse All

 
 Get notified when these documents are updated.

Data Sheet (7)

Document NameDescriptionVersionLast Updated
Si5335.pdf
Si5335 Data Sheet1.04/9/2012
Si5338.pdf
Si5338 Data Sheet1.13/28/2012
SL2309.pdf
SL2309 Data Sheet1.33/9/2011
SL23EP04.pdf
SL23EP04 Data Sheet2.13/30/2011
SL23EP05.pdf
SL23EP05 Data Sheet0.03/11/2011
SL23EP08.pdf
SL23EP08 Data Sheet1.03/11/2011
SL23EP09.pdf
SL23EP09 Data Sheet2.03/30/2011

User Guides (2)

Document NameDescriptionVersionLast Updated
Si5338-56-PROG-EVB.pdf
Si5338/56-PROG-EVB Users Guide0.46/25/2010
Si5338-EVB.pdf
Si5338-EVB User Guide1.411/16/2011

Application Notes (9)

Document NameDescriptionVersionLast Updated
AN360.pdf
AN360: Crystal Selection Guide for Si533x and Si5355/56 Devices0.53/28/2012
AN377.pdf
AN377: Timing and Synchronization in Broadcast Video0.19/9/2009
AN408.pdf
AN408: Termination Options for Any-Frequency, Any Output Clock Generators and Clock Buffers0.411/23/2010
AN428.pdf
AN428: Jump Start: In-System, Flash-Based Programming for Silicon Labs’ Timing Products0.610/5/2010
AN473.pdf
AN473: Configuring the Si5338 Evaluation Board in Zero Delay Mode0.112/10/2009
AN491.pdf
AN491: Power Supply Rejection for Low Jitter Clocks0.14/2/2010
an56.pdf
AN56: Calculating Total Output Jitter for PLLs0.35/4/2012
AN562.pdf
AN562: PCI Express 3.0 Jitter Requirements0.11/5/2011
AN581.pdf
AN581: Meeting SerDes Jitter Requirements Simplified with Silicon Labs Clocks and Oscillators0.19/2/2011

White Papers (4)

Document NameDescriptionVersionLast Updated
Configurable-Tiny-Clocks-Reduce-Space-Power-and-EMI.pdf
Configurable Tiny Clocks Reduce Space, Power and EMI in Consumer Electronics Designs1.01/27/2012
MultiSynthWhitePaper.pdf
MultiSynth White Paper0415104/15/2010
PCIe-Clock-Source-Selection.pdf
Selecting the Optimum PCIe Clock Source1.01/10/2012
Timing-ICs-Keep-Beat-with-Needs-of-Todays-Embedded-Market.pdf
Timing ICs Keep Beat with Needs of Today’s Embedded Market1.011/21/2011

Miscellaneous (7)

Document NameDescriptionVersionLast Updated
ppr-programmable-product-request-form.docx
Programmable Product Request Form (PPR)3.03/23/2012
Si5338-RM.pdf
Si5338 Reference Manual: Configuring the Si5338 without ClockBuilder Desktop (replaces AN411)1.03/28/2012
Silicon-Labs-Timing-Cross-Reference.pdf
Silicon Labs Timing Cross-Reference to Xilinx, Altera and Lattice FPGA Devices3.05/3/2012
timing-solutions-for-cavium-processors.pdf
Silicon Labs' Timing Solutions for Cavium Processors1.27/15/2011
timing-solutions-for-freescale-processors.pdf
Silicon Labs' Timing Solutions for Freescale Processors1.02/10/2012
Timing-Solutions-for-Altera.pdf
Timing Solutions for Altera0.312/7/2011
timing-solutions-for-plx-technology.pdf
Timing Solutions for PLX Technology1.011/8/2011

PCN (6)

Document NameDescriptionVersionLast Updated
1107132 Si5330, Si5334, Si5338, Si5355, Si5356 Shipment Media Change std.pdf
1107132 Si5330, Si5334, Si5338, Si5355, Si5356 Shipment Media Change std
11090810 Test to UTL std.pdf
11090810 Test to UTL std
1109084_SL Assembly Transfer to UTAC Thailand std reissue.pdf
1109084 SL Assembly Transfer to UTAC Thailand std reissue
1110101B_Bulletin to expand OFC for ship OSEP parts.pdf
1110101B_Bulletin to expand OFC for ship OSEP parts
1203281B_Si5338_DocumentationUpdate_Bulletin_std.pdf
1203281B_Si5338_DocumentationUpdate_Bulletin_std
1204091B_ClockBuilder Desktop Software v5.0.0 Availability-Silicon_Labs.pdf
1204091B_ClockBuilder Desktop Software v5.0.0 Availability-Silicon_Labs

Design Tools    Expand All   Collapse All

 
 Get notified when these files are updated.

Software (3)

Document NameDescriptionVersionUpdated
AN428SW.zip
AN428 Jumpstart Software Ver 1.31.38/23/2010
release_notes_clockbuilder.txt
Release Notes for ClockBuilder Desktop6/27/2011
ClockBuilderDesktopSwInstall.zip
Si5335/38/51/56 ClockBuilder Desktop Software Version 5.05.03/17/2012

Models (15)

Document NameDescriptionVersionUpdated
si5338a-axxxxx-gm.ibs
Si5338A axxxxx IBIS Model3.66/14/2011
si5338b-axxxxx-gm.ibs
Si5338B axxxxx IBIS Model3.66/14/2011
si5338c-axxxxx-gm.ibs
Si5338C axxxxx IBIS Model3.66/14/2011
si5338d-axxxxx-gm.ibs
Si5338D axxxxx IBIS Model3.66/14/2011
si5338e-axxxxx-gm.ibs
Si5338E axxxxx IBIS Model3.66/14/2011
si5338f-axxxxx-gm.ibs
Si5338F axxxxx IBIS Model3.66/14/2011
si5338g-axxxxx-gm.ibs
Si5338G axxxxx IBIS Model3.66/14/2011
si5338h-axxxxx-gm.ibs
Si5338H axxxxx IBIS Model3.66/14/2011
si5338j-axxxxx-gm.ibs
Si5338J axxxxx IBIS Model3.66/14/2011
si5338k-axxxxx-gm.ibs
Si5338K axxxxx IBIS Model3.66/14/2011
si5338l-axxxxx-gm.ibs
Si5338L axxxxx IBIS Model3.66/14/2011
si5338m-axxxxx-gm.ibs
Si5338M axxxxx IBIS Model3.66/14/2011
si5338n-axxxxx-gm.ibs
Si5338N axxxxx IBIS Model3.66/14/2011
si5338p-axxxxx-gm.ibs
Si5338P axxxxx IBIS Model3.66/14/2011
si5338q-axxxxx-gm.ibs
Si5338Q axxxxx IBIS Model3.66/14/2011

Product Matrix


Part Number Available DocumentsControlPackageReference InputsClock OutputsInput FrequencyOutput FrequencyPhase Jitter (RMS)Output Format(s)VDDVDDO
Si5338AData Sheet
I2C4x4 mm 24-QFN148 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)0.16 - 710 MHz1.0 psLVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL 1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5338BData Sheet
I2C4x4 mm 24-QFN148 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)0.16 - 200 MHz1.0 psLVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL 1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5338CData Sheet
I2C4x4 mm 24-QFN148 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)0.16 - 200 MHz1.0 psLVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL 1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5338DData Sheet
I2C4x4 mm 24-QFN148 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)0.16 - 710 MHz1.0 psLVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL 1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5338EData Sheet
I2C4x4 mm 24-QFN148 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)0.16 - 200 MHz1.0 psLVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL 1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5338FData Sheet
I2C4x4 mm 24-QFN148 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)0.16 - 200 MHz1.0 psLVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL 1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5338GData Sheet
I2C4x4 mm 24-QFN148 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)0.16 - 710 MHz1.0 psLVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL 1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5338HData Sheet
I2C4x4 mm 24-QFN148 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)0.16 - 200 MHz1.0 psLVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL 1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5338JData Sheet
I2C4x4 mm 24-QFN148 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)0.16 - 200 MHz1.0 psLVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL 1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5338KData Sheet
I2C4x4 mm 24-QFN148 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)0.16 - 710 MHz1.0 psLVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL 1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5338LData Sheet
I2C4x4 mm 24-QFN148 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)0.16 - 200 MHz1.0 psLVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL 1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5338MData Sheet
I2C4x4 mm 24-QFN148 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)0.16 - 200 MHz1.0 psLVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL 1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5338NData Sheet
I2C4x4 mm 24-QFN448 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)0.16 - 710 MHz1.0 psLVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL 1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5338PData Sheet
I2C4x4 mm 24-QFN448 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)0.16 - 200 MHz1.0 psLVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL 1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
Si5338QData Sheet
I2C4x4 mm 24-QFN448 - 30 MHz (Xtal) or 5 - 710 MHz (Clock)0.16 - 200 MHz1.0 psLVPECL, LVDS, LVCMOS, HCSL, SSTL, HSTL 1.8 V, 2.5 V, 3.3 V1.8 V, 2.5 V, 3.3 V
SL2305Data Sheet
Pin8-pin TSSOP/SOIC151 - 140 MHz1 - 140 MHz> 1.0 psLVCMOS 3.3 V
SL2309Data Sheet
Pin16-pin TSSOP/SOIC1910 - 140 MHz10 - 140 MHz> 1.0 psLVCMOS 3.3 V
SL23EP04Data Sheet
Pin8-pin SOIC1410 - 220 MHz10 - 220 MHz> 1.0 psLVCMOS 2.5 V, 3.3 V
SL23EP05Data Sheet
Pin8-pin TSSOP/SOIC1510 - 220 MHz10 - 220 MHz> 1.0 psLVCMOS 2.5 V, 3.3 V
SL23EP08Data Sheet
Pin16-pin TSSOP/SOIC1810 - 220 MHz10 - 220 MHz> 1.0 psLVCMOS 2.5 V, 3.3 V
SL23EP09Data Sheet
Pin16-pin TSSOP/SOIC1910 - 220 MHz10 - 220 MHz> 1.0 psLVCMOS 2.5 V, 3.3 V

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Featured White Papers

Selecting the Optimum PCIe Clock Source

To ensure proper compliance with the PCIe standard, systems require careful attention to the timing subsystem and architecture. This article explores some of the standard clocking architectures for PCIe and considers their benefits for typical system applications, including: clock architecture selection (Common Refclk, Separate Refclk or Data Clocked Refclk), requirements in applications that use FPGAs, jitter performance of the reference clock, use of spread spectrum clocking, and more.

SyncE and IEEE 1588: Sync Distribution for a Unified Network

Since Ethernet or packet based networks operate asynchronously, many of the traditional applications that depend on synchronization are not supported. Designers increasingly need to combine services supplied by data efficient packet networks with the ones served by the large installed base of traditional SONET/SDH networks. Both Synchronous Ethernet (SyncE) and packet timing using the IEEE 1588 protocol offer viable solutions in unifying service delivery over both networks. Download this new app note from Silicon Labs to discover methods for transporting synchronization and potential synchronized timing implementations.

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Developers of new systems ideally should make decisions regarding clocking requirements early in the design process. Although clocking rates are critical parameters that should be known in advance, determining these rates sometimes requires experimentation and re-evaluation. The use of frequency-flexible, programmable crystal oscillators (XOs) as prototyping tools can facilitate the process of validating system performance and help streamline the overall product development cycle.

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