4-PLL Jitter Attenuating Clocks

Si5374 4-PLL Jitter Attenuating Clock Block Diagram

The Si5374/75 any-frequency jitter attenuating clocks integrate four independent jitter attenuating PLLs into a single device, providing industry-leading integration for space-constrained OTN (OTU1, OTU2, OTU3, OTU4) applications. The Si537x can generate any output frequency (2 kHz to 808 MHz) from any input frequency (2 kHz to 710 MHz) with industry-leading jitter performance (0.4 ps rms phase jitter).

Silicon Labs’ innovative DSPLL® technology provides any-frequency synthesis and jitter attenuation in a highly integrated PLL solution:

Eliminates the need for external VCXO and loop filter components
Minimizes BOM cost and complexity
Simplifies layout and improving immunity to board-level noise

Product Matrix Highlights

Device	In	Out	Applications
Si5374	8	8	SONET/SDH, ITU G.709 FEC, OTN, GbE, 10/100G, Wireless Base stations, DSLAM, Cable Infrastructure
Si5375	4	4	SONET/SDH, ITU G.709 FEC, OTN, GbE, 10/100G, Wireless Base stations, DSLAM, Cable Infrastructure

See all product matrix details

Features

Ultra low jitter generation: 0.4 ps rms phase jitter (12 kHz to 20 MHz)
Any-frequency synthesis
Digitally programmable loop bandwidth provides application-specific noise filtering (4 Hz to 8 kHz)
Meets G.8251 and OC-192 GR-253-CORE jitter specifications
Hitless switching w/integrated phase buildout
Manual or automatic (revertive, non-revertive) input clock selection
Synchronous and/or free-run operation
8 clock inputs
8 differential clock outputs
Accepts gapped clock inputs
Loss of lock, loss of signal alarms
User-selectable output clock signal format: LVPECL, LVDS, CML, CMOS
I²C programmable
On-chip voltage regulator with high PSRR
Pb-free, RoHS-compliant
Single supply operating at 1.8 or 2.5 V
Small size (10 mm x 10 mm 80-pin BGA)

Applications

Technologies

Learn more: patented DSPLL technology

Documentation Expand All Collapse All

Get notified when these documents are updated.

Data Sheet (2)

Document Name	Description	Version	Last Updated
Si5374.pdf	Si5374 Data Sheet	0.45	2/17/2012
Si5375.pdf	Si5375 Data Sheet	0.45	2/17/2012

User Guides (2)

Document Name	Description	Version	Last Updated
Si537x-EVB.pdf	Si537x-EVB User's Guide	0.5	3/6/2012
Si53xxReferenceManual.pdf	Si53xxReferenceManual	0.52	4/12/2012

Application Notes (4)

Document Name	Description	Version	Last Updated
AN513.pdf	AN513: Jitter Attenuation--Choosing the Right Phase-Locked Loop Bandwidth	0.1	6/10/2010
an56.pdf	AN56: Calculating Total Output Jitter for PLLs	0.3	5/4/2012
AN561.pdf	AN561: Introduction to Gapped Clocks and PLLs	0.1	11/29/2010
AN581.pdf	AN581: Meeting SerDes Jitter Requirements Simplified with Silicon Labs Clocks and Oscillators	0.1	9/2/2011

White Papers (3)

Document Name	Description	Version	Last Updated
Clock-Division_WP.pdf	Clock Division with Jitter and Phase Noise Measurements	1.0	7/12/2011
40-100G-Networking-WP.pdf	High-Performance Clock Integration Key to 40/100G Networks	1.0	10/6/2011
Timing-ICs-Keep-Beat-with-Needs-of-Todays-Embedded-Market.pdf	Timing ICs Keep Beat with Needs of Today’s Embedded Market	1.0	11/21/2011

Miscellaneous (5)

Document Name	Description	Version	Last Updated
Silicon-Labs-Timing-Cross-Reference.pdf	Silicon Labs Timing Cross-Reference to Xilinx, Altera and Lattice FPGA Devices	3.0	5/3/2012
timing-solutions-for-cavium-processors.pdf	Silicon Labs' Timing Solutions for Cavium Processors	1.2	7/15/2011
timing-solutions-for-freescale-processors.pdf	Silicon Labs' Timing Solutions for Freescale Processors	1.0	2/10/2012
Timing-Solutions-for-Altera.pdf	Timing Solutions for Altera	0.3	12/7/2011
timing-solutions-for-plx-technology.pdf	Timing Solutions for PLX Technology	1.0	11/8/2011

Design Resources

Design Tools Expand All Collapse All

Get notified when these files are updated.

Software (2)

Document Name	Description	Version	Updated
release_notes_si537xdspllsim.txt	Release Notes for the Si537x EVB Software		4/9/2012
Si537xEVBSoftwareInstall.zip	Si537x DSPLLsim EVB Software 2.3	2.3	4/9/2012

Models (1)

Document Name	Description	Version	Updated
si5375-c-cg.ibs	Si5375 IBIS Model	3.3	7/22/2011

Product Matrix

Part Number		Available Documents	Control	Package	Reference Inputs	Clock Outputs	Input Frequency	Output Frequency	Phase Jitter (RMS)	Output Format(s)	VDD	VDDO
Si5374		Data Sheet	I2C	80-pin BGA	8	8	0.002 - 710 MHz	0.002 - 808 MHz	350 fs rms typ	CMOS, LVDS, LVPECL, CML	1.8 V, 2.5 V	—
Si5375		Data Sheet	I2C	80-pin BGA	4	4	0.002 - 710 MHz	0.002 - 808 MHz	350 fs rms typ	CMOS, LVDS, LVPECL, CML	1.8 V, 2.5 V	—

Find products fast using the parametric search.

Education Center

Reference Manual

Any Frequency Precision Clocks Family Reference Manual

Training & Resources

Featured Videos

See How to Build a Custom Clock

Minimizing Noise and Interference with PSRR

Featured Utilities

Clock Tree Design Service

Silicon Labs clock tree design and consulting services help hardware designers simplify design and layout. Fill out the web form or upload files, and Silicon Labs will return a custom clock tree proposal within 3 business days based on your design.

ClockBuilder™ Wizard

The simple, easy-to-use ClockBuilder™ utility can be used to quickly develop custom, application-specific clock generators that support any combination of user-specified input/output frequencies.

Build Custom XO/VCXO

Specify a custom silicon or crystal oscillator and build a part number in minutes. Need to reorder? Look up a currently existing product by part number.

Parametric Search

Use this utility to search the selection of available clock generators and buffers, low jitter and jitter attenuating clock multipliers, synchronous ethernet, SONET/SDH clocks, crystal oscillators, and voltage-controlled crystal oscillators. Samples ship in less than two weeks!

Cross-Reference Search

Enter the part number from another company into the utility to find a list of Silicon Labs' products that can replace those parts. Once you find the products you need, you can click on the part number to see more details about the Silicon Labs' device, download the data sheet and export the results to Excel.

Featured White Papers

Selecting the Optimum PCIe Clock Source

To ensure proper compliance with the PCIe standard, systems require careful attention to the timing subsystem and architecture. This article explores some of the standard clocking architectures for PCIe and considers their benefits for typical system applications, including: clock architecture selection (Common Refclk, Separate Refclk or Data Clocked Refclk), requirements in applications that use FPGAs, jitter performance of the reference clock, use of spread spectrum clocking, and more.

SyncE and IEEE 1588: Sync Distribution for a Unified Network

Since Ethernet or packet based networks operate asynchronously, many of the traditional applications that depend on synchronization are not supported. Designers increasingly need to combine services supplied by data efficient packet networks with the ones served by the large installed base of traditional SONET/SDH networks. Both Synchronous Ethernet (SyncE) and packet timing using the IEEE 1588 protocol offer viable solutions in unifying service delivery over both networks. Download this new app note from Silicon Labs to discover methods for transporting synchronization and potential synchronized timing implementations.

Prototyping with Frequency-Flexible Crystal Oscillators

Developers of new systems ideally should make decisions regarding clocking requirements early in the design process. Although clocking rates are critical parameters that should be known in advance, determining these rates sometimes requires experimentation and re-evaluation. The use of frequency-flexible, programmable crystal oscillators (XOs) as prototyping tools can facilitate the process of validating system performance and help streamline the overall product development cycle.

Clocks and Oscillators

Title Content
4-PLL Jitter Attenuating Clocks

Product Matrix Highlights

Features

Applications

Technologies