1-PLL Jitter Attenuating Clocks

Si5324 Jitter Attenuating Clock Multiplier

The Si531x/2x/6x any-frequency jitter attenuating clocks generate any output frequency (2 kHz to 1.4 GHz) from any input frequency (2 kHz to 710 MHz) with industry-leading jitter performance (0.3 ps rms phase jitter).

Silicon Labs’ innovative DSPLL® technology provides any-frequency synthesis and jitter attenuation in a highly integrated PLL solution:

Eliminates the need for external VCXO and loop filter components
Minimizes BOM cost and complexity
Simplifies layout and improving immunity to board-level noise

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Features

Ultra low jitter generation: 0.3 ps rms phase jitter (12 kHz to 20 MHz)
Any-frequency synthesis
Digitally programmable loop bandwidth provides application-specific noise filtering (4 Hz to 8 kHz)
Meets G.8251 and OC-192 GR-253-CORE jitter specifications
Hitless switching w/integrated phase buildout
Manual or automatic (revertive, non-revertive) input clock selection
Synchronous or free-run operation
1, 2 or 4 clock inputs
1, 2 or 5 differential clock outputs
Accepts gapped clock inputs
Loss of lock (LOL), loss of signal (LOS), frequency offset (FOS) alarm outputs
User-selectable output clock signal format: LVPECL, LVDS, CML, CMOS
I²C/SPI programmable or pin-controlled
On-chip voltage regulator with high PSRR
Pb-free, RoHS compliant
Single supply operating at 1.8, 2.5 or 3.3 V
Small size (6 mm x 6 mm 36-pin QFN)

Applications

OC-3/12/48/192 line cards
OTN (OTU1, OTU2, OTU3, OTU4) line cards
Synchronous Ethernet
Wireless infrastructure
Wireless backhaul
Wireless repeater
Broadcast video
Cable/RF infrastructure
Data converter clocking
Optical modules
Test and measurement

Technologies

Learn more: patented DSPLL technology

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Data Sheet (10)

Document Name	Description	Version	Last Updated
Si5316.pdf	Si5316 Data Sheet	0.4
Si5317.pdf	Si5317 Data Sheet	1.1	4/18/2011
Si5319.pdf	Si5319 Data Sheet	1.0	12/8/2010
Si5323.pdf	Si5323 Data Sheet	1.0	1/18/2011
Si5324.pdf	Si5324 Data Sheet	0.25	11/3/2010
Si5326.pdf	Si5326 Data Sheet	1.0	9/30/2010
Si5327.pdf	Si5327 Data Sheet	0.4	5/2/2011
Si5366.pdf	Si5366 Data Sheet	0.3
Si5368.pdf	Si5368 Data Sheet	0.41	6/18/2009
Si5369.pdf	Si5369 Data Sheet	0.4	5/2/2011

User Guides (6)

Document Name	Description	Version	Last Updated
Si5316_19_22_23_24_25_26_27EVB.pdf	Si5316/19/22/23/24/25/26/27-EVB User's Guide	0.6	1/12/2012
Si5317-EVB.pdf	Si5317-EVB User's Guide	0.1	6/7/2010
Si5326-VTSS-EVB.pdf	Si5326-VTSS-EVB User Guide	0.2	12/19/2011
Si5365_66_67_68_69-EVB.pdf	Si5365/66/67/68/69-EVB User's Guide	0.6	1/12/2012
Si53xxReferenceManual.pdf	Si53xxReferenceManual	0.51	12/14/2011
Si5xx-ML52x-EVB.pdf	Si5xx-ML52x-EVB User Guide	0.2	9/23/2009

Application Notes (8)

Document Name	Description	Version	Last Updated
AN377.pdf	AN377: Timing and Synchronization in Broadcast Video	0.1	9/9/2009
AN420.pdf	AN420: SyncE and IEEE 1588: Sync Distribution For A Unified Network	0.2	10/28/2011
AN428.pdf	AN428: Jump Start: In-System, Flash-Based Programming for Silicon Labs’ Timing Products	0.6	10/5/2010
AN491.pdf	AN491: Power Supply Rejection for Low Jitter Clocks	0.1	4/2/2010
AN513.pdf	AN513: Jitter Attenuation--Choosing the Right Phase-Locked Loop Bandwidth	0.1	6/10/2010
AN561.pdf	AN561: Introduction to Gapped Clocks and PLLs	0.1	11/29/2010
AN581.pdf	AN581: Meeting SerDes Jitter Requirements Simplified with Silicon Labs Clocks and Oscillators	0.1	9/2/2011
AN591.pdf	AN591: Crystal Selection for the Si5315, Si5317, and Other Si53xx Any-Frequency Jitter Attenuating Clocks	0.3	10/31/2011

White Papers (3)

Document Name	Description	Version	Last Updated
Clock-Division_WP.pdf	Clock Division with Jitter and Phase Noise Measurements	1.0	7/12/2011
DSP_Driven_Clocks.PDF	DSP-driven High-performance Clock Sources Radically Alter System Timing Architectures White Paper
Timing-ICs-Keep-Beat-with-Needs-of-Todays-Embedded-Market.pdf	Timing ICs Keep Beat with Needs of Today’s Embedded Market	1.0	11/21/2011

Miscellaneous (5)

Document Name	Description	Version	Last Updated
Silicon-Labs-Timing-Cross-Reference.pdf	Silicon Labs Timing Cross-Reference to Xilinx, Altera and Lattice FPGA Devices	2.1	2/8/2012
timing-solutions-for-cavium-processors.pdf	Silicon Labs' Timing Solutions for Cavium Processors	1.2	7/15/2011
timing-solutions-for-freescale-processors.pdf	Silicon Labs' Timing Solutions for Freescale Processors	1.0	12/20/2011
Timing-Solutions-for-Altera.pdf	Timing Solutions for Altera	0.3	12/7/2011
timing-solutions-for-plx-technology.pdf	Timing Solutions for PLX Technology	1.0	11/8/2011

PCN (2)

Document Name	Description	Version	Last Updated
1104181_QS0503F2_Si5317_Datasheet.pdf	QS0503F2 Si5317 Datasheet
1007191.pdf	Si531X. Si532X Test Site Relocation-ASESG Std

Design Resources

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Software (3)

Document Name	Description	Version	Updated
AN428SW.zip	AN428 Jumpstart Software Ver 1.3	1.3	8/23/2010
release_notes_dspllsim.txt	Release Notes for the Precision Clock (DSPLLsim) EVB Software		12/14/2011
PrecisionClock_EVBSoftware.zip	Si531x/2x/6x DSPLLsim Software Version 4.6	4.6	12/14/2011

Models (18)

Document Name	Description	Version	Updated
si5316-c-gm.ibs	Si5316 IBIS Model	3.2	3/13/2011
si5317a-c-gm.ibs	Si5317a IBIS Model	3.2	3/13/2011
si5317b-c-gm.ibs	Si5317b IBIS Model	3.2	3/13/2011
si5317c-c-gm.ibs	Si5317c IBIS Model	3.2	3/13/2011
si5317d-c-gm.ibs	Si5317d IBIS Model	3.2	3/13/2011
si5319a-c-gm.ibs	Si5319a IBIS Model	3.2	3/13/2011
si5319b-c-gm.ibs	Si5319b IBIS Model	3.2	3/13/2011
si5319c-c-gm.ibs	Si5319c IBIS Model	3.2	3/13/2011
Si531x_2x_Any-rate_Clocks3v3IBIS.zip	Si531x/2x Any-Rate Precision Clock IBIS Model 3.3 V	2.0
si5323-c-gm.ibs	Si5323 IBIS Model	3.2	3/13/2011
si5323a-c-gm.ibs	Si5323a IBIS Model	3.2	3/13/2011
si5323b-c-gm.ibs	Si5323b IBIS Model	3.2	3/13/2011
si5323c-c-gm.ibs	Si5323c IBIS Model	3.2	3/13/2011
si5326a.ibs	Si5326a IBIS Model	3.2	3/13/2011
si5366-c-gq.ibs	Si5366 IBIS Model	3.2	3/13/2011
si5368a-c-gq.ibs	Si5368a IBIS Model	3.2	3/13/2011
si5368b-c-gq.ibs	Si5368B IBIS Model	3.2	3/13/2011
si5368c-c-gq.ibs	Si5368C IBIS Model	3.2	3/13/2011

Training (1)

Document Name	Description	Version	Updated
DSP_Driven_Clocks.PDF	DSP-driven High-performance Clock Sources Radically Alter System Timing Architectures White Paper

Product Matrix

Part Number	Available Documents	Control	Package	Reference Inputs	Clock Outputs	Input Frequency	Output Frequency	Phase Jitter (RMS)	Output Format(s)	VDD	VDDO
Si5316	Data Sheet	Pin	6x6mm 36-QFN	2	1	19-710	19-710	0.3 ps	LVPECL, LVDS, CML, LVCMOS	1.8, 2.5, 3.3V	1.8, 2.5, 3.3V
Si5317	Data Sheet	Pin	6x6 mm, 36-QFN	1	2	1-710	1-710	0.3 ps	LVPECL, LVDS, CML, LVCMOS	1.8, 2.5, 3.3V	1.8, 2.5, 3.3V
Si5317A	Data Sheet	Pin	6x6 mm, 36-QFN	1	2	1-711	1-711	0.3 ps	LVPECL, LVDS, CML, LVCMOS	1.8, 2.5, 3.3V	1.8, 2.5, 3.3V
Si5317B	Data Sheet	Pin	6x6 mm, 36-QFN	1	2	1-350	1-350	0.3 ps	LVPECL, LVDS, CML, LVCMOS	1.8, 2.5, 3.3 V	1.8, 2.5, 3.3 V
Si5317C	Data Sheet	Pin	6x6 mm, 36-QFN	1	2	1-200	1-200	0.3 ps	LVPECL, LVDS, CML, LVCMOS	1.8, 2.5, 3.3 V	1.8, 2.5, 3.3 V
Si5317D	Data Sheet	Pin	6x6 mm, 36-QFN	1	2	1-100	1-100	0.3 ps	LVPECL, LVDS, CML, LVCMOS	1.8, 2.5, 3.3 V	1.8, 2.5, 3.3 V
Si5319	Data Sheet	I2C/SPI	6x6mm 36-QFN	1	1	0.00-710	0.002-1417	0.3 ps	LVPECL, LVDS, CML, LVCMOS	1.8, 2.5, 3.3V	1.8, 2.5, 3.3V
Si5323	Data Sheet	Pin	6x6mm 36-QFN	2	2	0.008-707	0.008-1050	0.3 ps	LVPECL, LVDS, CML, LVCMOS	1.8, 2.5, 3.3V	1.8, 2.5, 3.3V
Si5324	Data Sheet	I2C/SPI	6x6mm 36-QFN	2	2	0.002-710	0.002-1417	0.3ps	LVPECL, LVDS, CML, LVCMOS	1.8, 2.5, 3.3V	1.8, 2.5, 3.3V
Si5326	Data Sheet	I2C/SPI	6x6mm 36-QFN	2	2	0.002-710	0.002-1417	0.3 ps	LVPECL, LVDS, CML, LVCMOS	1.8, 2.5, 3.3V	1.8, 2.5, 3.3V
Si5326A	Data Sheet	I2C/SPI	6x6mm 36-QFN	2	2	2 kHz-945 MHz, 970-1134 MHz, 1.213-1.4 GHz	2 kHz-945 MHz, 970-1134 MHz, 1.213-1.4 GHz	0.3 ps	LVPECL, LVDS, CML, LVCMOS	1.8, 2.5, 3.3 V	1.8, 2.5, 3.3 V
Si5326B	Data Sheet	I2C/SPI	6x6mm 36-QFN	2	2	2 kHz-808 MHz	2 kHz-808 MHz	0.3 ps	LVPECL, LVDS, CML, LVCMOS	1.8, 2.5, 3.3 V	1.8, 2.5, 3.3 V
Si5326C	Data Sheet	I2C/SPI	6x6mm 36-QFN	2	2	2 kHz-346 MHz	2 kHz-346 MHz	0.3 ps	LVPECL, LVDS, CML, LVCMOS	1.8, 2.5, 3.3 V	1.8, 2.5, 3.3 V
Si5327	Data Sheet	I2C/SPI	6x6mm 36-QFN	2	2	0.002 to 710	0.002 to 808	500 fs	CMOS, LVDS, LVPECL, CML
Si5366	Data Sheet	Pin	14x14mm 100-TQFP	4	5	0.008-707	0.008-1050	0.3 ps	LVPECL, LVDS, CML, LVCMOS	1.8, 2.5, 3.3V	n/a
Si5368	Data Sheet	I2C/SPI	14x14mm 100-TQFP	4	5	0.002-710	0.002-1417	0.3 ps	LVPECL, LVDS, CML, LVCMOS	1.8, 2.5, 3.3V	n/a
Si5368A	Data Sheet	I2C/SPI	14x14mm 100-TQFP	4	5	9 kHz-945 MHz, 970-1134 MHz, 1.213-1.417 GHz	9 kHz-945 MHz, 970-1134 MHz, 1.213-1.417 GHz	0.3 ps	LVPECL, LVDS, CML, LVCMOS	1.8, 2.5, 3.3 V	–
Si5368B	Data Sheet	I2C/SPI	14x14mm 100-TQFP	4	5	2 kHz-808 MHz	2 kHz-808 MHz	0.3 ps	LVPECL, LVDS, CML, LVCMOS	1.8, 2.5, 3.3 V	–
Si5368C	Data Sheet	I2C/SPI	14x14mm 100-TQFP	4	5	2 kHz-346 MHz	2 kHz-346 MHz	0.3 ps	LVPECL, LVDS, CML, LVCMOS	1.8, 2.5, 3.3 V	–
Si5369	Data Sheet	I2C/SPI	14x14mm 100-TQFP	4	5	0.002 to 710	0.002 to 1417	300 fs	CMOS, LVDS, LVPECL, CML

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Microprocessor-controlled devices provide virtually any frequency translation combination across this operating range. For ease of use, pin-controlled devices are preconfigured to support popular SONET/SDH, Ethernet, Fibre Channel, and HDTV frequencies. The any-rate precision clocks are based on Silicon Labs' 3rd-generation DSPLL® technology, which provides any-rate frequency synthesis and 300 fs rms jitter performance in a highly-integrated PLL solution that eliminates the need for external VCXO and loop filter components.

The DSPLL loop bandwidth is digitally-programmable from 4 Hz to 8.4 kHz, providing jitter performance optimization at the application level. Devices are offered in two package options: a 6 x 6 mm 36-pin QFN for devices with one or two clock outputs and a 14 x 14 mm 100-pin TQFP for products with five clock outputs. Given their frequency flexibility and outstanding jitter performance, Silicon Labs programmable any-rate precision clock ICs are ideal for providing clock multiplication, jitter attenuation and clock distribution in high-performance timing applications.

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1-PLL Jitter Attenuating Clocks

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