Product Matrix

Jitter Attenuating Clock Multipliers

Si5316/19/23/24/26/66/68
Silicon Labs' Si5316, Si5319, Si5323, Si5324, Si5326, Si5366 and Si5368 family of programmable any-rate precision clock ICs provide clock multiplication, jitter attenuation and clock distribution in high-performance timing applications requiring sub 1 ps jitter performance.

Block Diagram

 

Features

Ultra-low jitter clock outputs with jitter generation as low as 290 fs rms (12 kHz to 20 MHz)
Digitally programmable loop bandwidth  (4 Hz to 8.4 kHz)
Meets G.8251 and OC-192 GR-253-CORE jitter generation specifications
Hitless switching between input clocks with phase build-out
Manual or automatic (revertive, non-revertive) input clock selection
Loss of lock (LOL), loss of signal (LOS), frequency offset (FOS) alarm outputs
Free-run and digital hold mode
Configurable format per output (LVPECL, LVDS, CML, CMOS)
I²C/SPI programmable or pin-controlled
On-chip voltage regulator with high PSNR
Pb-free, RoHS compliant
Single Supply: 1.8, 2.5 or 3.3 V ±10% operation

Applications

Broadcast video - 3D/HD/SD-SDI Genlock
10/40/100G optical line cards
Any-rate, any-port, any-protocol line cards
OTN/SONET/SDH line cards
ITU G.709 and custom FEC rates
GbE/10G SyncE (LAN/WAN)
1/2/4/8/10G fiber channel
Wireless base stations
Cable infrastructure, CMTS
Optical modules
Test and measurement
Data converter clocking

Technologies

Learn more: patented DSPLL technology

Resources

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Product Matrix

Part NumberAvailable DocumentsControlInput TypeClock InputsClock OutputsInput Frequency (MHz)Output Frequency (MHz)RMS Phase JitterPLL BandwidthClock Output FormatPackage 
Si5316Data SheetPinClock2119 to 71019 to 7100.3 ps60 Hz to 8.4 kHzLVPECL, LVDS, CML, CMOS6x6mm 36-QFN
Si5319Data SheetI2C/SPICrystal, Clock110.002 to 7100.002 to 14170.3 ps60 Hz to 8.4 kHzLVPECL, LVDS, CML, CMOS6x6mm 36-QFN
Si5323Data SheetPinClock220.008 to 7070.008 to 10500.3 ps60 Hz to 8.4 kHzLVPECL, LVDS, CML, CMOS6x6mm 36-QFN
Si5324Data SheetI2C/SPICrystal, Clock220.002 to 7100.002 to 14170.3 ps4 Hz to 525 HzLVPECL, LVDS, CML, CMOS6x6mm 36-QFN
Si5326Data SheetI2C/SPICrystal, Clock220.002 to 7100.002 to 14170.3 ps60 Hz to 8.4 kHzLVPECL, LVDS, CML, CMOS6x6mm 36-QFN
Si5366Data SheetPinClock450.008 to 7070.008 to 10500.3 ps60 Hz to 8.4 kHzLVPECL, LVDS, CML, CMOS14x14mm 100-TQFP
Si5368Data SheetI2C/SPICrystal, Clock450.002 to 7100.002 to 14170.3 ps60 Hz to 8.4 kHzLVPECL, LVDS, CML, CMOS14x14mm 100-TQFP

 

Silicon Laboratories' programmable any frequency precision clock ICs provide clock multiplication, jitter attenuation and clock distribution in high-performance timing applications requiring sub 1 ps jitter performance.

The devices accept multiple clock inputs ranging from 2 kHz to 710 MHz and generate multiple independent, synchronous clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz.

Microprocessor-controlled devices provide virtually any frequency translation combination across this operating range. For ease of use, pin-controlled devices are preconfigured to support popular SONET/SDH, Ethernet, Fibre Channel, and HDTV frequencies. The any-rate precision clocks are based on Silicon Labs' 3rd-generation DSPLL® technology, which provides any-rate frequency synthesis and 300 fs rms jitter performance in a highly-integrated PLL solution that eliminates the need for external VCXO and loop filter components.

The DSPLL loop bandwidth is digitally-programmable from 4 Hz to 8.4 kHz, providing jitter performance optimization at the application level. Devices are offered in two package options: a 6 x 6 mm 36-pin QFN for devices with one or two clock outputs and a 14 x 14 mm 100-pin TQFP for products with five clock outputs. Given their frequency flexibility and outstanding jitter performance, Silicon Labs programmable any-rate precision clock ICs are ideal for providing clock multiplication, jitter attenuation and clock distribution in high-performance timing applications.