System-Level Overview
The Si5315 IC provides clock translation, jitter attenuation, and clock distribution for high-performance Synchronous Ethernet line card timing applications. The device accepts two clock inputs ranging from 8 kHz to 644.53 MHz and generates two equal frequency, low-jitter clock outputs ranging from 8 kHz to 644.53 MHz. For ease of use, the Si5315 is pin-controlled to enable simple device configuration of frequency plans, PLL loop bandwidth and input clock selection. The DSPLL locks to one of two input reference clocks and provides over 200 frequency translations to synchronize output clocks for Ethernet, SONET/SDH, and PDH line cards. The Si5315 implements internal state machines to control hitless switching between input clocks and holdover. Status alarms, loss of signal (LOS) and loss of lock (LOL) are provided on output pins to indicate a change in device status. This device is designed for systems with line cards that are synchronized to a redundant, centralized telecom or Ethernet backplane. The Si5315 translates a low-frequency clock from the telecom backplane to an Ethernet or SONET/SDH clock frequency to the PHY and filters the jitter to ensure compliance with related ITU-T and Telcordia standards.