SONET/SDH Precision Clocks

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Si5321 Precision Clock IC

​Silicon Labs’ SONET/SDH clock multiplier and jitter attenuator family provides the industry’s best performance in the smallest footprint. Offering jitter generation of less than 0.3 ps RMS (OC-192/STM-64), these devices outperform discrete implementations and hybrid clock solutions while integrating features such as selectable forward error correction (FEC), frequency scaling, pin-selectable loop filter bandwidths and MTIE-compliant hitless switching. Based on Silicon Labs’ DSPLL® technology, these clock ICs provide a fully-integrated PLL eliminating the need for sensitive external loop filter components and costly VCXOs. More...

SyncE & IEEE 1588: Sync Distribution for a Unified Network Application Note

Features

  • Ultra-low jitter clock output with jitter generation as low as 0.3 ps RMS
  • Clock output range from 19 to 2,775 MHz
  • Up to three switchable clock inputs
  • Loss-of-lock indication
  • Digital hold for loss-of-input clock
  • Small footprints
  • Available loop bandwidth settings - 800, 1600, 3200, 6400 and 12800 Hz
  • FEC scaling
  • Hitless switching
  • Low power consumption
 

Applications

  • SONET/SDH line/port cards
  • Core switches
  • Digital cross connects
  • Terabit routers
  • Metro and long haul SONET/SDH port cards
  • Optical modules
  • Gigabit Ethernet (GbE)
  • 10 GbE access
  • Backplane SERDES, ASIC clock drivers
  • Hybrid VXCO

Technologies

  • Learn more: patented DSPLL technology
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Documentation    Expand All   Collapse All

 
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Data Sheet (4)

Document NameDescriptionVersionLast Updated
si5310.pdf
Si5310 Data Sheet1.36/5/2008
si5320.pdf
Si5320 Data Sheet2.58/28/2008
si5321.pdf
Si5321 Data Sheet2.58/28/2008
si5364.pdf
Si5364 Data Sheet2.58/28/2008

User Guides (4)

Document NameDescriptionVersionLast Updated
si5310evb.pdf
Si5310-EVB User Guide0.71
si5320evb.pdf
Si5320-EVB User Guide0.4
si5321evb.pdf
Si5321-EVB User Guide0.4
Si5364evb.pdf
Si5364-EVB User Guide0.33

Application Notes (4)

Document NameDescriptionVersionLast Updated
AN256.pdf
AN256: Integrated Phase Noise0.412/9/2011
AN428.pdf
AN428: Jump Start: In-System, Flash-Based Programming for Silicon Labs’ Timing Products0.610/5/2010
AN581.pdf
AN581: Meeting SerDes Jitter Requirements Simplified with Silicon Labs Clocks and Oscillators0.19/2/2011
an59.pdf
AN59: Optimizing Design and Layout for the Si5318/20/21/64 Clock ICs1.0

White Papers (2)

Document NameDescriptionVersionLast Updated
DSP_Driven_Clocks.PDF
DSP-driven High-performance Clock Sources Radically Alter System Timing Architectures White Paper
Timing-ICs-Keep-Beat-with-Needs-of-Todays-Embedded-Market.pdf
Timing ICs Keep Beat with Needs of Today’s Embedded Market1.011/21/2011

Miscellaneous (5)

Document NameDescriptionVersionLast Updated
Silicon-Labs-Timing-Cross-Reference.pdf
Silicon Labs Timing Cross-Reference to Xilinx, Altera and Lattice FPGA Devices2.012/16/2011
timing-solutions-for-cavium-processors.pdf
Silicon Labs' Timing Solutions for Cavium Processors1.27/15/2011
timing-solutions-for-freescale-processors.pdf
Silicon Labs' Timing Solutions for Freescale Processors1.012/20/2011
Timing-Solutions-for-Altera.pdf
Timing Solutions for Altera0.312/7/2011
timing-solutions-for-plx-technology.pdf
Timing Solutions for PLX Technology1.011/8/2011
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Design Tools    Expand All   Collapse All

 
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Software (2)

Document NameDescriptionVersionUpdated
AN428SW.zip
AN428 Jumpstart Software Ver 1.31.38/23/2010
JitterCalculator1.0Installation.zip
Si5320/21/64 Jitter Simulation Software

Models (3)

Document NameDescriptionVersionUpdated
si5320g.ibs
Si5320 IBIS 3V3 Diff1.0
si5321g.ibs
Si5321 IBIS 3V3 Diff1.0
si5364g.ibs
Si5364 IBIS 3V3 Diff1.0

Training (1)

Document NameDescriptionVersionUpdated
DSP_Driven_Clocks.PDF
DSP-driven High-performance Clock Sources Radically Alter System Timing Architectures White Paper
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Product Matrix


Part Number Available DocumentsControlPackageReference InputsClock OutputsInput FrequencyOutput FrequencyPhase Jitter (RMS)Output Format(s)VDDVDDO
Si5310Data Sheet
Pin4x4 mm 20-QFN129.4 - 668150 - 167, 600 - 6680.9 psCML 2.5Vn/a
Si5320Data Sheet
Pin9x9mm 63-PBGA1119, 38, 77, 155, 311, 62219, 155, 6220.3 psCML 3.3Vn/a
Si5321Data Sheet
Pin9x9mm 63-PBGA1119, 38, 77, 155, 311, 62219, 38, 77, 155, 311, 622, 1244, 24880.3 psCML 3.3Vn/a
Si5364Data Sheet
Pin11x11mm 99-PBGA3419.4419, 155, 6220.3 psCML 3.3Vn/a

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Silicon Labs’ SONET/SDH clock multiplier and jitter attenuator timing IC family includes the Si5310 clock multiplier and the Si5320, Si5321 and Si5364 precision clock ICs.

Si5310 Clock Multiplier

The Si5310 is a fully-integrated low-power clock multiplier and clock regenerator IC designed to provide low-jitter clock synthesis/regeneration in high-speed communication systems.

The Si5310 synthesizes an output clock in either the 150–167 MHz or the 600–668 MHz frequency range from an input clock that is an integer submultiple between 10 and 311 MHz. Additionally, the Si5310 also regenerates a "clean" version of the input clock by using the clock synthesis phase-locked loop (PLL) to remove unwanted jitter and square up the input clock's rising and falling edges.

The Si5310 uses Silicon Labs’ patented DSPLL and features high performance, small size, low-power consumption and ease of use. It operates from a single 2.5 V supply and is packaged in a small 4 x 4 mm, 20-pin micro leaded package (MLP).

Si5320 Precision Clock IC

The Si5320 SONET/SDH precision clock multiplier and jitter attenuator IC provides jitter performance that significantly exceeds the jitter requirements of high-speed data communications systems, including OC-192/STM-64, OC-48/STM-16 and 10 Gigabit Ethernet.

The Si5320 generates a user-selectable output clock centered at 19, 155 or 622 MHz from an input clock centered at one of six frequencies between 19 and 622 MHz. Ideal for long-haul applications, the Si5320 supports frequency translation between standard SONET/SDH reference clock frequencies and 15/14 FEC frequencies.

The Si5320 uses Silicon Labs’ DSPLL technology and establishes a new standard for jitter performance, integration level and power usage in clock generation devices. It is available in a small 9 x 9 mm ball grid array (BGA) package, operates over a –20 to +85 °C temperature range and is powered from a single 3.3 V supply.

Si5321 Precision Clock IC

The Si5321 SONET/SDH precision clock multiplier and jitter attenuator IC features industry-leading jitter performance that significantly exceeds the jitter requirements of high-speed data communications systems, including OC-192/STM-64, OC-48/STM-16 and 10 Gigabit Ethernet.

The Si5321 generates a user-selectable output clock centered at 19, 39, 78, 155, 622, 1244 or 2488 MHz from an input clock centered at one of six frequencies between 19 and 622 MHz. The Si5321 supports frequency translation between standard SONET/SDH reference clock frequencies and FEC frequencies, including G.709 and 10 GbE FEC rates.

Using Silicon Labs’ DSPLL technology, the Si5321 extends Silicon Labs’ expertise for industry-leading jitter performance, integration level and power usage in clock generation devices and is available in a small 9 x 9 mm BGA package. It operates over a –20 to 85 °C temperature range and is powered from a single 3.3 V supply.

Si5364 Precision Clock IC

The Si5364 is a complete solution for ultra-low jitter, high-speed clock generation and distribution in precision clocking applications, such as OC-192/OC-48 SONET/SDH line/port cards.

This device phase locks to one of three reference inputs in the range of 19.44 MHz and generates four synchronous clock outputs that can be independently configured for operation in the 19, 155 or 622 MHz range (1x, 8x and 32x input clock). The device reference monitoring and clock switching functions support MTIE compliant clock switching with excellent output phase transient characteristics. FEC rates are supported with selectable 15/14 or 14/15 scaling of the clock multiplication ratios.

Using Silicon Labs’ DSPLL technology, the Si5364 establishes a new standard in performance and integration for ultra-low jitter clock generation and is available in a small 11 x 11 mm BGA package. It operates over a –20 to +85 °C temperature range and is powered from a single 3.3 V supply. ​

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Custom XO/VCXO Utilities

 

Training & Resources

Featured Videos

ClockBuilder Overview
ClockBuilderTM Overview
Minimizing Noise and Interference with PSRR
Minimizing Noise and Interference with PSRR
Si5350 Clock Generator Demo
Si5350 Clock Generator Demo

 

Featured Utilities

Clock Tree Design Services

Silicon Labs clock tree design and consulting services help hardware designers simplify design and layout. Fill out the web form or upload files, and Silicon Labs will return a custom clock tree proposal within 3 business days based on your design. The recommended solution will use the most state-of-the-art components available on the market to ensure your jitter, cost and space requirements are met.
» Clock Tree Design Services Web Utility

ClockBuilder™ Utility

The simple, easy-to-use ClockBuilder™ web-based utility can be used to quickly develop custom, application-specific clock generators that support any combination of user-specified input/output frequencies.
» ClockBuilder™ Utility

Build Custom XO/VCXO

Specify a custom silicon or crystal oscillator and build a part number in minutes. Need to reorder? Look up a currently existing product by part number.
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Parametric Search

Use this utility to search the selection of available clock generators and buffers, low jitter and jitter attenuating clock multipliers, synchronous ethernet, SONET/SDH clocks, crystal oscillators, and voltage-controlled crystal oscillators. Samples ship in less than two weeks!
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Cross-Reference Search

Enter the part number from another company into the utility to find a list of Silicon Labs' products that can replace those parts. Once you find the products you need, you can click on the part number to see more details about the Silicon Labs' device, download the data sheet and export the results to Excel.
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Featured White Papers

Selecting the Optimum PCIe Clock Source

To ensure proper compliance with the PCIe standard, systems require careful attention to the timing subsystem and architecture. This article explores some of the standard clocking architectures for PCIe and considers their benefits for typical system applications, including: clock architecture selection (Common Refclk, Separate Refclk or Data Clocked Refclk), requirements in applications that use FPGAs, jitter performance of the reference clock, use of spread spectrum clocking, and more.
» Selecting the Optimum PCIe Clock Source

SyncE and IEEE 1588: Sync Distribution for a Unified Network

Since Ethernet or packet based networks operate asynchronously, many of the traditional applications that depend on synchronization are not supported. Designers increasingly need to combine services supplied by data efficient packet networks with the ones served by the large installed base of traditional SONET/SDH networks. Both Synchronous Ethernet (SyncE) and packet timing using the IEEE 1588 protocol offer viable solutions in unifying service delivery over both networks. Download this new app note from Silicon Labs to discover methods for transporting synchronization and potential synchronized timing implementations.
» SyncE and IEEE 1588: Sync Distribution for a Unified Network

Enhancing Power Supply Rejection Ratio for Low-Jitter Clocks

Today's electronic systems require advanced timing design from top to bottom. Cost and performance optimization is important in all applications, and power delivery and noise coupling concerns are as critical as ever. This in-depth Silicon Labs white paper examines the primary sources of power supply noise, why some timing circuits are sensitive to power supply noise and how to minimize the impact of noise in jitter-sensitive applications.
» Enhancing Power Supply Rejection Ratio for Low-Jitter Clocks

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SONET/SDH Precision Clocks Web Part