Clock and Oscillator Training and Resources
Videos
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Web-Based Utilities
Silicon Labs clock tree design and consulting services help hardware designers simplify design and layout. Simply fill out the questionnaire or upload file(s) showing your existing clock tree and we will return a custom clock tree proposal within three business days. The recommended solution will use the most state-of-the-art components available on the market to ensure your jitter, cost and space requirements are met. In addition, Silicon Labs will provide layout reviews and schematic reviews of all designs created using this program.
The simple, easy-to-use ClockBuilder™ web-based utility can be used to quickly develop custom, application-specific clock generators that support any combination of user-specified input/output frequencies.
Specify a custom crystal oscillators, voltage-controlled crystal oscillator or silicon oscillator and build a part number in minutes.
Use this utility to search Silicon Labs selection of available clock generators and buffers, low jitter and jitter attenuating clock multipliers, synchronous Ethernet and SONET/SDH clocks. Samples ship in less than two weeks!
Search through a list of Silicon Labs available crystal oscillators and voltage-controlled crystal oscillators to find the perfect part for you next project. Samples ship in two weeks or less!
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White Papers
To ensure proper compliance with the PCIe standard, systems require careful attention to the timing subsystem and architecture. This article explores some of the standard clocking architectures for PCIe and considers their benefits for typical system applications, including: clock architecture selection (Common Refclk, Separate Refclk or Data Clocked Refclk), requirements in applications that use FPGAs, jitter performance of the reference clock, use of spread spectrum clocking, and more.
Every digital electronic system requires a repetitive periodic signal or frequency that sets the timing for all data transactions within the system and with interface devices. Silicon timing devices have gone through an evolution that impacts not only frequency generation but also board space occupation, power consumption, electromagnetic interference (EMI), and the flexibility of configuration to adapt to rapid changes in design cycles.
Since Ethernet or packet based networks operate asynchronously, many of the traditional applications that depend on synchronization are not supported. Designers increasingly need to combine services supplied by data efficient packet networks with the ones served by the large installed base of traditional SONET/SDH networks. Both Synchronous Ethernet (SyncE) and packet timing using the IEEE 1588 protocol offer viable solutions in unifying service delivery over both networks. Download this new app note from Silicon Labs to discover methods for transporting synchronization and potential synchronized timing implementations.
This in-depth Silicon Labs white paper focuses on how to simplify your timing design using glitch-free frequency shifting to address low power design challenges, as well as the complexity of generating a wide range of frequencies.
As clock speeds and communication channels run at ever higher frequencies, accurate jitter and phase noise measurements become more important, even as they become more difficult and expensive to manage. Here are some practical pointers and observations to assist in situations where clock signals have been divided down from higher frequency voltage-controlled oscillators (VCOs).
Developers of new systems ideally should make decisions regarding clocking requirements early in the design process. Although clocking rates are critical parameters that should be known in advance, determining these rates sometimes requires experimentation and re-evaluation. The use of frequency-flexible, programmable crystal oscillators (XOs) as prototyping tools can facilitate the process of validating system performance and help streamline the overall product development cycle.
Today's electronic systems require advanced timing design from top to bottom. Cost and performance optimization is important in all applications, and power delivery and noise coupling concerns are as critical as ever. This in-depth Silicon Labs white paper examines the primary sources of power supply noise, why some timing circuits are sensitive to power supply noise and how to minimize the impact of noise in jitter-sensitive applications.
Quartz crystal oscillators have long been the preferred choice for clock generation in consumer, computing, and communication applications, available in a wide range of frequencies, package sizes and stabilities. Yet for all their benefits, manufacturing complexity and reliability issues associated with quartz oscillators have driven the quest to develop alternative oscillator solutions that use micro electromechanical (MEMs) resonators or pure semiconductor solutions like the Si500.
A wide range of timing solutions are available, including crystal oscillators (XO), voltage-controlled crystal oscillators (VCXO), and clocks. No one size fits all strategy applies when it comes to component selection. This paper will help you pick the right device for your particular application.
Verwendungsbereich von Taktgebern und Oszillatoren
By their nature, FPGAs are power-hungry devices with complex power delivery requirements and multiple voltage rails. When FPGA power consumption increases, performance requirements on sensitive analog and mixed signal subsystems also increase, particularly on clocking subsystems that provide low jitter timing references for the FPGA and other board-level components. By using clock sources with integrated power supply noise rejection, designers can simplify power supply design and mitigate these design challenges.
Historical Perspective on Quartz Crystal Oscillators
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Presentations
Silicon Labs' Si570/71 any-rate XO/VCXO generates frequencies from 10 MHz to 1.4 GHz from a single device and are user-programmable via industry standard I2C interface.
Silicon Labs’ DSPLL-based, highly-integrated Si53xx ultra-low jitter clock multiplier ICs improve performance and simplify design.
The CMOS-based Si500 silicon oscillator enables the replacement of quartz and MEMS XOs with an IC solution.
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