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Silicon Laboratories' low jitter clock multipliers provide clock multiplication and clock distribution in high performance timing applications requiring sub 1 ps jitter performance without jitter attenuation. The devices accept multiple clock inputs ranging from 10 to 710 MHz and generate two independent, synchronous clock outputs ranging from 10 to 945 MHz and select frequencies to 1.4 GHz.
Microprocessor controlled devices provide a wide range of frequency translation combinations across this operating range. For ease of use, pin-controlled devices are preconfigured to support popular SONET/SDH, Ethernet, Fibre Channel and HDTV frequencies. The low jitter clock multipliers are based on Silicon Labs' 3rd-generation DSPLL® technology, which provides any-rate frequency synthesis and 0.6 ps rms jitter performance in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components.
The DSPLL loop bandwidth is digitally programmable from 30 kHz to 1.3 MHz. Devices are offered in two package options: a 6x6 mm 36-pin QFN for devices with two clock outputs and a 14x14 mm 100-pin TQFP for products with five clock outputs. Silicon Labs low jitter clock multipliers are ideal for providing clock multiplication and clock distribution in high performance timing applications.
Si5325 Block Diagram
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