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The Si5310 is a fully integrated low-power clock multiplier and clock regenerator IC designed to provide low jitter clock synthesis/regeneration in high-speed communication systems.
The Si5310 synthesizes an output clock in either the 150-167 MHz or the 600–668 MHz frequency range from an input clock that is an integer submultiple between 10 MHz and 311 MHz. Additionally, the Si5310 also regenerates a "clean" version of the input clock by using the clock synthesis phase-locked loop (PLL) to remove unwanted jitter and square up the input clock's rising and falling edges.
The Si5310 uses Silicon Laboratories’ patented DSPLL® to provide a level of performance that is typically achieved with discrete PLL implementations using costly crystal or SAW based components. The DSPLL approach uses digital signal processing algorithms to replace the analog loop filter and associated discrete passive components with digital circuitry. As a result, precise loop calibration is now possible to ensure optimal jitter performance over time, temperature and semiconductor process. Furthermore, integration of the entire PLL function into a single IC saves a significant amount of board space, makes the PLL much less sensitive to board level noise sources and eliminates performance degradations that result from the aging of discrete PLL components like crystal stabilized VCOs.
The Si5310 features high performance, small size, low power and ease of use. It operates from a single 2.5 V supply and is packaged in a small 4x4 mm, 20-pin Micro Leaded Package (MLP).
Si5310 Block Diagram
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