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The Si5320 SONET/SDH precision clock multiplier/jitter attenuator IC provides jitter performance that significantly exceeds the jitter requirements of high-speed data communications systems, including OC-192/STM-64, OC-48/STM-16 and 10 Gigabit Ethernet.
The Si5320 generates a user-selectable output clock centered at 19, 155 or 622 MHz from an input clock centered at one of six frequencies between 19 and 622 MHz. To support long-haul applications, frequency translation between standard SONET/SDH reference clock frequencies and 15/14 forward error correction (FEC) frequencies is also supported.
The Si5320 uses Silicon Laboratories’ DSPLL® technology to eliminate jitter, noise and the need for external loop filter components found in traditional PLL implementations. The DSPLL approach uses digital signal processing algorithms to replace the analog loop filter and associated discrete passive components with digital circuitry. This technology allows the Si5320 to provide selectable loop filter bandwidth settings of 800, 1600, 3200, 6400 and 12800 Hz, providing flexibility in jitter attenuation applications. Operation of the Si5320 is highly stable over process, temperature and voltage variations, producing jitter generation as low as 0.25 ps rms in OC-192 applications. The Si5320 also provides a digital hold capability that maintains a stable output clock in the event the input clock is lost.
The Si5320 establishes a new standard for jitter performance, integration level and power usage in clock generation devices and is available in a small 9x9 mm ball grid array (BGA) package. It operates over a –20 °C to 85 °C temperature range and is powered from a single 3.3 V supply.
Si5320 Block Diagram
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