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The Si5010 is a fully integrated low-power clock and data recovery (CDR) IC
designed for high-speed serial communication systems.
The Si5010 recovers timing information and data from a serial input at OC-3/12
or STM-1/4 rates. The Si5010 utilizes Silicon Laboratories' proprietary DSPLL®
technology to provide superior jitter performance that remains constant across
the entire industrial temperature range. DSPLL eliminates the external loop
filter components necessary in traditional CDR implementations thereby
improving jitter performance by reducing the device's sensitivity to
board-level noise. Removing these external components also eliminates concerns
related to component aging and supply voltage variations. In addition, the
Si5010 significantly exceeds all SONET/SDH jitter requirements, providing
additional design margin with respect to jitter generation, tolerance and
transfer. Application is further simplified by reducing external device
configuration via reference clock detection circuitry that automatically
configures the device for operation with one of three common reference clock
frequencies: 19 MHz, 77 MHz and 155 MHz.
The Si5010 sets a new standard for low jitter, small size and low power for
high speed CDR devices. It consumes 293 mW (typ OC-12) from a single 2.5 V
supply and comes standard in a 20-pin micro leaded package (MLP).
Si5010 Block Diagram
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