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The Si5017 combines a high sensitivity limiting amplifier and multi-rate clock
and data recovery (CDR) unit into a single IC.
The Si5017 extracts timing information and data from a serial input at OC-48
rates. Support for data 2.7 Gbps streams is also provided for OC-48/STM-16
applications that employ forward error correction (FEC). To simplify device
application and reduce board space requirements, the Si5017 eliminates the
need for an external reference clock by integrating this function into the
device. Enhanced analog and digital signal monitoring is also provided with
user programmable alarms to simplify detection of analog loss-of-signal (LOS)
and digital bit error rate (BER). To accommodate BER optimization for long
haul data links, user-programmable data slicing is available to reduce circuit
complexity.
The Si5017 utilizes Silicon Laboratories' proprietary DSPLL® technology to
provide superior jitter performance that remains constant across the entire
industrial temperature range. DSPLL eliminates the external loop filter
components necessary in traditional CDR implementations thereby improving
jitter performance by reducing the device's sensitivity to board-level noise.
Removing these external components also eliminates concerns related to
component aging and supply voltage variations. In addition, the Si5017
significantly exceeds all SONET/SDH jitter requirements, providing additional
design margin with respect to jitter generation, tolerance and transfer.
The Si5017 consumes 528 mW (typ OC-48) from a single 3.3 V supply and comes
packaged in a small 5 x 5 mm, 28-pin Micro-Leaded Package (MLP). The device
operates over the industrial temperature range (–20 °C to 85 °C.)
Si5017 Data Eye
Si5017 Block Diagram
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