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The Si5018 is a fully integrated low-power clock and data recovery (CDR) IC
designed for high-speed serial communication systems.
The Si5018 recovers timing information and data from a serial input at OC-48
or STM-16 rates. Support for data 2.7 Gbps streams is also provided for
OC-48/STM-16 applications that employ forward error correction (FEC).
The Si5018 utilizes Silicon Laboratories' proprietary DSPLL® technology to
provide superior jitter performance that remains constant across the entire
industrial temperature range. DSPLL eliminates the external loop filter
components necessary in traditional CDR implementations thereby improving
jitter performance by reducing the device's sensitivity to board-level noise.
Removing these external components also eliminates concerns related to
component aging and supply voltage variations. In addition, the Si5018
significantly exceeds all SONET/SDH jitter requirements, providing additional
design margin with respect to jitter generation, tolerance and transfer.
Application is further simplified by reducing external device configuration
via reference clock detection circuitry that automatically configures the
device for operation with one of three common reference clock frequencies: 19
MHz, 77 MHz and 155 MHz.
The Si5018 sets a new standard for low jitter, small size and low power for
high speed CDR ICs. It typically consumes 270 mW (OC-48 typ) from a single 2.5
V supply and comes in a 20-pin micro leaded package (MLP).
Si5018 Block Diagram
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