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The Si5040 is a high performance, protocol agnostic 10 Gbps XFP transceiver
featuring integrated jitter attenuating capability based on Silicon
Laboratories’ proven DSPLL
technology. 
The device is designed to perform reshaping, re-amplifying and retiming of the
bi-directional 10 Gbps serial data by integrating two independent Clock and
Data Recoveries (CDRs), two DSPLL-based Clock Multiplier Units (CMUs), and
data re-timers in both transmit and receive directions. The DSPLL-based CMU
and the data re-timer in the transmit direction eliminate the need for
external jitter clean up circuitry to achieve compliance with telecom and
datacom jitter specifications. The same DSPLL technology minimizes jitter in
the receive path ensuring error free operation with ASICs or FPGAs connected
via the XFI interface. The Si5040 provides three receive signal quality
monitors including analog loss-of-signal (LOS) detection, consecutive
identical digit (CID) detection, and a proprietary digital measure of receive
eye opening. Comprehensive diagnostics are also supported via two loop back
modes as well as pattern generation and check capability on both the receive
and transmit data paths.
The Si5040 provides industry leading jitter performance for all telecom and
datacom protocols between 9.9 and 11.4 Gbps, including OC-192/STM-64, 10 GbE,
10 G Fiber Channel, and their associated forward error correction (FEC) data
rates:
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OC192/STM64: 9.95 Gbps
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10 Gbps Ethernet LAN PHY: 10.3125 Gbps
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10 Gbps Fibre Channel: 10.51875 Gbps
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G.709 OTU2: 10.709 Gbps
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10 Gbps Ethernet + FEC: 11.0957 Gbps
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10 Gbps Fibre Channel + FEC: 11.3176 Gbps
To address XFP module space and power constraints, the Si5040 comes in a 5 x 5
mm LGA package and only consumes 575 mW typ.
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