|
The Si5100 is a complete low-power transceiver for high-speed serial
communication systems operating between 2.5 Gbps and 2.7 Gbps, making it
suitable for OC-48/STM-16 and OC-48/STM-16 applications that use 15/14 forward
error correction coding (FEC).
The receive path consists of a fully integrated limiting amplifier, clock and
data recovery unit (CDR) and a 1:16 deserializer. The transmit path combines
an eight word FIFO with flow control, low jitter clock multiplier unit (CMU)
and a 16:1 serializer. The CMU uses Silicon Laboratories' DSPLL® technology to
provide superior jitter performance while reducing design complexity by
eliminating external loop filter components. In addition, DSPLL supports
programmable loop filter bandwidths, eliminating the need for expensive
external VCXO's and clean-up PLL’s for jitter attenuation. To simplify BER
optimization in long haul applications, programmable slicing and sample phase
adjustment are supported.
The Si5100 provides a 16-bit, 155 MHz LVDS interface and is packaged in a
195-pin 15mm x 15mm ceramic ball grid array (CBGA) package. The device
operates from a single 1.8V supply.
Si5100 Data Eye
Si5100 Block Diagram
|
