#BATCHNAME TX_Synchronous_FIFO_Mode
Rev. 0.1 33
6.2.11. Transmitting Data in FIFO Mode
WDS Command:
# Set PWRDWN pin = LOW
L6
# Apply Software Reset
# Write Register 07: Operating & Function Control1
# Software Reset : set 'swres' bit to 1
S2 8780
# Fine tune the crystal to remove any offset.
# Write Register 09: Crystal Oscillator Load Capacitance Register
# Step through values in this register such that the TX output is at 915Mhz (±0.5 kHz)
S2 897a
# The PLL may also be offset to adjust frequency
# Not required if AFC is enabled or wider IF Filter is used
# Write Register 73, 74, 1D: Frequency Offset Register, Frequency Channel Control, AFC
Loop #Gearshift Override (Disable AFC)
# Step through different values of this register such that the TX output is at 915Mhz +/-
0.5 KHz.
S2 9D00
S2 F300
S2 F400
# Set Desired Center Frequency (950MHz)
# Use Calculator to determine the appropriate values for the registers.
# Write Register 75: Frequency Band Select
# sbsel = '1', hbsel = '1', fb= '10111'
S2 F577
# Write Register 76: Nominal Carrier Frequency 1
# Write Register 77: Nominal Carrier Frequency 0
S2 F67D
S2 F700
# Set Data Rate = 50K
# Use Calculator to determine the appropriate values for the registers.
# Write Register 6E: TX Data Rate 1 Register
S2 EE0C
# Write Register 6F: TX Data Rate 0 Register
S2 EFCD
# Set Deviation to 25KHz
# Write Register 72: Frequency Deviation
S2 F228
# Set GPIOs as digital data outputs to monitor TX related signals
# GPIO0, GPIO1, GPIO2 as digital test outputs
# Write Register 0B: GPIO Configuration 0
s2 8b0b
# Write Register 0C: GPIO Configuration 1
s2 8c0b
# Write Register 0D: GPIO Configuration 2
s2 8d0b
# Select appropriate internal digital signal. (please refer data sheet)
# Write Register 51 : Digital Test Bus Select
# Set Digital Test Bus to output signals at address 29H =41.
# GPIO0 : data_start, GPIO1 : tx_out, GPIO2 : pk_sent
s2 d129
# Set TX Packet Structure
# Set Transmit Header 3 value (optional)
# Write Register 3A : Transmit Header 3
# Set Transmit Header 3 = F0
s2 baf0
# Set Transmit Header 2 Value (optional)
# Write Register 3B : Transmit Header 2
#Set Transmit Header 2 = FF
s2 bbff
# Write Register 33: Header Control2 Register
# select Header 3 & Header 2, Fix packet Length, 2 sync words.
# txhdlen[2:0] = '010', fixpklen = '1', synclen[1:0]= '01'
s2 b32a
# Set transmit Preamble Length
# Write Register 34: Preamble Length Register
# Preamble Length = 0F + 1=16 nibbles.
s2 b40f
# Set data access control register to enable automatic TX packet handling. If CRC is
# enable, CRC byte will be added to the TX.
# Write Register 30: Data Access Control Register
# enpactx=1 : enable automatic packet handling of TX Path.
s2 b00C
# Set TX Data Clock Configuration, Modulation source (Direct Mode, FIFO Mode, PN9),
# Modulation Type (FSK, GFSK)
# Write Register 71: Modulation Mode Control 2 Register
# Set FIFO Mode with FSK Modulation
# dtmod[1:0]= '10' : FIFO Mode, modtyp[2:0] = '010' = FSK.
s2 f122
# Write data to the FIFO
# Write Register 7F: FIFO Access Register
# Set 1st data byte = 0F
s2 ff0f
# Turn Transmitter ON .
# Set VCO current trimming register for automatic calibration.
# Required for RevX Only.
# Write Register 5a: VCO Current Trimming Register
# vcocur[1:0] = '11', vcocorr[2:0] = '111', vcocorrov='1'
S2 da7f
# Write Register 07: Operating Mode & Function Control 1 Register
# txon = '1'
s2 8708
