#BATCHNAME RX_Direct_Mode_868.3MHz_50KDR_h1
#RX LO = 868.3MHz
# Set PWRDWN pin = LOW
L6
# Apply Software Reset
# Write Register 07: Operating & Function Control1
# Software Reset : set 'swres' bit to 1
S2 8780
# Write Register 55: Reduce xTAL Start-#up
S2 D540
# Set VCO Bias Current
S2 DA03
# Set FBDIV HC and disable TX boost
S2 D940
# Set DIG Regulator to 1.5V
S2 E602
# Write Register 62: Crystal Oscillator / Control Test
# Reduces crystal startup time. (Based on measurement results)
S2 E200
# Deltasigma ADC Tuning 2 Register
# Set Delta-Sigma ADC ref. to 0.8V
# This setting gives a better dynamic range for the ADC.
# adcref[2:0]= '111'
S2 E803
# Tune the Crystal to compensate for crystal offset.
# Write Register 09: Crystal Oscillator Load Capacitance
# Step through different values of this register such that the PGA / IF output is at
937.5KHz
# Please refer section on (Crystal Fine tuning for RX)
S2 897a
# The PLL may also be offset to adjust frequency
# Not required if AFC is enabled or wider IF Filter is used
# Write Register 73, 74, 1D: Frequency Offset Register, Frequency Channel Control, AFC
#Loop Gearshift Override (Disable AFC)
# Step through different values of this register such that the PGA / IF output is at
#937.5KHz
# Please refer section on (Crystal Fine tuning for RX)
#S2 9D00
#S2 F300
#S2 F400
# Enable AFC
S2 9D40
#Set AFC Band Limiter
S2 F228
# Set Desired Receive Frequency
# Use Calculator to determine the appropriate values for the registers.
# Write Register 75: Frequency Band Select
# sbsel = '1', hbsel = '1', fb= '10111'
S2 F573
# Write Register 76: Nominal Carrier Frequency 1
# Write Register 77: Nominal Carrier Frequency 0
S2 F667
S2 F7C0
# Enable AGC
# Write Register 69: AGC Override #1
# agcen = '1'
S2 E920
# Disable AFC (AFC is disabled in this revision of the chip)
# Write Register 1D: AFC Loop Gearshift Override Register
# enafc = '0'
S2 9D01
# Set Packet Hander and thresholds
# Set Preamble, Sync, CRC etc.
# Write Register 30: Data Access Control Register
# Set Packet Timing:
# enpactx = '1' :Enable TX Packet Handling,
# crc[1:0] = '00' : CRC=CCITT:
S2 B080
# Set Transmit Packet Length (expected receive packet length)
# Write Register 3E: Transmit Packet Length.
# pklen[7:0] = Set the expected length of packet to be received.
S2 BE18
# Set Preamble Length: Preamble length is set to max. for increasing preamble timeout.
This is only # for doing BER measurements. When using actual packet reception, this value
should be set to
# expected packets preamble length.
# Write Register 34: Preamble Length Register
S2 B47F
# Configure when to confirm if preamble is detected based on pattern matching '1010'.
# Write Register 35: Preamble Detection Control Register
#preath[4:0] = '00111'
# When preath + 1 = 8 nibbles of preamble (sequence of 1010s) is detected, preamble detect
signal
# will go Hi.
S2 B538
# Write Register 33: Header Control2 Register
# fixpklen = '1' : Receive packet of fixed bytes.
# synclen[1:0] = '01' : Set the receiver for 2 bytes of sync word detection.
# Set SYNC word length=2 Bytes: Sync Word 3 & 2
S2 B30A
# Setting the register below will cause no sync detection and preamble detection
# will be restarted after the programmed timeout. Used for test purposes only.
#S2 B30E
# Write Register 36: SYNC Word Byte 3
S2 B62D
# Write Register 37,38,39: SYNC Word Byte 2,1,0
S2 B7D4
S2 B8D4
S2 B9D4
# Select the receiver mode (FSK/GFSK etc.)
# Set FSK/GFSK mode of reception
# Set TR Data Clock out, Direct Mode data via GPIO,Modulation Mode - FSK/GFSK
# Write Register 71: Operating & Function Control 1 Register
# trclk[1:0] = '01' : TX Data Clk is available via the GPIO
# dtmod[1:0]= '00' : Direct Mode using TX_Data function via the GPIO pin.
# modtyp[1:0]= '011' : GFSK mode.
S2 F143
# Select desired signals on the GPIOs
# Set the Test Bus
# Set GPIO to monitor PGA/IF output. IF o/p should be centered at 937.5KHz.
# Write Register 0B: GPIO Configuration 0
# Set GPIO0= Analog Test N Output
S2 8B0C
# Write Register 50: Analog Test Bus
# Set Internal Analog Test Bus to PGA/IF output. IF o/p should be centered at 937.5KHz. If
not, then please compensate for crystal offset (refer section x).
# ATBp/n = PGA-Ip/n
S2 D003
# Write Register 0C: GPIO Configuration 1
# Set GPIO1= Digital Test Output
S2 8C8B
# Write Register 0D: GPIO Configuration 2
# Set GPIO1= Digital Test Output
S2 8D8B
# Write Register 51: Digital Test Bus
# Set Digital Test Bus Output on GPIO's: GPIO0=Bit Clock, GPIO1=Valid
# Preamble, GPIO2=RX Data
S2 D136
# Set Modem according to the desired data-rate, deviation, filter BW.
# Please use the EXCEL CALCULATOR to calculate the values for the following registers
# Set Modem Settings
# 50KBPS data rate, 25kHz dev, Mod Index=1, BW=95.3kHz
# Write Register 1C: IF Filter Bandwidth
# Set IF Filter Decimation Rate NDEC=3'h0
# Set IF Filter Coefficient Set FILSET=4'h4
S2 9C01
# Write Register 20: Clock Recovery Oversampling Ratio
S2 A050
# Write Register 21: NCO Offset (high bits)
S2 A101
# Write Register 22: NCO Offset (medium bits)
S2 A299
# Write Register 23: NCO Offset (low bits)
S2 A39A
# Write Register 24: Clock Recovery Timing Loop Gain (high bits)
S2 A406
# Write Register 25: Clock Recovery Timing Loop Gain (low bits)
S2 A568
# Write Reg. Clock Recovery Gearshift Override
S2 9F03
# Turn on the receiver
#### Turn the Receiver ON
# Write Register 07: Operation & Function Control 1
# rxon = '1'
S2 8704
