TUESDAYS at 9:00 AM CDT/ 16:00 CET
WEDNESDAYS AT 10:30 AM HKT
Join Us: September 2020 - January 2021
Learn from our Timing experts how to fast track your system designs in data centers, networking, industrial, automotive, and 5G markets. During each technical session, our experts address specific industry requirements, identify system requirements, and demonstrate how to leverage our feature-rich Timing portfolio to maximize system benefits. In this series, you will also learn about our powerful and easy-to-use software tools to simplify clock tree design and reduce time to market.
Register for the fall series now. The full schedule is below.
Learn More About Our Upcoming Webinars
9:00 CST/16:00 CET
|Design Considerations When Selecting a XO/VCXO Clock Reference for 56G/112G SerDes||Tuesday, Oct 13||Wednesday, Oct 14|
|Stop Guessing, Use Silicon Labs Timing Tools to Build Your Clock Tree||Tuesday, Oct 27||Wednesday, Oct 28|
|Optimize Timing Solutions for High Speed FPGA and Application Processor Designs||Tuesday, Nov 10||Wednesday, Nov 11|
|PCIe Gen 4/5/6 Specifications and Jitter Measurement Explained||Tuesday, Nov 17||Wednesday, Nov 18|
|Timing Solutions for 5G O-RAN Systems||Tuesday, Dec 1||Wednesday, Dec 2|
|AECQ-100 Timing Products for Automotive Applications||Tuesday, Jan 12||Wednesday, Jan 13|
|Timing Solutions for Open-Compute Systems||Tuesday, Jan 26||Wednesday, Jan 27|
|IEEE 1588 Timing Solutions for Non-Telecom Applications||Tuesday, Sep 15||Wednesday, Sep 16|
|Clock Jitter Demystified and Jitter Requirements for 56/112 Serdes||Tuesday, Sep 29||Wednesday, Sep 23|