Original Posting Date: September 10, 2014
When you’re designing for the Internet Infrastructure with the Si534x clock tree on a chip, you can reduce jitter to your lowest levels ever with these four guidelines:
Let’s look at each one in more detail.
1. Select the Differential Output Options (LVDS, LVPECL, HCSL)
Differential outputs produce balanced, complementary output signals designed to yield the best jitter performance. These differential signal formats also inherently produce minimal common mode noise—which also minimizes EMI—and they generally consume less power than CMOS formats.
2. Order the Output Clocks Carefully
The order in which you place your clocks can have a substantial impact on jitter performance. Taking some time to consider your clock placement can really pay off. Are clocks likely to experience crosstalk between each other located physically next to each other? If so, then you’ve just guaranteed they’ll contribute to jitter. It’s like sitting best friends across the room from each other in grade school so they can’t pass notes or whisper back and forth. Here’s an example, using the common integration band of 12 kHz to 20MHz from SONET OC-48:
If two adjacent clocks are closer to each other than 20 MHz, which is the farthest extent of the jitter integration band, you may have crosstalk issues. When a 155.52 MHz clock output is next to a 156.25 MHz clock output (a difference of a mere 730 kHz), the mixing differences will be well within the stated 12 kHz to 20 MHz jitter mask band. In this example, you’d want to avoid putting those two clocks next to each other. They’re just begging for trouble.
Of course, this guideline doesn’t apply to clocks that are simple integer multipliers of each other. A 125 MHz can go next to a 625 MHz clock because the edges of one clock will not be moving with respect to the edges of the other clock.
3. Separate Clocks with Unused Outputs
Unused clock outputs can physically separate clocks that would otherwise interfere with one another. For example, if there is an unused clock output, it can be placed between a 155.52 MHz and a 156.25 Mhz clock to physically separate them. The table below shows the benefits you can gain by rearranging the used output clocks.
Table 1: Impacts of Output Clock Ordering on Jitter Performance
4. Avoid Using CMOS Output Formats in Jitter Critical Applications
CMOS output buffers swing rail-to-rail and are not balanced, unlike output formats like LVPECL, LVDS, CML, and HCSL). This means CMOS outputs create significant current surges at all of the clock edges and, therefore, are prime crosstalk aggressors. Staying away from CMOS outputs altogether when designing a jitter sensitive application is highly recommended.
Sometimes, though, you don’t have a choice and you have to use CMOS formats. If you find yourself in that position, quarantine the CMOS clocks and keep them away from critical clock outputs that are not the same frequency.
If you’re using ClockBuilder Pro to help design your clock trees, select the ‘complementary output option rather than the ‘in-phase’ option to help balance the output current surges during transitions. You also want to avoid terminating the load of one side of a CMOS pair if it is unused but actively toggling.
Silicon Labs recommends that you consider using an external, low-jitter, differential mode to CMOS buffer. Place the buffer away from the Si534x device on the PCB to avoid coupling.
If you’d like to learn more about the finer points of optimizing jitter performance, you can read the full Application Note for a more thorough discussion.
Learn more about the Si534x here.