UCSC Silicon Valley Extension 2505 Augustine Dr Santa Clara, CA 95054
Presented by: Tony Smith
Breakfast and lunch will be provided
Jitter isn't just the unfortunate side effect of a caffeine bender. It can be a serious challenge when you’re designing with high frequency reference clocks. As communication standards demand ever higher speeds, especially in PCIe, 10/40/100G Ethernet, Broadcast Video and CPRI/OBSAI applications, it's becoming increasingly difficult to meet the constraints put on timing budgets.
Join us at our half-day workshop covering the in's and out's of all things jitter, including: