Measuring PCIe clock jitter can be a challenging task. Most differential clock signals are specified across a phase jitter filter mask of 12kHz-20MHz, however PCIe differential signals are specified and measured using a different set of complex filter masks. Further, each PCIe generation specification presents a different set of masks to measure PCIe clock jitter. To make things just a little more difficult, most oscilloscope manufacturers do not include the PCIe masks for measuring PCIe clock jitter, requiring designers to purchase costly add-on packages.
To make this whole process easier, Silicon Labs just completed and released a new, free software tool that measures PCIe clock jitter from any supplier using common oscilloscope waveform files. The tool is proven and approved by other PCI-SIG members, and provides compliance data and a report for any PCIe clock source on the market.
As all PCIe clocking suppliers know, it is a common customer request to have multiple sources for the PCIe timing solutions. This free tool also helps to ensure the complementary timing solutions provide similar performance, so if they are swapped out, the overall system performance doesn’t change unpredictably.
We have provided a few examples of our own PCIe clock generators’ compliance reports below. As you will see, the Silicon Labs PCIe clocks provide PCIe Gen4/3/2/1 compliance with better performance than the maximum PCIe timing specifications. This allows for some degree of design error while still meeting the PCIe clocking requirements. This is important in the complex designs using PCIe today, where even a small error can reduce data throughput and perceived performance of the whole system as a result.
We also just consolidated all our PCIe application notes, whitepapers, the free PCIe jitter measurement software, and videos in a single page on our website – The PCIe Learning Center.
For example, some of our solutions use Push/Pull outputs versus Constant Current outputs. As a result reduce power consumption by over 50% and BOM count by over 75%. We have built special boards and described the PCIe output performance in AN871: Alternative Output Terminations and AN951: Driving Long Output Traces to demonstrate and explain how this innovative, power efficient design can drive long trace lengths for complex designs while saving significant energy—an important consideration for today’s power-hungry designs.
We also provide a detailed examination of the new PCIe Gen4 jitter requirements in AN946: PCI Express (PCIe) 4.0 Jitter Requirements.
I hope you’ll find the new PCIe learning center and free PCIe jitter measurement tool valuable.