High-performance FPGAs play a key role in numerous applications including data centers, broadcast imaging, and industrial control. Unlike earlier generations, using high-performance FPGAs presents new design challenges. Rather than using simple integer clock multiplication of reference inputs or clock generation, high-end FPGAs require multiple non-integer-related frequencies to generate any output frequency without sacrificing jitter performance. To achieve this, a new clock reference architecture is required.
Traditional Clock Reference Architecture
Implementing a complex clock tree while still meeting severe space restrictions and a compressed time-to-market requires a new approach to clock generator design. The traditional architecture is based around a simple loop that generates a voltage-controlled oscillator output at a multiple of the desired frequency. In this architecture, the output clock frequency is a function of the input clock frequency and the PLL divider values. This model is suitable for simple integer clock multiplication of reference inputs or clock generation from a crystal input.
Solving the High-Performance FPGA Challenge
On the other hand, high-end FPGAs require multiple non-integer-related frequencies. The designer must use one or more custom crystals and multiple clock generator ICs to generate the required set of frequencies, increasing the cost, complexity and power consumption of the overall solution. Silicon Labs’ patented MultiSynth™ fractional divider architecture solves this problem. The MultiSynth architecture switches seamlessly to produce the exact output clock frequency with zero ppm error. This technique makes it possible to generate any output clock frequency without sacrificing jitter performance.
A comparison of (a) the traditional PLL and (b) the MultiSynth clock generation architectures
Integrated LDOs Reduce Noise and Improve Performance
In addition to the MultiSynth architecture, clock generators include multiple features that contribute to low jitter and save system cost. For example, noise on the power supply is a significant problem in high-performance clock devices. It affects the performance in two ways:
Power supplies based on switching topologies are the preferred choice in high-current, low-voltage designs because they are highly efficient. Unfortunately, they also generate significant noise, so FPGA system designers must add low-noise low-dropout (LDO) linear regulators, ferrite beads, and numerous filter capacitors to remove power-supply noise before it reaches the clock generator. This adds significant cost and increases the board size. However, Silicon Labs devices include multiple LDOs on the chip to largely eliminate the need for these external components.
Silicon Labs Solutions
In conjunction with the timing solutions products, Silicon Labs offers several software tools that help customers develop quick-turn, customized solutions. ClockBuilder Pro (CBPro) is a software tool that simplifies the task of getting from a clock-tree specification to an orderable part. The tool uses a step-by-step GUI format that includes more than 175 clock design rules to reduce design and debug time. The CBPro software package is freely available for download, and with the tool, designers can now develop an optimum solution and quickly evaluate sample parts. Other software tools include a Phase Noise to Jitter Calculator that helps translate FPGA phase noise specifications into jitter requirements.
Silicon Labs timing solutions are widely used in several FPGA reference designs. These evaluation and development kits enables quick customer adoption and accelerate time-to-market. Visit our clock and oscillator reference designs to get started.
To learn more about how Silicon Labs’ portfolio of clock generators can help meet your FPGA design requirements, read the full whitepaper.