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      • EFM32 Wonder and Leopard Gecko, Now 60% Smaller and 30% Thinner

        Nari | 10/289/2014 | 07:45 AM

        Original Posting Date: October 15, 2014

         

        We know you love our EFM32 Wonder Gecko Cortex-M4 and Leopard Gecko Cortex-M3 32-bit low-power MCUs, but now you can love them in even smaller chip scale packages (CSPs). How much smaller?

        wonderleopardgecko_table

         

        We’ve added a new Wonder and Leopard Gecko CSP 81-ball configuration with a 9X9 ball array and 0.4mm ball pitch. There are three new configurations each for Wonder and Leopard Gecko that are all footprint-compatible.

        wonderleopardgecko-transparent2

        Find out more about these new CSPs for EFM32 Leopard Gecko and Wonder Gecko at SiLabs.com.

      • Minimizing Additive Jitter

        Nari | 10/289/2014 | 07:32 AM

        What contributes to a clock distribution buffer’s additive phase noise performance, and how can you optimize performance without increasing costs? We’ll take a look a few key considerations.

        If you’re working on clocks, you understand the importance of power supply decoupling and signal integrity. What you can sometimes overlook is that the input rise and fall time has a significant impact on additive phase jitter. While on first glance this is true, what makes the statement even more accurate is to consider both the amplitude versus rise and fall time, which is expressed as Volts/ns—or slew rate.

         

        Calculating slew rate with digital or analog components

        Most engineers would associate slew rate with analog components, such as an op-amp, and it’s uncommon to see a slew rate requirement in a digital component data sheet. Even though we’re still dealing with digital logic levels or inputs, slew is just a more accurate way to describe what can really improve or degrade additive phase jitter. Take for example a differential LVDS signal which has a 350 mV single ended amplitude and a 400 ps rise and fall time measured at 20% and 80%, the differential slew rate would be (2 x 350 mV x 0.6) / (400 ps) or 1.05 V/ns. For the purpose of this post only differential slew rate is used.

         

        As an example shown in Table 1, note the additive jitter specification includes a description of slew rate, output frequency and output logic format as all have an effect on additive jitter.

         

        additivejitterpart1table1Table 1: Recommended Operating Conditions

         

        A clock distribution IC does not generate a clock but rather regenerates and provides multiple copies. As such phase noise cannot be measured unless an input is applied and total jitter is measured—the clock buffer’s contribution is referred to as additive phase jitter. In order to characterize the phase jitter contribution due to the buffer, the source is first measured, then the source plus DUT is measured and finally phase jitter is calculated by using the following equation:

        Note that when a clock buffer’s additive jitter and the source jitter number (usually given as an rms value) are provided, a root sum square value will be used to calculate total jitter:

         

        How slew rate impacts jitter performance

        It is important to know what factors will have an impact on the jitter performance when adding a distribution buffer to a clock tree. This is also very important when reading data sheets, as how the supplier specifies their buffer’s jitter performance can greatly impact the number you see in the data sheet. For example, two buffers with similar performance may show very different additive jitter specifications, if one vendor used a much faster slew rate than the other.

        slewrate4

         

        Figure 1. Additive Jitter vs. Slew Rate for Two Different Buffer Families

         

        Figure 1 shows the additive phase jitter versus input slew rate for two different clock buffers. In both cases the additive jitter decreases or improves as slew rate increases. What is interesting are the results shown in red can appear to be overall better. However, it’s actually more sensitive and quickly degrades at lower slew rates, such as a low frequency sine wave or CMOS clock. This graph highlights the importance of comparing additive phase jitter using the same slew rate values.

         

        There are many more considerations that come into play when you’re considering the cause of additive jitter in your buffers. For a full discussion of the causes and solutions to additive jitter, read the full application note here.

         

      • Meet the industry’s smallest PCIe Gen 1/2/3 clock generator

        Nari | 10/289/2014 | 07:29 AM

        Bigger definitely isn’t better when it comes to silicon. That’s why Silicon Labs is proud to announce the industry’s smallest PCIe Gen 1, 2 and 3 compliant clock generator, measuring only 2 mm X 2.5 mm, using our low-power PCIe and CMEMs technology.

         

        The Si50122 does not need a reference crystal or clock input. The reference frequency source is integrated with the PCIe clock generator, using Silicon Labs’ CMEMS technology. The output buffers of the device utilizes low-power push-pull architecture to eliminate all external termination circuitry needed in traditional constant current mode architecture. This results in reduced BOM components and board space savings.

        Let’s take a look under the hood (or inside the box) for more details.

         

        Increases reliability by using CMEMS instead of quartz

        Our CMEMS have a 10-year guaranteed operating life and frequency stability across an operating temperature range of -40°C to 85°C. Even under harsh conditions like wide temperature swings, shocks and extended vibration, the integrated CMEMS in Si50122 will provide reliable and guaranteed performance. It also eliminates common startup and reliability issues associated with quartz crystal.

        Since there are no moving parts in CMEMS, the clock solution is very robust and not susceptible to drops. In handheld applications like digital cameras, the user no longer needs to worry about breaking the crystal if they drop the camera because the crystal has been replaced by CMEMS.

         

        Simplify your design and your BOM

        Utilizing push-pull output and CMEMS technologies allows for simplified trace routing. All you need to do is route clock signals from the output pins of Si50122 to a PCIe endpoint, instead of having to route signals from external crystal to the clock generator, and then to an endpoint.

         

        The Si50122 comes in a small form-factor 10-pin TDFN package, saving precious board space in applications where PCB real estate is critical. Our low-power HCSL push-pull architecture does not require external termination resistors or reference current resistors. Most of our competitors’ devices use older constant current mode output buffer technology, requiring 4 external termination resistors per output, plus one reference current resistor.

         

        Another advantage of utilizing our CMEMs technology together with low-power push-pull output buffers allows you to eliminate numerous external passive components, reducing component count to consolidate your BOM and reduce cost. Compared to a competitor’s 2-output constant-current PCIe clock generator, the Si50122 will reduce BOM component count by nine resistors, one 25MHz crystal, and 2 crystal loading capacitors. Take a look at the solutions to see the difference for yourself.

        Si50122_interior
        Go from multiple components taking up precious board space to the 2.5mmX2mm Si50122.

         

        High performance, low power

        Using push-pull technology also provides benefits in power consumption, while still meeting PCIe Gen1/2/3 maximum jitter requirements with margin. For example:

        • ICS557-03 Power consumption: 257.4 mW (IDD = 78 mA)
        • Si50122 Power consumption: 66 mW (IDD = 20 mA)

        There’s no need to sacrifice space for performance when you choose the Si50122 crystal-less PCIe clock solution. To find out more about the Si50122, visit our product page.

      • INFOGRAPHIC: MCU Interfaces and the IoT

        Nari | 10/289/2014 | 07:26 AM

        For our last post on 8-bit MCUs and the IoT, take a look at this infographic exploring why these simpler processors have a big part to play in the future of the IoT. Spoiler alert—it’s all about the nature of IoT devices and versatility.

         

        8BITMCU

         

        Today’s interconnected IoT ecosystem favors IC devices with a wide variety of interfaces since the heterogeneous nature of the embedded marketplace requires these devices to be able to converse in as many “dialects” as possible.

        A significant number of IoT applications are “thin client” in nature. This is what makes them a natural fit for an 8-bit machine with limited flash and onboard RAM. For example, most sensor applications where voltages/currents must be sensed and operated upon and then transmitted upstream are suited to an 8-bit machine. Examples include gas and oxygen sensors in connected home applications and pressure sensors in commercial/industrial applications.

        Simple control applications are also better suited to 8-bit rather than 32-bit machines, especially if complex real-time I/O manipulation is necessary. Specifically, the 8051 architecture allows fast I/O bit manipulation with concurrent logical operations, which is useful in control applications.

         

        These applications are usually very space- and power-sensitive, which also plays to the strengths of 8-bit devices such as the high-speed 8051 MCUs from Silicon Labs. Note that various ARM Cortex-M series devices can also play in these applications, but, given the board area and power and real-time limitations of the systems, an 8-bit machine with a more deterministic execution model will perform better.

        Explore our full family of exceptional 8-bit MCUs.

      • The Lowdown on Sleep Current: Does Active Current Still Matter?

        Nari | 10/289/2014 | 07:23 AM

        Original Posting Date: September 23, 2014

         

        Many of the most common capacitive sensing-enabled products, such as remote controls, set-top box front panels and wall-mounted control interfaces, tend to stay inactive much more often than they’re active. A television remote control might sit on a coffee table 16 hours of a day before the user finally gets the chance to sit down and watch some TV. Since these devices stay in an ultra-low power state the vast majority of the time, the amount of current the MCU controlling the device draws when the device is active doesn’t matter, right?

         

        Wrong. The truth is that a design that’s been optimized for minimal current draw remains power conscientious during all operational states, from a design’s lowest power idle state to its most computationally intense active state. In capacitive sensing applications, a low power state means that scanning happens at a lower frequency, and a ‘candidate touch’ will switch the MCU to an active mode where scanning happens at a higher frequency to create a system that’s responsive to user input.

         

        activesleepcurrentblogpic

         

        Let’s say a designer is creating a system powered by two AA batteries. The system uses a capacitive sensing MCU that runs two states of operation: the lowest power state uses 500 nA and the highest power state uses 10 mA of current. The design team estimates that the system will be active 30 minutes of every day, where the capacitive sensor needs to be in its highest power state to scan buttons and respond to user input. Thirty minutes a day is about 2 percent of the device’s time, so the average current draw when factoring in both active and low power modes works out to be around 200 uA. Excluding other components in the system that might also draw current, the two 2700 mAh AA batteries will be drained in about three years of use.

         

        Now let’s run those same numbers with a system that has an active mode current draw of 5 mA instead of 10 mA. Even though the system only runs in active mode for 30 minutes a day, the average current draw for this 5 mA system works out to be 100 uA – half of the previous design. This means that we've effectively doubled our battery life by reducing our active mode current by 50 percent. An extension of battery life to this degree can mean all the difference in customer experience.

         

        So how can a developer reduce active mode current draw? Two strategies can be used: use as little current as possible while in active mode, and stay in active mode for as little time as possible. Silicon Labs' capacitive sensing MCUs help developers pursue both strategies through numerous design optimizations:

         

        • Our fast and accurate capacitance to digital converter means that the system can do more scans per unit time than many competing MCUs.
        • Capacitive channel binding means that the capacitive sensing block can scan multiple inputs simultaneously, when the system only needs to determine if a touch is happening somewhere on the sensing surface. When firmware detects a ‘bound touch’, the system can break the binding and scan inputs individually.
        • A low power oscillator can be used when system timing is not critical. This oscillator provides around a 20MHz system clock at a fraction of the current draw of the precision internal oscillator.
        • A 150 uA suspend mode gives developers an easy-to-enter/quick-to-exit intermediate low power state when the system is waiting for an event to occur but cannot yet enter its lowest power state.
        • Memory retention across low power mode means that the system doesn’t have to reinitialize capacitive sensing registers or RAM when it enters active mode. This means a system can get back to sampling and processing quickly and revert back to a low power state as quickly as possible.

        All capacitive sensing applications trade current draw for responsiveness. Generally, the more current allocated to capacitive sensing, the more robust and responsive the system becomes. In designs with slower capacitive sensing MCUs or MCUs with less design attention paid to low power operation, developers often have to sacrifice battery life to preserve the user experience. With a combination of a fast capacitive sensing block and low power design features, Silicon Labs makes it easy to design a responsive system that is power conscientious in all modes of operation.

         

        Learn more about our full line of capacitive sensors here.

      • Managing User Input: Apps Processors vs. Capacitive Touch Sensors

        Nari | 10/289/2014 | 07:20 AM

        Original Posting Date: September 22, 2014

         

        When designing an embedded system, developers must decide whether a function should be controlled by a discrete component of the design, or whether that functionality can be covered by an existing, more centralized part in the system. For instance, developers of systems with an analog input component may have to decide between designing a system with a discrete analog IC, and designing a system where the MCU has an on-chip analog-to-digital converter.

         

        A system’s user interface is another function where a designer must consider whether to centralize functionality or create a sub-system to cover that functionality. As MCUs become more powerful and functionally dense, it can be tempting to control all user interface features from a centralized host processor. One reason this design style is tempting is because assigning all responsibility to a host processor can reduce BOM cost, as well as manufacturing and test time. It can make a system appear to be easier to design and control because so much functionality is packed into a single chip. However, in most cases, partitioning off the interface responsibilities into a discrete system component creates a system that is more energy-efficient, responsive and faster to design and debug.

         

        Embedded systems with powerful host processors tend to be energy-hungry. The more functionality piled onto the host processor, the more often the processor will be in a high-current active mode of operation. In order for a user interface to be responsive, the host processor will have to frequently poll inputs and monitor the interface’s state. This monitoring becomes even more burdensome in systems that use a capacitive sensing surface as an interface style because capacitive sensing requires post-processing to convert capacitance values to qualified touch events. If the developer designs the system so that the capacitive sensing user interface is controlled by a smaller, more energy-efficient MCU designed for that specific purpose, such as the capacitive touch MCUs offered by Silicon Labs, then the host processor can stay in a low power state a higher percentage of the time and system current consumption can be greatly reduced.

         

        In a system with a discrete touch MCU used to monitor a user interface, a system will tend to be more responsive to touches. This is because the MCU monitoring touch is often assigned only this task, meaning that it will not have to periodically service other interrupts or cover other responsibilities that steal processor cycles and memory from the touch interface. The touch processor can fully qualify a touch autonomously, without any involvement from a host processor that could slow down touch-qualifying decisions. This speed and focus results in a system with reliable – and reliably fast – touch detection.

         

        Finally, developing a discrete and autonomous touch sensing component in an embedded system adds modularity to the design that promotes concurrent development between team members. The team members working on the touch design do not need to worry about their code stealing chip resources from the host processor’s other responsibilities. All of the work of the touch interface can instead be distilled down to a simple interface between the touch MCU and the host processor. Usually this is a serial interface with at most two data lines describing touch events, and possibly an interrupt pin that goes active when a new touch event has been qualified. Development and debug by system engineers on the product can concentrate on the output generated on that serial interface. This abstraction of the touch interface also enables a system design team to develop multiple touch interface variants in the prototype stage, and because each variant would use the same serial interface, the cost of switching out variants for tests is minimal compared to the cost of switching a host processor or a host processor’s code base to examine performance differences between capacitive sensing solutions on the market.

         

        Factors as wide-ranging as current consumption constraints, printed circuit board sizes, end product price targets and radiated noise all factor into system developers’ decisions on whether to lump multiple functions into a single system component or decentralize functionality across multiple components. Silicon Labs’ capacitive sensing MCU solutions make it easy to develop a discreet touch interface component on a board that is power-friendly, responsive, and reliable.

         

        Explore the full range of Silicon Labs capacitive sensing MCU solutions.

      • Touch Sensors vs. Mechanical Buttons

        Nari | 10/289/2014 | 07:16 AM

        Original Posting Date: September 19, 2014

         

        In recent years, capacitive touch interfaces have become commonplace on products that have traditionally used mechanical buttons. Products as diverse as remote controls, wall-mounted panels, white goods appliances, and of course smart phones all now routinely use capacitive input surfaces. Despite the popularity of capacitive sensing surfaces, designers should weigh both the advantages and disadvantages of capacitive sensing technology against older mechanical button technology before deciding on the best interface for their products.

         

        In many cases, mechanical buttons require less current to monitor than capacitive sensing inputs because mechanical buttons can be tied to port match wake-ups that allow the system to be in an extremely low power state without waking for any monitoring or maintenance. Mechanical buttons are also generally less susceptible to generating false positive touch events due to coupled interference on the MCU’s input pin. This is because mechanical buttons are monitored using digital input pin logic, whereas capacitive sensing solutions require more sensitive analog hardware. Finally, mechanical buttons tend to do a better job of sensing touches from gloved hands, because many fabrics electrically insulate fingers and prevent capacitive sensing solutions from detecting them.

         

        Capacitive sensing inputs became a popular choice for interface design because of the flexibility offered by capacitive sensing input surfaces compared to mechanical inputs. With capacitive sensing inputs, buttons can be shaped in a wide variety of ways, and slider and control wheel designs can be implemented in a way that can be visually attractive while not adding additional manufacturing burden.  A capacitive sensing input surface enables designers to create attractive and distinct products.

         

        Capacitive sensing inputs also mean fewer mechanical parts on a bill of materials relative to a design with mechanical buttons. Many capacitive sensing interfaces consist only of a PCB with electrodes, an acrylic overlay, and a decal adhered to the overlay. This reduced BOM count can lower manufacturing cost and time. Fewer mechanical parts also means lower risk of failure in the field, as capacitive sensing buttons don’t wear out and break like mechanical buttons do.

         

        Mechanical and capacitive solutions both have susceptibility to moisture, however. Mechanical button designs that are not waterproof can be permanently damaged when water slips into the product’s circuitry, often through gaps in the mechanical button components of the interface. Capacitive sensing solutions are often more robust against permanent damage because the acrylic overlays are often a solid acrylic material with no gaps or seams where moisture can enter. However, capacitive sensing solutions can detect false positive touch events due to moisture on the sensing surface without sophisticated firmware-implemented countermeasures.

         

        Silicon Laboratories’ capacitive sensing technology minimizes some of the potential disadvantages of capacitive sensing interfaces. Low power functionality on capacitive sensing MCUs provides an average current draw of less than 1 uA in most applications, which matches the lowest power state of many MCUs monitoring mechanical buttons in sleep mode. The capacitive sensing firmware library, aided by a high frequency on-chip system clock and large Flash/RAM footprint, provides the processing and buffering horsepower to guard against an array of interference sources that could lead to false positive touch events in other MCUs.

         

        Developers decide to design with mechanical buttons or capacitive sensing buttons based on a set of criteria ranging from use cases and environments to 'look and feel' design choices. Silicon Labs’ capacitive sensing MCUs provide a robust capacitive sensing option that mitigates potential use case disadvantages and enables developers to concentrate on look and feel design choices.

        Explore our whole family of capacitive sensing MCUs.

      • Not a Clock Tree Expert? We’ve got you covered.

        Nari | 10/289/2014 | 07:12 AM

        Original Posting Date: September 18, 2014

         

        Designing clock trees is tedious but necessary task facing today’s high-speed network system designers.

        We know you are under incredible pressure to deliver the highest quality products at competitive prices and with very stringent deadlines. We also realize you often do not have time to become PLL configuration experts. Silicon Labs has invested in tools to make it fast and easy to design your entire clock trees in minutes without needing to take the time to become wizards for every spec and every device in the clock tree.

        If any of the following challenges apply to you, our Clock Tree Expert tool might be your ticket to timing bliss:

         

        • Do you need to use timing ICs that require a diverse set of frequencies, formats and voltages?
        • Are your clock specifications very difficult to meet due to high data rates?
        • Does your project demand high cost-per-bit?
        • Do you face compressed time-to-market requirements?

        Our new Clock Tree Expert is a web-based tool that makes timing architecture configuration easier and faster by automating the design of clock trees. You’ll no longer need to spend time researching timing topologies or have to remember every part number and spec for each component in the clock tree. Worrying about BOM count and time to market is a thing of the past with Clock Tree Expert.

         

        clocktreeexpert

         

         

        So how does the Clock Tree Expert work? Just type in your clock requirements (formats, frequencies, etc.), and our intuitive tool will generate a custom clock tree recommendation within minutes. From there you can save your designs, create a BOM list, customize parts or go straight to the ordering process.

        The Clock Tree Expert is the latest addition to Silicon Labs’ timing tools including Clock Builder Pro that are designed to simplify the entire timing customization process.

         

        Click here to check out the Clock Tree Expert for yourself.

        To see Silicon Labs’ wide range of timing tools and products, please visit www.silabs.com/timing-tools.

      • Four Simple Rules for Optimal Jitter Performance in Internet Infrastructure Designs

        Nari | 10/289/2014 | 07:08 AM

        Original Posting Date: September 10, 2014

         

        When you’re designing for the Internet Infrastructure with the Si534x clock tree on a chip, you can reduce jitter to your lowest levels ever with these four guidelines:

         

        1. Select the Differential Output Options (LVDS, LVPECL, HCSL)
        2. Order the Output Clocks Carefully
        3. Separate Clocks with Unused Outputs
        4. Avoid Using CMOS Output Formats in Jitter Critical Applications

        Let’s look at each one in more detail.

         

        1. Select the Differential Output Options (LVDS, LVPECL, HCSL)

        Differential outputs produce balanced, complementary output signals designed to yield the best jitter performance. These differential signal formats also inherently produce minimal common mode noise—which also minimizes EMI—and they generally consume less power than CMOS formats.

         

        2. Order the Output Clocks Carefully

        The order in which you place your clocks can have a substantial impact on jitter performance. Taking some time to consider your clock placement can really pay off. Are clocks likely to experience crosstalk between each other located physically next to each other? If so, then you’ve just guaranteed they’ll contribute to jitter. It’s like sitting best friends across the room from each other in grade school so they can’t pass notes or whisper back and forth. Here’s an example, using the common integration band of 12 kHz to 20MHz from SONET OC-48:

        If two adjacent clocks are closer to each other than 20 MHz, which is the farthest extent of the jitter integration band, you may have crosstalk issues. When a 155.52 MHz clock output is next to a 156.25 MHz clock output (a difference of a mere 730 kHz), the mixing differences will be well within the stated 12 kHz to 20 MHz jitter mask band. In this example, you’d want to avoid putting those two clocks next to each other. They’re just begging for trouble.

        Of course, this guideline doesn’t apply to clocks that are simple integer multipliers of each other. A 125 MHz can go next to a 625 MHz clock because the edges of one clock will not be moving with respect to the edges of the other clock.

         

        3. Separate Clocks with Unused Outputs

        Unused clock outputs can physically separate clocks that would otherwise interfere with one another. For example, if there is an unused clock output, it can be placed between a 155.52 MHz and a 156.25 Mhz clock to physically separate them. The table below shows the benefits you can gain by rearranging the used output clocks.

         

        improving-jitter-10gbps-figure1-table

        Table 1: Impacts of Output Clock Ordering on Jitter Performance

         

        4. Avoid Using CMOS Output Formats in Jitter Critical Applications

        CMOS output buffers swing rail-to-rail and are not balanced, unlike output formats like LVPECL, LVDS, CML, and HCSL). This means CMOS outputs create significant current surges at all of the clock edges and, therefore, are prime crosstalk aggressors. Staying away from CMOS outputs altogether when designing a jitter sensitive application is highly recommended.

        Sometimes, though, you don’t have a choice and you have to use CMOS formats. If you find yourself in that position, quarantine the CMOS clocks and keep them away from critical clock outputs that are not the same frequency.

        If you’re using ClockBuilder Pro to help design your clock trees, select the ‘complementary output option rather than the ‘in-phase’ option to help balance the output current surges during transitions. You also want to avoid terminating the load of one side of a CMOS pair if it is unused but actively toggling.

         

        Silicon Labs recommends that you consider using an external, low-jitter, differential mode to CMOS buffer. Place the buffer away from the Si534x device on the PCB to avoid coupling.

        If you’d like to learn more about the finer points of optimizing jitter performance, you can read the full Application Note for a more thorough discussion.

        Learn more about the Si534x here.

      • Build your clock tree designs without worrying about phase locked loops and register settings

        Nari | 10/289/2014 | 07:05 AM

        Original Posting Date: September 8, 2014

         

        ClockBuilder Pro software helps you design advanced clock tress fast by generating a frequency plan for supported clock generators, jitter attenuating clock multipliers, and network synchronizers. Let's take a look at how to create your own custom devices in 3 simple steps.

        Step 1. Configure: ClockBuilder Pro helps you configure a very complex, high-performance clock in an intuitive, graphical user interface that incorporates more than 150 years of Silicon Labs’ timing expertise.

         

        ClockBuilder-Pro-1

         

         

        Step 2. Evaluate: The tool allows you to confirm that configuration directly on an evaluation board using the same software with one click and verify the performance of your clock tree quickly.

         

        ClockBuilder-Pro-2

         

         

        Step 3. Customize: You can also sample a custom clock matching your configuration exactly within 2 weeks.

         

        ClockBuilder-Pro-3

         

        Do you want to try the tool yourself? Download the user's guide and the software tool to get started quickly!

         

        ClockBuilder User’s Guide:

        http://www.silabs.com/Support%20Documents/TechnicalDocs/Si5345EVB.pdf

        Software Tool:

        http://www.silabs.com/products/clocksoscillators/Pages/timing-software-development-tools.aspx