Today, we’ve announced the purchase of the IEEE 1588 precision time protocol (PTP) software and module assets from Qulsar. This addition to Silicon Labs’ IEEE 1588 portfolio uniquely positions us to simplify development and adoption of IEEE 1588 synchronization in 5G wireless, transport and access networks and accelerates time to market.
For years, Silicon Labs has been a leading provider of timing solutions for infrastructure applications with a broad portfolio of crystal oscillators, and voltage-controlled crystal oscillators (XO/VCXOs), clock generators, clock buffers, jitter attenuators and network synchronizers.
Expanding our portfolio to include IEEE 1588 software and modules extends Silicon Labs to a broader range of customers with a growing need for precise time synchronization, such as small cells, optical transport, smart grid and automotive. Silicon Labs can address cost-sensitive PTP software-only applications such as small cells with a standards-compliant turnkey solution. The 1588 modules make it easy to add IEEE 1588 to a design by tightly integrating PTP software and physical layer hardware in a plug-and-play solution.
The purchase includes all Qulsar modules (PTP master, gateway, boundary clocks and slave clocks) as well as IEEE 1588 servo and stack software, development tools and board support packages (BSPs) for a wide range of applications spanning small cells, optical transport, smart grid, automotive and 5G wireless infrastructure.
Automotive manufacturers across the globe are announcing aggressive plans to launch new models of battery electric vehicles (BEVs), plug-in hybrid electric vehicles (PHEVs) and full-hybrid electric vehicles (FHEV). As automotive designs move to electrification, high-wattage power electronics become critical components in the drivetrain and battery systems. These high-wattage electronics need to be communicated with and controlled by low-voltage digital controllers requiring electrical isolation of the low-voltage side from the high-power system. In these applications, galvanic isolation is required to allow the digital controllers to safely interface with the high-voltage systems of a modern EV.
Electric Vehicle System Overview
EV/HEV battery management systems typically include four major circuit assemblies:
Battery Management System Overview
The BMS manages stored power in a non-board high voltage (HV) battery and delivers power to the rest of the vehicle. The main functions include cell balancing, cell health and wear leveling, charge and discharge monitoring, and safety assurance. These functions require galvanic isolation to separate lower voltage systems from high voltage domain in the following ways:
DC-DC Converter Overview
DC-DC converters are used to convert DC voltages from one voltage domain to another for powering various auxiliary systems. Isolation products have numerous uses inside DC-DC converters in the electrical domains of EV or HEV. These functions require galvanic isolation to separate control systems from high-voltage domains in the following areas:
On-Board Chargers Overview
The OBC converts AC power from an external charging source into a DC voltage that is used to charge the battery pack in the vehicle. In addition, the OBC performs other functions including charge rate monitoring and protection.
In the OBC system, isolated gate drivers are used to chop the input signal into a switched square wave to drive a transformer to create the required output DC voltage. This output voltage can be monitored to provide closed-loop feedback to the system controller using isolated analogy sensors. Furthermore, the entire system can be monitored and controlled via an isolated CAN bus with digital isolators with and without integrated DC/DC power converters.
Traction Inverter Overview:
Traction inverters are used to convert stored DC high voltage from a battery or DC bus link into multi-phase AC power for driving a traction motor. Isolation products have numerous uses inside traction inverters in the drive train of EV or HEV through the following:
Silicon Labs Solutions:
The race to electrify automotive fleets is accelerating with more vehicles arriving from more manufacturers every year. Semiconductor-based isolation offers significant advantages over legacy optocoupler solutions, which make them an ideal choice in demanding EV applications.
Silicon Labs offers a broad portfolio with a rich variety of digital isolators, isolated gate drivers, and current sensors. With robust qualification, support, and excellent technical performance, learn more about how you can fit Silicon Labs’ product offerings in your design solutions in this Quick Reference Guide.
High-performance FPGAs play a key role in numerous applications including data centers, broadcast imaging, and industrial control. Unlike earlier generations, using high-performance FPGAs presents new design challenges. Rather than using simple integer clock multiplication of reference inputs or clock generation, high-end FPGAs require multiple non-integer-related frequencies to generate any output frequency without sacrificing jitter performance. To achieve this, a new clock reference architecture is required.
Traditional Clock Reference Architecture
Implementing a complex clock tree while still meeting severe space restrictions and a compressed time-to-market requires a new approach to clock generator design. The traditional architecture is based around a simple loop that generates a voltage-controlled oscillator output at a multiple of the desired frequency. In this architecture, the output clock frequency is a function of the input clock frequency and the PLL divider values. This model is suitable for simple integer clock multiplication of reference inputs or clock generation from a crystal input.
Solving the High-Performance FPGA Challenge
On the other hand, high-end FPGAs require multiple non-integer-related frequencies. The designer must use one or more custom crystals and multiple clock generator ICs to generate the required set of frequencies, increasing the cost, complexity and power consumption of the overall solution. Silicon Labs’ patented MultiSynth™ fractional divider architecture solves this problem. The MultiSynth architecture switches seamlessly to produce the exact output clock frequency with zero ppm error. This technique makes it possible to generate any output clock frequency without sacrificing jitter performance.
A comparison of (a) the traditional PLL and (b) the MultiSynth clock generation architectures
Integrated LDOs Reduce Noise and Improve Performance
In addition to the MultiSynth architecture, clock generators include multiple features that contribute to low jitter and save system cost. For example, noise on the power supply is a significant problem in high-performance clock devices. It affects the performance in two ways:
Power supplies based on switching topologies are the preferred choice in high-current, low-voltage designs because they are highly efficient. Unfortunately, they also generate significant noise, so FPGA system designers must add low-noise low-dropout (LDO) linear regulators, ferrite beads, and numerous filter capacitors to remove power-supply noise before it reaches the clock generator. This adds significant cost and increases the board size. However, Silicon Labs devices include multiple LDOs on the chip to largely eliminate the need for these external components.
Silicon Labs Solutions
In conjunction with the timing solutions products, Silicon Labs offers several software tools that help customers develop quick-turn, customized solutions. ClockBuilder Pro (CBPro) is a software tool that simplifies the task of getting from a clock-tree specification to an orderable part. The tool uses a step-by-step GUI format that includes more than 175 clock design rules to reduce design and debug time. The CBPro software package is freely available for download, and with the tool, designers can now develop an optimum solution and quickly evaluate sample parts. Other software tools include a Phase Noise to Jitter Calculator that helps translate FPGA phase noise specifications into jitter requirements.
Silicon Labs timing solutions are widely used in several FPGA reference designs. These evaluation and development kits enables quick customer adoption and accelerate time-to-market. Visit our clock and oscillator reference designs to get started.
To learn more about how Silicon Labs’ portfolio of clock generators can help meet your FPGA design requirements, read the full whitepaper.