Silicon Labs has decided to withdraw from exhibiting at Embedded World 2020 as a precautionary measure in response to the coronavirus (COVID-19) situation. We are closely monitoring the evolving situation and following the guidance of leading health and government authorities.

We share the concerns of the global community as the coronavirus is affecting the daily lives of many people around the world. Our highest priority is the health and safety of our employees and their families, as well as customers, partners and other stakeholders.

We thank the NürnbergMesse GmbH for understanding this difficult decision.

Today we announced an exciting new expansion to our Zigbee portfolio: EFR32MG22. Designed for eco-friendly IoT products deployed in mesh networks, MG22 is the smallest, lowest power Zigbee SoC on the market today. Based on our award-winning Wireless Gecko Series 2 platform, MG22 SoCs are an ideal choice for a wide variety of applications including smart home sensors, lighting controls and building and industrial automation.

Optimized for Zigbee Green Power energy harvesting applications, MG22 SoCs provide a best-in-class connectivity solution for challenging, power-sensitive wireless applications. Zigbee Green Power technology can help address environmental concerns by reducing residential, commercial and industrial energy footprints, one IoT device at a time. To learn more about Zigbee Green Power, click here.

As a founding member of Zigbee Alliance, Silicon Labs has decades of experience in Zigbee technology and the largest number of Zigbee SoCs and modules deployed. For more information about our new MG22 SoCs, click here.

We’re joining forces with Rainus, Zliide and Quuppa at EuroShop, the industry’s leading retail trade fair, to demonstrate an asset tracking solution using Bluetooth® angle of arrival (AoA) technology for micro-location of merchandise on the retail floor. The companies’ joint demo is located in the Rainus Booth A15 in Hall 7 at EuroShop, February 16-20, 2020, in Düsseldorf, Germany.

The demo showcases sub-1-meter indoor asset tracking with Bluetooth Low Energy and combines the following technologies:

• Silicon Labs’ low-power, small-footprint Bluetooth SoCs and software
• Rainus’s electronic shelf labels (ESL) for remote and dynamic pricing management
• Zliide’s asset tag – an intelligent version of the classic loss prevention tag – for a seamless buying experience
• Quuppa locators and position engine for tracking ESLs and smart tags attached to merchandise, enabling a fully integrated omnichannel shopping experience.

Omnichannel strategies define the ability of retailer or consumer brands to collect consumer data, drive customer loyalty and improve customer retention. To create a seamless customer experience across all channels, retail infrastructure requires a connected environment to provide consistent pricing across channels, promotional offers, personalized communications and cross-channel inventory visibility.

According to Retail TouchPoints®, 87 percent of retailers report that creating a seamless customer experience across all channels is the most important business goal of their company’s omnichannel strategy.

“We are excited to see a rapidly increasing interest in developing various Bluetooth direction finding-based applications and services for the retail sector, improving the omnichannel shopping experience,” said Fabio Belloni, chief customer officer and co-founder of Quuppa.

“Efficient collection of customer insight data and complementary relationships among different sales channels are the paramount challenges for today’s retail industry,” said Morten Møgelmose, CEO and co-founder of Zliide. “By creating the world’s first intelligent security tag that can communicate with the customers’ mobile devices, Zliide aims to provide fashion retailers with a tool for effortless data collection while allowing their customers to smoothly transition between channels.”

“According to Gartner, 65 percent of enterprises will require indoor location asset tracking by 2022,” said Ross Sabolcik, vice president and general manager of IoT commercial and industrial products at Silicon Labs. “As the first wireless SoC supplier to support Bluetooth direction finding, we offer optimized Bluetooth silicon, software and development tools to help our customers design low-cost, low-power products to fuel the market with smart traceable products for the growing location positioning ecosystem.”

For more information about our Bluetooth direction finding silicon, software and development tools, visit silabs.com/bluetooth-direction-finding.

The smart home is the new rising standard for a “home sweet home.” With increasing connectivity of home appliances and devices, IoT technology has enabled the smart home ecosystem to expand based on consumer demand for interoperability. At CES 2020, Matt Johnson, our SVP & GM IoT Products, spoke in an interview with EETimes about the exciting future of the smart home and shared his predictions on industry growth over the next decade.

 

As Matt stated in the interview, one of the major challenges to the growth of the smart home market is interoperability. Developers are expected to move quickly across competing industry standards, while consumers demand smart home devices that work seamlessly with the ones they currently use.

Project Connected Home over IP and Z-Wave Alliance have recently announced plans to make smart home technology more compatible, enabling technology access for developers, better consumer experience and faster industry growth. We also recently launched EFRBG22, a secure Bluetooth 5.2 SoC delivering industry-leading energy efficiency that can extend battery life beyond five years, allowing for highly accurate motion tracking that can be used in a variety of home applications. These technologies help fulfill the needs of consumers and enable connected intelligence to function in a faster, safer and more cost-effective way.  

As IoT expands the smart home market, consumer dreams of a smart, connected home are becoming a reality. Despite challenges in a fragmented market, issues in interoperability, and slow adoption, Silicon Labs helped jumpstart the movement of homes embracing connectivity. We are excited to host the "Works With" Smart Home Conference in Austin, Sept 9-11, bringing smart home designers and developers interested in creating products that work with the world's largest smart home ecosystems. To learn more and sign up, click here. Use code WWSH to receive a discount off registration.

To watch Matt’s full interview with EETimes, click here.

First published 5.31.2016

There’s no denying the role connectivity plays in regards to devices and how efficiently they communicate information. While wireless capabilities continue to make headlines, there’s still a great deal of value in wired specifications, first and foremost with USB connections.

USB connectors are easy to confuse. They’ve come in many shapes and sizes over the years beginning with Mini, Micro, Type-A, Type-B and now Type-C. For reference, a USB type simply refers to the shape of the ports and plugs while the version, such as 1.1, 2.0, or the current USB 3.1, usually denotes speed. The Type-A connector connects into a host, such as a laptop, while the Type-B connector plugs into a peripheral device. Type-A is always the flat and wide connector shown in the figure below while Type-B can show up in many different shapes due to the differences in devices it connects into.

USB Type-C was first introduced in 2014, implemented to some degree in 2015 (more notably on Macbooks), and is increasingly becoming a standard for many devices in 2016. It’s being called “a leap forward” in connectivity and for good reason.

USB Type-C separates itself from its predecessors because it:

• Can send or deliver up to 100W of power to charge a high-current device
• Supports USB 3.1 with data transfer speeds of up to 10 Gbps
• Will support up to two 4K displays at a 60Hz refresh rate
• Maintains backwards compatibility with USB 2.0
• Has reversible connectors so it does not matter which end is used and in what direction
• Cuts down on waste by eliminating the need for multiple connectors

Though it can handle a wide variety of tasks that previously took multiple cables, Type-C’s versatility comes at a cost because USB’s once-simple inner workings of cables, ports, dongles, and hubs have been replaced by more complex embedded components. There are two main complications that arise when developing Type-C solutions. The first relates to power distribution. A Type-C connector can send or receive up to 100W of power, but this can be a problem for devices that don’t require that much power.

The second common roadblock when developing a Type-C solution deals with the potential for communication failures due to the increase in supported communication standards. Since communication between hosts and devices requires detecting and processing digital and analog signals, an embedded MCU is required. Silicon Labs can alleviate these issues through the creation of it’s new MCU, which integrates more functionalities in a package as small as 3X3 mm².

Although it’s clear USB Type-C represents a new wave of enhanced connectivity, it unfortunately can cause problems for developers and designers. To learn more about how we’re simplifying Type-C development, download this whitepaper.

We’ve also released a comprehensive reference design featuring cost-effective, ultra-low-power EFM8 microcontrollers (MCUs), USB Power Delivery (PD) protocol stacks certified by the USB Implementation Forum (USB-IF), and USB Billboard Device source code.

Our reference design provides a complete solution for a USB Type-C to DisplayPort (DP) adapter, making it easy to communicate with legacy products that do not support USB-C. Available to qualified developers at no charge, the reference design includes schematics, software libraries and stacks, source code, code examples and access to Simplicity Studio™ development tools, enabling developers to design USB-C cables and adapters quickly, easily and at minimal cost.

Get all the details about the USB Type-C reference design including software stacks, schematics, documentation, tools, and EFM8 MCU information at www.silabs.com/usb-type-c.

Introduction

In the last Timing 201 post, I discussed the parasitic Phase-Locked Loop (PLL) in which an independent oscillator can couple energy in to a PLL’s VCO so as to influence or even take over the PLL’s output frequency and phase. I then reviewed some basic injection theory, including the concept of injection lock range.

Given the amount of material I would like to cover, I am going to follow-up that post with two more articles.  This installment, Part 2, will discuss how to minimize injection sensitivity generally. Part 3, to come later, will cover the topic of measuring injection sensitivity.  

A Brief Review

Per the last article, injection pulling or locking refers to when one independent oscillator disturbs or locks the frequency and phase of another independent near-synchronous oscillator. We then reviewed injection theory after Wolaver (1991) culminating in this equation with the important take-aways noted.

ILBW (Injection Lock Bandwidth)

Wolaver treated the injection constant or gain KINJ as the injection lock range. It is useful to regard this lock range as the Injection Lock Bandwidth (ILBW) to contrast it with the PLL’s loop bandwidth (BW). From here on, I will use this nomenclature. The bottom line is that, in order to minimize the risk of injection locking, we want BW > ILBW.  Ideally, BW would be significantly greater than the PLL’s ILBW.

The factors in the formula suggest where we might run in to trouble. For example, LC tank oscillators, especially when integrated, have much lower Q compared to crystal oscillators. Further, the trend is for higher and higher frequency clocks. The resonant tank frequency itself is usually dictated by something on the order of 2 times the maximum 50% duty cycle output clock frequency we would like to support. So we should be on guard for this issue when considering narrow band (NB) and high frequency low-Q VCO tank circuit PLLs.

So why don’t we routinely run in to injection problems today? Well you still can, if you are rolling your own NB discrete synchronous PLLs and especially if you co-locate them. This article series is in part an attempt to warn you of some possible concerns.

Board and IC designers have learned over the years to adopt injection resistant practices and PLL topologies. First, let’s begin by considering some typical injection mechanisms. 

Injection Mechanisms

There are several common injection mechanisms in which aggressor oscillator noise may couple in to a tank oscillator circuit. The first two listed are suggested by the figure below:

1. Power supply noise transmitted through the PCB or IC substrate
2. EM fields directly coupled in to the tank circuit
3. Conducted noise via board traces and IC pins

We can mitigate, or reduce the impact, of injection by directly addressing these injection mechanisms and/or by using more injection resistant system-level approaches.

Injection Mitigation via Good EMC Design

Injection can be regarded as a special topic within the field of EMC (Electromagnetic Compatibility). We can minimize injection noise power applied at the tank for each of these mechanisms using good practices for designers cognizant of general Electromagnetic Interference (EMI) issues.

1. Power supply noise through PCB or IC substrate

• Power supply bypassing or filtering

2. EM fields directly coupling to the tank circuit

• Employing separation and shielding

3. Conducted noise via board traces and IC pins

• Applying signal filtering and good PCB layout: planes, short traces, etc.

All of the above methods attack the problem by reducing the strength of the aggressor noise PINJ.  However, in addition to these direct approaches, there are some other more systemic ways of minimizing injection problems.

Injection Mitigation via Thoughtful Frequency Planning

You may recall that I mentioned the general problem of injection pulling and locking arises when working with signals and oscillators that are synchronous or nearly so. What do I mean by nearly-synchronous? A SONET application board with lots of clock I/O all running at or near SONET frequencies within a few ppm of each other is a classic example.

One approach, if you have multiple PLLs or clock devices co-located on the same printed circuit board, is to configure them so that the VCO frequencies are asynchronous from each other. For example, consider an application where you have two adjacent Si570 I2C-Programmable XOs on a PCB. You can minimize the risk of injection crosstalk (XTALK) by configuring the devices so that their internal DCOs or Digitally Controlled Oscillators are well off frequency from each other.

Consider the Si570 Detailed Block Diagram below taken from this datasheet.  In the diagram, HS_DIV refers to the DCO High Speed Divider with possible values [4-7, 9, 11].  N1 is the CLKOUT Output Divider with allowed values [1] and [2, 4, 6, …, 27].  Finally, the datasheet constrains the DCO frequency to 4.850 GHz £ fosc £ 5.67 GHz. Given these constraints, there can often be multiple frequency plan solutions that output the same clock frequency.

For example, the DCOs can be made significantly asynchronous even when the output clocks are identical in frequency. Here are two valid Si570 configurations that both yield f1 = 155.52 MHz outputs.

• fosc1 = f1 x HS_DIV x N1 = 155.52 MHz x 4 x 8 = 4.976640 GHz.
• fosc2 = f1 x HS_DIV x N1 = 155.52 MHz x 9 x 4 = 5.598720 GHz.

In this instance, each DCO frequency is asynchronous, greatly minimizing the risk of injection XTALK.

Injection Mitigation via Beneficial Clock Architectures

One architectural approach is to simply minimize the number of PLLs, and therefore VCOs, with associated tank circuits, that might be susceptible to injection XTALK.

An example clock generator that minimizes the number of PLLs is the Si5338 I2C-Programmable Any-Frequency, Any-Output Quad Clock Generator. The functional block diagram below is taken from the Si5338 datasheet.

The Si5338 design consists primarily of a single wideband PLL with a bandwidth typically 1.6 MHz, followed by 4 “MultiSynth” dividers which can support four independent output clocks. The MultiSynth dividers are Silicon Labs’ proprietary low jitter fractional dividers that incorporate phase error correction. This whitepaper discusses this approach. Please note that there are other lower jitter clock generators employing similar architectures, with more clock I/O, such as the Si5332.

A second injection resistant architectural approach is to embed the potentially susceptible VCO tank circuit in a wideband PLL. (Recall that we want BW > ILBW.) An example jitter attenuator device that improves injection rejection in this way is the Si5380 which uses a nested dual loop architecture as shown in the diagram below. This illustration is taken from the “Optimizing Clock Synthesis in Small Cells and Heterogeneous Networks” whitepaper.

In this topology, the LC tank circuit VCO is integrated in a wideband (fast) inner loop which itself acts as the DCO for a narrowband (slow) outer loop. Please note that the Si5380 has been superseded by the more flexible, higher performance Si5386.

References

The same references that applied to the previous Timing 201 post apply here. They are listed below, for convenience.

Some material covered here was presented at the Austin Conference on Integrated Systems and Circuits (ACISC) in 2009. If you are interested, email me to request a copy of the paper “Practical Issues Measuring and Minimizing Injection Pulling in Board-level Oscillator and PLL Applications” and accompanying slides.

As mentioned previously, the best practical overall book treatment of injection lock that I am familiar with is in Wolaver’s text:

• D.H. Wolaver, Phase-Locked Loop Circuit Design, 1991, Prentice-Hall, pp. 97-104. 

This is a slim volume for a PLL book but it punches well above its weight in terms of information.  

Here are several foundational papers worth reading on the topic of injection.

• R. Adler, “A Study of Locking Phenomena in Oscillators,” Proc. IRE and Waves and Electrons, vol. 34 (June 1946), pp. 351-357. 
• K. Kurokawa, "Injection Locking of Microwave Solid-State Oscillators," Proc, IEEE 61, 1386 (1973).
• B. Razavi, “A Study of Injection Pulling and Locking in Oscillators,” IEEE J. Solid-State Circuits, vol. 39, pp. 1415-1424, September 2004. 

If you have favorite references you would like to share, please pass them along to me.

Conclusion

To recap, there are a number of ways that IC, board, and system designers can reduce the risk of injection pulling or injection lock.

1. Good EMC Design
2. Thoughtful Frequency Planning
3. Beneficial Clock Architectures
   • Minimize the number of PLLs and therefore VCOs
   • Embed susceptible VCOs in a wideband PLL

Looking ahead, it turns out it is often not practical to straightforwardly calculate the ratio of PINJ/PT and therefore KINJ or ILBW. Next time I will review how one may measure ILBW in the lab.

I hope you have enjoyed this Timing 201 article. As always, if you have topic suggestions, or there are questions appropriate for this blog you would like answered, please send them to kevin.smith@silabs.com with the words “Timing 201” in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on.

Cheers,
Kevin