Official Blog of Silicon Labs

      • Ethernet’s Role in Hyperscale Computing

        Lance Looper | 02/36/2018 | 11:51 AM

        Significant investment is pouring into data centers as the enterprise market accelerates its increased use of cloud-based computing solutions and the demand for lower latency intensifies. Wireless networks are also experiencing tremendous change as networks move from 4G/LTE to LTE-Advanced and 5G systems.


        In a new whitepaper by James Wilson, Senior Marketing Director of Timing Products at Silicon Labs, details how data centers and wireless networks are equipping themselves to handle these enormous changes by adopting high-speed 100G Ethernet. Although a popular and cost-effective solution, the increased use of optical high-speed Ethernet is driving the need for high-performance clock and frequency control products in both wireless network and data center environments.  

        The new paper details why clock and frequency products are playing a crucial role in these two technological evolutions. For example, several specific technical obstacles have arisen within data centers as they use the Ethernet to support the rapid shift of enterprise workloads to cloud infrastructure. The majority of data center traffic stays within the data center as workload processing is distributed across multiple computer nodes, posing a serious problem to data centers. To clear this hurdle, data centers are starting to optimize their network architecture to support distributed, virtualized computing by connecting every switch to each other, otherwise known as hyperscale computing.

        The Ethernet is critical to making hyperscale possible as data center switches quickly move from 25G, to 50G, to 100G to expedite data transfer and network efficiency. This speedy migration is driving data center equipment manufacturers to upgrade switch and access ports to higher speeds, fueling the need for higher performance, lower jitter timing solutions. Ultra-low jitter clocks and oscillators are necessary in these applications because high clock noise can result in unacceptably high bit-error rates or lost traffic.

        As the paper details, mobile networks are also experiencing seismic change as operators prepare to support mobile data traffic expected to grow by 49 exabytes per month by 2021, a sevenfold increase since 2016. To meet the aggressive bandwidth demands, wireless networks are being re-architected and optimized for data transport with widescale adoption of high-speed Ethernet in radio access networks (RAN). The whitepaper lays out how the wireless industry is starting to re-envision base station architectures. Unlike the distributed model of 4G/LTE, where RF and baseband processing functions were split into separate remote radio heads (RRH) and base band units (BBU), the connection between baseband and radio elements, known as the fronthaul network, are being optimized for LTE-Advanced/5G networks.

        To ensure fronthaul networks can handle the new bandwidth constraints being placed on them with the proposed new architecture, numerous standards have developed. Highlighted in detail within the paper, the new fronthaul standards are driving the need for frequency flexible timing solutions that can support both LTE and Ethernet clocking in radio heads, small cells, and pico cells. These new solutions provide the opportunity for hardware designs to unify all clock synthesis into a single, small-form factor IC.

        For wireless infrastructure and data center architects, the paper is a must read. Providing readers with detailed architecture and IC illustrations, the article will give readers better perspective on effectively leveraging the Ethernet while maintaining flexible, accurate timing and synchronization – which ultimately, prevents the loss of traffic and/or data error in either environment.


        Read the full paper here.






      • Timing 101 #6: The Case of the Spurious Phase Noise Part I

        Lance Looper | 01/29/2018 | 11:19 AM

        Hello and welcome to another edition of the Timing 101 blog from Silicon Labs' Kevin Smith. It’s a new year and time for a new post!

        In this month’s article, I will discuss spurs in clock phase noise measurements. Most everyone in timing will recognize spurs as the distinctive spikes in the phase noise plot below. They are generally undesired and in the frequency synthesis business low level spurs are not uncommon. They are the foam on the beer as it were. This particular plot comes from an AWG or Arbitrary Waveform Generator configured for 100 MHz sinusoidal output with 1 MHz FM. I will be using this plot or similar versions of this data throughout this article.

        What is not always appreciated is their relative significance and how they should be displayed and accounted for in applications and troubleshooting. They can also be generated for device and system evaluation and characterization.

        In this first post, I will briefly review spurs and their distinctive characteristics. Next, I will discuss how to account for them when calculating total RMS phase jitter. Finally, I will sum up with my assessment of the relative merits of the three approaches to displaying spurs (or not) in phase noise plots. Looking ahead to part 2, I will discuss the usefulness of generating spurs on purpose for evaluation and testing.

        What are spurs?

        The technical term spur is short for spurious which comes from the Latin spurius meaning illegitimate or false. See for example the entry here. There is another more general use of the word spur which refers to a spike or protuberance as in cowboy spurs and the San Antonio Spurs. Coincidentally, both meanings are somewhat fitting in this context.

        Here spurs are carrier or clock frequency spectral imperfections measured in the frequency domain just like phase noise. However, unlike phase noise they are discrete frequency components. This gives these features several particular and interesting characteristics:

        1. Spurs are deterministic.
        2. Spur power is independent of bandwidth.
        3. Spurs contribute bounded peak jitter in the time domain.

        Let me expand a little bit on each of these characteristics in turn.

        Spurs are deterministic

        Spurs are generally undesirable and to be distinguished from the harmonics needed to constitute a square wave or trapezoidal wave clock. Their specific frequencies can aid us in determining their origins and relative importance. For example, they can be caused by systemic sources such as board power supply noise, crosstalk, mixing, modulation, PLL architecture, and power line harmonics.

        PLLs effectively sample the input clock, usually through a PFD (Phase Frequency Detector), and therefore must suppress update rate spurs. Further, PLLs that synthesize fractional output frequencies typically yield spurs due to fractional division.

        Spur power is independent of bandwidth

        This is true for discrete frequency components generally and can be observed directly on a spectrum analyzer. By contrast non-deterministic noise power is proportional to bandwidth. Consider the 2 side-by-side plots below displaying a 100 MHz sinusoidal carrier with +/- 100 kHz FM sidebands acting as spurs. The traces were averaged over 5 runs and the span was set to 300 kHz. The only difference between the 2 plots is the RBW or Resolution Bandwidth.

        In the left hand side plot the RBW = 6.25 kHz. In the right hand side plot the RBW = 291 Hz. You can see by the red line annotations that the peaks remain essentially the same magnitude while the noise level dropped going left to right. I “eyeballed” the noise to be about a 10 dB delta between the plots. We expect the noise to decrease narrowing the RBW from 6.25 kHz to 291 Hz by 10*log10(6.25 kHz/291 Hz) = 10*log10(16) = 12 dB which is reasonably close in this case. Note that the discrete frequency components get narrower also.



        Spurs contribute bounded peak jitter in the time domain.

        Each spur can be regarded as a phase modulation sideband to the carrier whose amplitude determines the peak phase deviation contribution. This useful feature can be exploited in testing and I will discuss this topic in the next post. By contrast, peak phase deviation is unbounded for random phase noise.

        Accounting for Spurs

        Phase noise in a phase noise plot is a power spectral density measurement displayed on a per Hertz basis, i.e. in units of dBc/Hz, and then integrated over a jitter bandwidth to yield an RMS phase jitter quantity. The units make sense since [dBc/Hz] x [Hz] = [dBc], a measure of the RMS phase jitter power with respect to the carrier. Statistical methods then have to be used to estimate the peak phase jitter over that same bandwidth. (Phase noise instruments do not actually measure the phase noise in 1 Hz increments but use a larger RBW depending on the offset frequency range.)

        The RMS jitter contribution for each spur can be calculated as follows. (See for example Silicon Labs app note AN256: Integrated Phase Noise.)

        L(f) here is taken to be the spur power in dBc at offset frequency f for carrier frequency f0. The proper way to account for spurs when calculating RMS jitter for both phase noise + spurs is to add each spur’s individual jitter power contribution in RSS (Root Sum Square) with the RMS phase jitter due to noise only.

        We can demonstrate this with an example.

        The left-hand plot below is a phase noise plot for the example nominal 100 MHz clock with spurs omitted. The right-hand plot is the same phase noise plot but with spurs identified and explicitly displayed in dBc. For this instrument, spurs in dBc are displayed in a different color than the phase noise. In the first case the RMS phase jitter measured between 12 kHz to 20 MHz was calculated as 668.837 fs. In the second case, the RMS phase jitter measured was recorded as 878.156 fs. This is an increase of about 209 fs or about a 31% increase.

        An interesting question is how spurs are identified in phase noise test equipment. This particular instrument defines a threshold in terms of how much higher a peak has to be than the standard deviation of the noise based on a moving average. The default spurious sensibility setting is 3 x standard deviation (sigma) which has proven to be a good practical value.

        To see why the spurs contributed this much additional jitter, note that there are 3 spurs shown in band, i.e. between 12 kHz and 20 MHz offset. In the table below I list the 3 spurs together with their individual RMS jitter contributions as calculated per the cited formula. The 1 MHz spur due to FM dominates. (The spur offset frequency location and amplitude came directly from the instrument’s spur list.)

        Now, let’s RSS all these values together:

        This is very close to the 878.156 fs reported by the instrument. You can go through a similar exercise, entering spurious data separately, using our online Phase Noise to Jitter Calculator.


        Displaying Spurs

        You may have noticed that the very first phase noise plot had spikes that looked different (shorter) than the plot with spurs in dBc above. Let's put the two figures together side-by-side. You can see now that the left-hand side plot has the spurs in the same color as the phase noise. The spurs in the left-hand plot are depicted in units of dBc/Hz. That is the instrument scales the spur down by normalizing them with respect to the RBW as follows:

        Spur peak [dBc/Hz] = Spur amplitude [dBc] – 10*log10 (RBW)

        In most instruments the RBW will vary from Hz to MHz, depending on the offset frequency range, usually on the order of 10% down to 1% of the offset frequency. The instrument may or may not explicitly provide the RBW. However, we can always deduce it.

        You will recall the largest spur at 1 MHz was displayed as -72 dBc in the right-hand plot. In the left-hand plot the same spur is depicted roughly speaking as a skinny triangle with the peak measuring about -117.5 dBc/Hz and a base that now extends slightly below and above 1 MHz offset. So we can calculate the RBW at 1 MHz offset as follows:



        You may wonder why the "spurs in dBc/Hz" view is useful. If all you care about is the impact of the RMS phase noise then this view helps puts things in proper perspective versus the non-spurious phase noise. In some cases, sales and field applications engineers may regard the right-hand style plot as unduly alarming though they contain approximately equivalent information.

        On the other hand, the right-hand style plot is more accurate and more useful for troubleshooting. Note that in this particular example, going left to right, the calculated RMS jitter differs increasing from 809.574 fs versus 878.156 fs respectively for an increase of about 8%. Further, it is very useful to know the dBc value of the spur directly without being concerned about the instrument's RBW at a particular offset frequency.

        The table above summarizes my assessment of the relative merits of the three approaches to displaying spurs. Your mileage may vary.



        This month I’ve discussed spurs in phase noise measurements. I hope you have enjoyed this Timing 101 article. This is only a brief introduction as entire books could be written just on this topic. I will return to this subject in The Case of the Spurious Phase Noise Part II next time to discuss generating and using spurs for testing.

        As always, if you have topic suggestions, or there are questions you would like answered, appropriate for this blog, please send them to with the words Timing 101 in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on.




      • Timing 101: The Case of the PLL’s VCO High Pass Transfer Function

        Lance Looper | 12/353/2017 | 12:04 PM

        Welcome to another edition of the Timing 101 blog from Silicon Labs' Kevin Smith.

        We have been doing some internal training recently and a common question that comes up is how and why a Phase Locked Loop (PLL) treats phase noise differently depending on whether it comes from the input clock or the VCO (Voltage Controlled Oscillator). Most everyone understands that input clock phase noise is jitter attenuated, i.e. the PLL acts like a low pass filter to input phase noise. However, it is not as readily apparent why a PLL should act like a high pass filter to VCO phase noise. This is the Case of the PLL’s VCO High Pass Transfer Function and the subject of this month’s post.

        First, I will review the basic feedback loop and its transfer function. Next, I will generalize the process for signals injected at different locations around the loop. I will then generate and compare the transfer functions for a PLL both from the input clock and the VCO perspective. Finally, I’ll wrap up by offering some intuition and discussing the application considerations.

        Feedback Review

        Consider the basic feedback diagram in the figure below where the variables and blocks are functions of the Laplace complex frequency variable ‘s’. The intermediate variable S representing  error should be considered likewise. The forward gain is G(s) and the feedback gain H(s). I(s) and O(s) are the input and output signals respectively.

        The closed loop transfer function TF for O(s)/I(s) is derived as follows.

        Now what happens if we break up the forward path gain G(s) in to two separate blocks, G1(s) and G2(s) and inject a new signal X(s) as illustrated below? X(s) is additive as with noise.


        By linearity, the transfer function TF for O(s)/x(s) is derived as follows where I(s) is set to 0.

        It turns out we can generalize for any X(s) injection point anywhere around the feedback loop as follows. The term “Loop Gain” refers to the multiplication of all the gain elements going around the closed loop. In this particular example, the Loop Gain = G1(s)*G2(s)*H(s).

        We can now apply these developments to the basic PLL.


        Input Clock Phase Noise Transfer Function

        Consider the basic linear “small signal” PLL diagram below.


        Going clockwise around the loop, the components in the diagram are as follows.

        • Kp represents the gain of the phase detector, usually a PFD (Phase Frequency Detector).
        • F(s) is the low pass filter as a function of complex frequency ‘s’.
        • Kv is the gain of the VCO and the 1/s term represents the integration action of the VCO. That is, the Laplace transform of the integral of Kv*phase is Kv/s.
        • 1/N is the gain of the feedback divider.

        We can now generate the TF for Theta_o(s)/ Theta_i(s) almost by inspection by noting that the forward gain is KpF(s)Kv/s and the loop gain is [KpF(s)Kv/s]/N.

        For reasons of stability F(s) is always a low pass filter so its value is either constant in value or rolls off with increasing frequency. In either case the overall closed loop behavior for the PLL is itself a low pass filter.

        This PLL transfer function is covered in many textbooks and articles but a more detailed and recent discussion on this topic is contained in the article “Phase Locked Loop Noise Transfer Functions” by Peter Delos published in High Frequency Electronics, January, 2016.


        VCO Phase Noise Transfer Function

        Now consider the basic PLL diagram modified below to also inject VCO phase noise via variable Theta_v(s).

         We can generate the TF for Theta_o(s)/ Theta_v(s) by noting that the forward gain from the VCO phase noise injection point is simply unity and the loop gain is [KpF(s)Kv/s]/N as before.

        Again, F(s) is a low pass filter so it is either constant in value or rolls off. Unlike the transfer function for the input clock, the numerator here has a zero at the origin. In this case the overall closed loop behavior for the PLL is now a high pass filter.

        Some Intuition

        OK, I know some of you may be saying, I get the math but I don’t really, intuitively, understand why the PLL acts as a high pass filter to VCO phase noise. Let me offer some food for thought that may provide some intuition.

        Consider the expected difference in behavior for a phase step at Theta_i versus Theta_v:

        • We know that a phase step at Theta_i is not immediately output at Theta_o. Rather, it will take some time, depending on the loop bandwidth, for the PLL to respond and properly step the output phase to track the change in the input clock’s phase. This is analogous to a voltage step applied to a low pass filter.
        • By contrast, a phase step at the output due to Theta_v must be immediately output at Theta_o. There is nothing to prevent this.  The loop then has to put things right in order to correctly track the input clock again. Depending on the loop bandwidth, it will take time for the output clock to lose the excess phase. This behavior is analogous to a voltage step applied to a high pass filter.

        Application Considerations

        The 2 dominant sources of phase noise in a PLL are typically the input clock and the VCO. As we have seen, the PLL treats each source's noise differently, i.e. as a low pass and a high pass filter respectively.

        The application consequences are as follows:

        1. If an input clock has relatively low phase noise versus the VCO, one typically uses a relatively wide bandwidth (BW) PLL in order to attenuate the VCO's phase noise. In this context, a wide bandwidth typically means something on the order of 100s of kHz to MHz. This is how clock generators or clock multipliers are designed. (Note that BW cannot be arbitrarily large for reasons related to stability and the need to suppress phase detector spurs.)

        2. On the other hand, if an input clock has relatively high phase noise versus the VCO, one typically uses a relatively narrow bandwidth PLL in order to attenuate the input clock's phase noise. In this context, a narrow bandwidth means something on the order of kHz or less, usually much less. This is how jitter attenuators are designed.

        Understanding this tradeoff and the ability to adjust the bandwidth "knob" is a key to troubleshooting PLLs and optimizing their application.



        This month I’ve reviewed how a PLL's VCO phase noise transfer function arises and its unique high pass behavior. I’ve also offered some intuition and discussed the application considerations.

        I hope you have enjoyed this Timing 101 article. It’s the last post for 2017. Happy Holidays and

        Happy New Year to all of you!

        As always, if you have topic suggestions, or there are questions you would like answered, appropriate for this blog, please send them to with the words Timing 101 in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading.

        Keep calm and clock on.




      • Timing 101: The Case of the Jitterier Divided-Down Clock

        kgsmith | 10/296/2017 | 12:47 PM

        Hello and welcome to the “Clocktoberfest” edition of the Timing 101 blog from Silicon Labs.


        Nice weather is starting to arrive here in central Texas. By late September and October we get hints of cooler and less humid days to come. Those of us of German descent, and plenty who are not, may celebrate Oktoberfest or some local variant such as Wurstfest in nearby New Braunfels. So “Happy Clocktoberfest!” from the Timing group.


        This month I am going to discuss a very common question that arises when measuring the phase noise and phase jitter of relatively low clock frequencies. All things being equal, we generally expect divided-down lower frequency clocks to yield lower phase noise than higher frequency clocks. Quantitatively, you may recall this as the 20log(N) rule.


        However, the 20log(N) rule only applies to phase noise and not integrated phase noise or phase jitter. Phase jitter should generally measure about the same. Further, as we get low enough in frequency we do not find this relation to hold true in actual measurements. So the question this month is - why is that?


        The 20log(N) Rule

        First, a quick review of the 20log(N) rule for those who may not be familiar with it:

        If the carrier frequency of a clock is divided down by a factor of N then we expect the phase noise to decrease by 20log(N). For example, every division by a factor 2 should result in a decrease of phase noise by 20log(2) or about 6 dB.  The primary assumption here is a noiseless conventional digital divider.


        Why is this? The output of a practical digital divider is rising and falling edges with the signal at a logic high or low level otherwise. Jitter is presented at the rising and falling edges only. The proportion of jitteriness to each clock cycle is reduced. Our intuition may suggest that if we reduce the number of jittery edges then we reduce the jitter transmitted by the divided down clock. That turns out to be correct.


        Formally, this can be written as follows:





        What About Phase Jitter?

        We integrate SSB phase noise L(f) [dBc/Hz] to obtain rms phase jitter in seconds as follows for “brick wall” integration from f1 to f2 offset frequencies in Hz and where f0 is the carrier or clock frequency.

        phase jitter.png


        In practice the quantities involved are small enough for good clocks that the RMS phase jitter, for a 12 kHz to 20 MHz jitter bandwidth, is on the order of 10s to 100s of femtoseconds.


        Note that the rms phase jitter in seconds is inversely proportional to f0. When frequency is divided down, the phase noise, L(f), goes down by a factor of 20log(N). However, since the frequency goes down by N also, the phase jitter expressed in units of time is constant. Therefore, phase noise curves, related by 20log(N), with the same phase noise shape over the jitter bandwidth, are expected to yield the same phase jitter in seconds.


        An Example

        Let’s look at a specific example. As an experiment, I took an Si5345 jitter attenuator, input a 25 MHz clock, and configured it so that I only changed an (internal) output divider by factors of 2 to obtain frequencies running from 800 MHz down to 50 MHz. I then measured the phase noise using an Agilent (now Keysight) E5052B and compared the phase noise and phase jitter for each case. Five runs were averaged and correlated for each frequency. I omitted any spurs for clarity and to simplify the experiment.


        Through the magic of MS Paint and use of the “Transparent Selection” feature I am able to overlay all of the E5052B screen caps as follows. (If the runs are identical each time only unique text is obscured.) In the figure below, the traces generally run top to bottom in descending carrier frequency, i.e. 800 MHz, then 400 MHz, etc. on down to 50 MHz. The shapes of the curves are the same except where the curves are compressed at the highest offset frequencies.



        I then tabulated the measured phase jitter results over the 12 kHz to 20 MHz jitter bandwidth as follows:


        Timing Table.png


        There are two immediate observations we can make from the overlaid plots and the table.


        1. The separation between the curves is close to what we would expect applying the 20log(N) rule until the traces begin to appear compressed toward the 100s of kHz to MHz offset


        1. The RMS phase jitter in fs is approximately the same for 800 MHz down to 200 MHz. However, for the 100 MHz and 50 MHz cases the expected phase jitter is way


        Despite the 20log(N) rule, the phase jitter is getting worse as I decrease the output clock frequency, especially below 200 MHz. These lower frequency clocks measure far jitterier than expected. Thus arises the case of the jitterier divided-down clock.  So what’s going on?


        Curve compression due to the apparent phase noise floor appears responsible for the differences in the calculated RMS phase jitter. Let’s verify that by comparing the data from 10 kHz to 20 MHz offset for the 800 MHz and 100 MHz cases. All of the spot phase noise data came from the original markers plotted except for the 20 MHz points which were estimated from the screen cap plots. (Note that for a factor of 8 or 23 we would expect a delta of 3 x 6 dB or 18 dB in phase noise.)



        Taking just these values and entering them in to the Silicon Labs online Phase Noise to Jitter Calculator we obtain the following.


        Table 3.png


        Not too shabby for the online calculator considering it only had 5 data points to work with!


        Now let’s modify the 100 MHz dataset to remove the higher offset frequency compression as follows. The 18 dB Δ is as would be otherwise expected applying the 20log(N) rule.




        Entering the modified values in to the online calculator we add its calculation to the table as highlighted:




        This exercise confirms that the curve compression accounts for the significant difference in phase jitter

        measured between the 800 MHz and 100 MHz cases.


        The Noise Floor

        All of the traces flatten or get close to flattening by 20 MHz offset. So, what is the apparent or effective noise floor? Note that in general this will be some RSS (Root Sum Square) combination of the instrument phase noise floor and the DUT’s far offset phase noise. For example, if both the DUT and the instrument had an effective phase noise of –153 dBc/Hz at 20 MHz offset then the RSS result would be 3 dB higher or –150 dBc/Hz.


        If the instrument noise floor was well below the DUT's we would expect the spot phase noise at 20 MHz offset to decrease by 6 dB, for every division by a factor of 2, from that measured for the 800 MHz clock. But that is not what happened. See the table and accompanying figure below:


        Table 6.png


        Phase Noise.png


        The phase noise floor is not varying monotonically which suggest multiple factors may be involved. Reviewing the E5052B specs indicates that the SSB phase noise sensitivity should decrease slightly as the carrier frequency is lowered. Also, far offset phase noise from the DUT (Device Under Test) is typically dominated by the output driver’s phase noise and that’s unlikely to vary in this way. We are most likely running in to a combination of the instrument's "actual" phase noise floor as a function of input frequency plus aliasing on the part of the DUT. The Si5345's frequency divider edges can be regarded as sampling the phase noise of the internal clock presented to the divider. This factor is independent of the instrument. It is understood that aliasing can occur but quantifying the specific contribution due to aliasing can be problematic.




        This paper suggests that provided the noise BW of the input signal is > 4 x divider output frequency v0 then divided PM (Phase Modulation) noise will degrade via aliasing by 10log[(BW/2v0) +1]. The aliasing described primarily impacts the far offsets where we are interested.


        The authors write:

        "Aliasing of the broadband noise generally has a much smaller effect on the close-to-carrier noise

        because it is typically many orders of magnitude higher than the wideband noise."


        In these particular measurements, estimated noise floor degradation for the lowest carrier frequencies are plausible assuming a given BW and instrument noise floor. However, no one solution appears to accommodate all the data. It might require operating the device at the highest output frequency and then employing external dividers and filters to properly sort this out. Perhaps in some future post.


        Additional Reading

        While this month's post has concentrated on phase noise, it should be noted that divided spurs can be aliased or folded in the same way as the authors cited above discuss. One of my colleagues has demonstrated this also and I recommend his article for further reading.



        We have reviewed the impact that a phase noise instrument’s apparent or effective phase noise floor can have on both the phase noise curve and phase jitter measurement of sufficiently low frequency clocks. After you have worked with your DUTs and phase noise equipment for some time you will recognize what a typical phase noise curve will look like, the approximate phase noise floor of the equipment, and what are reasonable expectations for phase jitter. Certainly, for the cases above, we would take have to take phase jitter measurements below 200 MHz with a grain of salt. If in doubt, try a similar configuration at a higher frequency for comparison. You will only miss the secondary phase noise degradation due to any instrument noise floor variation and/or aliasing due to higher division factors.


        As always, if you have topic suggestions, or there are questions you would like answered, appropriate for this blog, please send them to with the words Timing 101 in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on.




        1. The derivation here is adapted from a slim but information packed book by Dr. William “Bill” Egan

        called Frequency Synthesis by Phase Lock published in 1981. See section 4.5, “Effect of Modulation

        of a Divided Signal”, pages 75-76. (There is a later and much expanded edition of this book.) Dr. Egan

        has passed on but he was a great engineer, author, and teacher in Silicon Valley. He wrote several

        excellent, clear, and precise books on frequency synthesis, PLLs, and RF systems design.


        2. A. SenGupta and F.L. Walls, “Effect of Aliasing on Spurs and PM Noise in Frequency Dividers”, 2000

        IEEE/EIA International Frequency Control Symposium and Exhibition, pages 541 – 548.

        Retrieved from


        3. H. Mitchell, "Perfect Timing: performing clock division with jitter and phase noise measurements", EE

        Times, 8/25/2011. Howell's paper covers this topic from a different perspective with some additional

        detail using data from the previous generation Si5324. He also demonstrates spur aliasing by mixing the

        outputs of separate RF signal generators. Retrieved from

      • Delivering the Industry’s Best Jitter Performance and Power Efficiency on a Single Chip

        Lance Looper | 09/270/2017 | 10:00 AM

        This week we’ve released the new Si522xx PCIe clock generators, bringing best-in-industry jitter performance and energy efficiency to PCI Express® (PCIe®) Gen1/2/3/4 applications. This new clock family delivers on the stringent requirements of PCIe Gen 4 and Separate Reference Independent Spread (SRIS) standards with 20 percent jitter margin to spare, and its jitter performance (0.4 ps RMS) also provides up to 60 percent jitter margin for PCIe Gen 3.


        The PCIe standard, originally developed as a serial interconnect for desktop PCs, and has become popular in blade servers, storage equipment, embedded computing, IP gateways, industrial systems, and consumer electronics. High-output clock generators like the Si522x family reduce the number of buffers needed as data bus usage expands in these types of systems. Designed specifically for clock-distribution-intensive applications, the Si522x family supports up to 12 outputs from a single device. This higher output count per device reduces BOM cost. The clocks’ output drivers take advantage of our innovative push-pull HCSL technology, eliminating external resistors required by conventional constant-current output drivers.


        Additionally, internal power filtering prevents power supply noise from affecting jitter performance while reducing component count, saving about 30 percent of board space compared to competing solutions.


        Developers designing battery-powered applications like digital cameras are especially concerned about power consumption. The 2-output Si52202 clock is optimized for low-power 1.5 V to 1.8 V applications, offering the lowest power consumption for PCIe applications. Packaged in a small 3 mm x 3 mm 20-pin QFN, the clock is also 45 percent smaller than competing solutions.


        For more information, visit




      • Timing 101: The Case of the Ouroboros Clock

        kgsmith | 09/264/2017 | 10:00 AM

        Hello and welcome to another Timing 101 blog article.  


        In this post, I will go over an interesting and curious clock chip feedback arrangement that comes up from time to time. It can arise accidentally, or as an attempted recovery or test mode, but should generally be avoided as explained. Further, understanding the Ouroboros clock might help explain some odd behavior in a complicated timing application. Before diving in to exactly what I mean by an "Ouroboros" clock, let's review some basic clock switching terminology and the standard input clock switching configuration.


        Some Basic Clock Switching Terminology

        Clock chips often support switching from one input clock to another based on some qualifying criteria such as LOS (Loss of Signal) or an OOF (Out of Frequency) condition. Here’s the terminology most often used:


        Freerun Mode:

        Output clock based on an

        attached crystal, or other resonator, or substitute external reference clock. The output clock's frequency stability, wander, and jitter characteristics are determined by the chip's crystal oscillator for example, independent of an input clock.


        Holdover Mode:

        Output clock based on historical frequency data of a selected input clock and employed when the input clock is lost and no valid alternate is available.  Usually historical data must be collected over some minimum time window to be considered valid. The frequency accuracy is only as good as the data collected.


        Locked Mode:

        Output clock frequency and phase locked to a selected input clock, i.e. normal operation.


        The Standard Input Clock Switching Configuration

        Consider the illustration in the figure below where two jitter attenuator clock ICs are cascaded. This could be for additional jitter attenuation or for optimizing frequency plans and distribution. For the purposes of illustration, the devices are depicted as very simplified Si5345 block diagrams. In this figure there are two input clocks supplied to Device #1, IN0 and IN3. In typical applications one clock may be regarded as the "primary" clock and the other as the "secondary" or backup clock. The primary clock might be recovered from network data while the secondary clock relies on a local oscillator. If the primary clock fails or is disqualified by LOS or OOF, then the clock chip switches to the secondary clock. This is usually intended to keep "downstream" devices up and running.  If the primary clock returns and is valid then the clock IC may revert to it, or not, depending on the option selected.


        The presumption here is that as long as either of these two clocks is present then a valid locked mode clock will be yielded at OUT0 supplying an input clock to downstream Device #2.  In fact, if both input clocks to Device #1 were lost the device could go in to holdover mode, as described above, or even freerun mode, and still yield a temporary reasonable output clock.


        Clock Config.png



        The Ouroboros Clock Configuration  

        In standard applications, downstream clocks are not fed back to upstream clock inputs. Rather they are usually scaled or jitter attenuated versions of upstream independent stable or data-derived clocks.  


        But what if we did attempt the configuration shown in Figure 2 below?  In this case, one of the outputs of downstream Device #2 is being fed back in to upstream Device #1. This might be intended as a temporary expedient backup clock.




        Now what happens when we lose our primary clock IN0 as suggested by Figure 3 below? The secondary or backup clock IN3 to Device #1 relies on the output of Device #2. Note that this is just a locked version of Device #1's output.  We generally do not do see this sort of connection with one device but it is proposed occasionally with applications involving 2 devices. Even then, engineers will usually intuit that we are trying to get away with something.


        Clock Congif with Arrows.png


        This is the Ouroboros clock configuration. (And yes, it does sound almost like a Big Bang Theory episode title.) The Ouroborus clock configuration is so named because its feedback resembles the mythological symbol for a snake chasing (or biting) its tail.  According to the Wiktionary entry the word comes from the Greek words ourá for "tail" and bóros, for "devouring or swallowing".  See the illustration below in Figure 4. It is an ancient symbol for cyclic infinity and the term fits this application.


        Ouroboros Snake copy.png


        A Gedanken

        Let’s consider a simplified gedanken or thought experiment consisting of a single basic PLL.  Then assume that it has successfully been placed in to the Ouroboros configuration as follows in Figure 5 below.




        Now we can think through the probable consequences. If everything is ideal and there is no PFD (Phase Frequency Detector) error output then the situation is at least marginally stable. However, even ignoring loop noise, it is most likely in a practical PLL that there is a fixed phase offset between the clocks presented at PFD (+) and PFD (-). In normal PLL operation the VCO can be adjusted so as to frequency and phase lock the output clock to the independent input clock. In the Ouroboros configuration, there is nothing the VCO can do to reduce phase error.


        Assume the output clock is measured with phase just a little bit faster, at PFD (+) versus PFD (-). The loop will then attempt to track for that by tuning the VCO to a higher frequency. But a relative phase difference will still be present. So, the loop will continue attempting to correct for the measured phase error until the VCO is “railed” at its highest frequency.  Note that, to generalize, the VCO could be tuned either higher or lower in frequency depending on the polarity of the phase difference. All that matters is that a phase delta be seen by the PFD that leads to a runaway condition.


        Trying to accomplish this with two Si5345s is just this problem writ large, albeit with further complications due to clock validation and switching logic. In addition there will always be slight part to part variations in output frequency and calculated HO frequency. These can also drive the PFD in one direction or another where 2 separate devices are involved.


        Lab Confirmation

        So, what really happens in the lab? Consider a project plan with these attributes:

        • IN0: 100 MHz
        • IN1: 100 MHz
        • OUT0: 100 MHz
        • Nominal Bandwidth: 100.000 Hz
        • Fastlock Enable Off
        • Ramped Exit from Holdover
        • OOF IN0 and IN1:
          • Assertion Threshold 100 ppm         
          • De-assertion Threshold   98 ppm


        Now take such a project plan and apply it to 2 Si5345 evaluation boards, configured as shown in the second figure above, except using IN1 instead of IN3 as the secondary or backup input clock. 


        Apply a signal generator to Device #1 IN0 and let both boards run until HOLD_HIST_VALID is true.  What happens when you remove the 100 MHz input clock at IN0?


        Initially only LOS[0] is reported by Device #1. Otherwise all is well. However, the output clock frequency from Device #2 starts ramping in frequency (it can be ramping up or down in general but happened to be ramping up in my particular experiment.)


        Eventually the output clock from Device #2 being used as the backup input clock goes far enough out of frequency that it fails Device #1’s OOF criterion. The settled conditions are as follows:


        • Device #1 goes in to holdover mode
        • Device #2 operates in locked mode.


        Note that in general there is no reason why the devices could not be stable with each in the opposite states. Our experience has been that most of the time there is a preferred set of states but you will see the alternate set from time to time, almost as if there is a chaotic element to the results.


        In this case, the Ouroboros configuration didn’t really buy us anything except perhaps a little time.  However, note that the output frequency was ramping the entire time until Device #1’s OOF[1] asserted and Device #2 still ends up relying on Device #1 HO clock. That’s just one potential issue for this impractical configuration. But there’s another potentially worse effect.


        Ouroboros Oscillation

        This configuration can also result in a positive feedback system that can be made to oscillate, leading to puzzling and odd behavior.  In particular, this can happen if one of the devices can be made to enter and exit HO.  For example, this phenomenon can be observed if the project plan OOF specs are tightened as follows.


        • OOF IN0 and IN1:
          • Assertion Threshold 000 ppm      
          • De-assertion Threshold 9375 ppm


        Now the two devices will interact with each other and may never settle. Below is an annotated frequency plot of Device #2 output clock data from a logging frequency recorder. You can see that the Device #2 output frequency is slowly oscillating frequency-wise with a varying period on the order of 8 or 9 seconds.


        Frequency vs Time copy.png


        There are three features noted on the plot above about the state of Device #1 as Device #2's output frequency varies:

        1. Device #1 is in holdover or HO mode
        2. Device #1 is in ramped exit from HO
        3. Device #1 is entering in to HO

        During this time period no alarms are issued by Device #2. This state can last indefinitely. I started one trial of this experiment on a Friday afternoon and it was still cycling on Monday morning.  The devices can even exchange roles as to which one is in the HO state!

        Having a device constantly entering and exiting HO is even worse than simply going straight in to HO.



        The bottom line is that the Ouroboros clock configuration either does nothing useful except delay entering HO or can even trigger an oscillation which produces repetitive wander in the output clock. Downstream clocks should generally stay downstream.


        I hope you have enjoyed this Timing 101 article and will understand the implications if you spot an Ouroboros Robot Happy


        As always, if you have topic suggestions, or there are questions you would like answered, appropriate for this blog, please send them to with the words Timing 101 in the subject line.  I will give them consideration and see if I can fit them in. Thanks for reading.


        Keep calm and clock on,


      • Estimate the Range of Your Wireless Application

        Lance Looper | 08/229/2017 | 08:58 AM

        Silicon Labs provides RF range calculators for customers to help estimate the actual range of their wireless applications. Simple RF Range Calculator is available to download here.



        RF range depends on the following parameters

        • Conducted TX output power, the power driven to the antenna input [dBm]
        • TX antenna gain [dBi]
        • Conducted receiver sensitivity [dBm]
        • RX antenna gain [dBi]
        • Frequency [MHz]

        Propagation factor, depends on the environment

        • n = 2 for ideal free space propagation
        • n = 2.8-3 for typical line of sight propagation
        • n = 4 for outdoor wet soil
        • For multi-path propagation (indoor or outdoor with several buildings/objects) “n” can vary between 4 and 6 based on the actual environment


        Simple RF Range Calculator

        This simple RF range calculator is for those customers who don’t want to deal with difficult RF questions just simply would like to get fast and reasonable results for both outdoor and indoor environments.


        Key Features:

        • Fast and simple while accurate
        • Built in propagation factors, based on field measurements
        • Antenna height fixed to 1 to 1.2 meters
        • Supports all the unlicensed bands and custom frequency channels as well



        Simple RF Range Calculator provides fast and accurate result as the customer selected the frequency band and set TX and RX parameters:

        RC1 copy.png

        Simple RF Range Calculator with frequency band selection


        Frequency bands and custom frequency channels also can be selected:

        RC2 copy.png

        Simple RF Range Calculator with custom frequency channel set up



        TX Output Power and RX Sensitivity need to set up based on the radio device’s actual link parameters based on the data sheet. If the exact antenna parameters are unknown notes at the right side can help to determine the closest values:

        RC3 copy.png

         Simple RF Range Calculator with notes


      • Timing 101: The Case of the (Apparently) Jittery Jitter Attenuated Clock

        kgsmith | 08/220/2017 | 07:02 PM

        Hello and welcome to this inaugural article for Timing 101. My goal is to introduce and review technical topics of interest to board and systems designers who apply timing components or ICs (aka “clock chips”). Clock chips deliver frequency and phase information via clock waveforms, and in some cases packetized time information.


        In this post, I will go over a common test set-up measurement situation whose results may be unexpected when one initially encounters jitter attenuators. I will first review some requisite background material, then present the "mystery" and its root cause, and finally suggest an improved test set-up.


        Jitter and Phase Noise in a Nutshell

        Briefly, clocks are periodic signals with digital signal levels used to sample data in a synchronous digital system. In other words, clocks provide the “heartbeat” or cadence necessary for sampling and sequentially processing data in synchronous digital circuits or systems. They are usually, but not always, at or near 50% duty cycle.


        Ideal clocks would provide a perfect specified frequency and phase to optimize this process. However, practical clocks have timing jitter which can be defined as the short-term timing variation of the clock edges from their ideal values. One reason to care about clock jitter for synchronous digital systems is that it eats into the timing margins and, therefore, the reliability and validity of the data.


        There is also a frequency domain counterpart to jitter: phase noise. Phase noise measures the random short-term phase fluctuations of a clock. It’s an indication of the spectral purity of the clock.


        In short, this is a tabular or graphical plot of L(f) [script ell of f]; the noise power in one phase modulation sideband versus carrier power, at frequency offsets from the carrier. For example, -70 dBc/Hz at 100 kHz and –150 dBc/Hz at 20 MHz. The dBc/Hz units refer to power in dB relative to the carrier power per Hertz of bandwidth. Phase noise is typically measured using a phase noise analyzer or a spectrum analyzer with a phase noise option.


        Often shown on the same plot are non-random short-term clock phase fluctuations referred to as spurs or spurious. These spurs, depicted as discrete components, have units of dBc.


        As with other systems analyses, we will generally find it easier to understand clock devices and clock distribution networks or clock trees in the frequency domain. (I plan to cover phase noise and spurs in more detail in a subsequent post.)


        The Role of Jitter Attenuators

        It’s not uncommon to have to work with (or at least start with) relatively noisy or jittery clocks. These can arise for a number of reasons. For example, when the clock is:

        • recovered from a serial data stream
        • sourced from a noisy IC such as an FPGA or a noisy PC Board
        • derived from a TCXO or OCXO with good wander specs that is otherwise jittery
        • "gapped" meaning that for synchronization purposes there are missing edges


        In such cases, we need a particular type of clock device, a jitter attenuator or "jitter cleaner", to attenuate or minimize phase noise and spurs over the offset frequencies of interest. The resulting output clock is then distributed to the devices that need its improved jitter performance.


        The distinguishing characteristic of Jitter Attenuators is that they are essentially narrowband Phase Locked Loops (PLLs) with a "low pass" jitter transfer function. That is these devices attenuate jitter components whose frequencies are greater than the PLL's loop bandwidth (BW). Modern jitter attenuators often have programmable loop BWs over a wide range, from as low as 0.1 Hz to as high as 1 or a few kHz.


        By contrast, another category of clock chip, the clock generator, is a wideband PLL used primarily for clock multiplication from a low jitter source. These devices usually have fixed loop bandwidths on the order of 100s of kHz to 1 MHz.


        The Measurement Problem

        So what's the problem? Well, every so often a customer will contact us and write something like 'We're testing one of your clock chips and comparing the output clock versus the input clock and it seems surprisingly jittery'. Invariably we will find that the test set-up boils down to something like the following where the oscilloscope is being triggered by the jittery input clock.   


        Timing IMage.png


        The result will often look similar to that shown in the below. In this example the jitter attenuator is an Si5347 with loop BW = 100 Hz. The top yellow trace is the input clock which is a 25 MHz sine wave from a signal generator with 1 kHz FM, 100 Hz deviation applied. The bottom green trace is the output clock which is also 25 MHz just to keep things simple.

         Picture1 copy.png


        Shouldn't the output clock be less jittery? Is it jitter attenuated or not? This is the case of the (apparently) jittery jitter attenuated clock.


        Given the measurement set-up shown earlier, three factors must be present to observe this apparent mystery:

        1. The input clock is jittery.
        2. The output clock is less jittery. In other words, the jitter attenuator is doing its job.
        3. The output clock is being triggered by (compared to) the input clock.


        Now you should be able to recognize the basic problem even if disguised in a more complicated application.


        Note that if you triggered on the output clock then the input clock would look jittery by comparison. See below. Which clock appears jittery then is just a question of trigger perspective. This particular scope measurement is not conclusive without knowing which clock was more jittery a priori.


        Picture2 copy.png


        Diagnosis by Loop Bandwidth 

        You can obtain some insight as to what's really going on with this particular test configuration by playing with the Jitter Attenuator's loop bandwidth. Try narrowing and widening the BW and then observing the results on the scope.


        Assuming a jittery input clock, you should generally see that widening the BW makes the output clock appear less jittery versus the input clock. This is because widening the BW means the PLL will track the input clock more, jitter and all. In Figure 4 below, the Si5347’s loop BW has been widened to 4 kHz. There is essentially no jitter attenuation and the output clock does not appear jittery compared to the input clock.

         Picture3 copy.png


        Conversely, narrowing the BW makes the output clock appear more jittery versus the input clock. That's because a narrower loop BW corresponds to more jitter attenuation. Ironically, it is the very success of the jitter attenuator in this test configuration that is the root cause of the apparent mystery. If the output clock simply tracked the input clock then the trigger source would be irrelevant. In the figure below, the Si5347’s loop BW is narrowed back down to 100 Hz.

         Picture4 copy.png


        A jitter attenuated clock is generally different from its jittery input clock, above and beyond any frequency scaling. If its spectrum has significantly changed, this should be relatively obvious when measuring and comparing the phase noise of each clock. However, as I mentioned before, this takes specialized equipment such as a phase noise analyzer or a spectrum analyzer with a phase noise option.


        Third Party Arbitration

        OK, so what's a better way to simultaneously compare the jittery input and jitter attenuated output clocks if all you have is a scope? Find a third party to arbitrate. In other words, find or generate a low jitter reference clock integer-related and synchronous to both the input and output clocks. Then use this reference as the trigger for both the input and output clocks. See the revised test set-up diagram in the figure below. Now you can clearly and fairly compare the jitter of the input and output clocks simultaneously in the time domain.


        Timing Image 2.png


        Here are a couple of example plots in which all the oscilloscope traces are 25 MHz as before. The top yellow trace is the jittery (frequency modulated) input clock and the middle green trace is the jitter attenuator’s output clock. The bottom blue trace is the new low jitter reference clock being used as the trigger. In the first instance, in the figure below, the jitter attenuator’s loop BW is 4 kHz and the output clock is fairly jittery just like the input clock.


        Picture5 copy.png


        In the second instance, in the figure below, the jitter attenuator’s loop BW is 100 Hz and the output clock is much less jittery. In this particular example, the standard deviation of the jitter attenuated clock’s cycle to cycle jitter dropped from 8.2 ps to 1.1 ps when the loop BW was decreased from 4 kHz to 100 Hz.


        Picture6 copy.png



        I hope you have enjoyed this first Timing 101 article and, if you are new to the field, that you won't be caught off guard should you run in to this scenario.


        Some of the subjects I hope to cover in later installments include a deeper dive in to jitter, phase noise, clock trees, wander, and output clock formats. If you have topic suggestions, or there are questions you would like answered, appropriate for this blog, please send them to with the words Timing 101 in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading.


        Keep calm and clock on. And click here for more information



      • Speed Does Not Kill: Power Supplies with Fast Switching Frequency Get Safer

        Lance Looper | 05/136/2017 | 10:00 AM

        The more power generated by a smaller power supply, the more cost effective it is and the less room it takes in the design. Designers can improve W/mm3 with faster switching. Switching technology using Gallium Nitride (GaN) or Silicon Carbide (SiC) allows faster switching rates than are currently available—up to 20 times faster.


        The technologies’ lateral structures, compared to vertical for silicon, make them low-charge devices capable of switching hundreds of volts in mere nano-seconds (ns). The challenge is that they require isolated gate drivers to work, and today’s technology typically cannot support the required noise immunity from their superfast switching.


        Faster Switching - SMPS Want It

        Fast power switching is most prevalent in switched mode power supplies (SMPS). SMPS convert their input power from ac to dc (ac-dc) or from dc to dc (dc-dc). In most cases, they also change voltage levels to suit the needs of the application.


        SMPS Graphic.png

        Typical ac-dc SMPS block diagram


        The new GaN and SiC technology switches faster and is more efficient than current switches. But their faster switching causes higher switching transients as shown in the figure below with a typical 600 V high side rail.

        Switching Transients.png

        Switching transients in a power converter


        GaN switching times are typically about 5ns, or about 10x - 20x faster than conventional systems. In this case, the 600 V high voltage rail results in a 120 kV/µs transient (600 V / 5 ns = 120 V/ns or 120 kV/µs).


        CMTI – Common Mode Transient Immunity – the Key Isolated Gate Driver Spec

        The isolated gate drivers controlling the power switches have to be designed to withstand these noise transients without creating glitches or latching-up. The ability of the driver to withstand these common mode noise transients is generally defined as CMTI (common mode transient immunity), and is expressed in units of kV/µs.



        What are the Isolated Gate Driver Options?

        Isolated gate drivers must preserve the integrity of the isolation from the primary to the secondary side. There are a number of isolated gate driver solutions available today:


        • Junction-isolated drivers – With 50 kV/µs for latch-up immunity (CMTI proxy), these are not suitable for new, fast-switching tech’s requirement.
        • Opto-coupled drivers – With 10-50 kV/µs for latch-up immunity (CMTI proxy), these are still not good enough.
        • Transformer-coupled drivers – Getting closer with 50-100 kV/µs for latch-up immunity (CMTI proxy), but these are still not adequate.
        • Capacitive-coupled drivers – She’s got it where it counts. These explicitly specify CMTI at 200 kV/µs (MIN) for signal integrity and 400 kV/µs (MAX) for latch-up immunity. These exceed the 120 kV/µs requirement.


        There are other advantages for these drivers. Their latency (propagation delay) can be as much as 10x better than popular optocoupled gate drivers, and their part-to-part matching can be more than 10x better. This provides the designer with another key advantage—the system’s overall modulation scheme can be fine-tuned for maximum efficiency (W/mm3) and safety without having to accommodate specification slop. They also support lower voltage operation (2.5 V compared to 5 V) and a wider operating temperature range.


        Plus, they offer advanced features such as input noise filters, asynchronous shutdown capability, and multiple configurations such as half bridge or dual independent drivers in a single package.

        Finally, they are rated to 60 years of operating life at high voltage conditions, longer than any other comparable solution.


        Power supply designers want to maximize their W/mm3 using the fastest power switching technology available. The latest GaN- and SiC-based switches are the fastest available technology today, but isolated require gate drivers with very high noise immunity (CMTI).


        The Si827x isolated gate drivers from Silicon Labs meet GaN’s and SiC’s noise immunity requirements with margin to spare (120 kV/µs required, 200 kV/µs supplied).



      • Simplifying RAN Timing Using DSPLL Technology

        Lance Looper | 11/320/2016 | 11:12 AM

        We recently published this e-book describing some of the requirements, architectures, and system requirements that come with deploying heterogeneous networks by telecom companies to meet capacity and coverage requirements.  


        RAN Clocking_Cover.png


        RAN Clocking_2.png


        RAN Clocking_3.png


        RAN Clocking_4.png


        To read the rest of the eBook, click here