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## Official Blog of Silicon Labs

## Timing 101 #10: The Case of the Half-terminated Differential Output Clock

IntroductionIn this month’s post, I will review a basic, but sometimes overlooked, best practice necessary for making proper output clock measurements.

Those of you familiar with our clock IC evaluation boards know that we generally AC-couple our input and output clocks and provide separate SMA RF connectors for each polarity of the differential clock signal. This is the most flexible approach in terms of being able to immediately connect output clocks to single-ended 50 Ω inputs on test equipment such as frequency counters, oscilloscopes, phase noise analyzers, spectrum analyzers, etc. The AC-coupling capacitors keep us from attempting to impose a DC bias on test equipment inputs and vice-versa.

Here’s the best practice rule:

Bothpolarities of differential output buffers should be terminated when making measurements. This include the polarity that is not being measured. What are the consequences for not doing this? That is the subject of this article,The Case of the Half-terminated Differential Output Clock.Example Phase Noise MeasurementFirst, let’s work in the frequency domain. Consider the phase noise plot below. It is from OUT0 of an Si5345 evaluation board for these 2 cases annotated in the screen capture.

The output format is 2.5V LVDS AC-coupled with the nominal frequency set to 161.1328125 MHz based on the current CBPro sample plan. The board is actually in Free Run mode just to minimize the bench set-up.

In the first case, the 12 kHz to 20 MHz RMS phase jitter measured 89.512 fs. This curve was saved in memory. In the second case, the 12 kHz to 20 MHz RMS phase jitter increased to 124.16 fs. That’s not bad but the relative increase is about 39%. That is a significant impact.

Example Oscilloscope MeasurementsNext we’ll work in the time domain. Consider the oscilloscope plots below. The top trace is OUT0 assigned to channel 2, OUT0B is assigned to channel 3, and the common mode (CM) voltage is computed as f1. Note that since we are on the far side of the AC-coupling capacitor, we aren’t measuring the DC value but rather the noise represented by the average value of AC-coupled OUT0 and OUT0B. (The difference in scales here is to accommodate the half-terminated case and is not relevant to the calculation.)

In this first screen capture, both oscilloscope inputs are set to 50 Ω. The waveform shapes look reasonable and the CM noise is about 38mVpp on average.

In this second screen capture, the only difference is that OUT0B’s input has been set to 1 MΩ. Now

bothwaveform shapes are larger and distorted. Further, the CM noise has increased to about 344 mVpp on average. This is almost an order of magnitude increase in CM noise.Note that in these experiments, the time domain measurements are much more striking than the frequency domain measurements. The phase noise differences might even have been glossed over in automated testing. A good argument for a lab bench to have both types of instrumentation!

Root CauseWhy is terminating only half of the output clock having such an impact? We don’t need to know all the details of the buffer’s design but a simplified model will provide some insight. Consider the figure below.

Components in the left hand side box are internal to the IC and illustrate a simplified model of a CML or Current Mode Logic driver that can be made compatible with several swing formats. The AC-coupling caps are usually on the EVB and the load resistor R shown here is typically 50 Ω as for test equipment. Transmission lines are not illustrated but PCB traces and coaxial cable can all be assumed to be nominal 50 Ω. (The AC coupled load terminations can also be regarded as 100 Ω differential across CLKP and CLKN where the center-tap CM voltage is GND.)

Some notable features include the following:

The driver is symmetric and designed for specific DC biasing over expected terminated operation. DC-coupled loads would need to have a common voltage exactly equal to Vcm in order to not impact the intended bias. This is why we need to AC-couple to instrument loads.

However, even if we are AC-coupled, if we don’t have symmetric loads, then the driver will be imbalanced and the result is that the output common mode voltage Vcm will be modulated which can impact biasing and operation. In this particular case the CM feedback circuit is clearly unable to keep up. The performance of the measured terminated half-circuit is degraded by the operation of the unterminated half-circuit.

CrosstalkHalf-terminated differential outputs can even impact neighboring output driver performance in subtle ways. In this experiment, we continue to work with an Si5345 EVB as before. The phase noise plot below is for OUT0 set to nominal 161.1328125 MHz as before with OUT0B terminated. Adjacent channel OUT1/OUT1B is set to nominal 2 times that or 322.265625 MHz. Both polarities are properly terminated. The 12 kHz to 20 MHz phase jitter measured 94.32 fs averaged over 5 sweeps. Spurs are depicted in dBc so we can see the details.

The next phase noise plot is for OUT0 again, under previous conditions, except this time neighboring output OUT1B is

unterminated. There is not a significant increase in phase jitter. However, we have clearly introduced 2 new spurs above the powerline frequencies region as annotated below.These were identified in the instrument spur list as 140.374 kHz at -104.874 dBc and 4.90 MHz at -108.235 dBc. There is no obvious mathematical relationship yet this is a consistent result for this board and configuration. For wireless applications interested in the reason for every spur we can at least attribute these to the adjacent channel’s improper termination.

Termination OptionsThere are a number of termination options for our evaluation boards, and similar application boards, depending on what’s available at your bench. These include:

If one is attempting to make careful measurements on a 12 output evaluation board that could call for 24 – 1 or 23 SMA terminations. That’s a fair number. So what to do?

One approach is to just make sure that the nearest channel output clocks to the measured clock are terminated. That cuts the quantity down quite a lot. The other is to use RF pads or attenuators as described in the next section.

Attenuators as Lab Expedient TerminationsIn our lab we have many multi-channel clock EVBs which can consume a large quantity of terminations during testing. If a lot of us are working in the lab simultaneously, we can’t always terminate every clock exactly the way we would like. So another approach is to use a high value RF pad or attenuator as a lab expedient termination.

Commercially available attenuators are PI attenuators made up of a 3-resistor network. That is, the resistor network resembles the Greek letter "pi". The first resistor R1 is shunted to GND, followed by R2 in series, followed by another R1 shunted to GND.

Using an online calculator such as at https://www.microwaves101.com/calculators/858-attenuator-calculator we can calculate the R1 and R2 values and the resulting effective Rload assuming no connection past the attenuator. The table below lists the effective load using 6 dB, 10 dB, and 20 dB terminations.

You can see that for increasing attenuator values the effective impedance looking in to the attenuator alone increases. By 20 dB attenuation it’s an almost perfect termination. This can be very handy at times. The results using this technique are indistinguishable from purpose-built terminations.

ConclusionI hope you have enjoyed this Timing 101 article. I’ve given you some insight as to why it’s a best practice to terminate even unmeasured differential outputs. And provided a tip for using an attenuator as a lab expedient termination if necessary.

As always, if you have topic suggestions, or there are questions you would like answered, appropriate for this blog, please send them to kevin.smith@silabs.com with the words Timing 101 in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on.

Cheers,

Kevin

Below are the other Timing 101 articles:

Timing 101: The Case of the (Apparently) Jittery Jitter Attenuated Clock

Timing 101: The Case of the Ouroboros Clock

Timing 101: The Case of the Jitterier Divided-Down Clock

Timing 101: The Case of the Split Termination

Timing 101: The Case of the PLL’s VCO High Pass Transfer Function

Timing 101: The Case of the Spurious Phase Noise Part I

Timing 101: The Case of the Spurious Phase Noise Part II

Timing 101 The Case of the Cycle-to-Cycle Jitter Rule of Thumb

Timing 101: The Case of the Discrepant Scope Measurements

Timing 101: The Case of the Half-terminated Differential Output Clock

## Programmable Clocks Simplify Board-Level FPGA Designs

One of our timing customers sees a real opportunity in the way FPGA-based designs are commercialized and brought to market.

Jim Bittman, principal hardware engineer, founded BittWare in 1989. The company was recently acquired and today is BittWare, a Molex company, with headquarters in Concord, New Hampshire. Back in the 1990s, BittWare was focused on DSP boards—but in the early 2000s the company realized a new opportunity for growth using a new generation of powerful FPGAs. Switching from designing and manufacturing DSP-based boards to those with large FPGAs was not simple, however, as the nature of these devices brought significant engineering challenges for early adopters like BittWare.

FPGAs combine programmable logic, embedded high-speed transceivers, protocol IP controllers, digital signal processing, memory controllers, and a tremendous amount of computational power. FPGAs are truly the brains in modern electronic designs. But to unlock and harness the power of the industry’s latest FPGAs, system designers are faced with a formidable system integration challenge. Designs require network connectivity, high speed serial interfaces to share data across chips and boards, memory, power, timing and other resources. Designers need to develop solutions that can be brought to market quickly and efficiently. And there is also a need to develop customized solutions that are uniquely tailored for different markets and customers.

That’s where BittWare comes in. BittWare develops Intel and Xilinx board-level solutions that combine FPGAs with 10/40/100GbE high-speed networking interfaces, PCIe Gen 1, Gen 2 or Gen 3 connectivity, DDR4 memory, Silicon Labs low jitter programmable clocks and a board management controller for advanced system monitoring. The boards are based upon industry-standard commercially-off-the-shelf (COTS) form factors to ensure compatibility and interoperability with chassis and single board computer vendors. The benefit? BittWare’s customers get a turnkey solution that significantly reduces technology risk and accelerates time-to-revenue.

Another challenge is that different applications often require different frequency clocks to support different networking protocols and control plane functions. BittWare and Silicon Labs worked closely together to address this challenge by building support into BittWare’s software so that their customers can

directlycustomize Silicon Labs’ programmable clocks for their own applications. One common hardware platform can be easily adapted to support a broad range of different applications. The hardware, including clocking, is remotely field-upgradable, so new applications can be enabled quickly via software upgrades.A broad range of markets are benefiting from these system-level turnkey solutions, including broadcast video, finance, instrumentation, government and military/aerospace. In particular, applications like cyber security, high frequency trading, and high-performance computing in data centers require rapid reprogrammability to support innovative new features and services.

By combining Intel and Xilinx programmable FPGAs and Silicon Labs programmable clocks in their designs, BittWare is powering the next wave of innovation in high-speed electronics design.

To learn more about Silicon Labs' timing solutions, click here.

## Six-Degrees of Separation

It has been postulated that every human is connected to every other human with only six relationships between. It has also been proven that probabilistically, you can be in a room with 23 people and have a 50 percent chance of two people having the same birthday. These connections are all around us. It turns out that digital electronic frequencies seem to have an even tighter relationship when viewed by their fractional relationships.

Rational numbers are numbers that can be written it the form of a + b/c where a, b, & c are all integers. This is a handy way to work with frequencies because of the extensive relationships we have found between seemingly unrelated applications.

Fractional RelationshipsAt Silicon Labs, we see a lot of seemingly unique frequencies from our customers. Consequently, we are in a prime spot to observe relationships between frequencies.

Recently, we received a request for a Si5338 frequency plan that had the following frequencies:

Input: 185.439560440 MHz

OUT1: 148.5 MHz

OUT2: 148.351648352 MHz

OUT3: 27 MHz

Upon initial inspection, there are no nice fractional relationships between these numbers. When such complex divider values are needed, it limits the ability of our algorithms to optimize the performance. So, we dug in a bit to understand the real source of these high-precision numbers.

First, we noted that some of these frequencies look to be related to the SMPTE standard where the line data rate can be 1485Mbps or 2970Mbps. 27MHz is also used by SMPTE systems. In SMPTE, the fraction 1000/1001 is deployed to avoid interference.

Armed with the customer’s entered frequencies and our knowledge of the SMPTE standards, we begin our detective work:

185.439560440 * 1001/1000 = 185.62500000044

If we can truncate those last two digits, we would have a nice fractional value, but where did those odd values come from. Let’s truncate and find out. Often, we are looking to get to a line rate of something we have seen before. To do so, we often see line rates that are multiples of the clocks by factors of 2, 4, 8, 16, 10, or 20.

185.625000000 * 2 = 371.25

185.625000000 * 4 = 742.5

185.625000000 * 8 = 1485

185.625000000 * 16 = 2970

185.625000000 * 10 = 1856.25

185.625000000 * 20 = 3712.5

Here we have found two SMPTE-related numbers 1485 and 2970. Eureka! So:

185.439560440 is better written as 2970/16/1001*1000 or 185.4395604 4395604 4395604 (repeating)

Armed with our new knowledge, we can apply these fractions and base numbers to take full advantage of our frequency planning algorithms. To enter these values, we have created a frequency editor that can accept equations.

Pulling up CBPro for the Si5338, and proceeding to the input frequency page:

Continuing this for the outputs:

As you can see at the bottom of the window, the frequency plan is valid and the design is ok, which means it has been optimized. Entering the frequencies as they were given, yields an unrealizable plan.

This same frequency entry form is available throughout CBPro for our clock generators, jitter attenuators, and synchronization clock products.

ConclusionBy entering the input and output frequencies as the full fraction values, CBPro can best optimize to achieve the desired synchronous result (no frequency error) with the lowest jitter possible. The frequency editor in CBPro accepts multiplication, division, addition, subtraction, and even PPM addition giving you the easiest path to creating the frequencies you need in your designs. If you are unsure if the relationships exist, we are here to help you.

(CBPro can be downloaded from Silicon Labs website from http://www.silabs.com/cbpro)

## Timing 101 #8: The Case of the Cycle-to-Cycle Jitter Rule of Thumb

IntroductionIn this post,

The Case of the Cycle-to-Cycle Jitter Rule of Thumb,I will review a rule of thumb that can be used for estimating the RMS cycle-to-cycle jitter if all you have available is the RMS period jitter. The reason I’m doing so this month is that a couple of colleagues of mine recently asked me to reconcile a particular Timing Knowledge Base article versus one of our app notes . I first observed this rule of thumb in the lab and subsequently learned more about it.What’s the Rule of Thumb?It’s real simple. If the period jitter distribution is Gaussian or normal, then the cycle-to-cycle jitter can be estimated from the period jitter as follows:

Jcc (RMS) = sqrt(3) * Jper (RMS)I first recorded this in a Timing Knowledge Base article Estimating RMS Cycle to Cycle Jitter from RMS Period Jitter. I wrote at the time the following statement:

The sqrt(3) factor arises from the definitions of period jitter and cycle-to-cycle jitter in terms of the timing jitter of each clock edge versus a reference clock.

I will spend a little bit more time on this thought today and attack the problem from several different angles.

What’s the Question?In our application note, A Primer On Jitter, Jitter Measurement and Phase-Locked Loops

,the figure below shows the following slopes for post-processing phase noise into timing jitter metrics. Period jitter and cycle-to-cycle jitter are shown as high pass filters with 20 dBc/dec and 40dB/dec slopes, respectively. This is correct and a useful illustration to keep in mind.The question is how can RMS cycle-to-cycle jitter be larger than RMS period jitter, per the sqrt(3) rule,

andthe cycle-to-cycle jitter filter have a steeper slope? The answer is that it’s not just the slope that determines the end result. More on that later.Some TerminologyBefore proceeding, here are a couple of definitions adapted from AN279: Estimating Period Jitter from Phase Noise.

Cycle-to-cycle jitter- The short-term variation in clock period betweenadjacentclock cycles. This jitter measure, abbreviated here as JCC, may be specified as either an RMS or peak-to-peak quantity.Period jitter- The short-term variation in clock period overallmeasured clock cycles, compared to the average clock period. This jitter measure, abbreviated here as JPER, may be specified as either an RMS or peak-to-peak quantity.The distinction between these time domain jitter measurements is important, hence the italicized terms above. (By the way, you can find old examples in the academic and trade literature where these terms may mean different things, so always double-check the context). The terms here are as used presently and in standards such as JEDEC Standard No. 65B, “Definition of Skew Specifications for Standard Logic Devices”.

Example Lab MeasurementFirst, the following example lab measurement comes straight from the KB article. The annotated image has been made more compact for convenience.

There are three items called out on the screen capture.

Example Excel DemonstrationYou can also demonstrate this rule in Excel simulations. Exploring the effect, I generated a spreadsheet where I took an ideal clock edge and then jittered the edges by taking random samples from a Gaussian distribution. I then took the period measurements, and the cycle to cycle measurements, over five trials each for 30 edges, and 100 edges with the clock edges representing a jittery 100 MHz clock. Note that since the cycle-to-cycle jitter results are signed, i.e. positive or negative, we should expect the standard deviation of these quantities to be larger, all else being equal. The 100 edges trials were usually much closer to the sqrt(3) rule than the 30 edges trials but you could still see the general effect even over just 30 edges.

If you are interested in playing with it, the spreadsheet is attached as

CCJ_ROT_Demonstrator.xlsx.An ExplanationSo how does this rule of thumb arise? As mentioned previously, I first observed this in the lab years ago and learned I could count on it. Yet, I have seen little written about this. Eventually I ran across Statek Technical Note 35,

An overview of oscillator jitter. The explanation below is a somewhat simplified and modified version of that derivation where the quantities are expected values for a “large” time series (recall my comments about 100 edges converging to the rule better than 30 edges.)Let the variable below represent the variance of a single edge’s timing jitter, i.e. the difference in time of a jittery edge versus an ideal edge.

Every period measured then is the difference between 2 successive edge values, where each edge jitter has variance s2j. Period jitter is sometimes referred to as the first difference of the timing jitter. Since cycle-to-cycle jitter is the difference between adjacent periods it can be referred to as the second difference of the timing jitter.

If each edge’s jitter is independent then the variance of the period jitter can be written as

This is just what we would expect per the Variance Sum Law. You can see an example here, which states that for

independent(uncorrelated) variables:However, we can’t calculate cycle-cycle jitter quite as easily since in every cycle-to-cycle measurement we use one “interior” clock edge

twiceand therefore we must account for this. Instead we write:Since each edge’s jitter is assumed to be independent and have the same statistical properties we can drop the cross correlation terms and write:

The ratio of the variances is therefore

This is an interesting and unexpected result, at least to me :)

Post-Processing Phase NoiseAN279: Estimating Period Jitter from Phase Noise describes how one can estimate period jitter from phase noise based on applying a 4[sin(pi*f*tau)]^2 weighting factor to the phase noise integration. The weighting factor is predominately a +20 dB/dec high pass filter until reaching a peak at the half-carrier frequency.

It turns out that you can use a similar approach to calculating cycle-to-cycle jitter. This requires applying a {4[sin(pi*f*tau)]^2}^2 or 16[sin(pi*f*tau)]^4 weighting factor which is predominately a

+40 dB/dechigh pass filter until reaching a peak at the half-carrier frequency. This is exactly what AN687refers to.So how can a sharper HPF skirt integrate such that cycle-to-cycle jitter is larger than the period jitter and the sqrt(3) rule applies?

I had to dig up my old Matlab program which I used when writing that app note. Fortunately, I still had the file and the original data. I then ran a modified version of the program and compared the results for max fOFFSET where the phase noise dataset is extended and truncated at both fc/2 and fc. The answer is that while the cycle-to-cycle HPF skirt is steeper the maximum is also higher. See the plots below. The blue wide trace is the period jitter weighted (filtered) phase noise and the red wide trace is the cycle-to-cycle jitter weighted phase noise. It’s the larger far offset phase noise contributions that make the difference.

The original data was for a 160 MHz CMOS oscillator which had a scope measured period jitter at the time of about 2 ps. To be conservative, it was for that reason that I often ran the integration further out than fc/2. Scopes are lower noise now and it would be interesting to go find the original device under test and measure it on a better instrument. My main interest here is to see if the sqrt(3) relationship holds true. As you can see, the rule of thumb holds up in both cases.

ConclusionWell I hope you have enjoyed this Timing 101 article. The sqrt (3) rule of thumb for cycle-to-cycle jitter holds up well in the lab, in Excel spreadsheet simulations, and when post-processing phase noise.

As always, if you have topic suggestions, or there are questions you would like answered, appropriate for this blog, please send them to kevin.smith@silabs.com with the words Timing 101 in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on.

Cheers,

Kevin

Below are the other Timing 101 articles:

Timing 101: The Case of the (Apparently) Jittery Jitter Attenuated Clock

Timing 101: The Case of the Ouroboros Clock

Timing 101: The Case of the Jitterier Divided-Down Clock

Timing 101: The Case of the Split Termination

Timing 101: The Case of the PLL’s VCO High Pass Transfer Function

Timing 101: The Case of the Spurious Phase Noise Part I

Timing 101: The Case of the Spurious Phase Noise Part II

Timing 101: The Case of the Discrepant Scope Measurements

Timing 101: The Case of the Half-terminated Differential Output Clock

## Timing 101 #7: The Case of the Spurious Phase Noise Part II

Hello and welcome to another chapter in our

Timing 101series from Silicon Labs' Kevin Smith.IntroductionIn this article, I want to continue last month’s discussion regarding spurs in clock phase noise measurements. There were a few items I just couldn’t include previously due to lack of time and space.

You will recall from last time that spurs are discrete frequency components in clock phase noise plots. Spurs are typically few and low amplitude, but generally undesirable as they contribute to a clock’s total jitter.

However, spurs can also be used for evaluation and characterization of timing devices. We can use lab sources configured for low-level modulation to apply spurious frequency components, directly or indirectly, as input stimuli to a clock device or system. The resulting output clock spurs are then measured with a spectrum analyzer or phase noise analyzer.

In this post,

The Case of the Spurious Phase Noise Part II, I will briefly review suitable signal modulation options. Next I will discuss some notable measurements. Finally, I will give results for a select example, jitter transfer.Modulation Selection, i.e. Not All Spurs are Created EqualThere are three basic analog modulation options to most lab grade generators, i.e., AM, FM, or PM, referring to Amplitude Modulation, Frequency Modulation, and Phase Modulation, respectively. Each have their place in our “spur toolbox.” But first a digression. Consider each of the spectrum analyzer screen caps below. The carrier is nominal 100 MHz and there are a pair of symmetric spurs on each side at 100 kHz offset from the carrier. Each spur is about 60 dB down from the carrier.

Can you tell which screen cap corresponds to AM, FM, or PM? No, not really, not without additional information. In this particular example, the images are in alphabetical order.

So, why are they so hard to distinguish? There are several reasons:

Let’s look at the last couple of points in some detail. The following relations are adapted from the appendix in Keysight Technologies’ Spectrum Analysis Amplitude and Frequency Modulation app note.

Note: TheseFM componentsare the samemagnitudeas for AM, but unlike AM there is aminussign in front of the lower sideband. However, since the spectrum analyzer does not preserve phase information, low modulation AM, FM, and PM components look the same.In general, the SSB or single sideband spur to carrier ratio of AM, FM, or PM is 20*log10 (Modulation Index/2). For example, given 200 Hz peak-peak frequency deviation and 100 kHz frequency modulation, we expect a SSB spur as follows:

SL = 20 log10 {(200/2)/100E3} = -60 dBc

Now, here’s the practical aspect of using FM versus PM. If your source supports PM, then you can directly enter the amount of peak phase modulation. You need not change this setting as you step the modulation frequency or spur offset frequency. However, if your source only supports FM, then the frequency modulation index must be maintained per the following relation.

In this case, you will need to scale the peak frequency deviation Delta-f together with the modulation frequency fm in order to keep Beta constant.

So What Tests Can We Do with Modulation Spurs?Generally, we will measure output clock spurs in the frequency domain using either a spectrum analyzer or a phase noise analyzer. We choose different modulation methods depending on what stimulus we need to apply to the system. The table below summarizes some notable measurements. I will briefly discuss each of these tests and then focus on the last one in a bit more detail.

You will note that either FM or PM can be used to generate input clock spurs for jitter transfer testing. The only thing you will need to keep track of is the phase or frequency modulation index. Modern AWGs (Arbitrary Waveform Generators) typically support AM, FM, and PM. Higher frequency RF and Microwave signal generators also support at least FM.

Here are some more details about each of the tests mentioned in the table.

Input AM-to-PM ConversionA high gain well designed clock buffer will tend to reject AM and only pass along phase (timing) error. However, no input clock buffer is perfect and some AM-to-PM conversion can take place. The mechanism and amount of such conversion will in general differ depending on the modulation frequency.

The set-up for this test is straight forward, i.e. apply an input clock with AM and then check for an output clock spur offset at the amplitude modulation frequency. There are a few considerations to keep in mind when doing this type of test:

in the instrument.PSRPSR or Power Supply Rejection is similar to the previous test in that AM is applied. However, in this case, it is not the input clock that is modulated. Rather AM is introduced indirectly via the power supply and then spurs measured as before. This type of measurement also goes by other names such as PSRR (Power Supply Rejection Ratio) or power supply ripple testing.

In addition to the earlier AM-to-PM considerations, there are a few others:

This topic alone deserves much separate treatment. Please see Silicon Labs app note AN491: Power Supply Rejection for Low-Jitter Clocks for further details. Where there are multiple rails, and/or removing bypass caps may be a performance issue, you can leave them in and simply do straightforward performance testing as described in Silicon Labs’ app note AN887: Si534X and Power Supply Noise.

Jitter TransferA relatively quick way to check the transfer curve of a clock PLL chip is to apply low level PM or FM spurs and step the modulation offset frequency from well below the expected loop bandwidth to well above it. Then using a phase noise analyzer, with Max Hold enabled, you will see how the applied spurs roll off. The intersection of the asymptotes of the spur amplitudes allows one to estimate the loop bandwidth.

You can kind of tell what’s going on by looking at the phase noise, but using a fixed modulation index input clock allows us to more precisely measure the transfer function. The 2 screen caps below were taken applying a phase modulated 25 MHz input clock (0.2° phase deviation) to an Si5345 jitter attenuator and measuring the phase noise continuously in Max Hold for a 100 MHz output clock.

In the first case, figure below, the DSPLL bandwidth is set 400 Hz. The plot shows that the annotated asymptotic lines intersect right around 400 Hz, as expected. The roll-off in the vicinity of the corner frequency is a little over 30 dB/dec.

In the second case, figure below, the DSPLL bandwidth is set to 4 kHz. This time the plot shows that the annotated asymptotic lines intersect around 4.5 kHz, which is a little wider than the nominal target. The roll-off in the vicinity of the corner frequency here looks closer to 25 dB/dec.

The use of the Max Hold feature allows us to make a “quick and dirty” manual measurement. However, we could make more careful measurements using averaging and storing spur amplitudes across ensembles of runs in order to accurately characterize the loop bandwidth of the DUT.

ConclusionWell, that’s it for this month. In this post, I’ve extended our discussion on spurs in phase noise measurements to include some thoughts on using them for test purposes. I hope you have enjoyed this Timing 101 article.

As always, if you have topic suggestions, or there are questions you would like answered, appropriate for this blog, please send them to kevin.smith@silabs.com with the words Timing 101 in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on.

Cheers,

Kevin

Below are the other Timing 101 articles:

Timing 101: The Case of the (Apparently) Jittery Jitter Attenuated Clock

Timing 101: The Case of the Ouroboros Clock

Timing 101: The Case of the Jitterier Divided-Down Clock

Timing 101: The Case of the Split Termination

Timing 101: The Case of the PLL’s VCO High Pass Transfer Function

Timing 101: The Case of the Spurious Phase Noise Part I

Timing 101 The Case of the Cycle-to-Cycle Jitter Rule of Thumb

Timing 101: The Case of the Discrepant Scope Measurements

Timing 101: The Case of the Half-terminated Differential Output Clock

## Ethernet’s Role in Hyperscale Computing

Significant investment is pouring into data centers as the enterprise market accelerates its increased use of cloud-based computing solutions and the demand for lower latency intensifies. Wireless networks are also experiencing tremendous change as networks move from 4G/LTE to LTE-Advanced and 5G systems.

In a new whitepaper by James Wilson, Senior Marketing Director of Timing Products at Silicon Labs, details how data centers and wireless networks are equipping themselves to handle these enormous changes by adopting high-speed 100G Ethernet. Although a popular and cost-effective solution, the increased use of optical high-speed Ethernet is driving the need for high-performance clock and frequency control products in both wireless network and data center environments.

The new paper details why clock and frequency products are playing a crucial role in these two technological evolutions. For example, several specific technical obstacles have arisen within data centers as they use the Ethernet to support the rapid shift of enterprise workloads to cloud infrastructure. The majority of data center traffic stays within the data center as workload processing is distributed across multiple computer nodes, posing a serious problem to data centers. To clear this hurdle, data centers are starting to optimize their network architecture to support distributed, virtualized computing by connecting every switch to each other, otherwise known as hyperscale computing.

The Ethernet is critical to making hyperscale possible as data center switches quickly move from 25G, to 50G, to 100G to expedite data transfer and network efficiency. This speedy migration is driving data center equipment manufacturers to upgrade switch and access ports to higher speeds, fueling the need for higher performance, lower jitter timing solutions. Ultra-low jitter clocks and oscillators are necessary in these applications because high clock noise can result in unacceptably high bit-error rates or lost traffic.

As the paper details, mobile networks are also experiencing seismic change as operators prepare to support mobile data traffic expected to grow by 49 exabytes per month by 2021, a sevenfold increase since 2016. To meet the aggressive bandwidth demands, wireless networks are being re-architected and optimized for data transport with widescale adoption of high-speed Ethernet in radio access networks (RAN). The whitepaper lays out how the wireless industry is starting to re-envision base station architectures. Unlike the distributed model of 4G/LTE, where RF and baseband processing functions were split into separate remote radio heads (RRH) and base band units (BBU), the connection between baseband and radio elements, known as the fronthaul network, are being optimized for LTE-Advanced/5G networks.

To ensure fronthaul networks can handle the new bandwidth constraints being placed on them with the proposed new architecture, numerous standards have developed. Highlighted in detail within the paper, the new fronthaul standards are driving the need for frequency flexible timing solutions that can support both LTE and Ethernet clocking in radio heads, small cells, and pico cells. These new solutions provide the opportunity for hardware designs to unify all clock synthesis into a single, small-form factor IC.

For wireless infrastructure and data center architects, the paper is a must read. Providing readers with detailed architecture and IC illustrations, the article will give readers better perspective on effectively leveraging the Ethernet while maintaining flexible, accurate timing and synchronization – which ultimately, prevents the loss of traffic and/or data error in either environment.

Read the full paper here.

## Timing 101 #6: The Case of the Spurious Phase Noise Part I

Hello and welcome to another edition of the Timing 101 blog from Silicon Labs' Kevin Smith. It’s a new year and time for a new post!

In this month’s article, I will discuss spurs in clock phase noise measurements. Most everyone in timing will recognize spurs as the distinctive spikes in the phase noise plot below. They are generally undesired and in the frequency synthesis business low level spurs are not uncommon. They are the foam on the beer as it were. This particular plot comes from an AWG or Arbitrary Waveform Generator configured for 100 MHz sinusoidal output with 1 MHz FM. I will be using this plot or similar versions of this data throughout this article.

What is not always appreciated is their relative significance and how they should be displayed and accounted for in applications and troubleshooting. They can also be generated for device and system evaluation and characterization.

In this first post, I will briefly review spurs and their distinctive characteristics. Next, I will discuss how to account for them when calculating total RMS phase jitter. Finally, I will sum up with my assessment of the relative merits of the three approaches to displaying spurs (or not) in phase noise plots. Looking ahead to part 2, I will discuss the usefulness of generating spurs on purpose for evaluation and testing.

What are spurs?The technical term spur is short for spurious which comes from the Latin spurius meaning illegitimate or false. See for example the entry here. There is another more general use of the word spur which refers to a spike or protuberance as in cowboy spurs and the San Antonio Spurs. Coincidentally, both meanings are somewhat fitting in this context.

Here spurs are carrier or clock frequency spectral imperfections measured in the frequency domain just like phase noise. However, unlike phase noise they are discrete frequency components. This gives these features several particular and interesting characteristics:

Let me expand a little bit on each of these characteristics in turn.

Spurs are deterministicSpurs are generally undesirable and to be distinguished from the harmonics needed to constitute a square wave or trapezoidal wave clock. Their specific frequencies can aid us in determining their origins and relative importance. For example, they can be caused by systemic sources such as board power supply noise, crosstalk, mixing, modulation, PLL architecture, and power line harmonics.

PLLs effectively sample the input clock, usually through a PFD (Phase Frequency Detector), and therefore must suppress update rate spurs. Further, PLLs that synthesize fractional output frequencies typically yield spurs due to fractional division.

Spur power is independent of bandwidthThis is true for discrete frequency components generally and can be observed directly on a spectrum analyzer. By contrast non-deterministic noise power is proportional to bandwidth. Consider the 2 side-by-side plots below displaying a 100 MHz sinusoidal carrier with +/- 100 kHz FM sidebands acting as spurs. The traces were averaged over 5 runs and the span was set to 300 kHz. The only difference between the 2 plots is the RBW or Resolution Bandwidth.

In the left hand side plot the RBW = 6.25 kHz. In the right hand side plot the RBW = 291 Hz. You can see by the red line annotations that the peaks remain essentially the same magnitude while the noise level dropped going left to right. I “eyeballed” the noise to be about a 10 dB delta between the plots. We expect the noise to decrease narrowing the RBW from 6.25 kHz to 291 Hz by 10*log10(6.25 kHz/291 Hz) = 10*log10(16) = 12 dB which is reasonably close in this case. Note that the discrete frequency components get narrower also.

Spurs contribute bounded peak jitter in the time domain.Each spur can be regarded as a phase modulation sideband to the carrier whose amplitude determines the peak phase deviation contribution. This useful feature can be exploited in testing and I will discuss this topic in the next post. By contrast, peak phase deviation is unbounded for random phase noise.

Accounting for SpursPhase noise in a phase noise plot is a power spectral density measurement displayed on a per Hertz basis, i.e. in units of dBc/Hz, and then integrated over a jitter bandwidth to yield an RMS phase jitter quantity. The units make sense since [dBc/Hz] x [Hz] = [dBc], a measure of the RMS phase jitter power with respect to the carrier. Statistical methods then have to be used to estimate the peak phase jitter over that same bandwidth. (Phase noise instruments do not actually measure the phase noise in 1 Hz increments but use a larger RBW depending on the offset frequency range.)

The RMS jitter contribution for each spur can be calculated as follows. (See for example Silicon Labs app note AN256: Integrated Phase Noise.)

L(

f) here is taken to be the spur power in dBc at offset frequency f for carrier frequency f0. The proper way to account for spurs when calculating RMS jitter for both phase noise + spurs is to add each spur’s individual jitter power contribution in RSS (Root Sum Square) with the RMS phase jitter due to noise only.We can demonstrate this with an example.

The left-hand plot below is a phase noise plot for the example nominal 100 MHz clock with spurs omitted. The right-hand plot is the same phase noise plot but with spurs identified and explicitly displayed in dBc. For this instrument, spurs in dBc are displayed in a different color than the phase noise. In the first case the RMS phase jitter measured between 12 kHz to 20 MHz was calculated as 668.837 fs. In the second case, the RMS phase jitter measured was recorded as 878.156 fs. This is an increase of about 209 fs or about a 31% increase.

An interesting question is how spurs are identified in phase noise test equipment. This particular instrument defines a threshold in terms of how much higher a peak has to be than the standard deviation of the noise based on a moving average. The default spurious sensibility setting is 3 x standard deviation (sigma) which has proven to be a good practical value.

To see why the spurs contributed this much additional jitter, note that there are 3 spurs shown in band, i.e. between 12 kHz and 20 MHz offset. In the table below I list the 3 spurs together with their individual RMS jitter contributions as calculated per the cited formula. The 1 MHz spur due to FM dominates. (The spur offset frequency location and amplitude came directly from the instrument’s spur list.)

Now, let’s RSS all these values together:

This is very close to the 878.156 fs reported by the instrument. You can go through a similar exercise, entering spurious data separately, using our online Phase Noise to Jitter Calculator.

Displaying SpursYou may have noticed that the very first phase noise plot had spikes that looked different (shorter) than the plot with spurs in dBc above. Let's put the two figures together side-by-side. You can see now that the left-hand side plot has the spurs in the same color as the phase noise. The spurs in the left-hand plot are depicted in units of dBc/Hz. That is the instrument scales the spur down by normalizing them with respect to the RBW as follows:

Spur peak [dBc/Hz] = Spur amplitude [dBc] – 10*log10 (RBW)In most instruments the RBW will vary from Hz to MHz, depending on the offset frequency range, usually on the order of 10% down to 1% of the offset frequency. The instrument may or may not explicitly provide the RBW. However, we can always deduce it.

You will recall the largest spur at 1 MHz was displayed as -72 dBc in the right-hand plot. In the left-hand plot the same spur is depicted roughly speaking as a skinny triangle with the peak measuring about -117.5 dBc/Hz and a base that now extends slightly below and above 1 MHz offset. So we can calculate the RBW at 1 MHz offset as follows:

You may wonder why the "spurs in dBc/Hz" view is useful. If all you care about is the impact of the RMS phase noise then this view helps puts things in proper perspective versus the non-spurious phase noise. In some cases, sales and field applications engineers may regard the right-hand style plot as unduly alarming though they contain approximately equivalent information.

On the other hand, the right-hand style plot is more accurate and more useful for troubleshooting. Note that in this particular example, going left to right, the calculated RMS jitter differs increasing from 809.574 fs versus 878.156 fs respectively for an increase of about 8%. Further, it is very useful to know the dBc value of the spur directly without being concerned about the instrument's RBW at a particular offset frequency.

The table above summarizes my assessment of the relative merits of the three approaches to displaying spurs. Your mileage may vary.

ConclusionThis month I’ve discussed spurs in phase noise measurements. I hope you have enjoyed this Timing 101 article. This is only a brief introduction as entire books could be written just on this topic. I will return to this subject in

The Case of the Spurious Phase Noise Part IInext time to discuss generating and using spurs for testing.Cheers,

Kevin

Below are the other Timing 101 articles:

Timing 101: The Case of the (Apparently) Jittery Jitter Attenuated Clock

Timing 101: The Case of the Ouroboros Clock

Timing 101: The Case of the Jitterier Divided-Down Clock

Timing 101: The Case of the Split Termination

Timing 101: The Case of the PLL’s VCO High Pass Transfer Function

Timing 101: The Case of the Spurious Phase Noise Part II

Timing 101 The Case of the Cycle-to-Cycle Jitter Rule of Thumb

Timing 101: The Case of the Discrepant Scope Measurements

Timing 101: The Case of the Half-terminated Differential Output Clock

## Timing 101: The Case of the PLL’s VCO High Pass Transfer Function

Welcome to another edition of the Timing 101 blog from Silicon Labs' Kevin Smith.We have been doing some internal training recently and a common question that comes up is how and why a Phase Locked Loop (PLL) treats phase noise differently depending on whether it comes from the input clock or the VCO (Voltage Controlled Oscillator). Most everyone understands that input clock phase noise is jitter attenuated, i.e. the PLL acts like a low pass filter to input phase noise. However, it is not as readily apparent why a PLL should act like a high pass filter to VCO phase noise. This is the Case of the PLL’s VCO High Pass Transfer Function and the subject of this month’s post.

First, I will review the basic feedback loop and its transfer function. Next, I will generalize the process for signals injected at different locations around the loop. I will then generate and compare the transfer functions for a PLL both from the input clock and the VCO perspective. Finally, I’ll wrap up by offering some intuition and discussing the application considerations.

Feedback ReviewConsider the basic feedback diagram in the figure below where the variables and blocks are functions of the Laplace complex frequency variable ‘s’. The intermediate variable S representing error should be considered likewise. The forward gain is G(s) and the feedback gain H(s). I(s) and O(s) are the input and output signals respectively.

The closed loop transfer function TF for O(s)/I(s) is derived as follows.

Now what happens if we break up the forward path gain G(s) in to two separate blocks, G1(s) and G2(s) and inject a new signal X(s) as illustrated below? X(s) is additive as with noise.

By linearity, the transfer function TF for O(s)/x(s) is derived as follows where I(s) is set to 0.

It turns out we can generalize for any X(s) injection point anywhere around the feedback loop as follows. The term “Loop Gain” refers to the multiplication of all the gain elements going around the closed loop. In this particular example, the Loop Gain = G1(s)*G2(s)*H(s).

We can now apply these developments to the basic PLL.

Input Clock Phase Noise Transfer FunctionConsider the basic linear “small signal” PLL diagram below.

Going clockwise around the loop, the components in the diagram are as follows.

We can now generate the TF for Theta_o(s)/ Theta_i(s) almost by inspection by noting that the forward gain is KpF(s)Kv/s and the loop gain is [KpF(s)Kv/s]/N.

For reasons of stability F(s) is always a low pass filter so its value is either constant in value or rolls off with increasing frequency. In either case the overall closed loop behavior for the PLL is itself a low pass filter.

This PLL transfer function is covered in many textbooks and articles but a more detailed and recent discussion on this topic is contained in the article “Phase Locked Loop Noise Transfer Functions” by Peter Delos published in High Frequency Electronics, January, 2016.

VCO Phase Noise Transfer FunctionNow consider the basic PLL diagram modified below to also inject VCO phase noise via variable Theta_v(s).

We can generate the TF for Theta_o(s)/ Theta_v(s) by noting that the forward gain from the VCO phase noise injection point is simply unity and the loop gain is [KpF(s)Kv/s]/N as before.

Again, F(s) is a low pass filter so it is either constant in value or rolls off. Unlike the transfer function for the input clock, the numerator here has a zero at the origin. In this case the overall closed loop behavior for the PLL is now a high pass filter.

Some IntuitionOK, I know some of you may be saying, I get the math but I don’t really, intuitively, understand why the PLL acts as a high pass filter to VCO phase noise. Let me offer some food for thought that may provide some intuition.

Consider the expected difference in behavior for a phase step at Theta_i versus Theta_v:

low passfilter.high passfilter.Application ConsiderationsThe 2 dominant sources of phase noise in a PLL are typically the input clock and the VCO. As we have seen, the PLL treats each source's noise differently, i.e. as a low pass and a high pass filter respectively.

The application consequences are as follows:

1. If an input clock has relatively low phase noise versus the VCO, one typically uses a relatively wide bandwidth (BW) PLL in order to attenuate the VCO's phase noise. In this context, a wide bandwidth typically means something on the order of 100s of kHz to MHz. This is how clock generators or clock multipliers are designed. (Note that BW cannot be arbitrarily large for reasons related to stability and the need to suppress phase detector spurs.)

2. On the other hand, if an input clock has relatively high phase noise versus the VCO, one typically uses a relatively narrow bandwidth PLL in order to attenuate the input clock's phase noise. In this context, a narrow bandwidth means something on the order of kHz or less, usually much less. This is how jitter attenuators are designed.

Understanding this tradeoff and the ability to adjust the bandwidth "knob" is a key to troubleshooting PLLs and optimizing their application.

ConclusionThis month I’ve reviewed how a PLL's VCO phase noise transfer function arises and its unique high pass behavior. I’ve also offered some intuition and discussed the application considerations.

I hope you have enjoyed this Timing 101 article. It’s the last post for 2017. Happy Holidays and

Happy New Year to all of you!

As always, if you have topic suggestions, or there are questions you would like answered, appropriate for this blog, please send them to kevin.smith@silabs.com with the words Timing 101 in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading.

Keep calm and clock on.

Cheers,

Kevin

Below are the other Timing 101 articles:

Timing 101: The Case of the (Apparently) Jittery Jitter Attenuated Clock

Timing 101: The Case of the Ouroboros Clock

Timing 101: The Case of the Jitterier Divided-Down Clock

Timing 101: The Case of the Split Termination

Timing 101: The Case of the Spurious Phase Noise Part I

Timing 101: The Case of the Spurious Phase Noise Part II

Timing 101 The Case of the Cycle-to-Cycle Jitter Rule of Thumb

Timing 101: The Case of the Discrepant Scope Measurements

Timing 101: The Case of the Half-terminated Differential Output Clock

## Timing 101: The Case of the Jitterier Divided-Down Clock

Hello and welcome to the “Clocktoberfest” edition of the

Timing 101blog from Silicon Labs.Nice weather is starting to arrive here in central Texas. By late September and October we get hints of cooler and less humid days to come. Those of us of German descent, and plenty who are not, may celebrate Oktoberfest or some local variant such as Wurstfest in nearby New Braunfels. So “Happy Clocktoberfest!” from the Timing group.

This month I am going to discuss a very common question that arises when measuring the phase noise and phase jitter of relatively low clock frequencies. All things being equal, we generally expect divided-down lower frequency clocks to yield lower phase noise than higher frequency clocks. Quantitatively, you may recall this as the 20log(N) rule.

However, the 20log(N) rule only applies to phase noise and not integrated phase noise or phase jitter. Phase jitter should generally measure about the same. Further, as we get low enough in frequency we do not find this relation to hold true in actual measurements. So the question this month is - why is that?

The 20log(N) RuleFirst, a quick review of the 20log(N) rule for those who may not be familiar with it:

If the carrier frequency of a clock is divided down by a factor of N then we expect the phase noise to decrease by 20log(N). For example, every division by a factor 2 should result in a decrease of phase noise by 20log(2) or about 6 dB. The primary assumption here is a noiseless conventional digital divider.

Why is this? The output of a practical digital divider is rising and falling edges with the signal at a logic high or low level otherwise. Jitter is presented at the rising and falling edges only. The proportion of jitteriness to each clock cycle is reduced. Our intuition may suggest that if we reduce the number of jittery edges then we reduce the jitter transmitted by the divided down clock. That turns out to be correct.

Formally, this can be written as follows:

What About Phase Jitter?We integrate SSB phase noise

L(f) [dBc/Hz] to obtain rms phase jitter in seconds as follows for “brick wall” integration from f1 to f2 offset frequencies in Hz and where f0 is the carrier or clock frequency.In practice the quantities involved are small enough for good clocks that the RMS phase jitter, for a 12 kHz to 20 MHz jitter bandwidth, is on the order of 10s to 100s of femtoseconds.

Note that the rms phase jitter in seconds is inversely proportional to f0. When frequency is divided down, the phase noise,

L(f), goes down by a factor of 20log(N). However, since the frequency goes down by N also, the phase jitter expressed in units of time is constant. Therefore, phase noise curves, related by 20log(N), with the same phase noise shape over the jitter bandwidth, are expected to yield the same phase jitter in seconds.An ExampleLet’s look at a specific example. As an experiment, I took an Si5345 jitter attenuator, input a 25 MHz clock, and configured it so that I only changed an (internal) output divider by factors of 2 to obtain frequencies running from 800 MHz down to 50 MHz. I then measured the phase noise using an Agilent (now Keysight) E5052B and compared the phase noise and phase jitter for each case. Five runs were averaged and correlated for each frequency. I omitted any spurs for clarity and to simplify the experiment.

Through the magic of MS Paint and use of the “Transparent Selection” feature I am able to overlay all of the E5052B screen caps as follows. (If the runs are identical each time only unique text is obscured.) In the figure below, the traces generally run top to bottom in descending carrier frequency, i.e. 800 MHz, then 400 MHz, etc. on down to 50 MHz. The shapes of the curves are the same except where the curves are compressed at the highest offset frequencies.

I then tabulated the measured phase jitter results over the 12 kHz to 20 MHz jitter bandwidth as follows:

There are two immediate observations we can make from the overlaid plots and the table.

Despite the 20log(N) rule, the phase jitter is getting worse as I decrease the output clock frequency, especially below 200 MHz. These lower frequency clocks measure far jitterier than expected. Thus arises the case of the jitterier divided-down clock. So what’s going on?

Curve compression due to the apparent phase noise floor appears responsible for the differences in the calculated RMS phase jitter. Let’s verify that by comparing the data from 10 kHz to 20 MHz offset for the 800 MHz and 100 MHz cases. All of the spot phase noise data came from the original markers plotted except for the 20 MHz points which were estimated from the screen cap plots. (Note that for a factor of 8 or 23 we would expect a delta of 3 x 6 dB or 18 dB in phase noise.)

Taking just these values and entering them in to the Silicon Labs online

Phase Noise to Jitter Calculatorwe obtain the following.Not too shabby for the online calculator considering it only had 5 data points to work with!

Now let’s modify the 100 MHz dataset to remove the higher offset frequency compression as follows. The 18 dB Δ is as would be otherwise expected applying the 20log(N) rule.

Entering the modified values in to the online calculator we add its calculation to the table as highlighted:

This exercise confirms that the curve compression accounts for the significant difference in phase jitter

measured between the 800 MHz and 100 MHz cases.

The Noise FloorAll of the traces flatten or get close to flattening by 20 MHz offset. So, what is the apparent or effective noise floor? Note that in general this will be some RSS (Root Sum Square) combination of the instrument phase noise floor and the DUT’s far offset phase noise. For example, if both the DUT and the instrument had an effective phase noise of –153 dBc/Hz at 20 MHz offset then the RSS result would be 3 dB higher or –150 dBc/Hz.

If the instrument noise floor was well below the DUT's we would expect the spot phase noise at 20 MHz offset to decrease by 6 dB, for every division by a factor of 2, from that measured for the 800 MHz clock. But that is not what happened. See the table and accompanying figure below:

The phase noise floor is not varying monotonically which suggest multiple factors may be involved. Reviewing the E5052B specs indicates that the SSB phase noise sensitivity should decrease slightly as the carrier frequency is lowered. Also, far offset phase noise from the DUT (Device Under Test) is typically dominated by the output driver’s phase noise and that’s unlikely to vary in this way. We are most likely running in to a combination of the instrument's "actual" phase noise floor as a function of input frequency plus aliasing on the part of the DUT. The Si5345's frequency divider edges can be regarded as sampling the phase noise of the internal clock presented to the divider. This factor is independent of the instrument. It is understood that aliasing can occur but quantifying the specific contribution due to aliasing can be problematic.

This paper suggests that provided the noise BW of the input signal is > 4 x divider output frequency v0 then divided PM (Phase Modulation) noise will degrade via aliasing by 10log[(BW/2v0) +1]. The aliasing described primarily impacts the far offsets where we are interested.

The authors write:

"Aliasing of the broadband noise generally has a much smaller effect on the close-to-carrier noise

because it is typically many orders of magnitude higher than the wideband noise."

In these particular measurements, estimated noise floor degradation for the lowest carrier frequencies are plausible assuming a given BW and instrument noise floor. However, no one solution appears to accommodate all the data. It might require operating the device at the highest output frequency and then employing external dividers and filters to properly sort this out. Perhaps in some future post.

Additional ReadingWhile this month's post has concentrated on phase noise, it should be noted that divided spurs can be aliased or folded in the same way as the authors cited above discuss. One of my colleagues has demonstrated this also and I recommend his article for further reading.

ConclusionWe have reviewed the impact that a phase noise instrument’s apparent or effective phase noise floor can have on both the phase noise curve and phase jitter measurement of sufficiently low frequency clocks. After you have worked with your DUTs and phase noise equipment for some time you will recognize what a typical phase noise curve will look like, the approximate phase noise floor of the equipment, and what are reasonable expectations for phase jitter. Certainly, for the cases above, we would take have to take phase jitter measurements below 200 MHz with a grain of salt. If in doubt, try a similar configuration at a higher frequency for comparison. You will only miss the secondary phase noise degradation due to any instrument noise floor variation and/or aliasing due to higher division factors.

Below are the other Timing 101 articles:

Timing 101: The Case of the (Apparently) Jittery Jitter Attenuated Clock

Timing 101: The Case of the Ouroboros Clock

Timing 101: The Case of the Split Termination

Timing 101: The Case of the PLL’s VCO High Pass Transfer Function

Timing 101: The Case of the Spurious Phase Noise Part I

Timing 101: The Case of the Spurious Phase Noise Part II

Timing 101 The Case of the Cycle-to-Cycle Jitter Rule of Thumb

Timing 101: The Case of the Discrepant Scope Measurements

Timing 101: The Case of the Half-terminated Differential Output Clock

Endnotes1. The derivation here is adapted from a slim but information packed book by Dr. William “Bill” Egan

called Frequency Synthesis by Phase Lock published in 1981. See section 4.5, “Effect of Modulation

of a Divided Signal”, pages 75-76. (There is a later and much expanded edition of this book.) Dr. Egan

has passed on but he was a great engineer, author, and teacher in Silicon Valley. He wrote several

excellent, clear, and precise books on frequency synthesis, PLLs, and RF systems design.

2. A. SenGupta and F.L. Walls, “Effect of Aliasing on Spurs and PM Noise in Frequency Dividers”, 2000

IEEE/EIA International Frequency Control Symposium and Exhibition, pages 541 – 548.

Retrieved from http://tf.boulder.nist.gov/general/pdf/1380.pdf.

3. H. Mitchell, "Perfect Timing: performing clock division with jitter and phase noise measurements", EE

Times, 8/25/2011. Howell's paper covers this topic from a different perspective with some additional

detail using data from the previous generation Si5324. He also demonstrates spur aliasing by mixing the

outputs of separate RF signal generators. Retrieved from

https://www.eetimes.com/document.asp?doc_id=1279033.

## Delivering the Industry’s Best Jitter Performance and Power Efficiency on a Single Chip

This week we’ve released the new Si522xx PCIe clock generators, bringing best-in-industry jitter performance and energy efficiency to PCI Express® (PCIe®) Gen1/2/3/4 applications. This new clock family delivers on the stringent requirements of PCIe Gen 4 and Separate Reference Independent Spread (SRIS) standards with 20 percent jitter margin to spare, and its jitter performance (0.4 ps RMS) also provides up to 60 percent jitter margin for PCIe Gen 3.

The PCIe standard, originally developed as a serial interconnect for desktop PCs, and has become popular in blade servers, storage equipment, embedded computing, IP gateways, industrial systems, and consumer electronics. High-output clock generators like the Si522x family reduce the number of buffers needed as data bus usage expands in these types of systems. Designed specifically for clock-distribution-intensive applications, the Si522x family supports up to 12 outputs from a single device. This higher output count per device reduces BOM cost. The clocks’ output drivers take advantage of our innovative push-pull HCSL technology, eliminating external resistors required by conventional constant-current output drivers.

Additionally, internal power filtering prevents power supply noise from affecting jitter performance while reducing component count, saving about 30 percent of board space compared to competing solutions.

Developers designing battery-powered applications like digital cameras are especially concerned about power consumption. The 2-output Si52202 clock is optimized for low-power 1.5 V to 1.8 V applications, offering the lowest power consumption for PCIe applications. Packaged in a small 3 mm x 3 mm 20-pin QFN, the clock is also 45 percent smaller than competing solutions.

For more information, visit www.silabs.com/pcie-learningcenter.