In the previous Timing 201 article, Timing 201 #7: The Case of the Dueling PLLs – Part 1, I referred to a Silicon Labs white paper that describes Silicon Labs’ DSPLL nested dual-loop architecture as used in the Si538x wireless jitter attenuators. I first discussed the general motivation for a dual-loop PLL and compared the cascaded (series) dual-loop PLL versus the nested dual-loop PLL architectures.
The practical advantages of the nested dual-loop approach in this example were to reduce the number of tuned oscillators from 2 to 1 and to eliminate the need for a sensitive external voltage control line. The tradeoff for a nested feedback control loop is that the inner loop must be faster than the outer loop. If the loop speeds (or bandwidths) are comparable, then the loops will contend or “duel” with each other.
In this Part 2 follow-up post, I will discuss in more detail how to calculate the phase noise of both these dual-loop PLL approaches.
Some Simplifying Assumptions
To emphasize the basic ideas without getting bogged down in too much detail, I will make the following simplifying assumptions:
Series Dual-Loop Phase Noise Calculations
The figure below is from the cited white paper and previous post. The two PLLs are in series with each other.
You will recall that the first PLL, PLL1, is narrowband (NB) and the second PLL, PLL2, is wideband. To calculate the phase noise, we will go left to right through the following steps.
These calculations have been done in the attached spreadsheet Timing_201_7_The_Case_of_the_Dueling_PLLs - Part 2.xlsx. See the “Series Dual-Loop” worksheet. The PLLs are assumed to be 2nd order with the NB PLL BW = 100 Hz and the WB PLL BW = 1 MHz. These parameters can be changed in the spreadsheet, but practically speaking, NB PLLs will be on the order of mHz to kHz. WB PLLs are typically 500 kHz to 2 MHz.
The resulting plot is as follows.
Nested Dual-Loop Phase Noise Calculations
The figure below is also repeated from the cited white paper and previous post. In this case, the two PLLs are nested with respect to each other.
Now the inner loop (IL) PLL is WB and the outer loop (OL) PLL is NB. To calculate the phase noise, we will proceed from the “inside out” through the following steps.
These calculations have also been done in the attached spreadsheet Timing_201_7_The_Case_of_the_Dueling_PLLs - Part 2.xlsx. As before, to keep things “apples to apples”, the PLLs are assumed to be 2nd order with the NB PLL BW = 100 Hz and the WB PLL BW = 1 MHz. See the “Nested Dual-Loop” worksheet. The resulting plot is as follows.
You will note how similar these plots are to each other. Let’s overlay the output phase noise plots together for comparison.
Series versus Nested Dual-Loop Phase Noise Plots
The output phase noise plots are overlaid on top of each other for direct comparison. As shown, they look identical. Further, if you experiment with the bandwidths of each PLL, for each topology, the best output phase noise is generally obtained by making PLL1 (or OL PLL) and PLL2 (or IL PLL) narrowband and wideband respectively. Even apart from stability considerations, both topologies benefit from wide separation between the bandwidths.
Why the Topological Equivalence?
This result is not necessarily to be expected so let’s walk through the steps again and compare the approaches.
LPF_WB (LPF_NB (Input) + HPF_NB (VCXO)) + HPF_WB (VCO)
LPF_WB * LPF_NB (Input) + LPF_WB * HPF_NB (VCXO) + HPF_WB (VCO)
The use of WB and NB notation versus PLL1, PLL2, IL PLL, and OL PLL is to help us make direct comparison between the two sets of calculations. LPF_WB means apply a wideband low pass filter to the phase noise in parenthesis. Two filter terms multiplied indicates applying both filters.
LPF_NB (Input) + HPF_NB (LPF_WB (XO) + HPF_WB (VCO))
LPF_NB (Input) + HPF_NB * LPF_WB (XO) + HPF_NB * HPF_WB (VCO)
LPF_WB * LPF_NB (Input) ≈ LPF_NB (Input)
HPF_NB * HPF_WB (VCO) ≈ HPF_WB (VCO)
In other words, the NB LPF and the WB HPF dominate the calculations for these LPF and HPF terms. This is why these topologies produce equivalent total phase noise when all else is equal.
I hope you have enjoyed this Timing 201 article. In this Part 2 follow-up post, I have discussed in more detail how to calculate the phase noise of both the series and nested dual-loop approaches. Finally, by using a simplified example with widely separated bandwidths, we can see that the approaches are essentially equivalent. There are particular advantages to the nested dual-loop approach which arise from an alternate practical implementation that yields phase noise equivalent to the series dual-loop approach.
As always, if you have topic suggestions or questions appropriate for this blog, please send them to email@example.com with the words Timing 201 in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on.