Introduction

You have probably read or heard that phase noise is the frequency domain equivalent of jitter in the time domain. That is essentially correct except for what would appear to be a somewhat arbitrary dividing line. Phase noise below 10 Hz offset frequency is generally considered wander as opposed to jitter.  

Consider the screen capture below where I have measured phase noise down to 1 Hz minimum offset and explicitly noted the 10 Hz dividing line. Wander is on the left hand side and jitter is on the right hand side. The phase noise plot trends as one might expect right through the 10 Hz line.  So what’s different about wander as opposed to jitter and why do we care? From the perspective of someone who takes a lot of phase noise plots, I consider this the case of the really slow jitter. It’s both slow in terms of phase modulation and in how long it takes to measure. 

The topic of wander covers a lot of material.  Even introducing the highlights will take more than one blog article. In this first post, I will discuss the differences between wander and jitter, the motivation for understanding wander, and go in to some detail regarding a primary wander metric: MTIE or Maximum Time Interval Error. Next in this mini-series, I will discuss TDEV or Time Deviation. Finally, I plan to wrap up with some example lab data.  

Some Formal Definitions

The 10 Hz dividing line, in common use today, has been used in synchronous optical networking (SONET) and synchronous digital hierarchy (SDH) standards for years.  For example, ITU-T G.810 (08/96) Definitions and terminology for synchronization networks [1] defines jitter and wander as follows.

4.1.12 (timing) jitter: The short-term variations of the significant instants of a timing signal from their ideal positions in time (where short-term implies that these variations are of frequency greater than or equal to 10 Hz).

4.1.15 wander: The long-term variations of the significant instants of a digital signal from their ideal position in time (where long-term implies that these variations are of frequency less than 10 Hz).

Similarly, the SONET standard Telcordia GR-253-CORE [2] states in a footnote

“Short-term variations” implies phase oscillations of frequency greater than or equal to some demarcation frequency. Currently, 10 Hz is the demarcation between jitter and wander in the DS1 to DS3 North American Hierarchy.

Wander and jitter are clearly very similar since they are both “variations of the significant instants of a timing signal from their ideal positions in time”. They are also both ways of looking at phase fluctuations or angle modulation (PM or FM). Their only difference would appear to be scale. However, that can be a significant practical difference.

Consider by analogy the electromagnetic radiation spectrum, which is divided into several different bands such as infrared, visible light, radio waves, microwaves, and so forth.  In some sense, these are all “light”. However, the different types of EM radiation are generated and detected differently and interact with materials differently. So it has always made historical and practical sense to divide the spectrum into bands. This is roughly analogous to the wander versus jitter case in that these categories of phase fluctuations differ technologically.   

Why 10 Hz?

So, how did this 10 Hz demarcation frequency come about? Generally speaking, wander represented timing fluctuations that could not be attenuated by typical PLLs of the day. PLLs in the network elements would just track wander, and so it could accumulate.  Networks have to use other means such as buffers or pointer adjustments to accommodate or mitigate wander. Think of the phase noise offset region, 10 Hz and above, as “PLL Land”.

Things have changed since these standards. Back in the day it was uncommon or impractical to measure phase noise below 10 Hz offset. Now phase noise test equipment can go down to 1 Hz or below. Likewise with digital and FW/SW PLLs it is possible to have very narrowband PLLs which can provide some “wander attenuation”. Nonetheless, 10 Hz offset remains a useful dividing line and lives on in the standards.

Wander Mechanisms

Clock jitter is due to the relatively high frequency inherent or intrinsic jitter of an oscillator or other reference ultimately caused by flicker noise, shot noise, and thermal noise.  Post processing by succeeding devices such as clock buffers, clock generators, and jitter attenuators can contribute to or attenuate this random noise. Systemic or deterministic jitter components also can occur due to crosstalk, EMI, power supply noise, reflections etc.

Wander, on the other hand, is caused by slower processes. These include lower frequency offset oscillator and clock device noise components, plus the following.

• Slight initial differences in frequency and phase between clocks
• Slow changes in frequency and phase between clocks due to environmental differences such as temperature or vibration     
• Frequency and phase transients caused by switching clocks

For a good discussion of some of these wander mechanisms and their impact on a network, see [3]. 

Since wander mechanisms are different, at least in scale, and networks tend to pass or accumulate wander, industry has focused on understanding and limiting wander through specifications and standards.  

Wander Terminology and Metrics  

You may recall the use of the terms jitter generation, jitter transfer, and jitter tolerance. These measurements can be summarized as follows.  

• Jitter Generation - How much jitter is output if a jitter-free input clock is applied 
• Jitter Tolerance - How much input jitter can be tolerated without affecting device performance
• Jitter Transfer - How much jitter is transferred if a jittery input clock is applied

These definitions generally apply to phase noise measurements made with frequency domain equipment such as phase noise analyzers or spectrum analyzers. They are useful when cascading network elements.    

By contrast, wander is typically measured with time domain equipment. Counterpart definitions apply as listed below.   

• Wander Generation - How much wander is output if a wander-free input clock is applied
• Wander Tolerance - How much input wander can be tolerated without affecting device performance
• Wander Transfer - How much wander is transferred if a wandering input clock is applied

Wander has its own peculiar metrics too.  In particular, standards bodies such as the ITU rely on masks that provide limits to wander generation, tolerance, and transfer based on one or both of the following two wander parameters. See for example ITU-T 8262 [4].

• MTIE (Maximum Time Interval Error)
• TDEV (Time Deviation)

Very briefly, MTIE looks at peak-peak clock noise over intervals of time as we will discuss below. TDEV is a sort of standard deviation of the clock noise after some filtering. We will discuss TDEV next time. 

Before going into detail about MTIE, let’s discuss the foundational measurements Time Error and TIE (Time Interval Error).  These are both defined in the previously cited ITU-T G.810.

Time Error (TE)

The Time Error function x(t) is defined as follows for a measured clock generating time T(t) versus a reference clock generating time Tref(t). The frequency standard Tref(t) can be regarded as ideal, i.e., Tref(t) = t.

Time Interval Error (TIE)

Similarly, the Time Interval Error function is then defined as follows, where the lower case Greek letter "tau" is the time interval or observation interval.

Maximum Time Interval Error (MTIE)

MTIE measures the maximum peak-peak variation of TIE for all observation times of length tau = n*tau0 within measurement period T. ITU-T G.810 gives the following formula for estimating MTIE

The sampling period represents the minimum measurement interval or observation interval. There are many terms used in the industry that are synonymous and should be recognizable in context: averaging time, sampling interval, sampling time, etc. This could mean every nominal period if you are using an oscilloscope to capture TIE data. However, most practical measurements over long periods of time are only sampling clocks. This would correspond to a frequency counter’s “gate time”, for example, if post-processing frequency data to obtain phase data.       

An MTIE Example

It’s better to show you the general idea at this point. Below, I have modified an illustration after ITU-T G.810 Figure II.1 and indicated a tau=1*tau0 observation interval or window as it is moved across the data.  (The data are for example only and do not come from the standard. I have also started at 0 as is customary to show changes in Time Error or phase since the start of the measurement.) The initial xppk peak-peak value at the location shown is about 1.1 ns – 0 ns = 1.1 ns.

Now slide the tau=1*tau0 observation interval right and the next xppk peak-peak value is 1.4 ns – 1.1 ns = 0.3 ns.

If we continue in this vein to the end of the data, we will find the worst case to be between 17*tau0 and 18*tau0 and the value is 7.0 ns – 4.0 ns = 3.0 ns. Therefore, the MTIE for tau=1*tau0 is 3.0 ns.

I have calculated the MTIE plot for this dataset in the attached Excel spreadsheet Example_MTIE_Calcs.xlsx. Note that the first value in the plot is 3 ns as just mentioned. This is a relatively simple example for illustration only.  MTIE data typically spans many decades and are plotted against masks on logarithmic scales.   

However, even this simple example suggests a couple of items to note about MTIE plots:

1. MTIE plots always increase monotonically.
   This is because MTIE acts as a max peak detector over an interval.  Larger variations in the data are encompassed as the observation interval increases.
2. Large transients will mask smaller transients.
   Again, a max peak detector will not reveal smaller variations.

Why is MTIE Useful?

MTIE is a relatively computation intensive measurement.  So what good are these type of plots?  There are at least two good reasons besides standards compliance:

1. MTIE can be used to size buffers. As noted here [3]:

2. MTIE indicates phase behavior. [4]   
   1. Plateaus correspond to a phase shift.
   2. Ramps correspond to a phase slope (frequency offset).

Conclusion

In this post, I have discussed the differences between wander and jitter, the motivation for understanding wander, and delved in to MTIE, a wander metric important to standards compliance and useful in sizing buffers.

I hope you have enjoyed this Timing 201 article. In the Part 2 follow-up post, I will discuss another important wander metric: TDEV or Time Deviation.   

As always, if you have topic suggestions or questions appropriate for this blog, please send them to kevin.smith@silabs.com with the words Timing 201 in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on.

Cheers,
Kevin

References

[1] ITU-T G.810 Definitions and terminology for synchronization networks
https://www.itu.int/rec/T-REC-G.810-199608-I/en

[2] Telcordia GR-253-CORE, Synchronous Optical Network (SONET) Transport Systems: Common Generic Criteria
The official version is orderable but not free from
https://telecom-info.njdepot.ericsson.net/site-cgi/ido/docs.cgi?ID=SEARCH&DOCUMENT=GR-253&.
My old copy is Issue 3, September 2000 but the fundamentals have not changed with the newer issues.

[3] Understanding Jitter and Wander Measurements and Standards, 2003
http://literature.cdn.keysight.com/litweb/pdf/5988-6254EN.pdf
This old Agilent (now Keysight) document remains a treasure, especially for SONET/SDH jitter and wander. See “Cause of wander” starting on p. 118.

[4] ITU-T G.8262 Timing characteristics of a synchronous equipment slave clock
https://www.itu.int/rec/T-REC-G.8262-201811-I/en

[5] K. Shenoi, Clocks, Oscillators, and PLLs, An introduction to synchronization and timing in telecommunications, WSTS – 2013, San Jose, April 16-18, 2013
https://tf.nist.gov/seminars/WSTS/PDFs/1-1_Qulsar_Shenoi_tutorial.pdf
An excellent tutorial. See slide 12.

[6] L. Cossart, Timing Measurement Fundamentals, ITSF November 2006.
http://www.chronos.co.uk/files/pdfs/itsf/2006/workshop/05-Cosart.pdf
Another excellent tutorial. See slides 40 – 41.

Introduction

RF and microwave frequency synthesizers often employ multiple connected PLLs. These architectures trade off complexity in favor of improved phase noise, smaller frequency step size, and faster switching [1]. In timing applications we may also employ multiple PLLs to combine timing functions and/or shape phase noise.   

For example, the white paper, “Optimizing Clock Synthesis in Small Cells and Heterogeneous Networks”, describes Silicon Labs’ DSPLL dual-loop architecture as used in the Si538x wireless jitter attenuators intended for small cell applications [2].  This particular approach is a nested dual-loop as opposed to a cascaded (concatenated) dual-loop. There are definite advantages to this implementation and some important considerations.

One consideration is the necessary bandwidth relationship between the inner and outer loops. This topic leads to the play on words in the main title of this blog post, The Case of the Dueling PLLs.  A second consideration is the difference in how one analyzes the phase noise for such an architecture, which arises from the fundamental difference between these two approaches as explained below. 

General Motivation for a Dual-Loop PLL Architecture

As you may recall from a previous blog post, there are two basic PLL clock applications [3]:

• Clock Generator (aka clock multiplier, frequency multiplier, etc.)
• Jitter Attenuator (aka jitter cleaner)

Low noise references are input to clock generators, which are usually wide bandwidth (e.g., 100s kHz to MHz). By contrast, jittery clocks are input to jitter attenuators, which are usually narrow bandwidth on the order of kHz or less.

But what if your clock application requires both functions? The most straightforward approach is to cascade the two PLLs in series as discussed in the next section. 

Cascaded Dual-Loop PLL Architecture

The figure below, taken from the cited white paper, illustrates a single-chip, cascaded dual-loop architecture. (Note that this sense of the term cascade is different from classic control system terminology. Here we mean two PLLs concatenated or in series.)

In this case, the left hand PLL1 with an analog Voltage Controlled Xtal Oscillator (VCXO) is used as a narrow band jitter attenuator stage.  The jitter attenuated clock signal is then input to the right hand PLL2, which is used as a wide band clock generator stage. The VCXO need not be very high in frequency but should have good close-in phase noise. This generally means a high Q crystal, which is why this component is typically external to the IC. This necessitates an external control voltage signal to the VCXO.

The on-chip VCO needs to be high enough in frequency so that the divided down clock can yield the necessary output clock frequencies. It also should have low phase noise at high offset frequencies.

This particular example is depicted as all analog with several external filter components and sensitive traces. However, there is no intrinsic reason why a cascaded dual-loop architecture could not be implemented more digitally and with filtering on-chip.

Because the PLLs in the example above are in-series and independent, the total output phase noise can be calculated as a cascade of phase noise processing elements as described in [3].  

Nested Dual-Loop PLL Architecture

The figure below, also from the cited white paper, illustrates a nested dual-loop architecture. In classic control system terminology, this would actually be considered a variation of a cascade control system. For clarity, I will use the term nested here. Think of it as the PLL equivalent of nested Matryoshka dolls.

In this case, the inner loop (IL) PLL is being used as the “VCO” or rather the Digitally Controlled Oscillator (DCO) of the outer loop (OL) PLL. This is the fundamental difference between these two approaches, which will determine how one calculates the total phase noise.

How does this work?

1. The output of the OL digital loop filter modulates the return path of the IL.
2. The output of the IL VCO is in fact the fOUT in the diagram. In practice, this output frequency is divided further to yield the necessary output clocks.

What are the advantages to this approach?

In this particular pair of examples, we reduce the number of tuned oscillators from two (VCXO and VCO) down to one (XO and VCO). This eliminates the need for one of the loop filters (be it internal or external) and a sensitive voltage control line, which must otherwise be routed externally. This decrease in components makes for a more compact solution which reduces the overall PCB footprint.

Could you implement a nested dual-loop with a VCXO?

Yes, in principle. There is no intrinsic reason why you couldn’t implement a nested dual-loop architecture that also uses an external VCXO.  Such an approach might even make sense if a particular VCXO has better phase noise performance, perhaps at a higher frequency (update rate). However, you would lose the specific advantages discussed previously. This is why the Si538x wireless jitter attenuators do not support an external VCXO.

What exactly is the Duel?

In these types of nested feedback control loops, the inner loop must be faster than the outer loop. If the loop speeds are comparable, then the loops will contend or “duel” with each other.

In PLL terms the inner loop must have a wider bandwidth than the outer loop.  This should make intuitive sense if you consider the relative difference in impact of inserting a really slow “DCO” into an otherwise fast PLL versus inserting a really fast “DCO” into an otherwise slow PLL. The former case significantly impacts the PLL and may even have stability or locking issues due to inserted additional delay. By contrast, the latter case is not impacted significantly. This tells us that the inner loop must be the faster (wider bandwidth) clock multiplier and the outer loop must be the slower (narrow bandwidth) jitter attenuator. Further, it tells us that at start-up and during the lock process, we want the inner loop PLL to stabilize and lock before the outer loop.

Another way of thinking about this is to recall that PLLs function as a low pass filter for phase noise arising from any source in the loop, except when they function as a high pass filter to VCO phase noise. For the OL PLL to modulate the IL’s return path without attenuation, the signal must be well within the IL BW.  

Incidentally, if you want to estimate one quantity from another, such as frequency step rise time from PLL bandwidth, you may use this relationship:

Tr [10%-90%] * BW [3dB] ≈ 0.35

See for example, Howard Johnson’s discussion in the article, PLL Response Time [5].  Per his article, the time bandwidth product varies from 0.35 to 0.38, depending on whether the PLL behaves closer to a single-pole or double-pole response.

How much faster or wider bandwidth must the inner loop be?  In mechanical engineering and process control systems, the differences in nested loop speeds can be relatively small.  A mechanical IL may be 5x to 10x faster than a mechanical OL. See for example Danielle Collins’ servo loop article in [6].  However, in timing applications, the difference in bandwidths is typically much greater. Nested dual-loop IL BWs are typically on the order of MHz, whereas OL BWs can be on the order of 10 Hz to 1 kHz, so the ratio is closer to the IL being 1000x to 100,000x faster than the OL. 

Note that for Si538x devices, the IL BW is wide (~ 1 MHz), fixed, and optimized.  Because it is so wide, there is no jitter attenuation at the device’s XO inputs, i.e., the XA/XB pins. Therefore, we should be careful that noise and interference does not couple into the device via the XO circuit at these pins. This is why we recommend low phase noise XOs to be placed as close as possible to the device so as to minimize PCB trace lengths.

Can this idea be extended?

Yes, in principle. The servo control loop article cited earlier discusses a servo motor control with three nested loops, inside to outside as follows: current feedback, velocity feedback, and position feedback. Similarly, you can “triple nest loop” clock PLLs to shape the phase noise to track select input clocks with different phase noise characteristics over different frequency offsets. However, this particular approach is not utilized by the Si538x devices.  

Conclusion

I hope you have enjoyed this Timing 201 article. In the Part 2 follow-up post, I will discuss in more detail how to calculate the phase noise of the nested dual-loop approach using a simplified example.

As always, if you have topic suggestions or questions appropriate for this blog, please send them to kevin.smith@silabs.com with the words Timing 201 in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on.

Cheers,
Kevin

References

[1] W. F. Egan, Advanced Frequency Synthesis by Phase Lock. Wiley, 2011. See for example section 7.1 regarding the Two-Loop Synthesizer where two loops interact via a mixer.

[2] Optimizing Clock Synthesis in Small Cells and Heterogeneous Networks
https://www.silabs.com/documents/public/white-papers/Silicon-Labs-Next-Generation-DSPLL-Technology-White-Paper---June-2015.pdf

[3] Timing 101 #11: The Case of the Noisy Source Clock Tree Part 1
https://www.silabs.com/community/blog.entry.html/2018/10/30/timing_101_11_the-2uqO

[4] Timing 101 #12: The Case of the Noisy Source Clock Tree Part 2
https://www.silabs.com/community/blog.entry.html/2018/12/21/timing_101_12_the-ikzY

[5] H. Johnson, PLL Response Time, High-Speed Digital Design Online Newsletter: Vol. 15 Issue 04,
http://www.sigcon.com/Pubs/news/15_04.htm

[6] D. Collins, Why is the bandwidth of a servo control loop important?, April 20, 2017, https://www.motioncontroltips.com/why-is-the-bandwidth-of-a-servo-control-loop-important/

Silicon Labs capped summer off with our first-ever Works With event, and we’re keeping the learning opportunities coming with the launch of Clock Talk, our biweekly timing-focused webinar series. Launched last week, Clock Talk brings some of our leading voices in timing experts to present on a range of topics that address specific industry pain points and equip attendees with the knowledge and tools needed to accelerate timing-intensive system designs. It is also an opportunity to learn about our best-in-class selection of timing products, including crystal oscillators, jitter attenuators, network synchronizers, and PCI Express (PCIe) clock generators and buffers. Clock Talks occur every Tuesday at 9:00 CST/16:00 CET in AMER/EMEA and Wednesday at 10:30 HKT in APAC. Each 45-minute session will conclude with a live 15-minute Q and A session with the presenter.

In the first in our series, IEEE 1588 Timing Solutions for Non-Telecom Applications, Senior Product Manager David Spencer discussed IEEE 1588 Precision Time Protocol (PTP). He outlined why PTP is important in power distribution, broadcast, and data center applications. David’s session is now available on-demand, as all Clock Talk webinars will be after the conclusion of their live presentations.

Upcoming sessions cover a wide range of topics, from an in-depth look at the types of clock jitter that affect SerDes performance to an overview of the OpenRAN initiative to define and build general-purpose, vendor-agnostic equipment for RAN solutions.

Here is the list of upcoming Clock Talk web events:

Register here for the entire Clock Talk series at once, so you’ll never miss a session or for individual sessions. You can find more information about our portfolio of timing solutions here, and if you have questions about a specific application or product, we’d love to hear from you.

Introduction

Some five years ago, a customer contacted us thinking they needed to return a clock generator device that would often go into a continuously resetting state after power-up.  We had never heard of such unusual behavior and wondered if there was anything wrong with this particular unit’s POR (Power On Reset) circuit. 

Fortunately, the customer had a small PC board that frequently exhibited the behavior, and which they could ship to us for troubleshooting in our lab.  This enabled us to more quickly determine the root cause and verify the solution.

It turned out that an overlooked spec for a passive component located elsewhere on the board was causing large consequences for the customer’s application. The lessons learned are generally applicable and the subject of this blog article, The Case of the Autonomously Resetting Clock Generator.

BLUF (Bottom Line Up Front)

The clock generator’s POR circuit was not at fault. In fact, it was behaving exactly as it should. Rather, an external 3.3 V regulator circuit was marginally stable. Oscillations on the 3.3 V rail could be sufficiently large to trigger autonomous resets.    

Browsing the Power Supply Voltages

The customer board took in +12 V and regulated this down to the +3.3 V and +1.8 V rails required by the Si5341 clock generator.  I used a lab power supply with pushbutton Output On/Off to provide the necessary +12 V input. This allowed me to manually and conveniently power cycle many times in order to observe and contrast a passing versus failing (continuously resetting) power-up event. The series of oscilloscope screen captures below display the 3.3 V (orange trace) at the top and the 1.8 V (blue trace) at the bottom.

The figure below shows the nominally settled behavior of the 3.3 V and 1.8 V after a failed power-up.  The 1.8 V supply is completely accurate. However, the 3.3 V supply is clearly oscillating and even periodically dropping down to about 2.4 V, far below the POR trip threshold. 

What about those occasions where the part successfully powers up? Per the figure below, both the 3.3 V and 1.8 V rails are at their nominal targets but the 3.3 V supply appears much noisier. This is another clue that the 3.3 V regulator circuit may be marginally stable.

I then looked at the start-up behavior. When the device fails, the 3.3 V supply starts oscillating straight away.

Even when the unit successfully powers up, as depicted below, the 3.3 V supply exhibits overshoot before settling down to a noisy nominal voltage.

An Informative Vendor Data Sheet

The customer was using a 500 mA LDO (Low Drop Out) regulator in a SOT-23-5 package. Reading the vendor’s data sheet, I noticed that the typical application drawing showed the output capacitor as a 2.2 uF tantalum.  Further, the data sheet explicitly stated that the output capacitor needed an ESR of about 1 Ω and that ultra-low ESR caps could cause oscillation.

Inspecting the output cap on the customer’s board revealed that it was a ceramic capacitor. These can have an ESR with an order of magnitude less than an electrolytic capacitor. So that suggested the next experiment to try.

Demonstrating the Fix

We hacked in a 1 Ω resistor in series with the ceramic capacitor in order to emulate the approximate ESR of a tantalum capacitor. A close-up photo of the hack is shown below. The brown component in the upper part of the “elbow” is the existing capacitor. The component marked “01Y” is the 1 Ω resistor.  

The hack was ugly but effective:

As the resulting screen cap shows above, the 3.3 V supply is much less noisy and the start-up transient is very small and quickly damped out. After many attempts, no autonomous resets were observed, current draw was as expected, and the device always yielded output clocks.  This outcome was good enough for the customer to take over and do additional verification testing for their particular application.

Some Lessons Learned

This Timing 201 case exemplifies several lessons learned. These are listed below, going from the general to the specific.

1. If you have a significantly puzzling problem, and can ship us a failing PC board, that can greatly speed up the overall debug process. I realize that may not always be possible due to availability, expense, intellectual property, or power/control issues. Reducing a failing board down to the lowest populated version may help mitigate some of these concerns.
2. When troubleshooting any functional device issue, it’s always worth double-checking the supply voltages. Regulator instabilities, more subtle than this case, may even show up as increased output clock phase noise or spurs.
3. Be aware that relatively older LDO regulators may have been designed for and require higher ESR caps than relatively newer LDO regulators.  The particular vendor used by this customer sells LDO regulators of both varieties, i.e. those that require 1 Ω ESR output stability caps and those that do not.
4. Finally, it’s a good idea to make sure that schematics and BOMs call out exactly what LDO output capacitor is needed so that no one accidentally orders and installs the wrong type.

Conclusion

I hope you have enjoyed this Timing 201 article.  

As always, if you have topic suggestions, or there are questions you would like answered, appropriate for this blog, please send them to kevin.smith@silabs.com with the words Timing 201 in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on.

Cheers,
Kevin

Introduction

In the last Timing 201 post, I discussed the parasitic Phase-Locked Loop (PLL) in which an independent oscillator can couple energy in to a PLL’s VCO so as to influence or even take over the PLL’s output frequency and phase. I then reviewed some basic injection theory, including the concept of injection lock range.

Given the amount of material I would like to cover, I am going to follow-up that post with two more articles.  This installment, Part 2, will discuss how to minimize injection sensitivity generally. Part 3, to come later, will cover the topic of measuring injection sensitivity.  

A Brief Review

Per the last article, injection pulling or locking refers to when one independent oscillator disturbs or locks the frequency and phase of another independent near-synchronous oscillator. We then reviewed injection theory after Wolaver (1991) culminating in this equation with the important take-aways noted.

ILBW (Injection Lock Bandwidth)

Wolaver treated the injection constant or gain KINJ as the injection lock range. It is useful to regard this lock range as the Injection Lock Bandwidth (ILBW) to contrast it with the PLL’s loop bandwidth (BW). From here on, I will use this nomenclature. The bottom line is that, in order to minimize the risk of injection locking, we want BW > ILBW.  Ideally, BW would be significantly greater than the PLL’s ILBW.

The factors in the formula suggest where we might run in to trouble. For example, LC tank oscillators, especially when integrated, have much lower Q compared to crystal oscillators. Further, the trend is for higher and higher frequency clocks. The resonant tank frequency itself is usually dictated by something on the order of 2 times the maximum 50% duty cycle output clock frequency we would like to support. So we should be on guard for this issue when considering narrow band (NB) and high frequency low-Q VCO tank circuit PLLs.

So why don’t we routinely run in to injection problems today? Well you still can, if you are rolling your own NB discrete synchronous PLLs and especially if you co-locate them. This article series is in part an attempt to warn you of some possible concerns.

Board and IC designers have learned over the years to adopt injection resistant practices and PLL topologies. First, let’s begin by considering some typical injection mechanisms. 

Injection Mechanisms

There are several common injection mechanisms in which aggressor oscillator noise may couple in to a tank oscillator circuit. The first two listed are suggested by the figure below:

1. Power supply noise transmitted through the PCB or IC substrate
2. EM fields directly coupled in to the tank circuit
3. Conducted noise via board traces and IC pins

We can mitigate, or reduce the impact, of injection by directly addressing these injection mechanisms and/or by using more injection resistant system-level approaches.

Injection Mitigation via Good EMC Design

Injection can be regarded as a special topic within the field of EMC (Electromagnetic Compatibility). We can minimize injection noise power applied at the tank for each of these mechanisms using good practices for designers cognizant of general Electromagnetic Interference (EMI) issues.

1. Power supply noise through PCB or IC substrate

• Power supply bypassing or filtering

2. EM fields directly coupling to the tank circuit

• Employing separation and shielding

3. Conducted noise via board traces and IC pins

• Applying signal filtering and good PCB layout: planes, short traces, etc.

All of the above methods attack the problem by reducing the strength of the aggressor noise PINJ.  However, in addition to these direct approaches, there are some other more systemic ways of minimizing injection problems.

Injection Mitigation via Thoughtful Frequency Planning

You may recall that I mentioned the general problem of injection pulling and locking arises when working with signals and oscillators that are synchronous or nearly so. What do I mean by nearly-synchronous? A SONET application board with lots of clock I/O all running at or near SONET frequencies within a few ppm of each other is a classic example.

One approach, if you have multiple PLLs or clock devices co-located on the same printed circuit board, is to configure them so that the VCO frequencies are asynchronous from each other. For example, consider an application where you have two adjacent Si570 I2C-Programmable XOs on a PCB. You can minimize the risk of injection crosstalk (XTALK) by configuring the devices so that their internal DCOs or Digitally Controlled Oscillators are well off frequency from each other.

Consider the Si570 Detailed Block Diagram below taken from this datasheet.  In the diagram, HS_DIV refers to the DCO High Speed Divider with possible values [4-7, 9, 11].  N1 is the CLKOUT Output Divider with allowed values [1] and [2, 4, 6, …, 27].  Finally, the datasheet constrains the DCO frequency to 4.850 GHz £ fosc £ 5.67 GHz. Given these constraints, there can often be multiple frequency plan solutions that output the same clock frequency.

For example, the DCOs can be made significantly asynchronous even when the output clocks are identical in frequency. Here are two valid Si570 configurations that both yield f1 = 155.52 MHz outputs.

• fosc1 = f1 x HS_DIV x N1 = 155.52 MHz x 4 x 8 = 4.976640 GHz.
• fosc2 = f1 x HS_DIV x N1 = 155.52 MHz x 9 x 4 = 5.598720 GHz.

In this instance, each DCO frequency is asynchronous, greatly minimizing the risk of injection XTALK.

Injection Mitigation via Beneficial Clock Architectures

One architectural approach is to simply minimize the number of PLLs, and therefore VCOs, with associated tank circuits, that might be susceptible to injection XTALK.

An example clock generator that minimizes the number of PLLs is the Si5338 I2C-Programmable Any-Frequency, Any-Output Quad Clock Generator. The functional block diagram below is taken from the Si5338 datasheet.

The Si5338 design consists primarily of a single wideband PLL with a bandwidth typically 1.6 MHz, followed by 4 “MultiSynth” dividers which can support four independent output clocks. The MultiSynth dividers are Silicon Labs’ proprietary low jitter fractional dividers that incorporate phase error correction. This whitepaper discusses this approach. Please note that there are other lower jitter clock generators employing similar architectures, with more clock I/O, such as the Si5332.

A second injection resistant architectural approach is to embed the potentially susceptible VCO tank circuit in a wideband PLL. (Recall that we want BW > ILBW.) An example jitter attenuator device that improves injection rejection in this way is the Si5380 which uses a nested dual loop architecture as shown in the diagram below. This illustration is taken from the “Optimizing Clock Synthesis in Small Cells and Heterogeneous Networks” whitepaper.

In this topology, the LC tank circuit VCO is integrated in a wideband (fast) inner loop which itself acts as the DCO for a narrowband (slow) outer loop. Please note that the Si5380 has been superseded by the more flexible, higher performance Si5386.

References

The same references that applied to the previous Timing 201 post apply here. They are listed below, for convenience.

Some material covered here was presented at the Austin Conference on Integrated Systems and Circuits (ACISC) in 2009. If you are interested, email me to request a copy of the paper “Practical Issues Measuring and Minimizing Injection Pulling in Board-level Oscillator and PLL Applications” and accompanying slides.

As mentioned previously, the best practical overall book treatment of injection lock that I am familiar with is in Wolaver’s text:

• D.H. Wolaver, Phase-Locked Loop Circuit Design, 1991, Prentice-Hall, pp. 97-104. 

This is a slim volume for a PLL book but it punches well above its weight in terms of information.  

Here are several foundational papers worth reading on the topic of injection.

• R. Adler, “A Study of Locking Phenomena in Oscillators,” Proc. IRE and Waves and Electrons, vol. 34 (June 1946), pp. 351-357. 
• K. Kurokawa, "Injection Locking of Microwave Solid-State Oscillators," Proc, IEEE 61, 1386 (1973).
• B. Razavi, “A Study of Injection Pulling and Locking in Oscillators,” IEEE J. Solid-State Circuits, vol. 39, pp. 1415-1424, September 2004. 

If you have favorite references you would like to share, please pass them along to me.

Conclusion

To recap, there are a number of ways that IC, board, and system designers can reduce the risk of injection pulling or injection lock.

1. Good EMC Design
2. Thoughtful Frequency Planning
3. Beneficial Clock Architectures
   • Minimize the number of PLLs and therefore VCOs
   • Embed susceptible VCOs in a wideband PLL

Looking ahead, it turns out it is often not practical to straightforwardly calculate the ratio of PINJ/PT and therefore KINJ or ILBW. Next time I will review how one may measure ILBW in the lab.

I hope you have enjoyed this Timing 201 article. As always, if you have topic suggestions, or there are questions appropriate for this blog you would like answered, please send them to kevin.smith@silabs.com with the words “Timing 201” in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on.

Cheers,
Kevin