I am designing with the QFN24 as the I/O voltage is 1.8V and I want to avoid a voltage translator on RX/TX.
Is it OK to have it bus-powered even if the host side is powered off (VIO = 0). Or I should make it self-powered and have VREGIN=VDD=3.3V (nominal)?
Thanks in advance.
As long as you're not violating any of the maximum specs in table 3.3, you should be fine.
In a test here, I tried VREGIN = 5V (bus powered), VDD = 3.3V, VIO = disconnected, I didn't see any leakage into the VIO rail. With VIO = 3.3V, and VDD / VREGIN disconnected, no leakage was seen on VDD/VREGIN.
The only issue that you might see is if VIO is 0V, and a GPIO pin voltage is 2.5V or higher (violating one of the specs). But, in your case, your IO voltages are 1.8V anyway, so even that shouldn't be an issue.
Thank you very much for your answer.
Could you do a check on the schematics below to see if I missed something. FWIW this is a redesign of an existing project that used CP2103 which we recently learned is NRND. So I made as little changes as possible in the schematics. Is it OK to leave UART inputs open?
I meant to say UART lines and not IO lines. My bad. by connecting VIO the way its shown in the bus powered reference design would show 5V levels on the UART? How would I go about with a device that interfaces with the CP2104 through UART but can tolerate only 3.3V on its pins?
could you elaborate your new question a bit?
how you would apply the power supply VIO/ VDD/ VREGIN, what's their voltage?
do you mean the logic voltage of TXD/RXD from the other part (that communicate with CP210x) is 5V?