This article describes the process for determining if a given codec, DAC, or ADC is compatible with the CP2114, CP2614, and CP2615 Audio Bridge devices.

Notes:

1. For brevity, the term ‘codec’ will be used to refer to all types of external audio devices (i.e. codec, DAC and ADC devices).
2. It is quite common for I2S-compatible codecs to use different signal names than those used in the I2S Bus Specification. This table describes the equivalent signal names:

The following steps should be performed to determine if a given codec is compatible with the CP2114/2614/2615:

1. Examine the codec and CP2114/2614/2615 specifications for possible incompatibilities. (More details are provided in the following sections.)
2. Develop and apply the appropriate CP2114/2614/2615 configuration file(s) based on information in the codec datasheet and specific requirements of the application.
3. Connect the codec evaluation board to the pin headers of the CP2114/2614/2615 evaluation board (EVB) using flying wires. For best signal integrity, connections should be made using shielded coax cable or twisted pairs (signal and digital ground).  To minimize ground inductance, connect multiple ground wires between the CP2114/2614/2615 and codec EVBs.  All connections should be as short as possible.
4. Perform testing to verify functionality, proper audio performance, and conformance with the specifications of the CP2114/2614/2615 and codec datasheets, and the overall requirements of the system.

The following sections describe the functional areas that should be examined to determine compatibility of a given codec with CP2114/2614/2615 devices.

Audio Interface Format

The CP2114/2614/2615 devices operate as an audio interface master (MCLK, LRCK, and SCK are outputs).  The codec must operate as an audio interface slave (MCLK, LRCK, and SCK are inputs).

The CP2114/2614/2615 devices support the following audio configurations:

The CP2114/2614/2615 support only I2S format; the CP2114 also supports Left-Justified format with 16 or 24 bits per sample.

Master Clock (MCLK) and Left/Right Clock (LRCK)

The CP2114 supports a sampling rate of 48 kHz only, and supports MCLK frequencies of 12.0 MHz (for 48 kHz sampling with an MCLK/LRCK ratio of 250), or 12.288 MHz (for 48 kHz sampling with an MCLK/LRCK ratio of 256). Codecs used with the CP2114 must support the 48 kHz sampling rate using either a 12.0 or 12.288 MHz MCLK.

The CP2614 and CP2615 support sampling rates of 44.1 kHz and 48 kHz, and support an MCLK frequency of 12.0 MHz only.  Codecs used with the CP2614/2615 must support 44.1 kHz and 48 kHz sampling rates with a 12.0 MHz MCLK.

LRCK is derived from MCLK, so these signals are frequency- and phase-locked.

Serial Clock (SCK)

The CP2114/2614/2615 serial clock (SCK) has 24 pulses per left/right sample, even when the audio sample size is 16-bits.  (An exception is the CP2114 running in 16-bit left-justified mode, in which case there are 16 SCK pulses per left/right sample.)

The SCK serial clock is ‘bursty’ (i.e. not continuous), and is low when LRCK changes state. The SCK pulses occur in between the LRCK transitions (i.e. SCK).

Although timing diagrams in many codec datasheets show a high-to-low SCK transition on each LRCK edge (as does the I2S Bus Specification), many such codecs have proven to work successfully. However, if the hardware implementation of a particular codec relies on SCK going low at LRCK transitions, the device may not be compatible.

I2C Interface (SCL and SDA)

The CP2114/2614/2615 devices provide an I2C interface for communicating with codec and other slave devices.  The I2C interface can be used for:

• Automatic application of initialization and shutdown sequences for any I2C slave device
• Applying register settings in response to playback volume and mute commands from host
• Performing user-defined I2C Write or Read operations with any I2C slave device

The CP2114/2614/2615 do not support multi-master I2C operation. There cannot be another I2C master in the system.  (An exception is when the CP2614/2615 is booted in Configuration Mode to allow an external master to reprogram the CP2614/2615 configuration.  In Configuration Mode the CP2614/2615 acts as an I2C slave.)

Mechanisms for Controlling Codec Mute and Volume

This table illustrates the possible methods of controlling Volume and Mute for Playback and Record:

The CP2114/2614/2615 devices provide a mechanism to linearly map audio playback volume settings (in dB) to the appropriate register values.  The devices support signed and unsigned register values, but the relationship between volume setting (in dB) and register setting must be directly proportional (i.e. register value increases as volume setting increases). An inversely proportional relationship (i.e. register value decreases as volume setting increases) is not supported.

Acoustic Echo Cancellation (AEC)
If the system requires acoustic echo cancellation, a 48 or 49.152 MHz external clock must be used to drive the CP2114 EXTCLK pin.  (The CP2614/2615 devices do not support the use of an external clock.)