Can I execute code on my Cortex-M3 SiM3xxxx device from an external memory using the EMIF?
Yes, it is possible to do this. However, code execution from an external memory will be much slower than internal code execution because the bus accesses are slower and the core cannot take advantage of the Advanced High-Performance Bus (AHB) features.
What is the USART or UART maximum baud rate limited by?
There are several things which may limit the maximum speed of the UART.
Maximum available clock
Interrupt handler efficiency
Maximum Available Clock
The baud rate equation for the USART or UART can be found in the corresponding reference manual. For example, with SiM3U1xx devices, the maximum baud rate is:
Where TBAUD and RBAUD are the 16-bit register fields and N is 2 or 16 depending on the IrDA enable bit for the transmitter or receiver. If transmit or receive N is equal to 2, the maximum baud rateisAPB/2. If transmit or receive N is equal to 16, the maximum baud rateisAPB/16.
The highest frequency signal that can be carried from device to device by a trace may be calculated as approximately:
where C is the capacitance of the trace and R is the impedance of the driver. For example, on the C8051F12x, the average driver impedance in normal mode at 3.3 V is approximately 500 ohm. Therefore, in the case where trace capacitance is 10 pF, the C8051F12x is capable of driving a signal at approximately 32 MHz. Even if the UART itself can be clocked at a higher frequency, the system will not work beyond 32 MHz.
Data Handling Efficiency
For a USART or UART to sustain a continuous data rate, the interrupt handler or DMA operation must complete in no more time then the USART or UART takes to make one transfer so the transmit or receive FIFOs do not reach completely full or completely empty status. Generally, this is not an issue. However, if the USART or UART is operating a near the core clock frequency (AHB), there will be little time for the handler or DMA to manage the data. The USART A and UART A modules do have automatic hardware flow control that can set or clear the handshaking pins as the USART or UART nears FIFO capacity, but this will slow down the overall transfer speed. For non-DMA transfers, if the handler attempts to perform a task that takes a long time, then the sustainable speed of the USART or UART may need to decrease to ensure the handler has time to complete between each transfer.
How can I use the CP2200 and the TCP/IP stack on devices other than the 'F34x/'F02x/'F12x?
To use the CP220x and TCP/IP stack on devices other than the 'F34x/'F02x/'F12x, you will need the TCP/IP stack source code. We recommend the following steps:
1. Contact MCU Applications Support and request the TCP/IP stack source code. 2. Generate a project for the 'F34x. 3. Use the instructions inside the source code package to replace the library with actual source. 4. Port the initialization routines to the MCU you will be using.
Most devices with an EMIF and at least 4KB RAM will run the TCP/IP stack.
I am trying to use one of your USB devices with a USB 3.0 socket. Are your devices compatible with the USB 3.0 standard?
USB 3.0 is backwards compatible with all previous USB versions, so our devices work with all USB 3.0 hubs and hosts. Our devices successfully enumerate and certify based on specifications found at www.usb.org.
Can not erase last page of flash with the CPFLASH_PageErase function providied by the tcp/ip stack.
The last page of flash contains the MAC address of the system. The tcp/ip library function CPFLASH_PageErase intentionally ignores erase requests to the last page in flash to ensure that the MAC address is not accidentally erased.
If you need to erase the last page of flash then you must manually perform the operation. Consult the MCU data sheet for information on how to perform flash erases. Generally the procedure to erase a page in flash containing the address [addr] will look like this:
void erase_page(unsigned int addr)
// Set the Flash Address Pointer to <addr>
FLASHADDRH = (addr >> 8); // Copy High Byte
FLASHADDRL = (addr & 0xFF); // Copy Low Byte
// Write the Flash unlock sequence 0xA5, 0xF1
FLASHKEY = 0xA5;
FLASHKEY = 0xF1;
// Set the Flash Busy bit
// Initiate the Flash erase
FLASHERASE = 0x01;
What are the timing requirements for the SPI's NSS pin?
When operating in 4-wire Master Mode, the NSS pin is toggled by firmware. The actual timing requirement is determined by your slave and not the master, because it is the slave that needs to accept the incoming data. Typically, pulling NSS low the instruction before writing to SPI0DAT is sufficient for the slave.