For an 'N/16' UART (example: UART0 on the C8051F12x), the minimum clock divisor for baud rate generation is 16.
The UART baud rate is determined by the overflow rate of the selected timer. Depending on the device, the available timers for baud rate generation my vary. The UART baud rate will be equal to the selected timer overflow rate divided by 16 when the 'SMODn' bit for the UART is equal to '1'. If 'SMODn' for the UART is equal to '0', the UART baud rate will be equal to the selected timer overflow rate divided by 32.
For example, to configure the UART for a baud rate of 9600 bps using Timer 2 as the baud rate source, you could configure the overflow rate of Timer 2 to equal 9600 * 16 = 153.6 kHz, and set 'SMODn' to '1'.
For an 'N/2' UART (example: UART1 on the C8051F12x), the minimum clock divisor for baud rate generation is 2.
The UART baud rate is determined by the overflow rate of Timer 1. Specifically, the UART baud rate is equal to the Timer 1 overflow frequency divided by 2.
For example, to configure the UART for a baud rate of 9600 bps, you would configure the overflow rate of Timer 1 to equal 9600 * 2 = 19.2 kHz.
What is the difference between devices with a JTAG debug interface and a C2 debug interface?
Answer
JTAG is an industry-standard 4-wire interface. It is found on many of Silicon Labs' MCU devices in large pin-count packages, such as the C8051F12x family. The JTAG interface on all but the C8051F20x/22x/23x families includes full boundary scan capability for in-circuit testing. While the C8051F20x/22x/23x do not have boundary scan capabilities, they can still participate in a boundary scan chain in 'BYPASS' mode.
The JTAG standard requires four dedicated pins for functionality. On devices which have only a few pins, implementing a JTAG interface is not feasible. It is for this reason that the C2 interface was developed.
The C2 interface is a proprietary 2-wire serial debug interface used primarily on Silicon Labs' MCU devices in low pin-count packages, such as the C8051F30x family. The C2 debug interface shares its two serial pins with other device pins (normally /RST and a GPIO pin) to minimize the amount of hardware 'used up' by the debug interface.
The Debug Interface specific to your device can be set in the Silicon Labs IDE in the Tools -> Debug Interface menu. This setting must be correct in order to connect to a device using the IDE. A schematic for each target board, which contains hardware information on using these interfaces, can be found in the appropriate Development Kit User's Guide.
Interface Knowledge Base
Baud Rate Configuration for N/16 UARTs
Question
How do I set the UART baud rate?
Answer
For an 'N/16' UART (example: UART0 on the C8051F12x), the minimum clock divisor for baud rate generation is 16.
The UART baud rate is determined by the overflow rate of the selected timer. Depending on the device, the available timers for baud rate generation my vary. The UART baud rate will be equal to the selected timer overflow rate divided by 16 when the 'SMODn' bit for the UART is equal to '1'. If 'SMODn' for the UART is equal to '0', the UART baud rate will be equal to the selected timer overflow rate divided by 32.
For example, to configure the UART for a baud rate of 9600 bps using Timer 2 as the baud rate source, you could configure the overflow rate of Timer 2 to equal 9600 * 16 = 153.6 kHz, and set 'SMODn' to '1'.
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Baud Rate Configuration for N/2 UARTs
Question
How do I set the UART baud rate?
Answer
For an 'N/2' UART (example: UART1 on the C8051F12x), the minimum clock divisor for baud rate generation is 2.
The UART baud rate is determined by the overflow rate of Timer 1. Specifically, the UART baud rate is equal to the Timer 1 overflow frequency divided by 2.
For example, to configure the UART for a baud rate of 9600 bps, you would configure the overflow rate of Timer 1 to equal 9600 * 2 = 19.2 kHz.
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JTAG and C2 Debug Interfaces
Question
What is the difference between devices with a JTAG debug interface and a C2 debug interface?
Answer
JTAG is an industry-standard 4-wire interface. It is found on many of Silicon Labs' MCU devices in large pin-count packages, such as the C8051F12x family. The JTAG interface on all but the C8051F20x/22x/23x families includes full boundary scan capability for in-circuit testing. While the C8051F20x/22x/23x do not have boundary scan capabilities, they can still participate in a boundary scan chain in 'BYPASS' mode.
The JTAG standard requires four dedicated pins for functionality. On devices which have only a few pins, implementing a JTAG interface is not feasible. It is for this reason that the C2 interface was developed.
The C2 interface is a proprietary 2-wire serial debug interface used primarily on Silicon Labs' MCU devices in low pin-count packages, such as the C8051F30x family. The C2 debug interface shares its two serial pins with other device pins (normally /RST and a GPIO pin) to minimize the amount of hardware 'used up' by the debug interface.
The Debug Interface specific to your device can be set in the Silicon Labs IDE in the Tools -> Debug Interface menu. This setting must be correct in order to connect to a device using the IDE. A schematic for each target board, which contains hardware information on using these interfaces, can be found in the appropriate Development Kit User's Guide.
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