I have a question regarding the I2C clock frequency. While setting a master, we need to specify the maximum clock frequency. However, is it possible to set a fixed frequency, not just the maximum I want to operate to?
For example, when I set the clock for a maximum of 400kHz and I use the oscilloscope to measure its frequency, it is no where near the maximum and usually around 200-300kHz depending on the clock high/low ratio.
1- Is it possible to set a fixed I2C clock frequency?
2- Is there any registers to know at what frequency it is currently operating (not the maximum I set it to, but the real frequency)
PS: I am not taking into consideration clock stretching from a slave.
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32-bit MCUs
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For EFM32/EFR32 components, the I2C frequency depends on the HF clock and how many prescalers are in series from that to the I2C module itself.
If your HF clock is 38.4 MHz, from HFXO, as is the case in the radio parts, the I2C frequency will be quite stable and fixed at some integer division of that frequency. With this Xtal, you would need prescaling somewhere in the clock path (the closer it is to HFCLK, the lower the overall power supply current, but there may be other peripherals also controlled by those prescalers higher in the clock tree) or in the I2C peripheral itself...at a minimum of 10, which would give you ~ 384 KHz.
There are no registers that tell you what the actual I2C frequency is, but you can calculate it from the HF clock frequency and all series prescaling involved.
0
On the BGM13P, the pull-ups on the SCL and SDA pins seems to be weak since the maximum frequency I can achieve is 100-200kHz.
Why does the pull-ups have so much impact on the I2C clock?
If I understand correctly, if I change the value of the pull-up, the frequency of the clock changes. Why?
Is there any fix without adding an external pull-up?
Thank you.
0
I suggest you use a oscilloscope to monitor the signal (rather than a logic analyzer).
If I understand correctly, if I change the value of the pull-up, the frequency of the clock changes. Why?
if you change the pull-up resistor value, I think the ramp-up slope would be greatly affected. the frequency would still keep same.
"Why does the pull-ups have so much impact on the I2C clock?"
The pullups have a very significant impact on both the clock line and the data line...but do not directly affect the clock frequency. I2C is an open-drain bus, meaning there is an active pulldown xistor on each of the clock and data lines at every node (Master or Slave) on the bus. The only way for the comm signals to go Hi is for the pullup resistors to pull them high. So, the faster the comm rate (higher the clock frequency), the lower the pullup resistance required to quickly charge the bus capacitance...whatever it may be due to the length of the bus wires, etc.
4.7K Ohm is usually a fair starting point for pullups on both clk and dat lines for 100 KBPs baud rates and similar. If you 4X that rate, then you will also likely need to reduce the pullup values to 3.9K, 2.2K, or even 1K....
Like delu said, the way to determine this is with an oscilloscope; there is no other way to examine the signal integrity based on bus capacitance and pullup resistor values.
I2C SCL Fixed Frequency
Hello,
I have a question regarding the I2C clock frequency. While setting a master, we need to specify the maximum clock frequency. However, is it possible to set a fixed frequency, not just the maximum I want to operate to?
For example, when I set the clock for a maximum of 400kHz and I use the oscilloscope to measure its frequency, it is no where near the maximum and usually around 200-300kHz depending on the clock high/low ratio.
1- Is it possible to set a fixed I2C clock frequency?
2- Is there any registers to know at what frequency it is currently operating (not the maximum I set it to, but the real frequency)
PS: I am not taking into consideration clock stretching from a slave.
For EFM32/EFR32 components, the I2C frequency depends on the HF clock and how many prescalers are in series from that to the I2C module itself.
If your HF clock is 38.4 MHz, from HFXO, as is the case in the radio parts, the I2C frequency will be quite stable and fixed at some integer division of that frequency. With this Xtal, you would need prescaling somewhere in the clock path (the closer it is to HFCLK, the lower the overall power supply current, but there may be other peripherals also controlled by those prescalers higher in the clock tree) or in the I2C peripheral itself...at a minimum of 10, which would give you ~ 384 KHz.
There are no registers that tell you what the actual I2C frequency is, but you can calculate it from the HF clock frequency and all series prescaling involved.
On the BGM13P, the pull-ups on the SCL and SDA pins seems to be weak since the maximum frequency I can achieve is 100-200kHz.
Why does the pull-ups have so much impact on the I2C clock?
If I understand correctly, if I change the value of the pull-up, the frequency of the clock changes. Why?
Is there any fix without adding an external pull-up?
Thank you.
I suggest you use a oscilloscope to monitor the signal (rather than a logic analyzer).
if you change the pull-up resistor value, I think the ramp-up slope would be greatly affected. the frequency would still keep same.
https://www.silabs.com/community/mcu/8-bit/knowledge-base.entry.html/2017/06/09/i2c_pull-up_resistor-rJbx
For I2C function, you would need an external pull-up resistor (the internal 40k pull-up is too weak).
https://www.silabs.com/community/wireless/zigbee-and-thread/knowledge-base.entry.html/2017/02/03/efr32_maximum_extern-GwG9
https://www.silabs.com/community/mcu/32-bit/knowledge-base.entry.html/2016/12/12/the_value_of_interna-27Yd
Also pay attention on the drive strength and slew rate setting.
https://www.silabs.com/community/mcu/32-bit/knowledge-base.entry.html/2016/01/14/drive_strength_diffe-W6yu.html
"Why does the pull-ups have so much impact on the I2C clock?"
The pullups have a very significant impact on both the clock line and the data line...but do not directly affect the clock frequency. I2C is an open-drain bus, meaning there is an active pulldown xistor on each of the clock and data lines at every node (Master or Slave) on the bus. The only way for the comm signals to go Hi is for the pullup resistors to pull them high. So, the faster the comm rate (higher the clock frequency), the lower the pullup resistance required to quickly charge the bus capacitance...whatever it may be due to the length of the bus wires, etc.
4.7K Ohm is usually a fair starting point for pullups on both clk and dat lines for 100 KBPs baud rates and similar. If you 4X that rate, then you will also likely need to reduce the pullup values to 3.9K, 2.2K, or even 1K....
Like delu said, the way to determine this is with an oscilloscope; there is no other way to examine the signal integrity based on bus capacitance and pullup resistor values.