I am working on BGM13P, when i am listening on SCL and SDA pins with a logic analyzer, it seems be inverted, the clock is on pin18 (PC10#15) and the data on pin 19 (PC11#15).
Any person known this behavior ?
Here it is.
I2C0->ROUTEPEN = I2C0->ROUTEPEN | I2C_ROUTEPEN_SCLPEN;
I2C0->ROUTELOC0 = (I2C0->ROUTELOC0 & (~_I2C_ROUTELOC0_SCLLOC_MASK)) | I2C_ROUTELOC0_SCLLOC_LOC15;
I2C0->ROUTEPEN = I2C0->ROUTEPEN | I2C_ROUTEPEN_SDAPEN;
I2C0->ROUTELOC0 = (I2C0->ROUTELOC0 & (~_I2C_ROUTELOC0_SDALOC_MASK)) | I2C_ROUTELOC0_SDALOC_LOC15
This location is working well, on the WSTK DevKit, but on the customized PCB with the same wiring, it is not working ! We have to change the location to SCL to 14 and SDA to 16, why this difference ?
According to BGM13P Data Sheet, For I2C0 routing location #15, CLK should be on PC11 and DAT on PC10. But, you say you see these reversed on the WSTK, yet working well - just confirming?
If so, I will have to confirm this...so, please stand by.
I am confusing between the locations.
It seems be ok now.
Can you share the data sheet from you have make the screen shot ?